diff options
author | acirillo87 <acirillo87@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-03-08 17:37:49 +0000 |
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committer | acirillo87 <acirillo87@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-03-08 17:37:49 +0000 |
commit | 42dc58dcb210207b3d3841fc81f72e85462dd313 (patch) | |
tree | acb8b6a3b3292fe53ac32ab3db516c20463617c4 /os/hal/platforms/SPC5xx | |
parent | f204c289145f883d6bff0e4b5f9a286074ef60be (diff) | |
download | ChibiOS-42dc58dcb210207b3d3841fc81f72e85462dd313.tar.gz ChibiOS-42dc58dcb210207b3d3841fc81f72e85462dd313.tar.bz2 ChibiOS-42dc58dcb210207b3d3841fc81f72e85462dd313.zip |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5386 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/SPC5xx')
-rw-r--r-- | os/hal/platforms/SPC5xx/FlexPWM_v1/flexpwm.h | 490 | ||||
-rw-r--r-- | os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c | 21 | ||||
-rw-r--r-- | os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h | 5 | ||||
-rw-r--r-- | os/hal/platforms/SPC5xx/eTimer_v1/etimer.h | 314 | ||||
-rw-r--r-- | os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c | 36 | ||||
-rw-r--r-- | os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h | 3 |
6 files changed, 836 insertions, 33 deletions
diff --git a/os/hal/platforms/SPC5xx/FlexPWM_v1/flexpwm.h b/os/hal/platforms/SPC5xx/FlexPWM_v1/flexpwm.h new file mode 100644 index 000000000..b13787a64 --- /dev/null +++ b/os/hal/platforms/SPC5xx/FlexPWM_v1/flexpwm.h @@ -0,0 +1,490 @@ +/*
+ * Licensed under ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file FlexPWM_v1/flexpwm.h
+ * @brief SPC5xx FlexPWM header file.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#ifndef _FLEXPWM_H_
+#define _FLEXPWM_H_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief SPC5 FlexPWM registers block.
+ * @note Redefined from the SPC5 headers because the non uniform
+ * declaration of the SubModules registers among the various
+ * sub-families.
+ */
+struct spc5_flexpwm_submodule {
+
+ union {
+ vuint16_t R;
+ } CNT; /* Counter Register */
+
+ union {
+ vuint16_t R;
+ } INIT; /* Initial Count Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t DBGEN :1;
+ vuint16_t WAITEN :1;
+ vuint16_t INDEP :1;
+ vuint16_t PWMA_INIT :1;
+ vuint16_t PWMB_INIT :1;
+ vuint16_t PWMX_INIT :1;
+ vuint16_t INIT_SEL :2;
+ vuint16_t FRCEN :1;
+ vuint16_t FORCE :1;
+ vuint16_t FORCE_SEL :3;
+ vuint16_t RELOAD_SEL :1;
+ vuint16_t CLK_SEL :2;
+ } B;
+ } CTRL2; /* Control 2 Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t LDFQ :4;
+ vuint16_t HALF :1;
+ vuint16_t FULL :1;
+ vuint16_t DT :2;
+ vuint16_t :1;
+ vuint16_t PRSC :3;
+ vuint16_t :3;
+ vuint16_t DBLEN :1;
+ } B;
+ } CTRL; /* Control Register */
+
+ union {
+ vuint16_t R;
+ } VAL[6]; /* Value Register 0->5 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t FRACAEN :1;
+ vuint16_t :10;
+ vuint16_t FRACADLY :5;
+ } B;
+ } FRACA; /* Fractional Delay Register A */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t FRACBEN :1;
+ vuint16_t :10;
+ vuint16_t FRACBDLY :5;
+ } B;
+ } FRACB; /* Fractional Delay Register B */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t PWMA_IN :1;
+ vuint16_t PWMB_IN :1;
+ vuint16_t PWMX_IN :1;
+ vuint16_t :2;
+ vuint16_t POLA :1;
+ vuint16_t POLB :1;
+ vuint16_t POLX :1;
+ vuint16_t :2;
+ vuint16_t PWMAFS :2;
+ vuint16_t PWMBFS :2;
+ vuint16_t PWMXFS :2;
+ } B;
+ } OCTRL; /* Output Control Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :1;
+ vuint16_t RUF :1;
+ vuint16_t REF :1;
+ vuint16_t RF :1;
+ vuint16_t CFA1 :1;
+ vuint16_t CFA0 :1;
+ vuint16_t CFB1 :1;
+ vuint16_t CFB0 :1;
+ vuint16_t CFX1 :1;
+ vuint16_t CFX0 :1;
+ vuint16_t CMPF :6;
+ } B;
+ } STS; /* Status Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :2;
+ vuint16_t REIE :1;
+ vuint16_t RIE :1;
+ vuint16_t :4;
+ vuint16_t CX1IE :1;
+ vuint16_t CX0IE :1;
+ vuint16_t CMPIE :6;
+ } B;
+ } INTEN; /* Interrupt Enable Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :6;
+ vuint16_t VALDE :1;
+ vuint16_t FAND :1;
+ vuint16_t CAPTDE :2;
+ vuint16_t CA1DE :1;
+ vuint16_t CA0DE :1;
+ vuint16_t CB1DE :1;
+ vuint16_t CB0DE :1;
+ vuint16_t CX1DE :1;
+ vuint16_t CX0DE :1;
+ } B;
+ } DMAEN; /* DMA Enable Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :10;
+ vuint16_t OUT_TRIG_EN :6;
+ } B;
+ } TCTRL; /* Output Trigger Control Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :4;
+ vuint16_t DISX :4;
+ vuint16_t DISB :4;
+ vuint16_t DISA :4;
+ } B;
+ } DISMAP; /* Fault Disable Mapping Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :5;
+ vuint16_t DTCNT0 :11;
+ } B;
+ } DTCNT0; /* Deadtime Count Register 0 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :5;
+ vuint16_t DTCNT1 :11;
+ } B;
+ } DTCNT1; /* Deadtime Count Register 1 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CA1CNT :3;
+ vuint16_t CA0CNT :3;
+ vuint16_t CFAWM :2;
+ vuint16_t EDGCNTAEN :1;
+ vuint16_t INPSELA :1;
+ vuint16_t EDGA1 :2;
+ vuint16_t EDGA0 :2;
+ vuint16_t ONESHOTA :1;
+ vuint16_t ARMA :1;
+ } B;
+ } CAPTCTRLA; /* Capture Control Register A */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t EDGCNTA :8;
+ vuint16_t EDGCMPA :8;
+ } B;
+ } CAPTCOMPA; /* Capture Compare Register A */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CB1CNT :3;
+ vuint16_t CB0CNT :3;
+ vuint16_t CFBWM :2;
+ vuint16_t EDGCNTBEN :1;
+ vuint16_t INPSELB :1;
+ vuint16_t EDGB1 :2;
+ vuint16_t EDGB0 :2;
+ vuint16_t ONESHOTB :1;
+ vuint16_t ARMB :1;
+ } B;
+ } CAPTCTRLB; /* Capture Control Register B */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t EDGCNTB :8;
+ vuint16_t EDGCMPB :8;
+ } B;
+ } CAPTCOMPB; /* Capture Compare Register B */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CX1CNT :3;
+ vuint16_t CX0CNT :3;
+ vuint16_t CFXWM :2;
+ vuint16_t EDGCNTX_EN :1;
+ vuint16_t INP_SELX :1;
+ vuint16_t EDGX1 :2;
+ vuint16_t EDGX0 :2;
+ vuint16_t ONESHOTX :1;
+ vuint16_t ARMX :1;
+ } B;
+ } CAPTCTRLX; /* Capture Control Register B */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t EDGCNTX :8;
+ vuint16_t EDGCMPX :8;
+ } B;
+ } CAPTCOMPX; /* Capture Compare Register X */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL0 :16;
+ } B;
+ } CVAL0; /* Capture Value 0 Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :12;
+ vuint16_t CVAL0CYC :4;
+ } B;
+ } CVAL0C; /* Capture Value 0 Cycle Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL1 :16;
+ } B;
+ } CVAL1; /* Capture Value 1 Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :12;
+ vuint16_t CVAL1CYC :4;
+ } B;
+ } CVAL1C; /* Capture Value 1 Cycle Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL2 :16;
+ } B;
+ } CVAL2; /* Capture Value 2 Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :12;
+ vuint16_t CVAL2CYC :4;
+ } B;
+ } CVAL2C; /* Capture Value 2 Cycle Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL3 :16;
+ } B;
+ } CVAL3; /* Capture Value 3 Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :12;
+ vuint16_t CVAL3CYC :4;
+ } B;
+ } CVAL3C; /* Capture Value 3 Cycle Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL4 :16;
+ } B;
+ } CVAL4; /* Capture Value 4 Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :12;
+ vuint16_t CVAL4CYC :4;
+ } B;
+ } CVAL4C; /* Capture Value 4 Cycle Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL5 :16;
+ } B;
+ } CVAL5; /* Capture Value 5 Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :12;
+ vuint16_t CVAL5CYC :4;
+ } B;
+ } CVAL5C; /* Capture Value 5 Cycle Register */
+
+ uint32_t FLEXPWM_SUB_reserved0; /* (0x04A - 0x050)/4 = 0x01 */
+
+};
+/* end of FLEXPWM_SUB_tag */
+
+struct spc5_flexpwm {
+
+ struct spc5_flexpwm_submodule SUB[4];
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :4;
+ vuint16_t PWMA_EN :4;
+ vuint16_t PWMB_EN :4;
+ vuint16_t PWMX_EN :4;
+ } B;
+ } OUTEN; /* Output Enable Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :4;
+ vuint16_t MASKA :4;
+ vuint16_t MASKB :4;
+ vuint16_t MASKX :4;
+ } B;
+ } MASK; /* Output Mask Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :8;
+ vuint16_t OUTA_3 :1;
+ vuint16_t OUTB_3 :1;
+ vuint16_t OUTA_2 :1;
+ vuint16_t OUTB_2 :1;
+ vuint16_t OUTA_1 :1;
+ vuint16_t OUTB_1 :1;
+ vuint16_t OUTA_0 :1;
+ vuint16_t OUTB_0 :1;
+ } B;
+ } SWCOUT; /* Software Controlled Output Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SELA_3 :2;
+ vuint16_t SELB_3 :2;
+ vuint16_t SELA_2 :2;
+ vuint16_t SELB_2 :2;
+ vuint16_t SELA_1 :2;
+ vuint16_t SELB_1 :2;
+ vuint16_t SELA_0 :2;
+ vuint16_t SELB_0 :2;
+ } B;
+ } DTSRCSEL; /* Deadtime Source Select Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t IPOL :4;
+ vuint16_t RUN :4;
+ vuint16_t CLDOK :4;
+ vuint16_t LDOK :4;
+ } B;
+ } MCTRL; /* Master Control Register */
+
+ int16_t FLEXPWM_reserved1;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t FLVL :4;
+ vuint16_t FAUTO :4;
+ vuint16_t FSAFE :4;
+ vuint16_t FIE :4;
+ } B;
+ } FCTRL; /* Fault Control Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t FTEST :1;
+ vuint16_t FFPIN :4;
+ vuint16_t :4;
+ vuint16_t FFLAG :4;
+ } B;
+ } FSTS; /* Fault Status Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :5;
+ vuint16_t FILT_CNT :3;
+ vuint16_t FILT_PER :8;
+ } B;
+ } FFILT; /* Fault FilterRegister */
+
+};
+/* end of FLEXPWM_tag */
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name FlexPWM units references
+ * @{
+ */
+#if SPC5_HAS_FLEXPWM0
+#define SPC5_FLEXPWM_0 (*(volatile struct spc5_flexpwm *)0xFFE24000UL)
+#endif
+
+#if SPC5_HAS_FLEXPWM1
+#define SPC5_FLEXPWM_1 (*(volatile struct spc5_flexpwm *)0xFFE28000UL)
+#endif
+/** @} */
+
+#endif /* _FLEXPWM_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c index ebeb56d66..b3af9845f 100644 --- a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c +++ b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c @@ -449,10 +449,8 @@ void pwm_lld_disable_submodule_channel(PWMDriver *pwmp, pwmp->flexpwmp->MCTRL.B.LDOK |= (0b0000 | (1U << sid));
}
-#if SPC5_PWM_USE_SMOD0 || SPC5_PWM_USE_SMOD1 || SPC5_PWM_USE_SMOD2 || \
- SPC5_PWM_USE_SMOD3 || defined(__DOXYGEN__)
/**
- * @brief Common SMOD0...SMOD3 IRQ handler.
+ * @brief Common SMOD0...SMOD7 IRQ handler.
* @note It is assumed that the various sources are only activated if the
* associated callback pointer is not equal to @p NULL in order to not
* perform an extra check in a potentially critical interrupt handler.
@@ -599,7 +597,6 @@ static void pwm_lld_serve_interrupt(PWMDriver *pwmp) { }
#endif
}
-#endif /* SPC5_PWM_USE_SMOD0 || ... || SPC5_PWM_USE_SMOD7 */
/*===========================================================================*/
/* Driver interrupt handlers. */
@@ -907,7 +904,7 @@ void pwm_lld_init(void) { #if (SPC5_PWM_USE_SMOD0)
/* Driver initialization.*/
pwmObjectInit(&PWMD1);
- PWMD1.flexpwmp = &FLEXPWM_0;
+ PWMD1.flexpwmp = &SPC5_FLEXPWM_0;
INTC.PSR[SPC5_FLEXPWM0_RF0_NUMBER].R = SPC5_PWM_SMOD0_PRIORITY;
INTC.PSR[SPC5_FLEXPWM0_COF0_NUMBER].R = SPC5_PWM_SMOD0_PRIORITY;
INTC.PSR[SPC5_FLEXPWM0_CAF0_NUMBER].R = SPC5_PWM_SMOD0_PRIORITY;
@@ -918,7 +915,7 @@ void pwm_lld_init(void) { #if (SPC5_PWM_USE_SMOD1)
/* Driver initialization.*/
pwmObjectInit(&PWMD2);
- PWMD2.flexpwmp = &FLEXPWM_0;
+ PWMD2.flexpwmp = &SPC5_FLEXPWM_0;
INTC.PSR[SPC5_FLEXPWM0_RF1_NUMBER].R = SPC5_PWM_SMOD1_PRIORITY;
INTC.PSR[SPC5_FLEXPWM0_COF1_NUMBER].R = SPC5_PWM_SMOD1_PRIORITY;
INTC.PSR[SPC5_FLEXPWM0_CAF1_NUMBER].R = SPC5_PWM_SMOD1_PRIORITY;
@@ -929,7 +926,7 @@ void pwm_lld_init(void) { #if (SPC5_PWM_USE_SMOD2)
/* Driver initialization.*/
pwmObjectInit(&PWMD3);
- PWMD3.flexpwmp = &FLEXPWM_0;
+ PWMD3.flexpwmp = &SPC5_FLEXPWM_0;
INTC.PSR[SPC5_FLEXPWM0_RF2_NUMBER].R = SPC5_PWM_SMOD2_PRIORITY;
INTC.PSR[SPC5_FLEXPWM0_COF2_NUMBER].R = SPC5_PWM_SMOD2_PRIORITY;
INTC.PSR[SPC5_FLEXPWM0_CAF2_NUMBER].R = SPC5_PWM_SMOD2_PRIORITY;
@@ -940,7 +937,7 @@ void pwm_lld_init(void) { #if (SPC5_PWM_USE_SMOD3)
/* Driver initialization.*/
pwmObjectInit(&PWMD4);
- PWMD4.flexpwmp = &FLEXPWM_0;
+ PWMD4.flexpwmp = &SPC5_FLEXPWM_0;
INTC.PSR[SPC5_FLEXPWM0_RF3_NUMBER].R = SPC5_PWM_SMOD3_PRIORITY;
INTC.PSR[SPC5_FLEXPWM0_COF3_NUMBER].R = SPC5_PWM_SMOD3_PRIORITY;
INTC.PSR[SPC5_FLEXPWM0_CAF3_NUMBER].R = SPC5_PWM_SMOD3_PRIORITY;
@@ -951,7 +948,7 @@ void pwm_lld_init(void) { #if (SPC5_PWM_USE_SMOD4)
/* Driver initialization.*/
pwmObjectInit(&PWMD5);
- PWMD5.flexpwmp = &FLEXPWM_1;
+ PWMD5.flexpwmp = &SPC5_FLEXPWM_1;
INTC.PSR[SPC5_FLEXPWM1_RF0_NUMBER].R = SPC5_PWM_SMOD4_PRIORITY;
INTC.PSR[SPC5_FLEXPWM1_COF0_NUMBER].R = SPC5_PWM_SMOD4_PRIORITY;
INTC.PSR[SPC5_FLEXPWM1_CAF0_NUMBER].R = SPC5_PWM_SMOD4_PRIORITY;
@@ -962,7 +959,7 @@ void pwm_lld_init(void) { #if (SPC5_PWM_USE_SMOD5)
/* Driver initialization.*/
pwmObjectInit(&PWMD6);
- PWMD6.flexpwmp = &FLEXPWM_1;
+ PWMD6.flexpwmp = &SPC5_FLEXPWM_1;
INTC.PSR[SPC5_FLEXPWM1_RF1_NUMBER].R = SPC5_PWM_SMOD5_PRIORITY;
INTC.PSR[SPC5_FLEXPWM1_COF1_NUMBER].R = SPC5_PWM_SMOD5_PRIORITY;
INTC.PSR[SPC5_FLEXPWM1_CAF1_NUMBER].R = SPC5_PWM_SMOD5_PRIORITY;
@@ -973,7 +970,7 @@ void pwm_lld_init(void) { #if (SPC5_PWM_USE_SMOD6)
/* Driver initialization.*/
pwmObjectInit(&PWMD3);
- PWMD7.flexpwmp = &FLEXPWM_1;
+ PWMD7.flexpwmp = &SPC5_FLEXPWM_1;
INTC.PSR[SPC5_FLEXPWM1_RF2_NUMBER].R = SPC5_PWM_SMOD6_PRIORITY;
INTC.PSR[SPC5_FLEXPWM1_COF2_NUMBER].R = SPC5_PWM_SMOD6_PRIORITY;
INTC.PSR[SPC5_FLEXPWM1_CAF2_NUMBER].R = SPC5_PWM_SMOD6_PRIORITY;
@@ -984,7 +981,7 @@ void pwm_lld_init(void) { #if (SPC5_PWM_USE_SMOD7)
/* Driver initialization.*/
pwmObjectInit(&PWMD4);
- PWMD8.flexpwmp = &FLEXPWM_1;
+ PWMD8.flexpwmp = &SPC5_FLEXPWM_1;
INTC.PSR[SPC5_FLEXPWM1_RF3_NUMBER].R = SPC5_PWM_SMOD7_PRIORITY;
INTC.PSR[SPC5_FLEXPWM1_COF3_NUMBER].R = SPC5_PWM_SMOD7_PRIORITY;
INTC.PSR[SPC5_FLEXPWM1_CAF3_NUMBER].R = SPC5_PWM_SMOD7_PRIORITY;
diff --git a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h index 7bb0d6b83..d51156c90 100644 --- a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h +++ b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h @@ -30,7 +30,7 @@ /*===========================================================================*/
/**
- * @name LINIER register bits definitions
+ * @name STS register bits definitions
* @{
*/
#define SPC5_STS_CMPF0 (1U << 0)
@@ -320,6 +320,7 @@ /*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
+#include "flexpwm.h"
/**
* @brief PWM mode type.
@@ -409,7 +410,7 @@ struct PWMDriver { /**
* @Pointer to the volatile FlexPWM registers block.
*/
- volatile struct FLEXPWM_tag *flexpwmp;
+ volatile struct spc5_flexpwm *flexpwmp;
};
/*===========================================================================*/
diff --git a/os/hal/platforms/SPC5xx/eTimer_v1/etimer.h b/os/hal/platforms/SPC5xx/eTimer_v1/etimer.h new file mode 100644 index 000000000..c0a0f2c76 --- /dev/null +++ b/os/hal/platforms/SPC5xx/eTimer_v1/etimer.h @@ -0,0 +1,314 @@ +/*
+ * Licensed under ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file eTimer_v1/etimer.h
+ * @brief SPC5xx eTimer header file.
+ *
+ * @addtogroup ICU
+ * @{
+ */
+
+#ifndef _ETIMER_H_
+#define _ETIMER_H_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief SPC5 FlexPWM registers block.
+ * @note Redefined from the SPC5 headers because the non uniform
+ * declaration of the SubModules registers among the various
+ * sub-families.
+ */
+struct spc5_etimer_submodule {
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t COMP1 :16;
+ } B;
+ } COMP1; /* Compare Register 1 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t COMP2 :16;
+ } B;
+ } COMP2; /* Compare Register 2 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPT1 :16;
+ } B;
+ } CAPT1; /* Capture Register 1 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPT2 :16;
+ } B;
+ } CAPT2; /* Capture Register 2 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t LOAD :16;
+ } B;
+ } LOAD; /* Load Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t HOLD :16;
+ } B;
+ } HOLD; /* Hold Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CNTR :16;
+ } B;
+ } CNTR; /* Counter Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CNTMODE :3;
+ vuint16_t PRISRC :5;
+ vuint16_t ONCE :1;
+ vuint16_t LENGTH :1;
+ vuint16_t DIR :1;
+ vuint16_t SECSRC :5;
+ } B;
+ } CTRL; /* Control Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t OEN :1;
+ vuint16_t RDNT :1;
+ vuint16_t INPUT :1;
+ vuint16_t VAL :1;
+ vuint16_t FORCE :1;
+ vuint16_t COFRC :1;
+ vuint16_t COINIT :2;
+ vuint16_t SIPS :1;
+ vuint16_t PIPS :1;
+ vuint16_t OPS :1;
+ vuint16_t MSTR :1;
+ vuint16_t OUTMODE :4;
+ } B;
+ } CTRL2; /* Control Register 2 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t STPEN :1;
+ vuint16_t ROC :2;
+ vuint16_t FMODE :1;
+ vuint16_t FDIS :4;
+ vuint16_t C2FCNT :3;
+ vuint16_t C1FCNT :3;
+ vuint16_t DBGEN :2;
+ } B;
+ } CTRL3; /* Control Register 3 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :6;
+ vuint16_t WDF :1;
+ vuint16_t RCF :1;
+ vuint16_t ICF2 :1;
+ vuint16_t ICF1 :1;
+ vuint16_t IEHF :1;
+ vuint16_t IELF :1;
+ vuint16_t TOF :1;
+ vuint16_t TCF2 :1;
+ vuint16_t TCF1 :1;
+ vuint16_t TCF :1;
+ } B;
+ } STS; /* Status Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t ICF2DE :1;
+ vuint16_t ICF1DE :1;
+ vuint16_t CMPLD2DE :1;
+ vuint16_t CMPLD1DE :1;
+ vuint16_t :2;
+ vuint16_t WDFIE :1;
+ vuint16_t RCFIE :1;
+ vuint16_t ICF2IE :1;
+ vuint16_t ICF1IE :1;
+ vuint16_t IEHFIE :1;
+ vuint16_t IELFIE :1;
+ vuint16_t TOFIE :1;
+ vuint16_t TCF2IE :1;
+ vuint16_t TCF1IE :1;
+ vuint16_t TCFIE :1;
+ } B;
+ } INTDMA; /* Interrupt and DMA Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CMPLD1 :16;
+ } B;
+ } CMPLD1; /* Compare Load Register 1 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CMPLD2 :16;
+ } B;
+ } CMPLD2; /* Compare Load Register 2 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CLC2 :3;
+ vuint16_t CLC1 :3;
+ vuint16_t CMPMODE :2;
+ vuint16_t CPT2MODE :2;
+ vuint16_t CPT1MODE :2;
+ vuint16_t CFWM :2;
+ vuint16_t ONESHOT :1;
+ vuint16_t ARM :1;
+ } B;
+ } CCCTRL; /* Compare and Capture Control Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :5;
+ vuint16_t FILTCNT :3;
+ vuint16_t FILTPER :8;
+ } B;
+ } FILT; /* Input Filter Register */
+
+};
+/* end of ETIMER_CHANNEL_tag */
+
+struct spc5_etimer {
+
+ struct spc5_etimer_submodule CHANNEL[8];
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t WDTOL :16;
+ } B;
+ } WDTOL; /* Watchdog Time-out Low Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t WDTOH :16;
+ } B;
+ } WDTOH; /* Watchdog Time-out High Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t FTEST :1;
+ vuint16_t FIE :4;
+ vuint16_t :4;
+ vuint16_t FLVL :4;
+ } B;
+ } FCTRL; /* Fault Control Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :4;
+ vuint16_t FFPIN :4;
+ vuint16_t :4;
+ vuint16_t FFLAG :4;
+ } B;
+ } FSTS; /* Fault Status Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :5;
+ vuint16_t FFILTCNT :3;
+ vuint16_t FFILTPER :8;
+ } B;
+ } FFILT; /* Fault Filter Register */
+
+ int16_t ETIMER_reserved1;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :8;
+ vuint16_t ENBL :8;
+ } B;
+ } ENBL; /* Channel Enable Register */
+
+ int16_t ETIMER_reserved2;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :11;
+ vuint16_t DREQ :5;
+ } B;
+ } DREQ[4]; /* DMA Request 0->3 Select Register */
+
+};
+/* end of ETIMER_tag */
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name FlexPWM units references
+ * @{
+ */
+#if SPC5_HAS_ETIMER0
+#define SPC5_ETIMER_0 (*(volatile struct spc5_etimer *)0xFFE18000UL)
+#endif
+
+#if SPC5_HAS_ETIMER1
+#define SPC5_ETIMER_1 (*(volatile struct spc5_etimer *)0xFFE1C000UL)
+#endif
+
+#if SPC5_HAS_ETIMER2
+#define SPC5_ETIMER_2 (*(volatile struct spc5_etimer *)0xFFE20000UL)
+#endif
+/** @} */
+
+#endif /* _FLEXPWM_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c b/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c index a2bd437e0..c90ef85e9 100644 --- a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c +++ b/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c @@ -740,126 +740,126 @@ void icu_lld_init(void) { #if SPC5_ICU_USE_SMOD0
/* Driver initialization.*/
icuObjectInit(&ICUD1);
- ICUD1.etimerp = &ETIMER_0;
+ ICUD1.etimerp = &SPC5_ETIMER_0;
ICUD1.smod_number = 0;
#endif
#if SPC5_ICU_USE_SMOD1
/* Driver initialization.*/
icuObjectInit(&ICUD2);
- ICUD2.etimerp = &ETIMER_0;
+ ICUD2.etimerp = &SPC5_ETIMER_0;
ICUD2.smod_number = 1;
#endif
#if SPC5_ICU_USE_SMOD2
/* Driver initialization.*/
icuObjectInit(&ICUD3);
- ICUD3.etimerp = &ETIMER_0;
+ ICUD3.etimerp = &SPC5_ETIMER_0;
ICUD3.smod_number = 2;
#endif
#if SPC5_ICU_USE_SMOD3
/* Driver initialization.*/
icuObjectInit(&ICUD4);
- ICUD4.etimerp = &ETIMER_0;
+ ICUD4.etimerp = &SPC5_ETIMER_0;
ICUD4.smod_number = 3;
#endif
#if SPC5_ICU_USE_SMOD4
/* Driver initialization.*/
icuObjectInit(&ICUD5);
- ICUD5.etimerp = &ETIMER_0;
+ ICUD5.etimerp = &SPC5_ETIMER_0;
ICUD5.smod_number = 4;
#endif
#if SPC5_ICU_USE_SMOD5
/* Driver initialization.*/
icuObjectInit(&ICUD6);
- ICUD6.etimerp = &ETIMER_0;
+ ICUD6.etimerp = &SPC5_ETIMER_0;
ICUD6.smod_number = 5;
#endif
#if SPC5_ICU_USE_SMOD6
/* Driver initialization.*/
icuObjectInit(&ICUD7);
- ICUD7.etimerp = &ETIMER_1;
+ ICUD7.etimerp = &SPC5_ETIMER_1;
ICUD7.smod_number = 0;
#endif
#if SPC5_ICU_USE_SMOD7
/* Driver initialization.*/
icuObjectInit(&ICUD8);
- ICUD8.etimerp = &ETIMER_1;
+ ICUD8.etimerp = &SPC5_ETIMER_1;
ICUD8.smod_number = 1;
#endif
#if SPC5_ICU_USE_SMOD8
/* Driver initialization.*/
icuObjectInit(&ICUD9);
- ICUD9.etimerp = &ETIMER_1;
+ ICUD9.etimerp = &SPC5_ETIMER_1;
ICUD9.smod_number = 2;
#endif
#if SPC5_ICU_USE_SMOD9
/* Driver initialization.*/
icuObjectInit(&ICUD10);
- ICUD10.etimerp = &ETIMER_1;
+ ICUD10.etimerp = &SPC5_ETIMER_1;
ICUD10.smod_number = 3;
#endif
#if SPC5_ICU_USE_SMOD10
/* Driver initialization.*/
icuObjectInit(&ICUD11);
- ICUD11.etimerp = &ETIMER_1;
+ ICUD11.etimerp = &SPC5_ETIMER_1;
ICUD11.smod_number = 4;
#endif
#if SPC5_ICU_USE_SMOD11
/* Driver initialization.*/
icuObjectInit(&ICUD12);
- ICUD12.etimerp = &ETIMER_1;
+ ICUD12.etimerp = &SPC5_ETIMER_1;
ICUD12.smod_number = 5;
#endif
#if SPC5_ICU_USE_SMOD12
/* Driver initialization.*/
icuObjectInit(&ICUD13);
- ICUD13.etimerp = &ETIMER_2;
+ ICUD13.etimerp = &SPC5_ETIMER_2;
ICUD13.smod_number = 0;
#endif
#if SPC5_ICU_USE_SMOD13
/* Driver initialization.*/
icuObjectInit(&ICUD14);
- ICUD14.etimerp = &ETIMER_2;
+ ICUD14.etimerp = &SPC5_ETIMER_2;
ICUD14.smod_number = 1;
#endif
#if SPC5_ICU_USE_SMOD14
/* Driver initialization.*/
icuObjectInit(&ICUD15);
- ICUD15.etimerp = &ETIMER_2;
+ ICUD15.etimerp = &SPC5_ETIMER_2;
ICUD15.smod_number = 2;
#endif
#if SPC5_ICU_USE_SMOD15
/* Driver initialization.*/
icuObjectInit(&ICUD16);
- ICUD16.etimerp = &ETIMER_2;
+ ICUD16.etimerp = &SPC5_ETIMER_2;
ICUD16.smod_number = 3;
#endif
#if SPC5_ICU_USE_SMOD16
/* Driver initialization.*/
icuObjectInit(&ICUD17);
- ICUD17.etimerp = &ETIMER_2;
+ ICUD17.etimerp = &SPC5_ETIMER_2;
ICUD17.smod_number = 4;
#endif
#if SPC5_ICU_USE_SMOD17
/* Driver initialization.*/
icuObjectInit(&ICUD18);
- ICUD18.etimerp = &ETIMER_2;
+ ICUD18.etimerp = &SPC5_ETIMER_2;
ICUD18.smod_number = 5;
#endif
diff --git a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h b/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h index 041eb95e9..606c91d2b 100644 --- a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h +++ b/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h @@ -475,6 +475,7 @@ /*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
+#include "etimer.h"
/**
* @brief ICU driver mode.
@@ -571,7 +572,7 @@ struct ICUDriver { /**
* @brief Pointer to the eTimerx registers block.
*/
- volatile struct ETIMER_tag *etimerp;
+ volatile struct spc5_etimer *etimerp;
/**
* @brief CCR register used for width capture.
*/
|