SPC560Dxx support added.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5847 35acf78f-673a-0410-8e92-d51de3d6d3f4

1 files changed, 0 insertions, 167 deletions

diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h
index 1f4b62572..95c4c72ab 100644
--- a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h
+++ b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h
@@ -33,173 +33,6 @@
 /* Driver constants.                                                         */

 /*===========================================================================*/

 

-/**

- * @name    MCR register definitions

- * @{

- */

-#define SPC5_MCR_MSTR                       (1U << 31)

-#define SPC5_MCR_CONT_SCKE                  (1U << 30)

-#define SPC5_MCR_DCONF_MASK                 (3U << 28)

-#define SPC5_MCR_FRZ                        (1U << 27)

-#define SPC5_MCR_MTFE                       (1U << 26)

-#define SPC5_MCR_PCSSE                      (1U << 25)

-#define SPC5_MCR_ROOE                       (1U << 24)

-#define SPC5_MCR_PCSIS7                     (1U << 23)

-#define SPC5_MCR_PCSIS6                     (1U << 22)

-#define SPC5_MCR_PCSIS5                     (1U << 21)

-#define SPC5_MCR_PCSIS4                     (1U << 20)

-#define SPC5_MCR_PCSIS3                     (1U << 19)

-#define SPC5_MCR_PCSIS2                     (1U << 18)

-#define SPC5_MCR_PCSIS1                     (1U << 17)

-#define SPC5_MCR_PCSIS0                     (1U << 16)

-#define SPC5_MCR_DOZE                       (1U << 15)

-#define SPC5_MCR_MDIS                       (1U << 14)

-#define SPC5_MCR_DIS_TXF                    (1U << 13)

-#define SPC5_MCR_DIS_RXF                    (1U << 12)

-#define SPC5_MCR_CLR_TXF                    (1U << 11)

-#define SPC5_MCR_CLR_RXF                    (1U << 10)

-#define SPC5_MCR_SMPL_PT_MASK               (3U << 8)

-#define SPC5_MCR_SMPL_PT(n)                 ((n) << 8)

-#define SPC5_MCR_FCPCS                      (1U << 2)

-#define SPC5_MCR_PES                        (1U << 1)

-#define SPC5_MCR_HALT                       (1U << 0)

-/** @} */

-

-/**

- * @name    RSER register definitions

- * @{

- */

-#define SPC5_RSER_TCF_RE                    (1U << 31)

-#define SPC5_RSER_DSITCF_RE                 (1U << 29)

-#define SPC5_RSER_EOQF_RE                   (1U << 28)

-#define SPC5_RSER_TFUF_RE                   (1U << 27)

-#define SPC5_RSER_SPITCF_RE                 (1U << 26)

-#define SPC5_RSER_TFFF_RE                   (1U << 25)

-#define SPC5_RSER_TFFF_DIRS                 (1U << 24)

-#define SPC5_RSER_DPEF_RE                   (1U << 22)

-#define SPC5_RSER_SPEF_RE                   (1U << 21)

-#define SPC5_RSER_DDIF_RE                   (1U << 20)

-#define SPC5_RSER_RFOF_RE                   (1U << 19)

-#define SPC5_RSER_RFDF_RE                   (1U << 17)

-#define SPC5_RSER_RFDF_DIRS                 (1U << 16)

-/** @} */

-

-/**

- * @name    CTAR registers definitions

- * @{

- */

-#define SPC5_CTAR_DBR                       (1U << 31)

-#define SPC5_CTAR_FMSZ_MASK                 (15U << 27)

-#define SPC5_CTAR_FMSZ(n)                   (((n) - 1) << 27)

-#define SPC5_CTAR_CPOL                      (1U << 26)

-#define SPC5_CTAR_CPHA                      (1U << 25)

-#define SPC5_CTAR_LSBFE                     (1U << 24)

-#define SPC5_CTAR_PCSSCK_MASK               (3U << 22)

-#define SPC5_CTAR_PCSSCK_PRE1               (0U << 22)

-#define SPC5_CTAR_PCSSCK_PRE3               (1U << 22)

-#define SPC5_CTAR_PCSSCK_PRE5               (2U << 22)

-#define SPC5_CTAR_PCSSCK_PRE7               (3U << 22)

-#define SPC5_CTAR_PASC_MASK                 (3U << 20)

-#define SPC5_CTAR_PASC_PRE1                 (0U << 20)

-#define SPC5_CTAR_PASC_PRE3                 (1U << 20)

-#define SPC5_CTAR_PASC_PRE5                 (2U << 20)

-#define SPC5_CTAR_PASC_PRE7                 (3U << 20)

-#define SPC5_CTAR_PDT_MASK                  (3U << 18)

-#define SPC5_CTAR_PDT_PRE1                  (0U << 18)

-#define SPC5_CTAR_PDT_PRE3                  (1U << 18)

-#define SPC5_CTAR_PDT_PRE5                  (2U << 18)

-#define SPC5_CTAR_PDT_PRE7                  (3U << 18)

-#define SPC5_CTAR_PBR_MASK                  (3U << 16)

-#define SPC5_CTAR_PBR_PRE2                  (0U << 16)

-#define SPC5_CTAR_PBR_PRE3                  (1U << 16)

-#define SPC5_CTAR_PBR_PRE5                  (2U << 16)

-#define SPC5_CTAR_PBR_PRE7                  (3U << 16)

-#define SPC5_CTAR_CSSCK_MASK                (15U << 12)

-#define SPC5_CTAR_CSSCK_DIV2                (0U << 12)

-#define SPC5_CTAR_CSSCK_DIV4                (1U << 12)

-#define SPC5_CTAR_CSSCK_DIV6                (2U << 12)

-#define SPC5_CTAR_CSSCK_DIV8                (3U << 12)

-#define SPC5_CTAR_CSSCK_DIV16               (4U << 12)

-#define SPC5_CTAR_CSSCK_DIV32               (5U << 12)

-#define SPC5_CTAR_CSSCK_DIV64               (6U << 12)

-#define SPC5_CTAR_CSSCK_DIV128              (7U << 12)

-#define SPC5_CTAR_CSSCK_DIV256              (8U << 12)

-#define SPC5_CTAR_CSSCK_DIV512              (9U << 12)

-#define SPC5_CTAR_CSSCK_DIV1024             (10U << 12)

-#define SPC5_CTAR_CSSCK_DIV2048             (11U << 12)

-#define SPC5_CTAR_CSSCK_DIV4096             (12U << 12)

-#define SPC5_CTAR_CSSCK_DIV8192             (13U << 12)

-#define SPC5_CTAR_CSSCK_DIV16384            (14U << 12)

-#define SPC5_CTAR_CSSCK_DIV32768            (15U << 12)

-#define SPC5_CTAR_ASC_MASK                  (15U << 8)

-#define SPC5_CTAR_ASC_DIV2                  (0U << 8)

-#define SPC5_CTAR_ASC_DIV4                  (1U << 8)

-#define SPC5_CTAR_ASC_DIV6                  (2U << 8)

-#define SPC5_CTAR_ASC_DIV8                  (3U << 8)

-#define SPC5_CTAR_ASC_DIV16                 (4U << 8)

-#define SPC5_CTAR_ASC_DIV32                 (5U << 8)

-#define SPC5_CTAR_ASC_DIV64                 (6U << 8)

-#define SPC5_CTAR_ASC_DIV128                (7U << 8)

-#define SPC5_CTAR_ASC_DIV256                (8U << 8)

-#define SPC5_CTAR_ASC_DIV512                (9U << 8)

-#define SPC5_CTAR_ASC_DIV1024               (10U << 8)

-#define SPC5_CTAR_ASC_DIV2048               (11U << 8)

-#define SPC5_CTAR_ASC_DIV4096               (12U << 8)

-#define SPC5_CTAR_ASC_DIV8192               (13U << 8)

-#define SPC5_CTAR_ASC_DIV16384              (14U << 8)

-#define SPC5_CTAR_ASC_DIV32768              (15U << 8)

-#define SPC5_CTAR_DT_MASK                   (15U << 4)

-#define SPC5_CTAR_DT_DIV2                   (0U << 4)

-#define SPC5_CTAR_DT_DIV4                   (1U << 4)

-#define SPC5_CTAR_DT_DIV6                   (2U << 4)

-#define SPC5_CTAR_DT_DIV8                   (3U << 4)

-#define SPC5_CTAR_DT_DIV16                  (4U << 4)

-#define SPC5_CTAR_DT_DIV32                  (5U << 4)

-#define SPC5_CTAR_DT_DIV64                  (6U << 4)

-#define SPC5_CTAR_DT_DIV128                 (7U << 4)

-#define SPC5_CTAR_DT_DIV256                 (8U << 4)

-#define SPC5_CTAR_DT_DIV512                 (9U << 4)

-#define SPC5_CTAR_DT_DIV1024                (10U << 4)

-#define SPC5_CTAR_DT_DIV2048                (11U << 4)

-#define SPC5_CTAR_DT_DIV4096                (12U << 4)

-#define SPC5_CTAR_DT_DIV8192                (13U << 4)

-#define SPC5_CTAR_DT_DIV16384               (14U << 4)

-#define SPC5_CTAR_DT_DIV32768               (15U << 4)

-#define SPC5_CTAR_BR_MASK                   (15U << 0)

-#define SPC5_CTAR_BR_DIV2                   (0U << 0)

-#define SPC5_CTAR_BR_DIV4                   (1U << 0)

-#define SPC5_CTAR_BR_DIV6                   (2U << 0)

-#define SPC5_CTAR_BR_DIV8                   (3U << 0)

-#define SPC5_CTAR_BR_DIV16                  (4U << 0)

-#define SPC5_CTAR_BR_DIV32                  (5U << 0)

-#define SPC5_CTAR_BR_DIV64                  (6U << 0)

-#define SPC5_CTAR_BR_DIV128                 (7U << 0)

-#define SPC5_CTAR_BR_DIV256                 (8U << 0)

-#define SPC5_CTAR_BR_DIV512                 (9U << 0)

-#define SPC5_CTAR_BR_DIV1024                (10U << 0)

-#define SPC5_CTAR_BR_DIV2048                (11U << 0)

-#define SPC5_CTAR_BR_DIV4096                (12U << 0)

-#define SPC5_CTAR_BR_DIV8192                (13U << 0)

-#define SPC5_CTAR_BR_DIV16384               (14U << 0)

-#define SPC5_CTAR_BR_DIV32768               (15U << 0)

-/** @} */

-

-/**

- * @name    PUSHR register definitions

- * @{

- */

-#define SPC5_PUSHR_CONT                     (1U << 31)

-#define SPC5_PUSHR_CTAS_MASK                (3U << 28)

-#define SPC5_PUSHR_CTAS(n)                  ((n) << 29)

-#define SPC5_PUSHR_EOQ                      (1U << 27)

-#define SPC5_PUSHR_CTCNT                    (1U << 26)

-#define SPC5_PUSHR_MASC                     (1U << 25)

-#define SPC5_PUSHR_MCSC                     (1U << 24)

-#define SPC5_PUSHR_PCS_MASK                 (255U << 16)

-#define SPC5_PUSHR_PCS(n)                   ((1U << (n)) << 16)

-#define SPC5_PUSHR_TXDATA_MASK              (0xFFFFU << 0)

-/** @} */

-

 /*===========================================================================*/

 /* Driver pre-compile time settings.                                         */

 /*===========================================================================*/