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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-05-28 09:51:52 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-05-28 09:51:52 +0000 |
| commit | 036f60f497d109038765567bad5b9dbe503e8326 (patch) | |
| tree | 3aaf9e89e9c2ef4bb44283ec7a5eaa98877c5e1b /os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h | |
| parent | c16062e326d35c438abf719e2371a3a55f868b71 (diff) | |
| download | ChibiOS-036f60f497d109038765567bad5b9dbe503e8326.tar.gz ChibiOS-036f60f497d109038765567bad5b9dbe503e8326.tar.bz2 ChibiOS-036f60f497d109038765567bad5b9dbe503e8326.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5765 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h')
| -rw-r--r-- | os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h index f16667f90..5be3ad3fa 100644 --- a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h +++ b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h @@ -301,6 +301,34 @@ #if !defined(SPC5_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
#endif
+
+/**
+ * @brief DSPI0 DMA priority.
+ */
+#if !defined(SPC5_SPI_DSPI0_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI0_IRQ_PRIO 10
+#endif
+
+/**
+ * @brief DSPI1 DMA priority.
+ */
+#if !defined(SPC5_SPI_DSPI1_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI1_IRQ_PRIO 10
+#endif
+
+/**
+ * @brief DSPI2 DMA priority.
+ */
+#if !defined(SPC5_SPI_DSPI2_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI2_IRQ_PRIO 10
+#endif
+
+/**
+ * @brief DSPI3 DMA priority.
+ */
+#if !defined(SPC5_SPI_DSPI3_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI3_IRQ_PRIO 10
+#endif
/** @} */
/*===========================================================================*/
@@ -433,6 +461,10 @@ struct SPIDriver { */
edma_channel_t rx_channel;
/**
+ * @brief Last frame of a transmission sequence.
+ */
+ uint32_t tx_last;
+ /**
* @brief TX intermediate buffer.
* @note This field is written by the TX1 DMA channel and read by the
* TX2 DMA channel.
|