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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-06-17 07:01:48 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-06-17 07:01:48 +0000 |
| commit | 1a76b0008ff6dabc22e1f7b07dcee8f1c38c7b2c (patch) | |
| tree | 50fa62b7a6cc4d11bcaed5f68bdd3e91c5172f65 /os/hal/platforms/SPC564Axx | |
| parent | e02105736dcf810de5855bc5a5fd40bf7727c852 (diff) | |
| download | ChibiOS-1a76b0008ff6dabc22e1f7b07dcee8f1c38c7b2c.tar.gz ChibiOS-1a76b0008ff6dabc22e1f7b07dcee8f1c38c7b2c.tar.bz2 ChibiOS-1a76b0008ff6dabc22e1f7b07dcee8f1c38c7b2c.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5863 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/SPC564Axx')
| -rw-r--r-- | os/hal/platforms/SPC564Axx/spc564a_registry.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/os/hal/platforms/SPC564Axx/spc564a_registry.h b/os/hal/platforms/SPC564Axx/spc564a_registry.h index ec584abdf..42ba13741 100644 --- a/os/hal/platforms/SPC564Axx/spc564a_registry.h +++ b/os/hal/platforms/SPC564Axx/spc564a_registry.h @@ -54,15 +54,6 @@ #define SPC5_HAS_DSPI3 TRUE
#define SPC5_HAS_DSPI4 FALSE
#define SPC5_DSPI_FIFO_DEPTH 16
-#define SPC5_DSPI1_TX1_DMA_CH_ID 12
-#define SPC5_DSPI1_TX2_DMA_CH_ID 24
-#define SPC5_DSPI1_RX_DMA_CH_ID 13
-#define SPC5_DSPI2_TX1_DMA_CH_ID 14
-#define SPC5_DSPI2_TX2_DMA_CH_ID 25
-#define SPC5_DSPI2_RX_DMA_CH_ID 15
-#define SPC5_DSPI3_TX1_DMA_CH_ID 16
-#define SPC5_DSPI3_TX2_DMA_CH_ID 26
-#define SPC5_DSPI3_RX_DMA_CH_ID 17
#define SPC5_DSPI1_EOQF_HANDLER vector132
#define SPC5_DSPI1_EOQF_NUMBER 132
#define SPC5_DSPI1_TFFF_HANDLER vector133
@@ -86,6 +77,15 @@ #define SPC5_HAS_EDMA TRUE
#define SPC5_EDMA_NCHANNELS 64
#define SPC5_EDMA_HAS_MUX FALSE
+#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 12
+#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 24
+#define SPC5_SPI_DSPI1_RX_DMA_CH_ID 13
+#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID 14
+#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID 25
+#define SPC5_SPI_DSPI2_RX_DMA_CH_ID 15
+#define SPC5_SPI_DSPI3_TX1_DMA_CH_ID 16
+#define SPC5_SPI_DSPI3_TX2_DMA_CH_ID 26
+#define SPC5_SPI_DSPI3_RX_DMA_CH_ID 17
/* eQADC attributes.*/
#define SPC5_HAS_EQADC TRUE
|