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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-04-29 09:17:13 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-04-29 09:17:13 +0000 |
| commit | 9bbb4ac554e3a32d5d9ffad9b4901e2e8ddb99ed (patch) | |
| tree | d3c5dffc446bb6e962a0203a37928c732b088e45 /os/hal/platforms/SPC564Axx/hal_lld.c | |
| parent | 406621d200096fd2881f66ba16ffbc896308de4f (diff) | |
| download | ChibiOS-9bbb4ac554e3a32d5d9ffad9b4901e2e8ddb99ed.tar.gz ChibiOS-9bbb4ac554e3a32d5d9ffad9b4901e2e8ddb99ed.tar.bz2 ChibiOS-9bbb4ac554e3a32d5d9ffad9b4901e2e8ddb99ed.zip | |
Added wait states to the RAM accesses as specified on the DS.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5643 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/SPC564Axx/hal_lld.c')
| -rw-r--r-- | os/hal/platforms/SPC564Axx/hal_lld.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/os/hal/platforms/SPC564Axx/hal_lld.c b/os/hal/platforms/SPC564Axx/hal_lld.c index 2115116c4..c6c67ba31 100644 --- a/os/hal/platforms/SPC564Axx/hal_lld.c +++ b/os/hal/platforms/SPC564Axx/hal_lld.c @@ -53,12 +53,6 @@ void hal_lld_init(void) {
uint32_t n;
- /* FLASH wait states and prefetching setup.*/
- FLASH_A.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
- FLASH_A.BIUCR2.R = 0;
- FLASH_B.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
- FLASH_B.BIUCR2.R = 0;
-
/* The SRAM is parked on the load/store port, for some unknown reason it
is defaulted on the instructions port and this kills performance.*/
XBAR.SGPCR2.B.PARK = 1; /* RAM slave on load/store port.*/
@@ -110,6 +104,13 @@ void hal_lld_init(void) { */
void spc_clock_init(void) {
+ /* Setting up RAM/Flash wait states and the prefetching bits.*/
+ ECSM.MUDCR.R = SPC5_RAM_WS;
+ FLASH_A.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
+ FLASH_A.BIUCR2.R = 0;
+ FLASH_B.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
+ FLASH_B.BIUCR2.R = 0;
+
#if !SPC5_NO_INIT
/* PLL activation.*/
FMPLL.ESYNCR1.B.EMODE = 1; /* Enhanced mode on. */
|