diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-10-02 12:41:17 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-10-02 12:41:17 +0000 |
| commit | 8579b5559cb2501dd8d0f56ab42f9209a3860c58 (patch) | |
| tree | 76567c95a9f1f58cee7264fdc4dbb447b81ee6cc /os/hal/platforms/SPC560Pxx | |
| parent | 60cd6f958b431b1f8268302b0636fffb7a71c538 (diff) | |
| download | ChibiOS-8579b5559cb2501dd8d0f56ab42f9209a3860c58.tar.gz ChibiOS-8579b5559cb2501dd8d0f56ab42f9209a3860c58.tar.bz2 ChibiOS-8579b5559cb2501dd8d0f56ab42f9209a3860c58.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4731 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/SPC560Pxx')
| -rw-r--r-- | os/hal/platforms/SPC560Pxx/hal_lld.c | 20 | ||||
| -rw-r--r-- | os/hal/platforms/SPC560Pxx/hal_lld.h | 31 |
2 files changed, 35 insertions, 16 deletions
diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.c b/os/hal/platforms/SPC560Pxx/hal_lld.c index 822e75cb2..de1467e97 100644 --- a/os/hal/platforms/SPC560Pxx/hal_lld.c +++ b/os/hal/platforms/SPC560Pxx/hal_lld.c @@ -92,7 +92,8 @@ void hal_lld_init(void) { to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
modes.*/
INTC.PSR[127].R = SPC5_PIT3_IRQ_PRIORITY;
- ME.PCTL[92].R = SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2);
+ halSPC560PSetPeripheralClockMode(92,
+ SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
reg = halSPC560PGetSystemClock() / CH_FREQUENCY - 1;
PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */
PIT.CH[3].LDVAL.R = reg;
@@ -207,6 +208,23 @@ bool_t halSPC560PSetRunMode(spc560prunmode_t mode) { return CH_SUCCESS;
}
+/**
+ * @brief Changes the clock mode of a peripheral.
+ *
+ * @param[in] n index of the @p PCTL register
+ * @param[in] pctl new value for the @p PCTL register
+ *
+ * @notapi
+ */
+void halSPC560PSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
+ uint32_t mode;
+
+ ME.PCTL[n].R = pctl;
+ mode = ME.MCTL.B.TARGET_MODE;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
+}
+
#if !SPC5_NO_INIT || defined(__DOXYGEN__)
/**
* @brief Returns the system clock under the current run mode.
diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.h b/os/hal/platforms/SPC560Pxx/hal_lld.h index f02194c2e..fcd94fd9e 100644 --- a/os/hal/platforms/SPC560Pxx/hal_lld.h +++ b/os/hal/platforms/SPC560Pxx/hal_lld.h @@ -416,26 +416,26 @@ /**
* @brief Peripheral mode 0 (run mode).
- * @note Do not change this setting, it is expected to be the "always run"
+ * @note Do not change this setting, it is expected to be the "never run"
* mode.
*/
#if !defined(SPC5_ME_RUN_PC0_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC0_BITS (SPC5_ME_RUN_PC_TEST | \
- SPC5_ME_RUN_PC_SAFE | \
- SPC5_ME_RUN_PC_DRUN | \
- SPC5_ME_RUN_PC_RUN0 | \
- SPC5_ME_RUN_PC_RUN1 | \
- SPC5_ME_RUN_PC_RUN2 | \
- SPC5_ME_RUN_PC_RUN3)
+#define SPC5_ME_RUN_PC0_BITS 0
#endif
/**
* @brief Peripheral mode 1 (run mode).
- * @note Do not change this setting, it is expected to be the "never run"
+ * @note Do not change this setting, it is expected to be the "always run"
* mode.
*/
#if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_RUN_PC1_BITS 0
+#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \
+ SPC5_ME_RUN_PC_SAFE | \
+ SPC5_ME_RUN_PC_DRUN | \
+ SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
#endif
/**
@@ -508,21 +508,21 @@ /**
* @brief Peripheral mode 0 (low power mode).
- * @note Do not change this setting, it is expected to be the "always run"
+ * @note Do not change this setting, it is expected to be the "never run"
* mode.
*/
#if !defined(SPC5_ME_LP_PC0_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC0_BITS (SPC5_ME_LP_PC_HALT0 | \
- SPC5_ME_LP_PC_STOP0)
+#define SPC5_ME_LP_PC0_BITS 0
#endif
/**
* @brief Peripheral mode 1 (low power mode).
- * @note Do not change this setting, it is expected to be the "never run"
+ * @note Do not change this setting, it is expected to be the "always run"
* mode.
*/
#if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__)
-#define SPC5_ME_LP_PC1_BITS 0
+#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
#endif
/**
@@ -720,6 +720,7 @@ extern "C" { void hal_lld_init(void);
void spc560p_clock_init(void);
bool_t halSPC560PSetRunMode(spc560prunmode_t mode);
+ void halSPC560PSetPeripheralClockMode(uint32_t n, uint32_t pctl);
#if !SPC5_NO_INIT
uint32_t halSPC560PGetSystemClock(void);
#endif
|