Systick works now, better SPC560P ME support.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4707 35acf78f-673a-0410-8e92-d51de3d6d3f4

3 files changed, 317 insertions, 7 deletions

diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.c b/os/hal/platforms/SPC560Pxx/hal_lld.c
index 3992aba8b..d84203e81 100644
--- a/os/hal/platforms/SPC560Pxx/hal_lld.c
+++ b/os/hal/platforms/SPC560Pxx/hal_lld.c
@@ -45,6 +45,25 @@
 /* Driver interrupt handlers.                                                */

 /*===========================================================================*/

 

+/**

+ * @brief   PIT channel 3 interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(vector127) {

+

+  CH_IRQ_PROLOGUE();

+

+  chSysLockFromIsr();

+  chSysTimerHandlerI();

+  chSysUnlockFromIsr();

+

+  /* Resets the PIT channel 3 IRQ flag.*/

+  PIT.CH[3].TFLG.R = 1;

+

+  CH_IRQ_EPILOGUE();

+}

+

 /*===========================================================================*/

 /* Driver exported functions.                                                */

 /*===========================================================================*/

@@ -55,11 +74,31 @@
  * @notapi

  */

 void hal_lld_init(void) {

+  extern void _vectors(void);

+  uint32_t reg;

 

   /* The system is switched to the RUN0 mode, the default for normal

      operations.*/

   if (halSPC560PSetRunMode(SPC560P_RUNMODE_RUN0) == CH_FAILED)

     chSysHalt();

+

+  /* INTC initialization, software vector mode, 4 bytes vectors, starting

+     at priority 0.*/

+  INTC.MCR.R        = 0;

+  INTC.CPR.R        = 0;

+  INTC.IACKR.R      = (uint32_t)_vectors;

+

+  /* PIT channel 3 initialization for Kernel ticks, the PIT is configured

+     to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other

+     modes.*/

+  INTC.PSR[127].R   = SPC560P_PIT3_IRQ_PRIORITY;

+  ME.PCTL[92].R     = SPC560P_ME_PCTL_RUN(2) | SPC560P_ME_PCTL_LP(2);

+  reg = halSPC560PGetSystemClock() / CH_FREQUENCY - 1;

+  PIT.PITMCR.R      = 1;        /* PIT clock enabled, stop while debugging. */

+  PIT.CH[3].LDVAL.R = reg;

+  PIT.CH[3].CVAL.R  = reg;

+  PIT.CH[3].TFLG.R  = 1;        /* Interrupt flag cleared.                  */

+  PIT.CH[3].TCTRL.R = 3;        /* Timer active, interrupt enabled.         */

 }

 

 /**

@@ -100,12 +139,30 @@ void spc560p_clock_init(void) {
   ME.SAFE.R         = SPC560P_ME_SAFE_MC_BITS;  /* SAFE run mode.           */

   ME.DRUN.R         = SPC560P_ME_DRUN_MC_BITS;  /* DRUN run mode.           */

   ME.RUN[0].R       = SPC560P_ME_RUN0_MC_BITS;  /* RUN0 run mode.           */

-  ME.RUN[1].R       = SPC560P_ME_RUN1_MC_BITS;  /* RUN0 run mode.           */

-  ME.RUN[2].R       = SPC560P_ME_RUN2_MC_BITS;  /* RUN0 run mode.           */

+  ME.RUN[1].R       = SPC560P_ME_RUN1_MC_BITS;  /* RUN1 run mode.           */

+  ME.RUN[2].R       = SPC560P_ME_RUN2_MC_BITS;  /* RUN2 run mode.           */

   ME.RUN[3].R       = SPC560P_ME_RUN3_MC_BITS;  /* RUN0 run mode.           */

   ME.HALT0.R        = SPC560P_ME_HALT0_MC_BITS; /* HALT0 run mode.          */

   ME.STOP0.R        = SPC560P_ME_STOP0_MC_BITS; /* STOP0 run mode.          */

 

+  /* Peripherals run and low power modes initialization.*/

+  ME.RUNPC[0].R     = SPC560P_ME_RUN_PC0_BITS;

+  ME.RUNPC[1].R     = SPC560P_ME_RUN_PC1_BITS;

+  ME.RUNPC[2].R     = SPC560P_ME_RUN_PC2_BITS;

+  ME.RUNPC[3].R     = SPC560P_ME_RUN_PC3_BITS;

+  ME.RUNPC[4].R     = SPC560P_ME_RUN_PC4_BITS;

+  ME.RUNPC[5].R     = SPC560P_ME_RUN_PC5_BITS;

+  ME.RUNPC[6].R     = SPC560P_ME_RUN_PC6_BITS;

+  ME.RUNPC[7].R     = SPC560P_ME_RUN_PC7_BITS;

+  ME.LPPC[0].R      = SPC560P_ME_LP_PC0_BITS;

+  ME.LPPC[1].R      = SPC560P_ME_LP_PC1_BITS;

+  ME.LPPC[2].R      = SPC560P_ME_LP_PC2_BITS;

+  ME.LPPC[3].R      = SPC560P_ME_LP_PC3_BITS;

+  ME.LPPC[4].R      = SPC560P_ME_LP_PC4_BITS;

+  ME.LPPC[5].R      = SPC560P_ME_LP_PC5_BITS;

+  ME.LPPC[6].R      = SPC560P_ME_LP_PC6_BITS;

+  ME.LPPC[7].R      = SPC560P_ME_LP_PC7_BITS;

+

   /* Switches again to DRUN mode (current mode) in order to update the

      settings.*/

   if (halSPC560PSetRunMode(SPC560P_RUNMODE_DRUN) == CH_FAILED)

@@ -116,8 +173,14 @@ void spc560p_clock_init(void) {
 

 /**

  * @brief   Switches the system to the specified run mode.

+ *

+ * @param[in] mode      one of the possible run modes

+ *

+ * @return              The operation status.

+ * @retval CH_SUCCESS   if the switch operation has been completed.

+ * @retval CH_FAILED    if the switch operation failed.

  */

-bool_t  halSPC560PSetRunMode(spc560prunmode_t mode) {

+bool_t halSPC560PSetRunMode(spc560prunmode_t mode) {

 

   /* Starts a transition process.*/

   ME.MCTL.R = SPC560P_ME_MCTL_MODE(mode) | SPC560P_ME_MCTL_KEY;

@@ -133,9 +196,34 @@ bool_t  halSPC560PSetRunMode(spc560prunmode_t mode) {
 

   /* Verifies that the mode has been effectively switched.*/

   if (ME.GS.B.S_CURRENTMODE != mode)

-    return TRUE;

+    return CH_FAILED;

 

-  return FALSE;

+  return CH_SUCCESS;

 }

 

+#if !SPC560P_NO_INIT || defined(__DOXYGEN__)

+/**

+ * @brief   Returns the system clock under the current run mode.

+ *

+ * @return              The system clock in Hertz.

+ */

+uint32_t halSPC560PGetSystemClock(void) {

+  uint32_t sysclk;

+

+  sysclk = ME.GS.B.S_SYSCLK;

+  switch (sysclk) {

+  case SPC560P_ME_GS_SYSCLK_IRC:

+    return SPC560P_IRC_CLK;

+  case SPC560P_ME_GS_SYSCLK_XOSC:

+    return SPC560P_XOSC_CLK;

+  case SPC560P_ME_GS_SYSCLK_FMPLL0:

+    return SPC560P_FMPLL0_CLK;

+  case SPC560P_ME_GS_SYSCLK_FMPLL1:

+    return SPC560P_FMPLL1_CLK;

+  default:

+    return 0;

+  }

+}

+#endif /* !SPC560P_NO_INIT */

+

 /** @} */

diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.h b/os/hal/platforms/SPC560Pxx/hal_lld.h
index 706b7f5c9..f9c1e099c 100644
--- a/os/hal/platforms/SPC560Pxx/hal_lld.h
+++ b/os/hal/platforms/SPC560Pxx/hal_lld.h
@@ -120,6 +120,17 @@
 /** @} */

 

 /**

+ * @name    ME_GS register bits definitions

+ * @{

+ */

+#define SPC560P_ME_GS_SYSCLK_MASK   (15U << 0)

+#define SPC560P_ME_GS_SYSCLK_IRC    (0U << 0)

+#define SPC560P_ME_GS_SYSCLK_XOSC   (2U << 0)

+#define SPC560P_ME_GS_SYSCLK_FMPLL0 (4U << 0)

+#define SPC560P_ME_GS_SYSCLK_FMPLL1 (5U << 0)

+/** @} */

+

+/**

  * @name    ME_ME register bits definitions

  * @{

  */

@@ -174,6 +185,38 @@
 #define SPC560P_ME_MCTL_MODE(n)     ((n) << 28)

 /** @} */

 

+/**

+ * @name    ME_RUN_PCx registers bits definitions

+ * @{

+ */

+#define SPC560P_ME_RUN_PC_TEST      (1U << 1)

+#define SPC560P_ME_RUN_PC_SAFE      (1U << 2)

+#define SPC560P_ME_RUN_PC_DRUN      (1U << 3)

+#define SPC560P_ME_RUN_PC_RUN0      (1U << 4)

+#define SPC560P_ME_RUN_PC_RUN1      (1U << 5)

+#define SPC560P_ME_RUN_PC_RUN2      (1U << 6)

+#define SPC560P_ME_RUN_PC_RUN3      (1U << 7)

+/** @} */

+

+/**

+ * @name    ME_LP_PCx registers bits definitions

+ * @{

+ */

+#define SPC560P_ME_LP_PC_HALT0      (1U << 8)

+#define SPC560P_ME_LP_PC_STOP0      (1U << 10)

+/** @} */

+

+/**

+ * @name    ME_PCTL registers bits definitions

+ * @{

+ */

+#define SPC560P_ME_PCTL_RUN_MASK    (7U << 0)

+#define SPC560P_ME_PCTL_RUN(n)      ((n) << 0)

+#define SPC560P_ME_PCTL_LP_MASK     (7U << 3)

+#define SPC560P_ME_PCTL_LP(n)       ((n) << 3)

+#define SPC560P_ME_PCTL_DBG         (1U << 6)

+/** @} */

+

 /*===========================================================================*/

 /* Driver pre-compile time settings.                                         */

 /*===========================================================================*/

@@ -369,6 +412,180 @@
                                      SPC560P_ME_MC_MVRON)

 #endif

 

+/**

+ * @brief   Peripheral mode 0 (run mode).

+ * @note    Do not change this setting, it is expected to be the "always run"

+ *          mode.

+ */

+#if !defined(SPC560P_ME_RUN_PC0_BITS) || defined(__DOXYGEN__)

+#define SPC560P_ME_RUN_PC0_BITS     (SPC560P_ME_RUN_PC_TEST |               \

+                                     SPC560P_ME_RUN_PC_SAFE |               \

+                                     SPC560P_ME_RUN_PC_DRUN |               \

+                                     SPC560P_ME_RUN_PC_RUN0 |               \

+                                     SPC560P_ME_RUN_PC_RUN1 |               \

+                                     SPC560P_ME_RUN_PC_RUN2 |               \

+                                     SPC560P_ME_RUN_PC_RUN3)

+#endif

+

+/**

+ * @brief   Peripheral mode 1 (run mode).

+ * @note    Do not change this setting, it is expected to be the "never run"

+ *          mode.

+ */

+#if !defined(SPC560P_ME_RUN_PC1_BITS) || defined(__DOXYGEN__)

+#define SPC560P_ME_RUN_PC1_BITS     0

+#endif

+

+/**

+ * @brief   Peripheral mode 2 (run mode).

+ * @note    Do not change this setting, it is expected to be the "only during

+ *          normal run" mode.

+ */

+#if !defined(SPC560P_ME_RUN_PC2_BITS) || defined(__DOXYGEN__)

+#define SPC560P_ME_RUN_PC2_BITS     (SPC560P_ME_RUN_PC_DRUN |               \

+                                     SPC560P_ME_RUN_PC_RUN0 |               \

+                                     SPC560P_ME_RUN_PC_RUN1 |               \

+                                     SPC560P_ME_RUN_PC_RUN2 |               \

+                                     SPC560P_ME_RUN_PC_RUN3)

+#endif

+

+/**

+ * @brief   Peripheral mode 3 (run mode).

+ * @note    Not defined, available to application-specific modes.

+ */

+#if !defined(SPC560P_ME_RUN_PC3_BITS) || defined(__DOXYGEN__)

+#define SPC560P_ME_RUN_PC3_BITS     (SPC560P_ME_RUN_PC_RUN0 |               \

+                                     SPC560P_ME_RUN_PC_RUN1 |               \

+                                     SPC560P_ME_RUN_PC_RUN2 |               \

+                                     SPC560P_ME_RUN_PC_RUN3)

+#endif

+

+/**

+ * @brief   Peripheral mode 4 (run mode).

+ * @note    Not defined, available to application-specific modes.

+ */

+#if !defined(SPC560P_ME_RUN_PC4_BITS) || defined(__DOXYGEN__)

+#define SPC560P_ME_RUN_PC4_BITS     (SPC560P_ME_RUN_PC_RUN0 |               \

+                                     SPC560P_ME_RUN_PC_RUN1 |               \

+                                     SPC560P_ME_RUN_PC_RUN2 |               \

+                                     SPC560P_ME_RUN_PC_RUN3)

+#endif

+

+/**

+ * @brief   Peripheral mode 5 (run mode).

+ * @note    Not defined, available to application-specific modes.

+ */

+#if !defined(SPC560P_ME_RUN_PC5_BITS) || defined(__DOXYGEN__)

+#define SPC560P_ME_RUN_PC5_BITS     (SPC560P_ME_RUN_PC_RUN0 |               \

+                                     SPC560P_ME_RUN_PC_RUN1 |               \

+                                     SPC560P_ME_RUN_PC_RUN2 |               \

+                                     SPC560P_ME_RUN_PC_RUN3)

+#endif

+

+/**

+ * @brief   Peripheral mode 6 (run mode).

+ * @note    Not defined, available to application-specific modes.

+ */

+#if !defined(SPC560P_ME_RUN_PC6_BITS) || defined(__DOXYGEN__)

+#define SPC560P_ME_RUN_PC6_BITS     (SPC560P_ME_RUN_PC_RUN0 |               \

+                                     SPC560P_ME_RUN_PC_RUN1 |               \

+                                     SPC560P_ME_RUN_PC_RUN2 |               \

+                                     SPC560P_ME_RUN_PC_RUN3)

+#endif

+

+/**

+ * @brief   Peripheral mode 7 (run mode).

+ * @note    Not defined, available to application-specific modes.

+ */

+#if !defined(SPC560P_ME_RUN_PC7_BITS) || defined(__DOXYGEN__)

+#define SPC560P_ME_RUN_PC7_BITS     (SPC560P_ME_RUN_PC_RUN0 |               \

+                                     SPC560P_ME_RUN_PC_RUN1 |               \

+                                     SPC560P_ME_RUN_PC_RUN2 |               \

+                                     SPC560P_ME_RUN_PC_RUN3)

+#endif

+

+/**

+ * @brief   Peripheral mode 0 (low power mode).

+ * @note    Do not change this setting, it is expected to be the "always run"

+ *          mode.

+ */

+#if !defined(SPC560P_ME_LP_PC0_BITS) || defined(__DOXYGEN__)

+#define SPC560P_ME_LP_PC0_BITS      (SPC560P_ME_LP_PC_HALT0 |               \

+                                     SPC560P_ME_LP_PC_STOP0)

+#endif

+

+/**

+ * @brief   Peripheral mode 1 (low power mode).

+ * @note    Do not change this setting, it is expected to be the "never run"

+ *          mode.

+ */

+#if !defined(SPC560P_ME_LP_PC1_BITS) || defined(__DOXYGEN__)

+#define SPC560P_ME_LP_PC1_BITS      0

+#endif

+

+/**

+ * @brief   Peripheral mode 2 (low power mode).

+ * @note    Do not change this setting, it is expected to be the "halt only"

+ *          mode.

+ */

+#if !defined(SPC560P_ME_LP_PC2_BITS) || defined(__DOXYGEN__)

+#define SPC560P_ME_LP_PC2_BITS      (SPC560P_ME_LP_PC_HALT0)

+#endif

+

+/**

+ * @brief   Peripheral mode 3 (low power mode).

+ * @note    Do not change this setting, it is expected to be the "stop only"

+ *          mode.

+ */

+#if !defined(SPC560P_ME_LP_PC3_BITS) || defined(__DOXYGEN__)

+#define SPC560P_ME_LP_PC3_BITS      (SPC560P_ME_LP_PC_STOP0)

+#endif

+

+/**

+ * @brief   Peripheral mode 4 (low power mode).

+ * @note    Not defined, available to application-specific modes.

+ */

+#if !defined(SPC560P_ME_LP_PC4_BITS) || defined(__DOXYGEN__)

+#define SPC560P_ME_LP_PC4_BITS      (SPC560P_ME_LP_PC_HALT0 |               \

+                                     SPC560P_ME_LP_PC_STOP0)

+#endif

+

+/**

+ * @brief   Peripheral mode 5 (low power mode).

+ * @note    Not defined, available to application-specific modes.

+ */

+#if !defined(SPC560P_ME_LP_PC5_BITS) || defined(__DOXYGEN__)

+#define SPC560P_ME_LP_PC5_BITS      (SPC560P_ME_LP_PC_HALT0 |               \

+                                     SPC560P_ME_LP_PC_STOP0)

+#endif

+

+/**

+ * @brief   Peripheral mode 6 (low power mode).

+ * @note    Not defined, available to application-specific modes.

+ */

+#if !defined(SPC560P_ME_LP_PC6_BITS) || defined(__DOXYGEN__)

+#define SPC560P_ME_LP_PC6_BITS      (SPC560P_ME_LP_PC_HALT0 |               \

+                                     SPC560P_ME_LP_PC_STOP0)

+#endif

+

+/**

+ * @brief   Peripheral mode 7 (low power mode).

+ * @note    Not defined, available to application-specific modes.

+ */

+#if !defined(SPC560P_ME_LP_PC7_BITS) || defined(__DOXYGEN__)

+#define SPC560P_ME_LP_PC7_BITS      (SPC560P_ME_LP_PC_HALT0 |               \

+                                     SPC560P_ME_LP_PC_STOP0)

+#endif

+

+/**

+ * @brief   PIT channel 3 IRQ priority.

+ * @note    This PIT channel is allocated permanently for system tick

+ *          generation.

+ */

+#if !defined(SPC560P_PIT3_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define SPC560P_PIT3_IRQ_PRIORITY   4

+#endif

+

 /*===========================================================================*/

 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

@@ -501,6 +718,9 @@ extern "C" {
   void hal_lld_init(void);

   void spc560p_clock_init(void);

   bool_t  halSPC560PSetRunMode(spc560prunmode_t mode);

+#if !SPC560P_NO_INIT

+uint32_t halSPC560PGetSystemClock(void);

+#endif

 #ifdef __cplusplus

 }

 #endif

diff --git a/os/hal/platforms/SPC560Pxx/platform.mk b/os/hal/platforms/SPC560Pxx/platform.mk
index 93deebba8..847e7e821 100644
--- a/os/hal/platforms/SPC560Pxx/platform.mk
+++ b/os/hal/platforms/SPC560Pxx/platform.mk
@@ -1,5 +1,7 @@
 # List of all the SPC560Pxx platform files.

-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560Pxx/hal_lld.c

+PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560Pxx/hal_lld.c \

+              ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c

 

 # Required include directories

-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC560Pxx

+PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC560Pxx \

+              ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1