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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-02-19 10:35:27 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-02-19 10:35:27 +0000 |
| commit | dda9064f21a37434dbdcbc8db26ceabc2f7a37df (patch) | |
| tree | 9483effba36af11f422c3cca86b4f45168e02fe8 /os/hal/platforms/SPC560BCxx | |
| parent | 759ce419bbadb3d284ba62a68b94a77ea8a93744 (diff) | |
| download | ChibiOS-dda9064f21a37434dbdcbc8db26ceabc2f7a37df.tar.gz ChibiOS-dda9064f21a37434dbdcbc8db26ceabc2f7a37df.tar.bz2 ChibiOS-dda9064f21a37434dbdcbc8db26ceabc2f7a37df.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5259 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/SPC560BCxx')
| -rw-r--r-- | os/hal/platforms/SPC560BCxx/hal_lld.h | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/os/hal/platforms/SPC560BCxx/hal_lld.h b/os/hal/platforms/SPC560BCxx/hal_lld.h index d92fb53bf..a0294a731 100644 --- a/os/hal/platforms/SPC560BCxx/hal_lld.h +++ b/os/hal/platforms/SPC560BCxx/hal_lld.h @@ -287,24 +287,24 @@ * @brief Peripherals Set 1 clock divider value.
* @note Zero means disabled clock.
*/
-#if !defined(SPC5_PHERIPERAL1_CLK_DIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_PHERIPERAL1_CLK_DIV_VALUE 2
+#if !defined(SPC5_PERIPHERAL1_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 2
#endif
/**
* @brief Peripherals Set 2 clock divider value.
* @note Zero means disabled clock.
*/
-#if !defined(SPC5_PHERIPERAL2_CLK_DIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_PHERIPERAL2_CLK_DIV_VALUE 2
+#if !defined(SPC5_PERIPHERAL2_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL2_CLK_DIV_VALUE 2
#endif
/**
* @brief Peripherals Set 3 clock divider value.
* @note Zero means disabled clock.
*/
-#if !defined(SPC5_PHERIPERAL3_CLK_DIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_PHERIPERAL3_CLK_DIV_VALUE 2
+#if !defined(SPC5_PERIPHERAL3_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2
#endif
/**
@@ -703,33 +703,33 @@ #endif
/* Check on the peripherals set 1 clock divider settings.*/
-#if SPC5_PHERIPERAL1_CLK_DIV_VALUE == 0
+#if SPC5_PERIPHERAL1_CLK_DIV_VALUE == 0
#define SPC5_CGM_SC_DC0 0
-#elif (SPC5_PHERIPERAL1_CLK_DIV_VALUE >= 1) && \
- (SPC5_PHERIPERAL1_CLK_DIV_VALUE <= 16)
-#define SPC5_CGM_SC_DC0 (0x80 | (SPC5_PHERIPERAL1_CLK_DIV_VALUE - 1))
+#elif (SPC5_PERIPHERAL1_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PERIPHERAL1_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC0 (0x80 | (SPC5_PERIPHERAL1_CLK_DIV_VALUE - 1))
#else
-#error "invalid SPC5_PHERIPERAL1_CLK_DIV_VALUE value specified"
+#error "invalid SPC5_PERIPHERAL1_CLK_DIV_VALUE value specified"
#endif
/* Check on the peripherals set 2 clock divider settings.*/
-#if SPC5_PHERIPERAL2_CLK_DIV_VALUE == 0
+#if SPC5_PERIPHERAL2_CLK_DIV_VALUE == 0
#define SPC5_CGM_SC_DC1 0
-#elif (SPC5_PHERIPERAL2_CLK_DIV_VALUE >= 1) && \
- (SPC5_PHERIPERAL2_CLK_DIV_VALUE <= 16)
-#define SPC5_CGM_SC_DC1 (0x80 | (SPC5_PHERIPERAL2_CLK_DIV_VALUE - 1))
+#elif (SPC5_PERIPHERAL2_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PERIPHERAL2_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC1 (0x80 | (SPC5_PERIPHERAL2_CLK_DIV_VALUE - 1))
#else
-#error "invalid SPC5_PHERIPERAL2_CLK_DIV_VALUE value specified"
+#error "invalid SPC5_PERIPHERAL2_CLK_DIV_VALUE value specified"
#endif
/* Check on the peripherals set 3 clock divider settings.*/
-#if SPC5_PHERIPERAL3_CLK_DIV_VALUE == 0
+#if SPC5_PERIPHERAL3_CLK_DIV_VALUE == 0
#define SPC5_CGM_SC_DC2 0
-#elif (SPC5_PHERIPERAL3_CLK_DIV_VALUE >= 1) && \
- (SPC5_PHERIPERAL3_CLK_DIV_VALUE <= 16)
-#define SPC5_CGM_SC_DC2 (0x80 | (SPC5_PHERIPERAL3_CLK_DIV_VALUE - 1))
+#elif (SPC5_PERIPHERAL3_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PERIPHERAL3_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC2 (0x80 | (SPC5_PERIPHERAL3_CLK_DIV_VALUE - 1))
#else
-#error "invalid SPC5_PHERIPERAL3_CLK_DIV_VALUE value specified"
+#error "invalid SPC5_PERIPHERAL3_CLK_DIV_VALUE value specified"
#endif
/*===========================================================================*/
|