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authoracirillo87 <acirillo87@35acf78f-673a-0410-8e92-d51de3d6d3f4>2013-06-01 18:34:05 +0000
committeracirillo87 <acirillo87@35acf78f-673a-0410-8e92-d51de3d6d3f4>2013-06-01 18:34:05 +0000
commitdd78c66c35fecadb890236fd870799a748ab5bbd (patch)
treefdd60c99469643022b89281dbf8f901cdd8c01e2 /os/hal/platforms/SPC560BCxx
parent8b44a6f5d51826bcfea510cf570b1231573f3daa (diff)
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5792 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/SPC560BCxx')
-rw-r--r--os/hal/platforms/SPC560BCxx/spc560bc_registry.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h
index 2d449a5b6..79a335075 100644
--- a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h
+++ b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h
@@ -109,6 +109,8 @@
#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER 71
#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 72
#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_NUMBER 73
+#define SPC5_FLEXCAN0_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_START_PCTL);
+#define SPC5_FLEXCAN0_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_STOP_PCTL);
#define SPC5_HAS_FLEXCAN1 TRUE
#define SPC5_FLEXCAN1_PCTL 17
@@ -129,6 +131,8 @@
#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER 91
#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER 92
#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_NUMBER 93
+#define SPC5_FLEXCAN1_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_START_PCTL);
+#define SPC5_FLEXCAN1_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_STOP_PCTL);
#define SPC5_HAS_FLEXCAN2 TRUE
#define SPC5_FLEXCAN2_PCTL 18
@@ -149,6 +153,8 @@
#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_NUMBER 111
#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_NUMBER 112
#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_NUMBER 113
+#define SPC5_FLEXCAN2_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_START_PCTL);
+#define SPC5_FLEXCAN2_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_START_PCTL);
#define SPC5_HAS_FLEXCAN3 TRUE
#define SPC5_FLEXCAN3_PCTL 19
@@ -169,6 +175,8 @@
#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_NUMBER 179
#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_NUMBER 180
#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_NUMBER 181
+#define SPC5_FLEXCAN3_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, SPC5_CAN_FLEXCAN3_START_PCTL);
+#define SPC5_FLEXCAN3_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, SPC5_CAN_FLEXCAN3_STOP_PCTL);
#define SPC5_HAS_FLEXCAN4 TRUE
#define SPC5_FLEXCAN4_PCTL 20
@@ -189,6 +197,8 @@
#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_NUMBER 196
#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_NUMBER 197
#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_NUMBER 198
+#define SPC5_FLEXCAN4_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, SPC5_CAN_FLEXCAN4_START_PCTL);
+#define SPC5_FLEXCAN4_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, SPC5_CAN_FLEXCAN4_STOP_PCTL);
#define SPC5_HAS_FLEXCAN5 TRUE
#define SPC5_FLEXCAN5_PCTL 21
@@ -209,6 +219,8 @@
#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_NUMBER 208
#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_NUMBER 209
#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_NUMBER 210
+#define SPC5_FLEXCAN5_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, SPC5_CAN_FLEXCAN5_START_PCTL);
+#define SPC5_FLEXCAN5_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, SPC5_CAN_FLEXCAN5_STOP_PCTL);
/** @} */
#endif /* _SPC560BC_REGISTRY_H_ */