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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-12-07 11:52:13 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-12-07 11:52:13 +0000 |
| commit | 10e2b91f3ecf6f85f8f4806bd99507e985c01cfe (patch) | |
| tree | 9cbe5bf915196f41ea4da44aa194dca3a275bac2 /os/hal/platforms/SAM4L/hal_lld.c | |
| parent | d3eb66ffd31e7bad8689b88a77c5d0f489b85e37 (diff) | |
| download | ChibiOS-10e2b91f3ecf6f85f8f4806bd99507e985c01cfe.tar.gz ChibiOS-10e2b91f3ecf6f85f8f4806bd99507e985c01cfe.tar.bz2 ChibiOS-10e2b91f3ecf6f85f8f4806bd99507e985c01cfe.zip | |
GPT, ICU, PWM tested on STM32F3xx.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4882 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/SAM4L/hal_lld.c')
| -rw-r--r-- | os/hal/platforms/SAM4L/hal_lld.c | 69 |
1 files changed, 63 insertions, 6 deletions
diff --git a/os/hal/platforms/SAM4L/hal_lld.c b/os/hal/platforms/SAM4L/hal_lld.c index 745da4686..608fb6fe7 100644 --- a/os/hal/platforms/SAM4L/hal_lld.c +++ b/os/hal/platforms/SAM4L/hal_lld.c @@ -33,6 +33,9 @@ /* Driver local definitions. */
/*===========================================================================*/
+#define SAM_PM_UNLOCK(addr) \
+ PM->PM_UNLOCK = BPM_UNLOCK_KEY(0xAAu) | BPM_UNLOCK_ADDR(addr)
+
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@@ -53,17 +56,71 @@ /* Driver exported functions. */
/*===========================================================================*/
-void sam4l_clock_init(void) {
+/**
+ * @brief Enables a module on one of the PBx buses.
+ * @note PB bridges are assumed to be already enabled.
+ *
+ * @param[in] bus_id id of the bus
+ * @param[in] module module address
+ */
+void sam_enable_module(uint32_t bus_id, uint32_t module) {
+ uint32_t mask;
+
+ mask = *(&PM->PM_CPUMASK + bus_id);
+ mask |= 1U << module;
+ SAM_PM_UNLOCK(((uint32_t)&PM->PM_CPUMASK - (uint32_t)PM) + (4 * bus_id));
+ *(&PM->PM_CPUMASK + bus_id) |= mask;
+}
+
+/**
+ * @brief Disables a module on one of the PBx buses.
+ * @note PB bridges are assumed to be already enabled.
+ *
+ * @param[in] bus_id id of the bus
+ * @param[in] module module index
+ */
+void sam_disable_module(uint32_t bus_id, uint32_t module) {
+ uint32_t mask;
+
+ mask = *(&PM->PM_CPUMASK + bus_id);
+ mask &= ~(1U << module);
+ SAM_PM_UNLOCK(((uint32_t)&PM->PM_CPUMASK - (uint32_t)PM) + (4 * bus_id));
+ *(&PM->PM_CPUMASK + bus_id) = mask;
+}
+
+/**
+ * @brief Clock initialization.
+ */
+void sam_clock_init(void) {
#if SAM_NO_INIT
+ /* Enables bridges.*/
+ sam_enable_module(SAM_CLK_GRP_HSB, SAM_HSB_PBA_BRIDGE);
+ sam_enable_module(SAM_CLK_GRP_HSB, SAM_HSB_PBB_BRIDGE);
+ sam_enable_module(SAM_CLK_GRP_HSB, SAM_HSB_PBC_BRIDGE);
+ sam_enable_module(SAM_CLK_GRP_HSB, SAM_HSB_PBD_BRIDGE);
+
#if SAM_USE_PICOCACHE
- /* Enable the PicoCache.*/
- sysclk_enable_peripheral_clock(HCACHE);
- HCACHE->HCACHE_CTRL = HCACHE_CTRL_CEN_YES;
- while ((HCACHE->HCACHE_SR & HCACHE_SR_CSTS_EN) == 0)
- ;
+ /* Enable the PicoCache.*/
+ sam_enable_module(SAM_CLK_GRP_PBB, SAM_PBB_HRAMC1_DATA);
+ sam_enable_module(SAM_CLK_GRP_PBB, SAM_PBB_HRAMC1_REGS);
+ HCACHE->HCACHE_CTRL = HCACHE_CTRL_CEN_YES;
+ while ((HCACHE->HCACHE_SR & HCACHE_SR_CSTS_EN) == 0)
+ ;
#endif
+ /* Setting up prescalers.*/
+ SAM_PM_UNLOCK((uint32_t)&PM->PM_CPUSEL);
+ PM->PM_CPUSEL = SAM_CPUSEL;
+ SAM_PM_UNLOCK((uint32_t)&PM->PM_PBASEL);
+ PM->PM_PBASEL = SAM_PBASEL;
+ SAM_PM_UNLOCK((uint32_t)&PM->PM_PBBSEL);
+ PM->PM_PBBSEL = SAM_PBBSEL;
+ SAM_PM_UNLOCK((uint32_t)&PM->PM_PBCSEL);
+ PM->PM_PBCSEL = SAM_PBCSEL;
+ SAM_PM_UNLOCK((uint32_t)&PM->PM_PBDSEL);
+ PM->PM_PBDSEL = SAM_PBDSEL;
+
#endif /* SAM_NO_INIT */
}
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