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| author | theShed <theShed@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-03-07 15:00:21 +0000 |
|---|---|---|
| committer | theShed <theShed@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-03-07 15:00:21 +0000 |
| commit | 09d8d2dfdc588422c7353314ab1f0fe61305b6b5 (patch) | |
| tree | 4fea43efde8b45905f7cda1a68fdda0c158d780f /os/hal/platforms/LPC8xx/system_LPC8xx.h | |
| parent | d2e3d96b8d5305c9e74a762b22abe403dd726ec2 (diff) | |
| download | ChibiOS-09d8d2dfdc588422c7353314ab1f0fe61305b6b5.tar.gz ChibiOS-09d8d2dfdc588422c7353314ab1f0fe61305b6b5.tar.bz2 ChibiOS-09d8d2dfdc588422c7353314ab1f0fe61305b6b5.zip | |
Initial LPC8xx port
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5376 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/LPC8xx/system_LPC8xx.h')
| -rw-r--r-- | os/hal/platforms/LPC8xx/system_LPC8xx.h | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/os/hal/platforms/LPC8xx/system_LPC8xx.h b/os/hal/platforms/LPC8xx/system_LPC8xx.h new file mode 100644 index 000000000..108baa842 --- /dev/null +++ b/os/hal/platforms/LPC8xx/system_LPC8xx.h @@ -0,0 +1,62 @@ +/******************************************************************************
+ * @file: system_LPC8xx.h
+ * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Header File
+ * for the NXP LPC8xx Device Series
+ * @version: V1.0
+ * @date: 16. Aug. 2012
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC8xx_H
+#define __SYSTEM_LPC8xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC8xx_H */
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