git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1852 35acf78f-673a-0410-8e92-d51de3d6d3f4

3 files changed, 67 insertions, 67 deletions

diff --git a/os/hal/platforms/LPC13xx/hal_lld.c b/os/hal/platforms/LPC13xx/hal_lld.c
index 86319a028..a3415ee90 100644
--- a/os/hal/platforms/LPC13xx/hal_lld.c
+++ b/os/hal/platforms/LPC13xx/hal_lld.c
@@ -71,7 +71,7 @@ void hal_lld_init(void) {
 

   /* SysTick initialization using the system clock.*/

   NVICSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK);

-  SysTick->LOAD = LPC11xx_SYSCLK / CH_FREQUENCY - 1;

+  SysTick->LOAD = LPC13xx_SYSCLK / CH_FREQUENCY - 1;

   SysTick->VAL = 0;

   SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |

                   SysTick_CTRL_ENABLE_Msk |

@@ -86,30 +86,30 @@ void LPC13xx_clock_init(void) {
   unsigned i;

 

   /* Flash wait states setting, the code takes care to not touch TBD bits.*/

-  FLASHCFG = (FLASHCFG & ~3) | LPC11xx_FLASHCFG_FLASHTIM;

+  FLASHCFG = (FLASHCFG & ~3) | LPC13xx_FLASHCFG_FLASHTIM;

 

   /* System oscillator initialization if required.*/

-#if LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT

-#if LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC

-  LPC_SYSCON->SYSOSCCTRL = LPC11xx_SYSOSCCTRL;

+#if LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT

+#if LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC

+  LPC_SYSCON->SYSOSCCTRL = LPC13xx_SYSOSCCTRL;

   LPC_SYSCON->PDRUNCFG &= ~(1 << 5);            /* System oscillator ON.    */

   for (i = 0; i < 200; i++)

     __NOP();                                    /* Stabilization delay.     */

-#endif /* LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC */

+#endif /* LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC */

 

   /* PLL initialization if required.*/

-  LPC_SYSCON->SYSPLLCLKSEL = LPC11xx_PLLCLK_SOURCE;

+  LPC_SYSCON->SYSPLLCLKSEL = LPC13xx_PLLCLK_SOURCE;

   LPC_SYSCON->SYSPLLCLKUEN = 1;                 /* Really required?         */

   LPC_SYSCON->SYSPLLCLKUEN = 0;

   LPC_SYSCON->SYSPLLCLKUEN = 1;

-  LPC_SYSCON->SYSPLLCTRL = LPC11xx_SYSPLLCTRL_MSEL | LPC11xx_SYSPLLCTRL_PSEL;

+  LPC_SYSCON->SYSPLLCTRL = LPC13xx_SYSPLLCTRL_MSEL | LPC13xx_SYSPLLCTRL_PSEL;

   LPC_SYSCON->PDRUNCFG &= ~(1 << 7);            /* System PLL ON.           */

   while ((LPC_SYSCON->SYSPLLSTAT & 1) == 0)     /* Wait PLL lock.           */

     ;

-#endif /* LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT */

+#endif /* LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT */

 

   /* Main clock source selection.*/

-  LPC_SYSCON->MAINCLKSEL = LPC11xx_MAINCLK_SOURCE;

+  LPC_SYSCON->MAINCLKSEL = LPC13xx_MAINCLK_SOURCE;

   LPC_SYSCON->MAINCLKUEN = 1;                   /* Really required?         */

   LPC_SYSCON->MAINCLKUEN = 0;

   LPC_SYSCON->MAINCLKUEN = 1;

@@ -119,11 +119,11 @@ void LPC13xx_clock_init(void) {
   /* ABH divider initialization, peripheral clocks are initially disabled,

      the various device drivers will handle their own setup except GPIO and

      IOCON that are left enabled.*/

-  LPC_SYSCON->SYSAHBCLKDIV = LPC11xx_SYSABHCLK_DIV;

+  LPC_SYSCON->SYSAHBCLKDIV = LPC13xx_SYSABHCLK_DIV;

   LPC_SYSCON->SYSAHBCLKCTRL = 0x0001005F;

 

   /* Peripheral clock dividers initialization.*/

-  LPC_SYSCON->UARTCLKDIV = LPC11xx_UART_PCLK_DIV;

+  LPC_SYSCON->UARTCLKDIV = LPC13xx_UART_PCLK_DIV;

 

   /* Memory remapping, vectors always in ROM.*/

   LPC_SYSCON->SYSMEMREMAP = 2;

diff --git a/os/hal/platforms/LPC13xx/hal_lld.h b/os/hal/platforms/LPC13xx/hal_lld.h
index 4203c19ae..fee051aee 100644
--- a/os/hal/platforms/LPC13xx/hal_lld.h
+++ b/os/hal/platforms/LPC13xx/hal_lld.h
@@ -43,12 +43,12 @@
 #define IRCOSCCLK               12000000    /**< High speed internal clock. */

 #define WDGOSCCLK               1600000     /**< Watchdog internal clock.   */

 

-#define SYSPLLCLKSEL_IRCOCS     0           /**< Internal RC oscillator

+#define SYSPLLCLKSEL_IRCOSC     0           /**< Internal RC oscillator

                                                  clock source.              */

 #define SYSPLLCLKSEL_SYSOSC     1           /**< System oscillator clock

                                                  source.                    */

 

-#define SYSMAINCLKSEL_IRCOCS    0           /**< Clock source is IRC.       */

+#define SYSMAINCLKSEL_IRCOSC    0           /**< Clock source is IRC.       */

 #define SYSMAINCLKSEL_PLLIN     1           /**< Clock source is PLLIN.     */

 #define SYSMAINCLKSEL_WDGOSC    2           /**< Clock source is WDGOSC.    */

 #define SYSMAINCLKSEL_PLLOUT    3           /**< Clock source is PLLOUT.    */

@@ -60,8 +60,8 @@
 /**

  * @brief   System PLL clock source.

  */

-#if !defined(LPC11xx_PLLCLK_SOURCE) || defined(__DOXYGEN__)

-#define LPC11xx_PLLCLK_SOURCE   SYSPLLCLKSEL_SYSOSC

+#if !defined(LPC13xx_PLLCLK_SOURCE) || defined(__DOXYGEN__)

+#define LPC13xx_PLLCLK_SOURCE   SYSPLLCLKSEL_SYSOSC

 #endif

 

 /**

@@ -69,39 +69,39 @@
  * @note    The value must be in the 1..32 range and the final frequency

  *          must not exceed the CCO ratings.

  */

-#if !defined(LPC11xx_SYSPLL_MUL) || defined(__DOXYGEN__)

-#define LPC11xx_SYSPLL_MUL      4

+#if !defined(LPC13xx_SYSPLL_MUL) || defined(__DOXYGEN__)

+#define LPC13xx_SYSPLL_MUL      6

 #endif

 

 /**

  * @brief   System PLL divider.

  * @note    The value must be chosen between (2, 4, 8, 16).

  */

-#if !defined(LPC11xx_SYSPLL_DIV) || defined(__DOXYGEN__)

-#define LPC11xx_SYSPLL_DIV      4

+#if !defined(LPC13xx_SYSPLL_DIV) || defined(__DOXYGEN__)

+#define LPC13xx_SYSPLL_DIV      4

 #endif

 

 /**

  * @brief   System main clock source.

  */

-#if !defined(LPC11xx_MAINCLK_SOURCE) || defined(__DOXYGEN__)

-#define LPC11xx_MAINCLK_SOURCE  SYSMAINCLKSEL_PLLOUT

+#if !defined(LPC13xx_MAINCLK_SOURCE) || defined(__DOXYGEN__)

+#define LPC13xx_MAINCLK_SOURCE  SYSMAINCLKSEL_PLLOUT

 #endif

 

 /**

  * @brief   AHB clock divider.

  * @note    The value must be chosen between (1...255).

  */

-#if !defined(LPC11xx_SYSCLK_DIV) || defined(__DOXYGEN__)

-#define LPC11xx_SYSABHCLK_DIV   1

+#if !defined(LPC13xx_SYSCLK_DIV) || defined(__DOXYGEN__)

+#define LPC13xx_SYSABHCLK_DIV   1

 #endif

 

 /**

  * @brief   UART clock divider.

  * @note    The value must be chosen between (1...255).

  */

-#if !defined(LPC11xx_UART_PCLK_DIV) || defined(__DOXYGEN__)

-#define LPC11xx_UART_PCLK_DIV   1

+#if !defined(LPC13xx_UART_PCLK_DIV) || defined(__DOXYGEN__)

+#define LPC13xx_UART_PCLK_DIV   1

 #endif

 

 /*===========================================================================*/

@@ -112,79 +112,79 @@
  * @brief   Calculated SYSOSCCTRL setting.
  */

 #if (SYSOSCCLK < 18000000) || defined(__DOXYGEN__)

-#define LPC11xx_SYSOSCCTRL      0

+#define LPC13xx_SYSOSCCTRL      0

 #else

-#define LPC11xx_SYSOSCCTRL      1

+#define LPC13xx_SYSOSCCTRL      1

 #endif

 

 /**

  * @brief   PLL input clock frequency.
  */

-#if (LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__)

-#define LPC11xx_SYSPLLCLKIN     SYSOSCCLK

-#elif LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOCS

-#define LPC11xx_SYSPLLCLKIN     IRCOSCCLK

+#if (LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__)

+#define LPC13xx_SYSPLLCLKIN     SYSOSCCLK

+#elif LPC13xx_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOCS

+#define LPC13xx_SYSPLLCLKIN     IRCOSCCLK

 #else

-#error "invalid LPC11xx_PLLCLK_SOURCE clock source specified"

+#error "invalid LPC13xx_PLLCLK_SOURCE clock source specified"

 #endif

 

 /**

  * @brief   MSEL mask in SYSPLLCTRL register.

  */

-#if (LPC11xx_SYSPLL_MUL >= 1) && (LPC11xx_SYSPLL_MUL <= 32) ||              \

+#if (LPC13xx_SYSPLL_MUL >= 1) && (LPC13xx_SYSPLL_MUL <= 32) ||              \

     defined(__DOXYGEN__)

-#define LPC11xx_SYSPLLCTRL_MSEL (LPC11xx_SYSPLL_MUL - 1)

+#define LPC13xx_SYSPLLCTRL_MSEL (LPC13xx_SYSPLL_MUL - 1)

 #else

-#error "LPC11xx_SYSPLL_MUL out of range (1...32)"

+#error "LPC13xx_SYSPLL_MUL out of range (1...32)"

 #endif

 

 /**

  * @brief   PSEL mask in SYSPLLCTRL register.
  */

-#if (LPC11xx_SYSPLL_DIV == 2) || defined(__DOXYGEN__)

-#define LPC11xx_SYSPLLCTRL_PSEL (0 << 5)

-#elif LPC11xx_SYSPLL_DIV == 4

-#define LPC11xx_SYSPLLCTRL_PSEL (1 << 5)

-#elif LPC11xx_SYSPLL_DIV == 8

-#define LPC11xx_SYSPLLCTRL_PSEL (2 << 5)

-#elif LPC11xx_SYSPLL_DIV == 16

-#define LPC11xx_SYSPLLCTRL_PSEL (3 << 5)

+#if (LPC13xx_SYSPLL_DIV == 2) || defined(__DOXYGEN__)

+#define LPC13xx_SYSPLLCTRL_PSEL (0 << 5)

+#elif LPC13xx_SYSPLL_DIV == 4

+#define LPC13xx_SYSPLLCTRL_PSEL (1 << 5)

+#elif LPC13xx_SYSPLL_DIV == 8

+#define LPC13xx_SYSPLLCTRL_PSEL (2 << 5)

+#elif LPC13xx_SYSPLL_DIV == 16

+#define LPC13xx_SYSPLLCTRL_PSEL (3 << 5)

 #else

-#error "invalid LPC11xx_SYSPLL_DIV value (2,4,8,16)"

+#error "invalid LPC13xx_SYSPLL_DIV value (2,4,8,16)"

 #endif

 

 /**

  * @brief   CCP frequency.
  */

-#define  LPC11xx_SYSPLLCCO   (LPC11xx_SYSPLLCLKIN * LPC11xx_SYSPLL_MUL *    \

-                              LPC11xx_SYSPLL_DIV)

+#define  LPC13xx_SYSPLLCCO   (LPC13xx_SYSPLLCLKIN * LPC13xx_SYSPLL_MUL *    \

+                              LPC13xx_SYSPLL_DIV)

 

-#if (LPC11xx_SYSPLLCCO < 156000000) || (LPC11xx_SYSPLLCCO > 320000000)

+#if (LPC13xx_SYSPLLCCO < 156000000) || (LPC13xx_SYSPLLCCO > 320000000)

 #error "CCO frequency out of the acceptable range (156...320)"

 #endif

 

 /**

  * @brief   PLL output clock frequency.

  */

-#define  LPC11xx_SYSPLLCLKOUT   (LPC11xx_SYSPLLCCO / LPC11xx_SYSPLL_DIV)

+#define  LPC13xx_SYSPLLCLKOUT   (LPC13xx_SYSPLLCCO / LPC13xx_SYSPLL_DIV)

 

-#if (LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOCS) || defined(__DOXYGEN__)

-#define LPC11xx_MAINCLK     IRCOSCCLK

-#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN

-#define LPC11xx_MAINCLK     LPC11xx_SYSPLLCLKIN

-#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC

-#define LPC11xx_MAINCLK     WDGOSCCLK

-#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT

-#define LPC11xx_MAINCLK     LPC11xx_SYSPLLCLKOUT

+#if (LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOCS) || defined(__DOXYGEN__)

+#define LPC13xx_MAINCLK     IRCOSCCLK

+#elif LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN

+#define LPC13xx_MAINCLK     LPC13xx_SYSPLLCLKIN

+#elif LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC

+#define LPC13xx_MAINCLK     WDGOSCCLK

+#elif LPC13xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT

+#define LPC13xx_MAINCLK     LPC13xx_SYSPLLCLKOUT

 #else

-#error "invalid LPC11xx_MAINCLK_SOURCE clock source specified"

+#error "invalid LPC13xx_MAINCLK_SOURCE clock source specified"

 #endif

 

 /**

  * @brief   AHB clock.

  */

-#if (LPC11xx_SYSCLK <= 50000000) || defined(__DOXYGEN__)

-#define  LPC11xx_SYSCLK     (LPC11xx_MAINCLK / LPC11xx_SYSABHCLK_DIV)

+#if (LPC13xx_SYSCLK <= 50000000) || defined(__DOXYGEN__)

+#define  LPC13xx_SYSCLK     (LPC13xx_MAINCLK / LPC13xx_SYSABHCLK_DIV)

 #else

 #error "AHB clock frequency out of the acceptable range (50MHz max)"

 #endif

@@ -192,18 +192,18 @@
 /**

  * @brief   Flash wait states.
  */

-#if (LPC11xx_SYSCLK <= 20000000) || defined(__DOXYGEN__)

-#define LPC11xx_FLASHCFG_FLASHTIM   0

-#elif LPC11xx_SYSCLK <= 40000000

-#define LPC11xx_FLASHCFG_FLASHTIM   1

+#if (LPC13xx_SYSCLK <= 20000000) || defined(__DOXYGEN__)

+#define LPC13xx_FLASHCFG_FLASHTIM   0

+#elif LPC13xx_SYSCLK <= 40000000

+#define LPC13xx_FLASHCFG_FLASHTIM   1

 #else

-#define LPC11xx_FLASHCFG_FLASHTIM   2

+#define LPC13xx_FLASHCFG_FLASHTIM   2

 #endif

 

 /**

  * @brief   UART clock.

  */

-#define  LPC11xx_UART_PCLK  (LPC11xx_MAINCLK / LPC11xx_UART_PCLK_DIV)

+#define  LPC13xx_UART_PCLK  (LPC13xx_MAINCLK / LPC13xx_UART_PCLK_DIV)

 

 /*===========================================================================*/

 /* Driver data structures and types.                                         */

diff --git a/os/hal/platforms/LPC13xx/serial_lld.c b/os/hal/platforms/LPC13xx/serial_lld.c
index 03a57d6ef..0db6907b3 100644
--- a/os/hal/platforms/LPC13xx/serial_lld.c
+++ b/os/hal/platforms/LPC13xx/serial_lld.c
@@ -62,7 +62,7 @@ static const SerialConfig default_config = {
 static void uart_init(SerialDriver *sdp) {

   LPC_UART_TypeDef *u = sdp->uart;

 

-  uint32_t div = LPC11xx_UART_PCLK / (sdp->config->sc_speed << 4);

+  uint32_t div = LPC13xx_UART_PCLK / (sdp->config->sc_speed << 4);

   u->LCR = sdp->config->sc_lcr | LCR_DLAB;

   u->DLL = div;

   u->DLM = div >> 8;