New NXP headers.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4219 35acf78f-673a-0410-8e92-d51de3d6d3f4

3 files changed, 123 insertions, 80 deletions

diff --git a/os/hal/platforms/LPC11xx/LPC11xx.h b/os/hal/platforms/LPC11xx/LPC11xx.h
index c07fe3b47..3f96459c7 100644
--- a/os/hal/platforms/LPC11xx/LPC11xx.h
+++ b/os/hal/platforms/LPC11xx/LPC11xx.h
@@ -1,28 +1,23 @@
-/**************************************************************************//**

- * @file     LPC11xx.h

- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File for 

- *           NXP LPC11xx Device Series

- * @version  V1.00

- * @date     17. November 2009

+/****************************************************************************

+ *   $Id:: LPC11xx.h 4070 2010-07-30 03:16:37Z usb00423                     $

+ *   Project: NXP LPC11xx software example  

  *

- * @note

- * Copyright (C) 2009 ARM Limited. All rights reserved.

+ *   Description:

+ *     CMSIS Cortex-M0 Core Peripheral Access Layer Header File for 

+ *     NXP LPC11xx Device Series 

  *

- * @par

- * ARM Limited (ARM) is supplying this software for use with Cortex-M 

- * processor based microcontrollers.  This file can be freely distributed 

- * within development tools that are supporting such ARM based processors. 

- *

- * @par

- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED

- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.

- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR

- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

- *

- ******************************************************************************/

-

-

+ ****************************************************************************

+ * Software that is described herein is for illustrative purposes only

+ * which provides customers with programming information regarding the

+ * products. This software is supplied "AS IS" without any warranties.

+ * NXP Semiconductors assumes no responsibility or liability for the

+ * use of the software, conveys no license or title under any patent,

+ * copyright, or mask work right to the product. NXP Semiconductors

+ * reserves the right to make changes in the software without

+ * notification. NXP Semiconductors also make no representation or

+ * warranty that such application will be suitable for the specified

+ * use without further testing or modification.

+****************************************************************************/

 #ifndef __LPC11xx_H__

 #define __LPC11xx_H__

 

@@ -53,7 +48,6 @@
  * ---------- Interrupt Number Definition -----------------------------------

  * ==========================================================================

  */

-

 typedef enum IRQn

 {

 /******  Cortex-M0 Processor Exceptions Numbers ***************************************************/

@@ -63,7 +57,7 @@ typedef enum IRQn
   PendSV_IRQn                   = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                     */

   SysTick_IRQn                  = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                 */

 

-/******  LPC13xx Specific Interrupt Numbers *******************************************************/

+/******  LPC11Cxx or LPC11xx Specific Interrupt Numbers *******************************************************/

   WAKEUP0_IRQn                  = 0,        /*!< All I/O pins can be used as wakeup source.       */

   WAKEUP1_IRQn                  = 1,        /*!< There are 13 pins in total for LPC11xx           */

   WAKEUP2_IRQn                  = 2,

@@ -77,6 +71,7 @@ typedef enum IRQn
   WAKEUP10_IRQn                 = 10,       

   WAKEUP11_IRQn                 = 11,       

   WAKEUP12_IRQn                 = 12,       

+  CAN_IRQn                      = 13,       /*!< CAN Interrupt                                    */

   SSP1_IRQn                     = 14,       /*!< SSP1 Interrupt                                   */

   I2C_IRQn                      = 15,       /*!< I2C Interrupt                                    */

   TIMER_16_0_IRQn               = 16,       /*!< 16-bit Timer0 Interrupt                          */

@@ -85,16 +80,18 @@ typedef enum IRQn
   TIMER_32_1_IRQn               = 19,       /*!< 32-bit Timer1 Interrupt                          */

   SSP0_IRQn                     = 20,       /*!< SSP0 Interrupt                                   */

   UART_IRQn                     = 21,       /*!< UART Interrupt                                   */

+  Reserved0_IRQn                = 22,       /*!< Reserved Interrupt                               */

+  Reserved1_IRQn                = 23,       

   ADC_IRQn                      = 24,       /*!< A/D Converter Interrupt                          */

   WDT_IRQn                      = 25,       /*!< Watchdog timer Interrupt                         */  

   BOD_IRQn                      = 26,       /*!< Brown Out Detect(BOD) Interrupt                  */

+  FMC_IRQn                      = 27,       /*!< Flash Memory Controller Interrupt                */

   EINT3_IRQn                    = 28,       /*!< External Interrupt 3 Interrupt                   */

   EINT2_IRQn                    = 29,       /*!< External Interrupt 2 Interrupt                   */

   EINT1_IRQn                    = 30,       /*!< External Interrupt 1 Interrupt                   */

   EINT0_IRQn                    = 31,       /*!< External Interrupt 0 Interrupt                   */

 } IRQn_Type;

 

-

 /*

  * ==========================================================================

  * ----------- Processor and Core Peripheral Section ------------------------

@@ -130,7 +127,7 @@ typedef struct
   __IO uint32_t SYSMEMREMAP;            /*!< Offset: 0x000 System memory remap (R/W) */

   __IO uint32_t PRESETCTRL;             /*!< Offset: 0x004 Peripheral reset control (R/W) */

   __IO uint32_t SYSPLLCTRL;             /*!< Offset: 0x008 System PLL control (R/W) */

-  __IO uint32_t SYSPLLSTAT;             /*!< Offset: 0x00C System PLL status (R/ ) */

+  __IO uint32_t SYSPLLSTAT;             /*!< Offset: 0x00C System PLL status (R/W ) */

        uint32_t RESERVED0[4];

 

   __IO uint32_t SYSOSCCTRL;             /*!< Offset: 0x020 System oscillator control (R/W) */

@@ -170,22 +167,30 @@ typedef struct
   __IO uint32_t PIOPORCAP0;             /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */           

   __IO uint32_t PIOPORCAP1;             /*!< Offset: 0x104 POR captured PIO status 1 (R/ ) */   

        uint32_t RESERVED10[18];

-

   __IO uint32_t BODCTRL;                /*!< Offset: 0x150 BOD control (R/W) */

        uint32_t RESERVED11[1];

   __IO uint32_t SYSTCKCAL;              /*!< Offset: 0x158 System tick counter calibration (R/W) */

-       uint32_t RESERVED12[41];          

+       uint32_t RESERVED12;

+  __IO uint32_t MAINREGVOUT0CFG;        /*!< Offset: 0x160 Main Regulator Voltage 0 Configuration */ 

+  __IO uint32_t MAINREGVOUT1CFG;        /*!< Offset: 0x164 Main Regulator Voltage 1 Configuration */

+       uint32_t RESERVED13[38];

 

   __IO uint32_t STARTAPRP0;             /*!< Offset: 0x200 Start logic edge control Register 0 (R/W) */     

   __IO uint32_t STARTERP0;              /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */      

-  __IO uint32_t STARTRSRP0CLR;          /*!< Offset: 0x208 Start logic reset Register 0  ( /W) */

+  __O  uint32_t STARTRSRP0CLR;          /*!< Offset: 0x208 Start logic reset Register 0  ( /W) */

   __IO uint32_t STARTSRP0;              /*!< Offset: 0x20C Start logic status Register 0 (R/W) */

-       uint32_t RESERVED14[8];

+  __IO uint32_t STARTAPRP1;             /*!< Offset: 0x210 Start logic edge control Register 0 (R/W). (LPC11UXX only) */     

+  __IO uint32_t STARTERP1;              /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W). (LPC11UXX only) */      

+  __O  uint32_t STARTRSRP1CLR;          /*!< Offset: 0x218 Start logic reset Register 0  ( /W). (LPC11UXX only) */

+  __IO uint32_t STARTSRP1;              /*!< Offset: 0x21C Start logic status Register 0 (R/W). (LPC11UXX only) */

+       uint32_t RESERVED17[4];

 

   __IO uint32_t PDSLEEPCFG;             /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */

   __IO uint32_t PDAWAKECFG;             /*!< Offset: 0x234 Power-down states after wake-up (R/W) */        

   __IO uint32_t PDRUNCFG;               /*!< Offset: 0x238 Power-down configuration Register (R/W) */

-       uint32_t RESERVED15[110];

+       uint32_t RESERVED15[101];

+  __O  uint32_t VOUTCFGPROT;            /*!< Offset: 0x3D0 Voltage Output Configuration Protection Register (W) */

+       uint32_t RESERVED16[8];

   __I  uint32_t DEVICE_ID;              /*!< Offset: 0x3F4 Device ID (R/ ) */

 } LPC_SYSCON_TypeDef;

 /*@}*/ /* end of group LPC11xx_SYSCON */

@@ -226,18 +231,18 @@ typedef struct
 

   __IO uint32_t PIO0_8;                 /*!< Offset: 0x060 I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 (R/W) */

   __IO uint32_t PIO0_9;                 /*!< Offset: 0x064 I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 (R/W) */

-  __IO uint32_t JTAG_TCK_PIO0_10;       /*!< Offset: 0x068 I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (R/W) */

+  __IO uint32_t SWCLK_PIO0_10;          /*!< Offset: 0x068 I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (R/W) */

   __IO uint32_t PIO1_10;                /*!< Offset: 0x06C I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1 (R/W) */

   __IO uint32_t PIO2_11;                /*!< Offset: 0x070 I/O configuration for pin PIO2_11/SCK0 (R/W) */

-  __IO uint32_t JTAG_TDI_PIO0_11;       /*!< Offset: 0x074 I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 (R/W) */

-  __IO uint32_t JTAG_TMS_PIO1_0;        /*!< Offset: 0x078 I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 (R/W) */

-  __IO uint32_t JTAG_TDO_PIO1_1;        /*!< Offset: 0x07C I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 (R/W) */

+  __IO uint32_t R_PIO0_11;              /*!< Offset: 0x074 I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 (R/W) */

+  __IO uint32_t R_PIO1_0;               /*!< Offset: 0x078 I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 (R/W) */

+  __IO uint32_t R_PIO1_1;               /*!< Offset: 0x07C I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 (R/W) */

 

-  __IO uint32_t JTAG_nTRST_PIO1_2;      /*!< Offset: 0x080 I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 (R/W) */

+  __IO uint32_t R_PIO1_2;               /*!< Offset: 0x080 I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 (R/W) */

   __IO uint32_t PIO3_0;                 /*!< Offset: 0x084 I/O configuration for pin PIO3_0/nDTR (R/W) */

   __IO uint32_t PIO3_1;                 /*!< Offset: 0x088 I/O configuration for pin PIO3_1/nDSR (R/W) */

   __IO uint32_t PIO2_3;                 /*!< Offset: 0x08C I/O configuration for pin PIO2_3/RI/MOSI1 (R/W) */

-  __IO uint32_t ARM_SWDIO_PIO1_3;       /*!< Offset: 0x090 I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 (R/W) */

+  __IO uint32_t SWDIO_PIO1_3;           /*!< Offset: 0x090 I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 (R/W) */

   __IO uint32_t PIO1_4;                 /*!< Offset: 0x094 I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 (R/W) */

   __IO uint32_t PIO1_11;                /*!< Offset: 0x098 I/O configuration for pin PIO1_11/AD7 (R/W) */

   __IO uint32_t PIO3_2;                 /*!< Offset: 0x09C I/O configuration for pin PIO3_2/nDCD (R/W) */

@@ -269,7 +274,6 @@ typedef struct
 } LPC_PMU_TypeDef;

 /*@}*/ /* end of group LPC11xx_PMU */

 

-

 /*------------- General Purpose Input/Output (GPIO) --------------------------*/

 /** @addtogroup LPC11xx_GPIO LPC11xx General Purpose Input/Output 

   @{

@@ -295,7 +299,6 @@ typedef struct
 } LPC_GPIO_TypeDef;

 /*@}*/ /* end of group LPC11xx_GPIO */

 

-

 /*------------- Timer (TMR) --------------------------------------------------*/

 /** @addtogroup LPC11xx_TMR LPC11xx 16/32-bit Counter/Timer 

   @{

@@ -356,7 +359,7 @@ typedef struct
   __IO uint32_t  RS485CTRL;             /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */

   __IO uint32_t  ADRMATCH;              /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */

   __IO uint32_t  RS485DLY;              /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */

-  __I  uint32_t  FIFOLVL;               /*!< Offset: 0x058 FIFO Level Register (R/ ) */

+  __I  uint32_t  FIFOLVL;               /*!< Offset: 0x058 FIFO Level Register (R) */

 } LPC_UART_TypeDef;

 /*@}*/ /* end of group LPC11xx_UART */

 

@@ -414,8 +417,11 @@ typedef struct
 {

   __IO uint32_t MOD;                    /*!< Offset: 0x000 Watchdog mode register (R/W) */

   __IO uint32_t TC;                     /*!< Offset: 0x004 Watchdog timer constant register (R/W) */

-  __O  uint32_t FEED;                   /*!< Offset: 0x008 Watchdog feed sequence register ( /W) */

-  __I  uint32_t TV;                     /*!< Offset: 0x00C Watchdog timer value register (R/ ) */

+  __O  uint32_t FEED;                   /*!< Offset: 0x008 Watchdog feed sequence register (W) */

+  __I  uint32_t TV;                     /*!< Offset: 0x00C Watchdog timer value register (R) */

+       uint32_t RESERVED0;

+  __IO uint32_t WARNINT;				/*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */

+  __IO uint32_t WINDOW;					/*!< Offset: 0x018 Watchdog timer window value register (R/W) */

 } LPC_WDT_TypeDef;

 /*@}*/ /* end of group LPC11xx_WDT */

 

@@ -436,6 +442,60 @@ typedef struct
 /*@}*/ /* end of group LPC11xx_ADC */

 

 

+/*------------- CAN Controller (CAN) ----------------------------*/

+/** @addtogroup LPC11xx_CAN LPC11xx Controller Area Network(CAN) 

+  @{

+*/

+typedef struct

+{

+  __IO uint32_t CNTL;				/* 0x000 */

+  __IO uint32_t STAT;

+  __IO uint32_t EC;

+  __IO uint32_t BT;

+  __IO uint32_t INT;

+  __IO uint32_t TEST;

+  __IO uint32_t BRPE;

+       uint32_t RESERVED0;

+  __IO uint32_t IF1_CMDREQ;			/* 0x020 */

+  __IO uint32_t IF1_CMDMSK;

+  __IO uint32_t IF1_MSK1;

+  __IO uint32_t IF1_MSK2;

+  __IO uint32_t IF1_ARB1;

+  __IO uint32_t IF1_ARB2;

+  __IO uint32_t IF1_MCTRL;

+  __IO uint32_t IF1_DA1;

+  __IO uint32_t IF1_DA2;

+  __IO uint32_t IF1_DB1;

+  __IO uint32_t IF1_DB2;

+       uint32_t RESERVED1[13];   

+  __IO uint32_t IF2_CMDREQ;			/* 0x080 */

+  __IO uint32_t IF2_CMDMSK;

+  __IO uint32_t IF2_MSK1;

+  __IO uint32_t IF2_MSK2;

+  __IO uint32_t IF2_ARB1;

+  __IO uint32_t IF2_ARB2;

+  __IO uint32_t IF2_MCTRL;

+  __IO uint32_t IF2_DA1;

+  __IO uint32_t IF2_DA2;

+  __IO uint32_t IF2_DB1;

+  __IO uint32_t IF2_DB2;

+       uint32_t RESERVED2[21];

+  __I  uint32_t TXREQ1;				/* 0x100 */

+  __I  uint32_t TXREQ2;

+       uint32_t RESERVED3[6];

+  __I  uint32_t ND1;				/* 0x120 */

+  __I  uint32_t ND2;

+       uint32_t RESERVED4[6];

+  __I  uint32_t IR1;				/* 0x140 */

+  __I  uint32_t IR2;

+       uint32_t RESERVED5[6];

+  __I  uint32_t MSGV1;				/* 0x160 */

+  __I  uint32_t MSGV2;

+       uint32_t RESERVED6[6];

+  __IO uint32_t CLKDIV;				/* 0x180 */

+} LPC_CAN_TypeDef;

+/*@}*/ /* end of group LPC11xx_CAN */

+

 #if defined ( __CC_ARM   )

 #pragma no_anon_unions

 #endif

@@ -462,9 +522,10 @@ typedef struct
 #define LPC_SSP0_BASE         (LPC_APB0_BASE + 0x40000)

 #define LPC_IOCON_BASE        (LPC_APB0_BASE + 0x44000)

 #define LPC_SYSCON_BASE       (LPC_APB0_BASE + 0x48000)

+#define LPC_CAN_BASE          (LPC_APB0_BASE + 0x50000)

 #define LPC_SSP1_BASE         (LPC_APB0_BASE + 0x58000)

 

-/* AHB peripherals                                                            */	

+/* AHB peripherals                                                            */

 #define LPC_GPIO_BASE         (LPC_AHB_BASE  + 0x00000)

 #define LPC_GPIO0_BASE        (LPC_AHB_BASE  + 0x00000)

 #define LPC_GPIO1_BASE        (LPC_AHB_BASE  + 0x10000)

@@ -485,6 +546,7 @@ typedef struct
 #define LPC_PMU               ((LPC_PMU_TypeDef    *) LPC_PMU_BASE   )

 #define LPC_SSP0              ((LPC_SSP_TypeDef    *) LPC_SSP0_BASE  )

 #define LPC_SSP1              ((LPC_SSP_TypeDef    *) LPC_SSP1_BASE  )

+#define LPC_CAN               ((LPC_CAN_TypeDef    *) LPC_CAN_BASE   )

 #define LPC_IOCON             ((LPC_IOCON_TypeDef  *) LPC_IOCON_BASE )

 #define LPC_SYSCON            ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)

 #define LPC_GPIO0             ((LPC_GPIO_TypeDef   *) LPC_GPIO0_BASE )

diff --git a/os/hal/platforms/LPC11xx/spi_lld.c b/os/hal/platforms/LPC11xx/spi_lld.c
index c8014f344..9fe7a1a3c 100644
--- a/os/hal/platforms/LPC11xx/spi_lld.c
+++ b/os/hal/platforms/LPC11xx/spi_lld.c
@@ -180,7 +180,7 @@ void spi_lld_init(void) {
   SPID1.ssp = LPC_SSP0;

   LPC_IOCON->SCK_LOC = LPC11xx_SPI_SCK0_SELECTOR;

 #if LPC11xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO0_10

-  LPC_IOCON->JTAG_TCK_PIO0_10 = 0xC2;       /* SCK0 without resistors.      */

+  LPC_IOCON->SWCLK_PIO0_10 = 0xC2;          /* SCK0 without resistors.      */

 #elif LPC11xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO2_11

   LPC_IOCON->PIO2_11 = 0xC1;                /* SCK0 without resistors.      */

 #else /* LPC11xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO0_6 */

diff --git a/os/hal/platforms/LPC11xx/system_LPC11xx.h b/os/hal/platforms/LPC11xx/system_LPC11xx.h
index 385fe3888..e4536b8a5 100644
--- a/os/hal/platforms/LPC11xx/system_LPC11xx.h
+++ b/os/hal/platforms/LPC11xx/system_LPC11xx.h
@@ -1,19 +1,17 @@
-/**************************************************************************//**

- * @file     system_LPC11xx.h

- * @brief    CMSIS Cortex-M0 Device Peripheral Access Layer Header File

- *           for the NXP LPC11xx Device Series

- * @version  V1.00

- * @date     17. November 2009

+/******************************************************************************

+ * @file:    system_LPC11xx.h

+ * @purpose: CMSIS Cortex-M0 Device Peripheral Access Layer Header File

+ *           for the NXP LPC11xx Device Series 

+ * @version: V1.0

+ * @date:    25. Nov. 2008

+ *----------------------------------------------------------------------------

  *

- * @note

- * Copyright (C) 2009 ARM Limited. All rights reserved.

+ * Copyright (C) 2008 ARM Limited. All rights reserved.

  *

- * @par

- * ARM Limited (ARM) is supplying this software for use with Cortex-M 

+ * ARM Limited (ARM) is supplying this software for use with Cortex-M0 

  * processor based microcontrollers.  This file can be freely distributed 

  * within development tools that are supporting such ARM based processors. 

  *

- * @par

  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED

  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.

@@ -26,14 +24,13 @@
 #ifndef __SYSTEM_LPC11xx_H

 #define __SYSTEM_LPC11xx_H

 

-#ifdef __cplusplus

-extern "C" {

-#endif

-

-#include <stdint.h>

-

-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */

+/* Vector Table Base ---------------------------------------------------------*/

+#define NVIC_VectTab_RAM             (0x10000000)

+#define NVIC_VectTab_FLASH           (0x00000000)

 

+extern uint32_t ClockSource;

+extern uint32_t SystemFrequency;    /*!< System Clock Frequency (Core Clock)  */

+extern uint32_t SystemAHBFrequency;

 

 /**

  * Initialize the system

@@ -42,23 +39,7 @@ extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  *
  * @return none

  *

  * @brief  Setup the microcontroller system.

- *         Initialize the System and update the SystemCoreClock variable.

+ *         Initialize the System and update the SystemFrequency variable.

  */

 extern void SystemInit (void);

-

-/**

- * Update SystemCoreClock variable

- *

- * @param  none

- * @return none

- *

- * @brief  Updates the SystemCoreClock with current core Clock 

- *         retrieved from cpu registers.

- */

-extern void SystemCoreClockUpdate (void);

-

-#ifdef __cplusplus

-}

 #endif

-

-#endif /* __SYSTEM_LPC11x_H */