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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-05-20 16:40:30 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-05-20 16:40:30 +0000 |
| commit | dce3d9cca32c68635d294fad4c3984a3492c3a9b (patch) | |
| tree | 557e29b1bce1bcebbe639ec7244a35dd76f1e6d1 /os/hal/platforms/LPC11Uxx/hal_lld.c | |
| parent | edf2ea75111ca62fbed9e557cadf343d4972a485 (diff) | |
| download | ChibiOS-dce3d9cca32c68635d294fad4c3984a3492c3a9b.tar.gz ChibiOS-dce3d9cca32c68635d294fad4c3984a3492c3a9b.tar.bz2 ChibiOS-dce3d9cca32c68635d294fad4c3984a3492c3a9b.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4223 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/LPC11Uxx/hal_lld.c')
| -rw-r--r-- | os/hal/platforms/LPC11Uxx/hal_lld.c | 124 |
1 files changed, 124 insertions, 0 deletions
diff --git a/os/hal/platforms/LPC11Uxx/hal_lld.c b/os/hal/platforms/LPC11Uxx/hal_lld.c new file mode 100644 index 000000000..9b1fac622 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/hal_lld.c @@ -0,0 +1,124 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file LPC11Uxx/hal_lld.c
+ * @brief LPC11Uxx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief Register missing in NXP header file.
+ */
+#define FLASHCFG (*((volatile uint32_t *)0x4003C010))
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+ /* SysTick initialization using the system clock.*/
+ nvicSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK);
+ SysTick->LOAD = LPC_SYSCLK / CH_FREQUENCY - 1;
+ SysTick->VAL = 0;
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk |
+ SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+ * @brief LPC11Uxx clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h.
+ * @note This function must be invoked only after the system reset.
+ *
+ * @special
+ */
+void lpc_clock_init(void) {
+ unsigned i;
+
+ /* Flash wait states setting, the code takes care to not touch TBD bits.*/
+ FLASHCFG = (FLASHCFG & ~3) | LPC_FLASHCFG_FLASHTIM;
+
+ /* System oscillator initialization if required.*/
+#if LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT
+#if LPC_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC
+ LPC_SYSCON->SYSOSCCTRL = LPC_SYSOSCCTRL;
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* System oscillator ON. */
+ for (i = 0; i < 200; i++)
+ __NOP(); /* Stabilization delay. */
+#endif /* LPC_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC */
+
+ /* PLL initialization if required.*/
+ LPC_SYSCON->SYSPLLCLKSEL = LPC_PLLCLK_SOURCE;
+ LPC_SYSCON->SYSPLLCLKUEN = 1; /* Really required? */
+ LPC_SYSCON->SYSPLLCLKUEN = 0;
+ LPC_SYSCON->SYSPLLCLKUEN = 1;
+ LPC_SYSCON->SYSPLLCTRL = LPC_SYSPLLCTRL_MSEL | LPC_SYSPLLCTRL_PSEL;
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* System PLL ON. */
+ while ((LPC_SYSCON->SYSPLLSTAT & 1) == 0) /* Wait PLL lock. */
+ ;
+#endif /* LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT */
+
+ /* Main clock source selection.*/
+ LPC_SYSCON->MAINCLKSEL = LPC_MAINCLK_SOURCE;
+ LPC_SYSCON->MAINCLKUEN = 1; /* Really required? */
+ LPC_SYSCON->MAINCLKUEN = 0;
+ LPC_SYSCON->MAINCLKUEN = 1;
+ while ((LPC_SYSCON->MAINCLKUEN & 1) == 0) /* Wait switch completion. */
+ ;
+
+ /* ABH divider initialization, peripheral clocks are initially disabled,
+ the various device drivers will handle their own setup except GPIO and
+ IOCON that are left enabled.*/
+ LPC_SYSCON->SYSAHBCLKDIV = LPC_SYSABHCLK_DIV;
+ LPC_SYSCON->SYSAHBCLKCTRL = 0x0001005F;
+
+ /* Memory remapping, vectors always in ROM.*/
+ LPC_SYSCON->SYSMEMREMAP = 2;
+}
+
+/** @} */
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