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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-10-04 14:36:34 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-10-04 14:36:34 +0000 |
| commit | 887ff945a901fac1fe18d6be7367b7f405a99e1a (patch) | |
| tree | fcfb99a686af80265943664dbd1e2587c4e6623c /os/hal/include | |
| parent | 2dd28213f179c0a6e0a1f889ee19f803df53c42f (diff) | |
| download | ChibiOS-887ff945a901fac1fe18d6be7367b7f405a99e1a.tar.gz ChibiOS-887ff945a901fac1fe18d6be7367b7f405a99e1a.tar.bz2 ChibiOS-887ff945a901fac1fe18d6be7367b7f405a99e1a.zip | |
Flash infrastructure rework based on WSPI, not complete.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12320 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os/hal/include')
| -rw-r--r-- | os/hal/include/hal_wspi.h | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/os/hal/include/hal_wspi.h b/os/hal/include/hal_wspi.h index 65f1fe9b0..69d2e2371 100644 --- a/os/hal/include/hal_wspi.h +++ b/os/hal/include/hal_wspi.h @@ -143,20 +143,20 @@ typedef struct { * ensured.
* @{
*/
-#define WSPI_CFG_INSTRUCTION_MODE_MASK (7LU << 0LU)
-#define WSPI_CFG_INSTRUCTION_MODE_NONE (0LU << 0LU)
-#define WSPI_CFG_INSTRUCTION_MODE_ONE_LINES (1LU << 0LU)
-#define WSPI_CFG_INSTRUCTION_MODE_TWO_LINES (2LU << 0LU)
-#define WSPI_CFG_INSTRUCTION_MODE_FOUR_LINES (3LU << 0LU)
-#define WSPI_CFG_INSTRUCTION_MODE_EIGHT_LINES (4LU << 0LU)
-
-#define WSPI_CFG_INSTRUCTION_DDR (1LU << 3LU)
-
-#define WSPI_CFG_INSTRUCTION_SIZE_MASK (3LU << 4LU)
-#define WSPI_CFG_INSTRUCTION_SIZE_8 (0LU << 4LU)
-#define WSPI_CFG_INSTRUCTION_SIZE_16 (1LU << 4LU)
-#define WSPI_CFG_INSTRUCTION_SIZE_24 (2LU << 4LU)
-#define WSPI_CFG_INSTRUCTION_SIZE_32 (3LU << 4LU)
+#define WSPI_CFG_CMD_MODE_MASK (7LU << 0LU)
+#define WSPI_CFG_CMD_MODE_NONE (0LU << 0LU)
+#define WSPI_CFG_CMD_MODE_ONE_LINE (1LU << 0LU)
+#define WSPI_CFG_CMD_MODE_TWO_LINES (2LU << 0LU)
+#define WSPI_CFG_CMD_MODE_FOUR_LINES (3LU << 0LU)
+#define WSPI_CFG_CMD_MODE_EIGHT_LINES (4LU << 0LU)
+
+#define WSPI_CFG_CMD_DDR (1LU << 3LU)
+
+#define WSPI_CFG_CMD_SIZE_MASK (3LU << 4LU)
+#define WSPI_CFG_CMD_SIZE_8 (0LU << 4LU)
+#define WSPI_CFG_CMD_SIZE_16 (1LU << 4LU)
+#define WSPI_CFG_CMD_SIZE_24 (2LU << 4LU)
+#define WSPI_CFG_CMD_SIZE_32 (3LU << 4LU)
#define WSPI_CFG_ADDR_MODE_MASK (7LU << 8LU)
#define WSPI_CFG_ADDR_MODE_NONE (0LU << 8LU)
|