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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-11-04 08:32:32 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-11-04 08:32:32 +0000 |
| commit | 11c39c1b95bb60026a1c811e63a16c63718e71d3 (patch) | |
| tree | 82985fc1de6f6cf0ca6b954e0b2b962adc04d596 /os/hal/include | |
| parent | 5da033f3619cdafa22be2e9d3cbe682bd35a5d67 (diff) | |
| download | ChibiOS-11c39c1b95bb60026a1c811e63a16c63718e71d3.tar.gz ChibiOS-11c39c1b95bb60026a1c811e63a16c63718e71d3.tar.bz2 ChibiOS-11c39c1b95bb60026a1c811e63a16c63718e71d3.zip | |
DTR mode apparently working.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12405 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os/hal/include')
| -rw-r--r-- | os/hal/include/hal_wspi.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/os/hal/include/hal_wspi.h b/os/hal/include/hal_wspi.h index 69d2e2371..c54c9ca2a 100644 --- a/os/hal/include/hal_wspi.h +++ b/os/hal/include/hal_wspi.h @@ -150,7 +150,7 @@ typedef struct { #define WSPI_CFG_CMD_MODE_FOUR_LINES (3LU << 0LU)
#define WSPI_CFG_CMD_MODE_EIGHT_LINES (4LU << 0LU)
-#define WSPI_CFG_CMD_DDR (1LU << 3LU)
+#define WSPI_CFG_CMD_DTR (1LU << 3LU)
#define WSPI_CFG_CMD_SIZE_MASK (3LU << 4LU)
#define WSPI_CFG_CMD_SIZE_8 (0LU << 4LU)
@@ -165,7 +165,7 @@ typedef struct { #define WSPI_CFG_ADDR_MODE_FOUR_LINES (3LU << 8LU)
#define WSPI_CFG_ADDR_MODE_EIGHT_LINES (4LU << 8LU)
-#define WSPI_CFG_ADDR_DDR (1LU << 11LU)
+#define WSPI_CFG_ADDR_DTR (1LU << 11LU)
#define WSPI_CFG_ADDR_SIZE_MASK (3LU << 12LU)
#define WSPI_CFG_ADDR_SIZE_8 (0LU << 12LU)
@@ -180,7 +180,7 @@ typedef struct { #define WSPI_CFG_ALT_MODE_FOUR_LINES (3LU << 16LU)
#define WSPI_CFG_ALT_MODE_EIGHT_LINES (4LU << 16LU)
-#define WSPI_CFG_ALT_DDR (1LU << 19LU)
+#define WSPI_CFG_ALT_DTR (1LU << 19LU)
#define WSPI_CFG_ALT_SIZE_MASK (3LU << 20LU)
#define WSPI_CFG_ALT_SIZE_8 (0LU << 20LU)
@@ -195,7 +195,9 @@ typedef struct { #define WSPI_CFG_DATA_MODE_FOUR_LINES (3LU << 24LU)
#define WSPI_CFG_DATA_MODE_EIGHT_LINES (4LU << 24LU)
-#define WSPI_CFG_DATA_DDR (1LU << 27LU)
+#define WSPI_CFG_DATA_DTR (1LU << 27LU)
+
+#define WSPI_CFG_DQS_ENABLE (1LU << 29LU)
#define WSPI_CFG_SIOO (1LU << 31LU)
/** @} */
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