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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-08-10 14:58:16 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-08-10 14:58:16 +0000 |
| commit | 51b16c7a2dbd4f3d0be30049a4dad702961bfb8b (patch) | |
| tree | 2e43247fbfc993d21f3b66381999e15886bdc81e /os/hal/boards/RAISONANCE_REVA_STM8S/board.c | |
| parent | ff1b36acdc78609a835e3e20bf9897399c08806f (diff) | |
| download | ChibiOS-51b16c7a2dbd4f3d0be30049a4dad702961bfb8b.tar.gz ChibiOS-51b16c7a2dbd4f3d0be30049a4dad702961bfb8b.tar.bz2 ChibiOS-51b16c7a2dbd4f3d0be30049a4dad702961bfb8b.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6126 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/boards/RAISONANCE_REVA_STM8S/board.c')
| -rw-r--r-- | os/hal/boards/RAISONANCE_REVA_STM8S/board.c | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/os/hal/boards/RAISONANCE_REVA_STM8S/board.c b/os/hal/boards/RAISONANCE_REVA_STM8S/board.c new file mode 100644 index 000000000..33e1fa1e9 --- /dev/null +++ b/os/hal/boards/RAISONANCE_REVA_STM8S/board.c @@ -0,0 +1,78 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+ROMCONST PALConfig pal_default_config =
+{
+ {
+ {VAL_GPIOAODR, 0, VAL_GPIOADDR, VAL_GPIOACR1, VAL_GPIOACR2},
+ {VAL_GPIOBODR, 0, VAL_GPIOBDDR, VAL_GPIOBCR1, VAL_GPIOBCR2},
+ {VAL_GPIOCODR, 0, VAL_GPIOCDDR, VAL_GPIOCCR1, VAL_GPIOCCR2},
+ {VAL_GPIODODR, 0, VAL_GPIODDDR, VAL_GPIODCR1, VAL_GPIODCR2},
+ {VAL_GPIOEODR, 0, VAL_GPIOEDDR, VAL_GPIOECR1, VAL_GPIOECR2},
+ {VAL_GPIOFODR, 0, VAL_GPIOFDDR, VAL_GPIOFCR1, VAL_GPIOFCR2},
+ {VAL_GPIOGODR, 0, VAL_GPIOGDDR, VAL_GPIOGCR1, VAL_GPIOGCR2},
+ }
+};
+#endif
+
+/*
+ * TIM 2 clock after the prescaler.
+ */
+#define TIM2_CLOCK (SYSCLK / 16)
+#define TIM2_ARR ((TIM2_CLOCK / CH_FREQUENCY) - 1)
+
+/*
+ * TIM2 interrupt handler.
+ */
+CH_IRQ_HANDLER(13) {
+
+ CH_IRQ_PROLOGUE();
+
+ chSysLockFromIsr();
+ chSysTimerHandlerI();
+ chSysUnlockFromIsr();
+
+ TIM2->SR1 = 0;
+
+ CH_IRQ_EPILOGUE();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+ /*
+ * TIM2 initialization as system tick.
+ */
+ CLK->PCKENR1 |= CLK_PCKENR1_TIM2;
+ TIM2->PSCR = 4; /* Prescaler divide by 2^4=16.*/
+ TIM2->ARRH = (uint8_t)(TIM2_ARR >> 8);
+ TIM2->ARRL = (uint8_t)(TIM2_ARR);
+ TIM2->CNTRH = 0;
+ TIM2->CNTRL = 0;
+ TIM2->SR1 = 0;
+ TIM2->IER = TIM2_IER_UIE;
+ TIM2->CR1 = TIM2_CR1_CEN;
+}
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