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author | edolomb <none@example.com> | 2019-01-17 15:19:20 +0000 |
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committer | edolomb <none@example.com> | 2019-01-17 15:19:20 +0000 |
commit | 29309f101a4828842c377ff11a3a59908aab05f2 (patch) | |
tree | f75aef8484bc3522621b128eb6bfeacd55ad0e47 /os/hal/boards/ATSAMA5D27_SOM1_NSEC | |
parent | 696701cd6fe254a4cb2e3f748cacabe853d42a9e (diff) | |
download | ChibiOS-29309f101a4828842c377ff11a3a59908aab05f2.tar.gz ChibiOS-29309f101a4828842c377ff11a3a59908aab05f2.tar.bz2 ChibiOS-29309f101a4828842c377ff11a3a59908aab05f2.zip |
Updated SAMA drivers (still incomplete)
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12543 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os/hal/boards/ATSAMA5D27_SOM1_NSEC')
-rw-r--r-- | os/hal/boards/ATSAMA5D27_SOM1_NSEC/board.c | 165 | ||||
-rw-r--r-- | os/hal/boards/ATSAMA5D27_SOM1_NSEC/board.h | 232 | ||||
-rw-r--r-- | os/hal/boards/ATSAMA5D27_SOM1_NSEC/board.mk | 9 |
3 files changed, 406 insertions, 0 deletions
diff --git a/os/hal/boards/ATSAMA5D27_SOM1_NSEC/board.c b/os/hal/boards/ATSAMA5D27_SOM1_NSEC/board.c new file mode 100644 index 000000000..74498464e --- /dev/null +++ b/os/hal/boards/ATSAMA5D27_SOM1_NSEC/board.c @@ -0,0 +1,165 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "hal.h"
+
+#define _PIOA ((Pio*)0xFC038000U)
+/*
+ * SAMA PIO CFGR masks.
+ */
+#define SAMA_PIO_FUNC_GPIO 0U
+#define SAMA_PIO_FUNC_PERIPH_A 1U
+#define SAMA_PIO_FUNC_PERIPH_B 2U
+#define SAMA_PIO_FUNC_PERIPH_C 3U
+#define SAMA_PIO_FUNC_PERIPH_D 4U
+#define SAMA_PIO_FUNC_PERIPH_E 5U
+#define SAMA_PIO_FUNC_PERIPH_F 6U
+#define SAMA_PIO_FUNC_PERIPH_G 7U
+#define SAMA_PIO_FUNC(n) (n)
+#define SAMA_PIO_DIR_INPUT (0U)
+#define SAMA_PIO_DIR_OUTPUT (1U << 8U)
+#define SAMA_PIO_PUEN (1U << 9U)
+#define SAMA_PIO_PDEN (1U << 10U)
+#define SAMA_PIO_IFEN (1U << 12U)
+#define SAMA_PIO_IFSCEN (1U << 13U)
+#define SAMA_PIO_OPD (1U << 14U)
+#define SAMA_PIO_SCHMITT (1U << 15U)
+#define SAMA_PIO_DRVSTR_LO (0U << 16U)
+#define SAMA_PIO_DRVSTR_ME (2U << 16U)
+#define SAMA_PIO_DRVSTR_HI (3U << 16U)
+
+#define SAMA_PIO_LOW 0U
+#define SAMA_PIO_HIGH 1U
+/*
+ * SAMA PIO default SIOSR, MSKR and CFGR values.
+ */
+#define SAMA_DEFAULT_SIOSR 0x00000000U
+#define SAMA_DEFAULT_SIONR 0xFFFFFFFFU
+#define SAMA_DEFAULT_MSKR 0xFFFFFFFFU
+#define SAMA_DEFAULT_CFGR SAMA_PIO_FUNC_GPIO | SAMA_PIO_PUEN | \
+ SAMA_PIO_DIR_INPUT | SAMA_PIO_SCHMITT
+
+/*
+ * This macro converts a pin identifier to a bitmask.
+ */
+#define SAMA_PIN_N(n) (1U << n)
+
+/**
+ * @brief SIU/SIUL register initializer type.
+ */
+typedef struct {
+ int32_t pio_id;
+ uint32_t pio_msk;
+ uint32_t pio_cfg;
+ uint32_t pio_ods;
+} sama_pio_init_t;
+
+/*
+ * @brief Initial setup of all defined pads.
+ * @note The list is terminated by a {-1, 0, 0, 0}
+ */
+static const sama_pio_init_t sama_inits[] = {
+ /* RGB Led Red */
+ {SAMA_PIOA,
+ SAMA_PIN_N(PIOA_LED_RED),
+ SAMA_PIO_FUNC_GPIO | SAMA_PIO_DIR_OUTPUT | SAMA_PIO_DRVSTR_HI,
+ SAMA_PIO_LOW},
+ /* UART1 */
+ {SAMA_PIOD,
+ SAMA_PIN_N(PIOD_URXD1) | SAMA_PIN_N(PIOD_UTXD1),
+ SAMA_PIO_FUNC_PERIPH_A,
+ SAMA_PIO_HIGH},
+ /* UART2 */
+ {SAMA_PIOD,
+ SAMA_PIN_N(PIOD_URXD2) | SAMA_PIN_N(PIOD_UTXD2),
+ SAMA_PIO_FUNC_PERIPH_A,
+ SAMA_PIO_HIGH},
+ /* MMC Slot0 pads -J12 SD card */
+ {SAMA_PIOA,
+ SAMA_PIN_N(PIOA_SDMMC0_CK) | SAMA_PIN_N(PIOA_SDMMC0_CMD) |
+ SAMA_PIN_N(PIOA_SDMMC0_DAT0) | SAMA_PIN_N(PIOA_SDMMC0_DAT1) |
+ SAMA_PIN_N(PIOA_SDMMC0_DAT2) | SAMA_PIN_N(PIOA_SDMMC0_DAT3) |
+ SAMA_PIN_N(PIOA_SDMMC0_DAT4) | SAMA_PIN_N(PIOA_SDMMC0_DAT5) |
+ SAMA_PIN_N(PIOA_SDMMC0_DAT6) | SAMA_PIN_N(PIOA_SDMMC0_DAT7) |
+ SAMA_PIN_N(PIOA_SDMMC0_WP) | SAMA_PIN_N(PIOA_SDMMC0_CD) |
+ SAMA_PIN_N(PIOA_SDMMC0_VDDSEL),
+ SAMA_PIO_FUNC_PERIPH_A | SAMA_PIO_DRVSTR_HI,
+ SAMA_PIO_HIGH},
+ /* list terminated*/
+ {-1, 0, 0, 0}
+};
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ sama_clock_init();
+ /* Configures ETH's pins */
+ palSetGroupMode(PIOD, PAL_PORT_BIT(PIOD_ETH_GTXCK) | PAL_PORT_BIT(PIOD_ETH_GTXEN) |
+ PAL_PORT_BIT(PIOD_ETH_GRXDV) | PAL_PORT_BIT(PIOD_ETH_GRXER) |
+ PAL_PORT_BIT(PIOD_ETH_GRX0) | PAL_PORT_BIT(PIOD_ETH_GRX1) |
+ PAL_PORT_BIT(PIOD_ETH_GTX0) | PAL_PORT_BIT(PIOD_ETH_GTX1) |
+ PAL_PORT_BIT(PIOD_ETH_GMDC) | PAL_PORT_BIT(PIOD_ETH_GMDIO),
+ 0U, PAL_SAMA_FUNC_PERIPH_D);
+}
+
+/**
+ * @brief Board-specific initialization code.
+ */
+void boardInit(void) {
+ unsigned i;
+
+ /* Configuring all PIO A pads with default configuration. */
+#if SAMA_HAS_PIOA
+ _PIOA->PIO_PIO_[SAMA_PIOA].S_PIO_MSKR = SAMA_DEFAULT_MSKR;
+ _PIOA->PIO_PIO_[SAMA_PIOA].S_PIO_CFGR = SAMA_DEFAULT_CFGR;
+#endif /* SAMA_HAS_PIOA */
+
+ /* Configuring all PIO B pads with default configuration. */
+#if SAMA_HAS_PIOB
+ _PIOA->PIO_PIO_[SAMA_PIOB].S_PIO_MSKR = SAMA_DEFAULT_MSKR;
+ _PIOA->PIO_PIO_[SAMA_PIOB].S_PIO_CFGR = SAMA_DEFAULT_CFGR;
+#endif /* SAMA_HAS_PIOB */
+
+ /* Configuring all PIO C pads with default configuration. */
+#if SAMA_HAS_PIOC
+ _PIOA->PIO_PIO_[SAMA_PIOC].S_PIO_MSKR = SAMA_DEFAULT_MSKR;
+ _PIOA->PIO_PIO_[SAMA_PIOC].S_PIO_CFGR = SAMA_DEFAULT_CFGR;
+#endif /* SAMA_HAS_PIOC */
+
+ /* Configuring all PIO D pads with default configuration. */
+#if SAMA_HAS_PIOD
+ _PIOA->PIO_PIO_[SAMA_PIOD].S_PIO_MSKR = SAMA_DEFAULT_MSKR;
+ _PIOA->PIO_PIO_[SAMA_PIOD].S_PIO_CFGR = SAMA_DEFAULT_CFGR;
+#endif /* SAMA_HAS_PIOD */
+
+ /* Initialize PIO registers for defined pads.*/
+ i = 0;
+ while (sama_inits[i].pio_id != -1) {
+ _PIOA->PIO_IO_GROUP[sama_inits[i].pio_id].PIO_MSKR = sama_inits[i].pio_msk;
+ _PIOA->PIO_IO_GROUP[sama_inits[i].pio_id].PIO_CFGR = sama_inits[i].pio_cfg;
+ if(sama_inits[i].pio_ods == SAMA_PIO_HIGH) {
+ _PIOA->PIO_IO_GROUP[sama_inits[i].pio_id].PIO_SODR = sama_inits[i].pio_msk;
+ }
+ else {
+ _PIOA->PIO_IO_GROUP[sama_inits[i].pio_id].PIO_CODR = sama_inits[i].pio_msk;
+ }
+ i++;
+ }
+}
diff --git a/os/hal/boards/ATSAMA5D27_SOM1_NSEC/board.h b/os/hal/boards/ATSAMA5D27_SOM1_NSEC/board.h new file mode 100644 index 000000000..a22cc1051 --- /dev/null +++ b/os/hal/boards/ATSAMA5D27_SOM1_NSEC/board.h @@ -0,0 +1,232 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Atmel SAM A5 D27 SOM1-EK1 board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ATSAM5D27_SOM1
+#define BOARD_NAME "Atmel SAM A5 D27 SOM1 evaluation kit 1"
+
+/*
+ * Ethernet PHY type.
+ */
+#define BOARD_PHY_ID MII_KSZ8081_ID
+#define BOARD_PHY_RMII
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(SAMA_OSCXTCLK)
+#define SAMA_OSCXTCLK 32768U
+#endif
+
+#if !defined(SAMA_MOSCXTCLK)
+#define SAMA_MOSCXTCLK 24000000U
+#endif
+
+/*
+ * MCU type as defined in the Atmel header.
+ */
+#define SAMA5D27
+
+/**
+ * Port identifiers.
+ */
+#define SAMA_PIOA 0U
+#define SAMA_PIOB 1U
+#define SAMA_PIOC 2U
+#define SAMA_PIOD 3U
+
+/*
+ * Forms a line identifier. In this driver the pad number is encoded in the
+ * lower 5 bits of line and the port in sixth and seventh bits.
+ */
+#define SAMA_LINE(port, pad) \
+ ((uint32_t)((uint32_t)(port << 5U)) | ((uint32_t)(pad)))
+
+/*
+ * Decodes a port identifier from a line identifier.
+ */
+#define SAMA_PORT(line) \
+ ((uint32_t)((line & 0xFFFFFFE0U) >> 5U)
+
+/**
+ * Decodes a pad identifier from a line identifier.
+ */
+#define SAMA_PAD(line) \
+ ((uint32_t)(line & 0x0000001FU))
+
+/*
+ * IO pins assignments.
+ */
+#define PIOA_SDMMC0_CK 0U
+#define PIOA_SDMMC0_CMD 1U
+#define PIOA_SDMMC0_DAT0 2U
+#define PIOA_SDMMC0_DAT1 3U
+#define PIOA_SDMMC0_DAT2 4U
+#define PIOA_SDMMC0_DAT3 5U
+#define PIOA_SDMMC0_DAT4 6U
+#define PIOA_SDMMC0_DAT5 7U
+#define PIOA_SDMMC0_DAT6 8U
+#define PIOA_SDMMC0_DAT7 9U
+#define PIOA_LED_RED 10U
+#define PIOA_SDMMC0_VDDSEL 11U
+#define PIOA_SDMMC0_WP 12U
+#define PIOA_SDMMC0_CD 13U
+#define PIOA_PIN14 14U
+#define PIOA_PIN15 15U
+#define PIOA_PIN16 16U
+#define PIOA_PIN17 17U
+#define PIOA_PIN18 18U
+#define PIOA_PIN19 19U
+#define PIOA_PIN20 20U
+#define PIOA_PIN21 21U
+#define PIOA_PIN22 22U
+#define PIOA_PIN23 23U
+#define PIOA_PIN24 24U
+#define PIOA_PIN25 25U
+#define PIOA_PIN26 26U
+#define PIOA_PIN27 27U
+#define PIOA_PIN28 28U
+#define PIOA_PIN29 29U
+#define PIOA_PIN30 30U
+#define PIOA_PIN31 31U
+
+#define PIOB_PIN0 0U
+#define PIOB_PIN1 1U
+#define PIOB_PIN2 2U
+#define PIOB_PIN3 3U
+#define PIOB_PIN4 4U
+#define PIOB_PIN5 5U
+#define PIOB_PIN6 6U
+#define PIOB_PIN7 7U
+#define PIOB_PIN8 8U
+#define PIOB_PIN9 9U
+#define PIOB_PIN10 10U
+#define PIOB_PIN11 11U
+#define PIOB_PIN12 12U
+#define PIOB_PIN13 13U
+#define PIOB_PIN14 14U
+#define PIOB_PIN15 15U
+#define PIOB_PIN16 16U
+#define PIOB_PIN17 17U
+#define PIOB_PIN18 18U
+#define PIOB_PIN19 19U
+#define PIOB_PIN20 20U
+#define PIOB_PIN21 21U
+#define PIOB_PIN22 22U
+#define PIOB_PIN23 23U
+#define PIOB_PIN24 24U
+#define PIOB_PIN25 25U
+#define PIOB_PIN26 26U
+#define PIOB_PIN27 27U
+#define PIOB_PIN28 28U
+#define PIOB_PIN29 29U
+#define PIOB_PIN30 30U
+#define PIOB_PIN31 31U
+
+#define PIOC_PIN0 0U
+#define PIOC_PIN1 1U
+#define PIOC_PIN2 2U
+#define PIOC_PIN3 3U
+#define PIOC_PIN4 4U
+#define PIOC_PIN5 5U
+#define PIOC_PIN6 6U
+#define PIOC_PIN7 7U
+#define PIOC_PIN8 8U
+#define PIOC_PIN9 9U
+#define PIOC_PIN10 10U
+#define PIOC_PIN11 11U
+#define PIOC_PIN12 12U
+#define PIOC_PIN13 13U
+#define PIOC_PIN14 14U
+#define PIOC_PIN15 15U
+#define PIOC_PIN16 16U
+#define PIOC_PIN17 17U
+#define PIOC_PIN18 18U
+#define PIOC_PIN19 19U
+#define PIOC_PIN20 20U
+#define PIOC_PIN21 21U
+#define PIOC_PIN22 22U
+#define PIOC_PIN23 23U
+#define PIOC_PIN24 24U
+#define PIOC_PIN25 25U
+#define PIOC_PIN26 26U
+#define PIOC_PIN27 27U
+#define PIOC_PIN28 28U
+#define PIOC_PIN29 29U
+#define PIOC_PIN30 30U
+#define PIOC_PIN31 31U
+
+#define PIOD_PIO0 0U
+#define PIOD_PIN1 1U
+#define PIOD_URXD1 2U
+#define PIOD_UTXD1 3U
+#define PIOD_PIO4 4U
+#define PIOD_PIO5 5U
+#define PIOD_PIO6 6U
+#define PIOD_PIO7 7U
+#define PIOD_PIN8 8U
+#define PIOD_ETH_GTXCK 9U
+#define PIOD_ETH_GTXEN 10U
+#define PIOD_ETH_GRXDV 11U
+#define PIOD_ETH_GRXER 12U
+#define PIOD_ETH_GRX0 13U
+#define PIOD_ETH_GRX1 14U
+#define PIOD_ETH_GTX0 15U
+#define PIOD_ETH_GTX1 16U
+#define PIOD_ETH_GMDC 17U
+#define PIOD_ETH_GMDIO 18U
+#define PIOD_PIO19 19U
+#define PIOD_PIO20 20U
+#define PIOD_PIO21 21U
+#define PIOD_PIO22 22U
+#define PIOD_URXD2 23U
+#define PIOD_UTXD2 24U
+#define PIOD_PIO25 25U
+#define PIOD_PIO26 26U
+#define PIOD_PIO27 27U
+#define PIOD_PIO28 28U
+#define PIOD_PIO29 29U
+#define PIOD_PIN30 30U
+#define PIOD_PIN31 31U
+
+/*
+ * IO lines assignments.
+ */
+#define BOARD_LINE(port, pad) \
+ ((uint32_t)((uint32_t)(port)) | ((uint32_t)(pad)))
+
+#define LINE_LED_RED BOARD_LINE(PIOA, 10U)
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ATSAMA5D27_SOM1_NSEC/board.mk b/os/hal/boards/ATSAMA5D27_SOM1_NSEC/board.mk new file mode 100644 index 000000000..fbc9baba7 --- /dev/null +++ b/os/hal/boards/ATSAMA5D27_SOM1_NSEC/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ATSAMA5D27_SOM1_NSEC/board.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ATSAMA5D27_SOM1_NSEC
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
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