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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-09-07 15:54:45 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-09-07 15:54:45 +0000 |
| commit | 05be7e1f50beb7857b9edbd1abdc21f823960ebc (patch) | |
| tree | a0320ec1fe2a696ad2ed1dbd1f94ae7b56021f40 /os/common | |
| parent | 5a7e462d462f7c6818a4675195643fa92fed3c17 (diff) | |
| download | ChibiOS-05be7e1f50beb7857b9edbd1abdc21f823960ebc.tar.gz ChibiOS-05be7e1f50beb7857b9edbd1abdc21f823960ebc.tar.bz2 ChibiOS-05be7e1f50beb7857b9edbd1abdc21f823960ebc.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12247 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os/common')
| -rw-r--r-- | os/common/startup/ARMCMx/compilers/GCC/ld/STM32F756xG.ld | 136 |
1 files changed, 136 insertions, 0 deletions
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F756xG.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F756xG.ld new file mode 100644 index 000000000..a79e3d605 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F756xG.ld @@ -0,0 +1,136 @@ +/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F756xG generic setup.
+ *
+ * RAM0 - Data, Heap.
+ * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH.
+ *
+ * Notes:
+ * BSS is placed in DTCM RAM in order to simplify DMA buffers management.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */
+ flash1 : org = 0x00200000, len = 1M /* Flash as ITCM */
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */
+ ram1 : org = 0x20010000, len = 240k /* SRAM1 */
+ ram2 : org = 0x2004C000, len = 16k /* SRAM2 */
+ ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */
+ ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */
+ ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash1);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash1);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash1);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash1);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram3);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram3);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram3);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Stack rules inclusion.*/
+INCLUDE rules_stacks.ld
+
+/*===========================================================================*/
+/* Custom sections for STM32F7xx. */
+/*===========================================================================*/
+
+/* RAM region to be used for nocache segment.*/
+REGION_ALIAS("NOCACHE_RAM", ram3);
+
+/* RAM region to be used for eth segment.*/
+REGION_ALIAS("ETH_RAM", ram3);
+
+SECTIONS
+{
+ /* Special section for non cache-able areas.*/
+ .nocache (NOLOAD) : ALIGN(4)
+ {
+ __nocache_base__ = .;
+ *(.nocache)
+ *(.nocache.*)
+ *(.bss.__nocache_*)
+ . = ALIGN(4);
+ __nocache_end__ = .;
+ } > NOCACHE_RAM
+
+ /* Special section for Ethernet DMA non cache-able areas.*/
+ .eth (NOLOAD) : ALIGN(4)
+ {
+ __eth_base__ = .;
+ *(.eth)
+ *(.eth.*)
+ *(.bss.__eth_*)
+ . = ALIGN(4);
+ __eth_end__ = .;
+ } > ETH_RAM
+}
+
+/* Code rules inclusion.*/
+INCLUDE rules_code.ld
+
+/* Data rules inclusion.*/
+INCLUDE rules_data.ld
+
+/* Memory rules inclusion.*/
+INCLUDE rules_memory.ld
+
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