Splitted the ARM starup tree. Created an ARMCAx-TZ specific tree.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11005 35acf78f-673a-0410-8e92-d51de3d6d3f4
author: isiora <none@example.com> 2017-11-14 22:43:14 +0000
committer: isiora <none@example.com> 2017-11-14 22:43:14 +0000
commit: 2e7c937f0b2d2505f707970d0f8f1c3086cae279 (patch)
tree: adedd6e99948a7b23a485c8047c6c165f7ae7c51 /os/common/startup
parent: 7b3fe37b28fd37d80de146de6f34665168323c83 (diff)
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65 files changed, 21042 insertions, 0 deletions
diff --git a/os/common/startup/ARMCAx-TZ/compilers/GCC/crt0.S b/os/common/startup/ARMCAx-TZ/compilers/GCC/crt0.S
new file mode 100644
index 000000000..43cb723ab
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/compilers/GCC/crt0.S
@@ -0,0 +1,152 @@
+/*
+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    crt0.S
+ * @brief   Generic ARM startup file.
+ *
+ * @addtogroup ARM_GCC_STARTUP
+ * @{
+ */
+
+#if !defined(__DOXYGEN__)
+
+                .set    MODE_USR, 0x10
+                .set    MODE_FIQ, 0x11
+                .set    MODE_IRQ, 0x12
+                .set    MODE_SVC, 0x13
+                .set    MODE_ABT, 0x17
+                .set    MODE_UND, 0x1B
+                .set    MODE_SYS, 0x1F
+
+                .set    I_BIT, 0x80
+                .set    F_BIT, 0x40
+
+                .text
+                .code   32
+                .balign 4
+
+/*
+ * Reset handler.
+ */
+                .global Reset_Handler
+Reset_Handler:
+                /*
+                 * Stack pointers initialization.
+                 */
+                ldr     r0, =__stacks_end__
+                /* Undefined */
+                msr     CPSR_c, #MODE_UND | I_BIT | F_BIT
+                mov     sp, r0
+                ldr     r1, =__und_stack_size__
+                sub     r0, r0, r1
+                /* Abort */
+                msr     CPSR_c, #MODE_ABT | I_BIT | F_BIT
+                mov     sp, r0
+                ldr     r1, =__abt_stack_size__
+                sub     r0, r0, r1
+                /* FIQ */
+                msr     CPSR_c, #MODE_FIQ | I_BIT | F_BIT
+                mov     sp, r0
+                ldr     r1, =__fiq_stack_size__
+                sub     r0, r0, r1
+                /* IRQ */
+                msr     CPSR_c, #MODE_IRQ | I_BIT | F_BIT
+                mov     sp, r0
+                ldr     r1, =__irq_stack_size__
+                sub     r0, r0, r1
+                /* Supervisor */
+                msr     CPSR_c, #MODE_SVC | I_BIT | F_BIT
+                mov     sp, r0
+                ldr     r1, =__svc_stack_size__
+                sub     r0, r0, r1
+                /* System */
+                msr     CPSR_c, #MODE_SYS | I_BIT | F_BIT
+                mov     sp, r0
+//                ldr     r1, =__sys_stack_size__
+//                sub     r0, r0, r1
+                /*
+                 * Early initialization.
+                 */
+#if !defined(THUMB_NO_INTERWORKING)
+                bl      __early_init
+#else /* defined(THUMB_NO_INTERWORKING) */
+                add     r0, pc, #1
+                bx      r0
+                .code   16
+                bl      __early_init
+                mov     r0, pc
+                bx      r0
+                .code   32
+#endif /* defined(THUMB_NO_INTERWORKING) */
+
+                /*
+                 * Data initialization.
+                 * NOTE: It assumes that the DATA size is a multiple of 4.
+                 */
+                ldr     r1, =_textdata
+                ldr     r2, =_data
+                ldr     r3, =_edata
+dataloop:
+                cmp     r2, r3
+                ldrlo   r0, [r1], #4
+                strlo   r0, [r2], #4
+                blo     dataloop
+                /*
+                 * BSS initialization.
+                 * NOTE: It assumes that the BSS size is a multiple of 4.
+                 */
+                mov     r0, #0
+                ldr     r1, =_bss_start
+                ldr     r2, =_bss_end
+bssloop:
+                cmp     r1, r2
+                strlo   r0, [r1], #4
+                blo     bssloop
+                /*
+                 * Late initialization.
+                 */
+#if !defined(THUMB_NO_INTERWORKING)
+                bl      __late_init
+#else /* defined(THUMB_NO_INTERWORKING) */
+                add     r0, pc, #1
+                bx      r0
+                .code   16
+                bl      __late_init
+                mov     r0, pc
+                bx      r0
+                .code   32
+#endif /* defined(THUMB_NO_INTERWORKING) */
+
+                /*
+                 * Main program invocation.
+                 */
+#if defined(THUMB_NO_INTERWORKING)
+                add     r0, pc, #1
+                bx      r0
+                .code   16
+                bl      main
+                ldr     r1, =__default_exit
+                bx      r1
+                .code   32
+#else /* !defined(THUMB_NO_INTERWORKING) */
+                bl      main
+                b       __default_exit
+#endif /* !defined(THUMB_NO_INTERWORKING) */
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/startup/ARMCAx-TZ/compilers/GCC/crt1.c b/os/common/startup/ARMCAx-TZ/compilers/GCC/crt1.c
new file mode 100644
index 000000000..dd08df45d
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/compilers/GCC/crt1.c
@@ -0,0 +1,72 @@
+/*
+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    ARMCMx/compilers/GCC/crt1.c
+ * @brief   Startup stub functions.
+ *
+ * @addtogroup ARMCMx_GCC_STARTUP
+ * @{
+ */
+
+#include <stdbool.h>
+
+/**
+ * @brief   Early initialization.
+ * @details This hook is invoked immediately after the stack initialization
+ *          and before the DATA and BSS segments initialization. The
+ *          default behavior is to do nothing.
+ * @note    This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak))
+#endif
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+void __early_init(void) {}
+/*lint -restore*/
+
+/**
+ * @brief   Late initialization.
+ * @details This hook is invoked after the DATA and BSS segments
+ *          initialization and before any static constructor. The
+ *          default behavior is to do nothing.
+ * @note    This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak))
+#endif
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+void __late_init(void) {}
+/*lint -restore*/
+
+/**
+ * @brief   Default @p main() function exit handler.
+ * @details This handler is invoked or the @p main() function exit. The
+ *          default behavior is to enter an infinite loop.
+ * @note    This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((noreturn, weak))
+#endif
+/*lint -save -e9075 [8.4] All symbols are invoked from asm context.*/
+void __default_exit(void) {
+/*lint -restore*/
+
+  while (true) {
+  }
+}
+
+/** @} */
diff --git a/os/common/startup/ARMCAx-TZ/compilers/GCC/ld/SAMA5D2.ld b/os/common/startup/ARMCAx-TZ/compilers/GCC/ld/SAMA5D2.ld
new file mode 100755
index 000000000..aacf3aa5c
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/compilers/GCC/ld/SAMA5D2.ld
@@ -0,0 +1,43 @@
+/*
+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * SAMA5D2 memory setup in trusted mode.
+ */
+MEMORY
+{
+    flash : org = 0x00200000, len = 64k
+    ram0  : org = 0x00210000, len = 64k
+    ram1  : org = 0x00000000, len = 0
+    ram2  : org = 0x00000000, len = 0
+    ram3  : org = 0x00000000, len = 0
+    ram4  : org = 0x00000000, len = 0
+    ram5  : org = 0x00000000, len = 0
+    ram6  : org = 0x00000000, len = 0
+    ram7  : org = 0x00000000, len = 0
+}
+
+/* RAM region to be used for stacks. This stack accommodates the processing
+   of all exceptions and interrupts*/
+REGION_ALIAS("STACKS_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+INCLUDE rules.ld
diff --git a/os/common/startup/ARMCAx-TZ/compilers/GCC/ld/rules.ld b/os/common/startup/ARMCAx-TZ/compilers/GCC/ld/rules.ld
new file mode 100644
index 000000000..ac4e969bd
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/compilers/GCC/ld/rules.ld
@@ -0,0 +1,223 @@
+/*
+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+__stacks_total_size__	    = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__;
+
+__ram0_start__          = ORIGIN(ram0);
+__ram0_size__           = LENGTH(ram0);
+__ram0_end__            = __ram0_start__ + __ram0_size__;
+__ram1_start__          = ORIGIN(ram1);
+__ram1_size__           = LENGTH(ram1);
+__ram1_end__            = __ram1_start__ + __ram1_size__;
+__ram2_start__          = ORIGIN(ram2);
+__ram2_size__           = LENGTH(ram2);
+__ram2_end__            = __ram2_start__ + __ram2_size__;
+__ram3_start__          = ORIGIN(ram3);
+__ram3_size__           = LENGTH(ram3);
+__ram3_end__            = __ram3_start__ + __ram3_size__;
+__ram4_start__          = ORIGIN(ram4);
+__ram4_size__           = LENGTH(ram4);
+__ram4_end__            = __ram4_start__ + __ram4_size__;
+__ram5_start__          = ORIGIN(ram5);
+__ram5_size__           = LENGTH(ram5);
+__ram5_end__            = __ram5_start__ + __ram5_size__;
+__ram6_start__          = ORIGIN(ram6);
+__ram6_size__           = LENGTH(ram6);
+__ram6_end__            = __ram6_start__ + __ram6_size__;
+__ram7_start__          = ORIGIN(ram7);
+__ram7_size__           = LENGTH(ram7);
+__ram7_end__            = __ram7_start__ + __ram7_size__;
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    . = 0;
+    _text = .;
+
+    startup : ALIGN(16) SUBALIGN(16)
+    {
+        KEEP(*(.vectors))
+        KEEP(*(.boot))
+    } > flash
+
+    constructors : ALIGN(4) SUBALIGN(4)
+    {
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+    } > flash
+
+    destructors : ALIGN(4) SUBALIGN(4)
+    {
+        PROVIDE(__fini_array_start = .);
+        KEEP(*(.fini_array))
+        KEEP(*(SORT(.fini_array.*)))
+        PROVIDE(__fini_array_end = .);
+    } > flash
+
+    .text : ALIGN(16) SUBALIGN(16)
+    {
+        *(.text)
+        *(.text.*)
+        *(.rodata)
+        *(.rodata.*)
+        *(.glue_7t)
+        *(.glue_7)
+        *(.gcc*)
+    } > flash
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > flash
+
+    .ARM.exidx : {
+        PROVIDE(__exidx_start = .);
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        PROVIDE(__exidx_end = .);
+     } > flash
+
+    .eh_frame_hdr :
+    {
+        *(.eh_frame_hdr)
+    } > flash
+
+    .eh_frame : ONLY_IF_RO
+    {
+        *(.eh_frame)
+    } > flash
+    
+    .textalign : ONLY_IF_RO
+    {
+        . = ALIGN(8);
+    } > flash
+
+    . = ALIGN(4);
+    _etext = .;
+    _textdata = _etext;
+
+    .stacks :
+    {
+        . = ALIGN(8);
+        __stacks_base__ = .;
+        __main_thread_stack_base__ = .;
+        . += __stacks_total_size__;
+        . = ALIGN(8);
+        __stacks_end__ = .;
+    } > STACKS_RAM
+
+    .data : ALIGN(4)
+    {
+        . = ALIGN(4);
+        PROVIDE(_data = .);
+        *(.data)
+        *(.data.*)
+        *(.ramtext)
+        . = ALIGN(4);
+        PROVIDE(_edata = .);
+    } > DATA_RAM AT > flash
+
+    .bss : ALIGN(4)
+    {
+        . = ALIGN(4);
+        PROVIDE(_bss_start = .);
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        PROVIDE(_bss_end = .);
+        PROVIDE(end = .);
+    } > BSS_RAM    
+
+    .ram0 (NOLOAD) : ALIGN(4)
+    {
+        . = ALIGN(4);
+        *(.ram0)
+        *(.ram0.*)
+        . = ALIGN(4);
+        __ram0_free__ = .;
+    } > ram0
+
+    .ram1 (NOLOAD) : ALIGN(4)
+    {
+        . = ALIGN(4);
+        *(.ram1)
+        *(.ram1.*)
+        . = ALIGN(4);
+        __ram1_free__ = .;
+    } > ram1
+
+    .ram2 (NOLOAD) : ALIGN(4)
+    {
+        . = ALIGN(4);
+        *(.ram2)
+        *(.ram2.*)
+        . = ALIGN(4);
+        __ram2_free__ = .;
+    } > ram2
+
+    .ram3 (NOLOAD) : ALIGN(4)
+    {
+        . = ALIGN(4);
+        *(.ram3)
+        *(.ram3.*)
+        . = ALIGN(4);
+        __ram3_free__ = .;
+    } > ram3
+
+    .ram4 (NOLOAD) : ALIGN(4)
+    {
+        . = ALIGN(4);
+        *(.ram4)
+        *(.ram4.*)
+        . = ALIGN(4);
+        __ram4_free__ = .;
+    } > ram4
+
+    .ram5 (NOLOAD) : ALIGN(4)
+    {
+        . = ALIGN(4);
+        *(.ram5)
+        *(.ram5.*)
+        . = ALIGN(4);
+        __ram5_free__ = .;
+    } > ram5
+
+    .ram6 (NOLOAD) : ALIGN(4)
+    {
+        . = ALIGN(4);
+        *(.ram6)
+        *(.ram6.*)
+        . = ALIGN(4);
+        __ram6_free__ = .;
+    } > ram6
+
+    .ram7 (NOLOAD) : ALIGN(4)
+    {
+        . = ALIGN(4);
+        *(.ram7)
+        *(.ram7.*)
+        . = ALIGN(4);
+        __ram7_free__ = .;
+    } > ram7
+}
+
+/* Heap default boundaries, it is defaulted to be the non-used part
+   of ram0 region.*/
+__heap_base__   = __ram0_free__;
+__heap_end__    = __ram0_end__;
diff --git a/os/common/startup/ARMCAx-TZ/compilers/GCC/mk/startup_sama5d2.mk b/os/common/startup/ARMCAx-TZ/compilers/GCC/mk/startup_sama5d2.mk
new file mode 100644
index 000000000..cafddb6b1
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/compilers/GCC/mk/startup_sama5d2.mk
@@ -0,0 +1,11 @@
+# List of the ChibiOS generic SAMA5D2 file.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCAx-TZ/compilers/GCC/crt1.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/boot.S \
+             $(CHIBIOS)/os/common/startup/ARMCAx-TZ/compilers/GCC/vectors.S \
+             $(CHIBIOS)/os/common/startup/ARMCAx-TZ/compilers/GCC/crt0.S
+
+STARTUPINC = ${CHIBIOS}/os/common/startup/ARMCAx-TZ/devices/SAMA5D2 \
+             $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core_A/Include 
+
+STARTUPLD  = ${CHIBIOS}/os/common/startup/ARMCAx-TZ/compilers/GCC/ld
diff --git a/os/common/startup/ARMCAx-TZ/compilers/GCC/rules.mk b/os/common/startup/ARMCAx-TZ/compilers/GCC/rules.mk
new file mode 100644
index 000000000..0b98a5334
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/compilers/GCC/rules.mk
@@ -0,0 +1,322 @@
+# ARM Cortex-Mx common makefile scripts and rules.
+
+##############################################################################
+# Processing options coming from the upper Makefile.
+#
+
+# Compiler options
+OPT = $(USE_OPT)
+COPT = $(USE_COPT)
+CPPOPT = $(USE_CPPOPT)
+
+# Garbage collection
+ifeq ($(USE_LINK_GC),yes)
+  OPT += -ffunction-sections -fdata-sections -fno-common
+  LDOPT := ,--gc-sections
+else
+  LDOPT :=
+endif
+
+# Linker extra options
+ifneq ($(USE_LDOPT),)
+  LDOPT := $(LDOPT),$(USE_LDOPT)
+endif
+
+# Link time optimizations
+ifeq ($(USE_LTO),yes)
+  OPT += -flto
+endif
+
+# Undefined state stack size
+ifeq ($(USE_UND_STACKSIZE),)
+  LDOPT := $(LDOPT),--defsym=__und_stack_size__=8
+else
+  LDOPT := $(LDOPT),--defsym=__und_stack_size__=$(USE_UND_STACKSIZE)
+endif
+
+# Abort stack size
+ifeq ($(USE_ABT_STACKSIZE),)
+  LDOPT := $(LDOPT),--defsym=__abt_stack_size__=8
+else
+  LDOPT := $(LDOPT),--defsym=__abt_stack_size__=$(USE_ABT_STACKSIZE)
+endif
+
+# FIQ stack size
+ifeq ($(USE_FIQ_STACKSIZE),)
+  LDOPT := $(LDOPT),--defsym=__fiq_stack_size__=64
+else
+  LDOPT := $(LDOPT),--defsym=__fiq_stack_size__=$(USE_FIQ_STACKSIZE)
+endif
+
+# IRQ stack size
+ifeq ($(USE_IRQ_STACKSIZE),)
+  LDOPT := $(LDOPT),--defsym=__irq_stack_size__=0x400
+else
+  LDOPT := $(LDOPT),--defsym=__irq_stack_size__=$(USE_IRQ_STACKSIZE)
+endif
+
+# Supervisor stack size
+ifeq ($(USE_SUPERVISOR_STACKSIZE),)
+  LDOPT := $(LDOPT),--defsym=__svc_stack_size__=8
+else
+  LDOPT := $(LDOPT),--defsym=__svc_stack_size__=$(USE_SUPERVISOR_STACKSIZE)
+endif
+
+# System stack size
+ifeq ($(USE_SYSTEM_STACKSIZE),)
+  LDOPT := $(LDOPT),--defsym=__sys_stack_size__=0x400
+else
+  LDOPT := $(LDOPT),--defsym=__sys_stack_size__=$(USE_SYSTEM_STACKSIZE)
+endif
+
+# Output directory and files
+ifeq ($(BUILDDIR),)
+  BUILDDIR = build
+endif
+ifeq ($(BUILDDIR),.)
+  BUILDDIR = build
+endif
+
+# Dependencies directory
+ifeq ($(DEPDIR),)
+  DEPDIR = .dep
+endif
+ifeq ($(DEPDIR),.)
+  DEPDIR = .dep
+endif
+
+OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \
+           $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp \
+           $(BUILDDIR)/$(PROJECT).list
+
+# Source files groups and paths
+ifeq ($(USE_THUMB),yes)
+  TCSRC += $(CSRC)
+  TCPPSRC += $(CPPSRC)
+else
+  ACSRC += $(CSRC)
+  ACPPSRC += $(CPPSRC)
+endif
+ASRC      = $(ACSRC) $(ACPPSRC)
+TSRC      = $(TCSRC) $(TCPPSRC)
+SRCPATHS  = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC)))
+
+# Various directories
+OBJDIR    = $(BUILDDIR)/obj
+LSTDIR    = $(BUILDDIR)/lst
+
+# Object files groups
+ACOBJS    = $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o)))
+ACPPOBJS  = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o)))
+TCOBJS    = $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o)))
+TCPPOBJS  = $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o)))
+ASMOBJS   = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
+ASMXOBJS  = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
+OBJS      = $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS)
+
+# Paths
+IINCDIR   = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
+LLIBDIR   = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
+
+# Macros
+DEFS      = $(DDEFS) $(UDEFS)
+ADEFS     = $(DADEFS) $(UADEFS)
+
+# Libs
+LIBS      = $(DLIBS) $(ULIBS)
+
+# Various settings
+MCFLAGS   = -mcpu=$(MCU)
+ODFLAGS   = -x --syms
+ASFLAGS   = $(MCFLAGS) $(OPT) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
+ASXFLAGS  = $(MCFLAGS) $(OPT) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
+CFLAGS    = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
+CPPFLAGS  = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
+LDFLAGS   = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH)/ld,--script=$(LDSCRIPT)$(LDOPT)
+
+# Thumb interwork enabled only if needed because it kills performance.
+ifneq ($(strip $(TSRC)),)
+  CFLAGS   += -DTHUMB_PRESENT
+  CPPFLAGS += -DTHUMB_PRESENT
+  ASFLAGS  += -DTHUMB_PRESENT
+  ASXFLAGS += -DTHUMB_PRESENT
+  ifneq ($(strip $(ASRC)),)
+    # Mixed ARM and THUMB mode.
+    CFLAGS   += -mthumb-interwork
+    CPPFLAGS += -mthumb-interwork
+    ASFLAGS  += -mthumb-interwork
+    ASXFLAGS += -mthumb-interwork
+    LDFLAGS  += -mthumb-interwork
+  else
+    # Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly.
+    CFLAGS   += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING
+    CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING
+    ASFLAGS  += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb
+    ASXFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb
+    LDFLAGS  += -mno-thumb-interwork -mthumb
+  endif
+else
+  # Pure ARM mode
+  CFLAGS   += -mno-thumb-interwork
+  CPPFLAGS += -mno-thumb-interwork
+  ASFLAGS  += -mno-thumb-interwork
+  ASXFLAGS += -mno-thumb-interwork
+  LDFLAGS  += -mno-thumb-interwork
+endif
+
+# Generate dependency information
+ASFLAGS  += -MD -MP -MF $(DEPDIR)/$(@F).d
+ASXFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+CFLAGS   += -MD -MP -MF $(DEPDIR)/$(@F).d
+CPPFLAGS += -MD -MP -MF $(DEPDIR)/$(@F).d
+
+# Paths where to search for sources
+VPATH     = $(SRCPATHS)
+
+#
+# Makefile rules
+#
+
+all: PRE_MAKE_ALL_RULE_HOOK $(OBJS) $(OUTFILES) POST_MAKE_ALL_RULE_HOOK
+
+PRE_MAKE_ALL_RULE_HOOK:
+
+POST_MAKE_ALL_RULE_HOOK:
+
+$(OBJS): | $(BUILDDIR) $(OBJDIR) $(LSTDIR)
+
+$(BUILDDIR):
+ifneq ($(USE_VERBOSE_COMPILE),yes)
+	@echo Compiler Options
+	@echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o
+	@echo
+endif
+	@mkdir -p $(BUILDDIR)
+
+$(OBJDIR):
+	@mkdir -p $(OBJDIR)
+
+$(LSTDIR):
+	@mkdir -p $(LSTDIR)
+
+$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+else
+	@echo Compiling $(<F)
+	@$(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(TCPPOBJS) : $(OBJDIR)/%.o : %.cpp $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+else
+	@echo Compiling $(<F)
+	@$(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ACOBJS) : $(OBJDIR)/%.o : %.c $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+else
+	@echo Compiling $(<F)
+	@$(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(TCOBJS) : $(OBJDIR)/%.o : %.c $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+else
+	@echo Compiling $(<F)
+	@$(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMOBJS) : $(OBJDIR)/%.o : %.s $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+else
+	@echo Compiling $(<F)
+	@$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMXOBJS) : $(OBJDIR)/%.o : %.S $(MAKEFILE_LIST)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+else
+	@echo Compiling $(<F)
+	@$(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(BUILDDIR)/$(PROJECT).elf: $(OBJS) $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+else
+	@echo Linking $@
+	@$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+endif
+
+%.hex: %.elf
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	$(HEX) $< $@
+else
+	@echo Creating $@
+	@$(HEX) $< $@
+endif
+
+%.bin: %.elf
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	$(BIN) $< $@
+else
+	@echo Creating $@
+	@$(BIN) $< $@
+endif
+
+%.dmp: %.elf
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	$(OD) $(ODFLAGS) $< > $@
+	$(SZ) $<
+else
+	@echo Creating $@
+	@$(OD) $(ODFLAGS) $< > $@
+	@echo
+	@$(SZ) $<
+endif
+
+%.list: %.elf
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	$(OD) -S $< > $@
+else
+	@echo Creating $@
+	@$(OD) -S $< > $@
+	@echo
+	@echo Done
+endif
+
+lib: $(OBJS) $(BUILDDIR)/lib$(PROJECT).a
+
+$(BUILDDIR)/lib$(PROJECT).a: $(OBJS)
+	@$(AR) -r $@ $^
+	@echo
+	@echo Done
+
+clean: CLEAN_RULE_HOOK
+	@echo Cleaning
+	-rm -fR $(DEPDIR) $(BUILDDIR)
+	@echo
+	@echo Done
+
+CLEAN_RULE_HOOK:
+
+#
+# Include the dependency files, should be the last of the makefile
+#
+-include $(shell mkdir $(DEPDIR) 2>/dev/null) $(wildcard $(DEPDIR)/*)
+
+# *** EOF ***
diff --git a/os/common/startup/ARMCAx-TZ/compilers/GCC/vectors.S b/os/common/startup/ARMCAx-TZ/compilers/GCC/vectors.S
new file mode 100644
index 000000000..e582678db
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/compilers/GCC/vectors.S
@@ -0,0 +1,104 @@
+/*
+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    ARM/compilers/GCC/vectors.s
+ * @brief   Interrupt vectors for ARM devices.
+ *
+ * @defgroup ARM_VECTORS ARM Exception Vectors
+ * @{
+ */
+
+#if defined(__DOXYGEN__)
+/**
+ * @brief   Unhandled exceptions handler.
+ * @details Any undefined exception vector points to this function by default.
+ *          This function simply stops the system into an infinite loop.
+ * @note    The default implementation is a weak symbol, the application
+ *          can override the default implementation.
+ *
+ * @notapi
+ */
+void _unhandled_exception(void) {}
+#endif
+
+#if !defined(__DOXYGEN__)
+
+                .section .vectors, "ax"
+                .code   32
+                .balign 4
+
+/*
+ * System entry points.
+ */
+                .global _start
+_start:
+                ldr     pc, _reset
+                ldr     pc, _undefined
+                ldr     pc, _swi
+                ldr     pc, _prefetch
+                ldr     pc, _abort
+                nop
+                ldr     pc, _irq
+                ldr     pc, _fiq
+
+_reset:
+                .word   Boot_Handler
+_undefined:
+                .word   Und_Handler
+_swi:
+                .word   Swi_Handler
+_prefetch:
+                .word   Prefetch_Handler
+_abort:
+                .word   Abort_Handler
+_fiq:
+                .word   Fiq_Handler
+_irq:
+                .word   Irq_Handler
+
+/*
+ * Default exceptions handlers. The handlers are declared weak in order to be
+ * replaced by the real handling code. Everything is defaulted to an infinite
+ * loop.
+ */
+                .weak   Reset_Handler
+Reset_Handler:
+                .weak   Und_Handler
+Und_Handler:
+                .weak   Swi_Handler
+Swi_Handler:
+                .weak   Prefetch_Handler
+Prefetch_Handler:
+                .weak   Abort_Handler
+Abort_Handler:
+                .weak   Fiq_Handler
+Fiq_Handler:
+                .weak   Irq_Handler
+Irq_Handler:
+                .weak   _unhandled_exception
+_unhandled_exception:
+                b       _unhandled_exception
+/*
+ * Default boot handler. Jump to Reset_Handler.
+ */
+                .section .boot, "ax"
+                .weak	Boot_Handler
+Boot_Handler:
+                b       Reset_Handler
+#endif
+
+/** @} */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/armparams.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/armparams.h
new file mode 100755
index 000000000..29e6613fe
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/armparams.h
@@ -0,0 +1,92 @@
+/*
+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    SAMA5D2/armparams.h
+ * @brief   ARM parameters for the SAMA5D2x.
+ *
+ * @defgroup ARM_SAMA5D2x Specific Parameters
+ * @ingroup ARM_SPECIFIC
+ * @details This file contains the ARM specific parameters for the
+ *          SAMA5D2x platform.
+ * @{
+ */
+
+#ifndef ARMPARAMS_H
+#define ARMPARAMS_H
+
+/**
+ * @brief   ARM core model.
+ */
+#define ARM_CORE                ARM_CORE_CORTEX_A5
+
+/**
+ * @brief   Cortex core model.
+ */
+#define CORTEX_MODEL            5
+
+/**
+ * @brief   Thumb-capable.
+ */
+#define ARM_SUPPORTS_THUMB      1
+
+/**
+ * @brief   Thumb2-capable.
+ */
+#define ARM_SUPPORTS_THUMB2     1
+
+/**
+ * @brief   VFPv4-D16 FPU.
+ */
+#define TARGET_FEATURE_EXTENSION_REGISTER_COUNT    16
+
+/**
+ * @brief   Implementation of the wait-for-interrupt state enter.
+ */
+#define ARM_WFI_IMPL            asm volatile ("wfi")
+
+#if !defined(_FROM_ASM_) || defined(__DOXYGEN__)
+/* If the device type is not externally defined, for example from the Makefile,
+   then a file named board.h is included. This file must contain a device
+   definition compatible with the vendor include file.*/
+#if !defined (SAMA5D21) && !defined (SAMA5D22) &&  !defined (SAMA5D23) &&   \
+    !defined (SAMA5D24) && !defined (SAMA5D25) &&  !defined (SAMA5D26) &&   \
+    !defined (SAMA5D27) && !defined (SAMA5D28)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+   from this header because we need this file to be usable also from
+   assembler source files. We verify that the info matches instead.*/
+#include "sama5d2x.h"
+
+/*lint -save -e9029 [10.4] Signedness comes from external files, it is
+  unpredictable but gives no problems.*/
+#if CORTEX_MODEL != __CORTEX_A
+#error "CMSIS __CORTEX_A mismatch"
+#endif
+
+/**
+ * @brief   Address of the IRQ vector register in the interrupt controller.
+ */
+#define ARM_IRQ_VECTOR_REG      0xF803C010U
+#else
+#define ARM_IRQ_VECTOR_REG      0xF803C010
+
+#endif
+#endif /* ARMPARAMS_H */
+
+/** @} */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/boot.S b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/boot.S
new file mode 100644
index 000000000..2b089a582
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/boot.S
@@ -0,0 +1,97 @@
+/*
+    ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    SAMA5D2/boot_tz.S
+ * @brief   SAMA5D2 boot-related code managing the trusted zone.
+ *
+ * @addtogroup SAMA5D2_BOOT
+ * @{
+ */
+#if !defined(__DOXYGEN__)
+
+                .set    SCR_NS,         0x01
+                .set    SCR_IRQ,        0x02
+                .set    SCR_FIQ,        0x04
+                .set    SCR_EA,         0x08
+                .set    SCR_FW,         0x10
+                .set    SCR_AW,         0x20
+                .set    AIC_REDIR_KEY,  0x5B6C0E26 << 1
+                .set    SFR_SN1, 	    0xF8030050
+                .set	SFR_AICREDIR,   0xF8030054
+                .set    SFR_L2CC_HRAMC, 0xF8030058
+                .set    L2CC_CR,        0x00A00100
+                .set    SCR_RESET_VAL,  (SCR_EA|SCR_IRQ)
+
+                .section .boot
+                .code   32
+                .balign 4
+/*
+ * Boot initialization code
+ */
+				.global Boot_Handler
+Boot_Handler:
+                /*
+                 * Set VBAR to system vectors table
+                 * Set MVBAR to monitor vectors table
+                 */
+                ldr     r0, =_start
+                mcr     p15, 0, r0, c12, c0, 0
+                ldr     r0, =_monitor_vectors
+                mcr     p15, 0, r0, c12, c0, 1
+                /*
+                 * Do not redirect secure interrupts to AIC
+                 */
+				ldr     r0, =AIC_REDIR_KEY
+				ldr     r1, =SFR_SN1
+				ldr     r1, [r1]
+				eor     r0, r0, r1
+				bic     r0, r0, #0x1
+				ldr     r1, =SFR_AICREDIR
+				str     r0, [r1]
+                /*
+                 * Reset SCTLR Settings
+                 */
+                mrc     p15, 0, r0, c1, c0, 0       // Read CP15 System Control register
+                bic     r0, r0, #(0x1 << 12)        // Clear I bit 12 to disable I Cache
+                bic     r0, r0, #(0x1 <<  2)        // Clear C bit  2 to disable D Cache
+                bic     r0, r0, #0x1                // Clear M bit  0 to disable MMU
+                bic     r0, r0, #(0x1 << 11)        // Clear Z bit 11 to disable branch prediction
+                bic     r0, r0, #(0x1 << 13)        // Clear V bit 13 to disable hivecs
+                mcr     p15, 0, r0, c1, c0, 0       // Write value back to CP15 System Control register
+                isb
+                /*
+                 * Turn off L2Cache
+                 */
+                bic     r0, r0, #0x1
+                ldr     r1, =L2CC_CR
+                str     r0, [r1]
+                /*
+                 * Configure the L2 cache to be used as an internal SRAM
+                 */
+                bic     r0, r0, #0x1
+                ldr     r1, =SFR_L2CC_HRAMC
+                str     r0, [r1]
+                /*
+                 * Configure the intial catching of the interrupts
+                 */
+                ldr     r0, =SCR_RESET_VAL          // IRQ and ABT to monitor in secure mode
+                mrc     p15, 0, r0, c1, c1, 0
+
+                b       Reset_Handler
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_acc.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_acc.h
new file mode 100644
index 000000000..b0b302a4f
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_acc.h
@@ -0,0 +1,127 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_ACC_COMPONENT_
+#define _SAMA5D2_ACC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Analog Comparator Controller */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_ACC Analog Comparator Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Acc hardware registers */
+typedef struct {
+  __O  uint32_t ACC_CR;        /**< \brief (Acc Offset: 0x00) Control Register */
+  __IO uint32_t ACC_MR;        /**< \brief (Acc Offset: 0x04) Mode Register */
+  __I  uint32_t Reserved1[7];
+  __O  uint32_t ACC_IER;       /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */
+  __O  uint32_t ACC_IDR;       /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */
+  __I  uint32_t ACC_IMR;       /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */
+  __I  uint32_t ACC_ISR;       /**< \brief (Acc Offset: 0x30) Interrupt Status Register */
+  __I  uint32_t Reserved2[24];
+  __IO uint32_t ACC_ACR;       /**< \brief (Acc Offset: 0x94) Analog Control Register */
+  __I  uint32_t Reserved3[19];
+  __IO uint32_t ACC_WPMR;      /**< \brief (Acc Offset: 0xE4) Write Protection Mode Register */
+  __I  uint32_t ACC_WPSR;      /**< \brief (Acc Offset: 0xE8) Write Protection Status Register */
+} Acc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */
+#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) Software Reset */
+/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */
+#define ACC_MR_SELMINUS_Pos 0
+#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) Selection for Minus Comparator Input */
+#define ACC_MR_SELMINUS(value) ((ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos)))
+#define   ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) Select TS */
+#define   ACC_MR_SELMINUS_ADVREF (0x1u << 0) /**< \brief (ACC_MR) Select ADVREF */
+#define   ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */
+#define   ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */
+#define   ACC_MR_SELMINUS_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AD0 */
+#define   ACC_MR_SELMINUS_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AD1 */
+#define   ACC_MR_SELMINUS_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AD2 */
+#define   ACC_MR_SELMINUS_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AD3 */
+#define ACC_MR_SELPLUS_Pos 4
+#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) Selection For Plus Comparator Input */
+#define ACC_MR_SELPLUS(value) ((ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos)))
+#define   ACC_MR_SELPLUS_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AD0 */
+#define   ACC_MR_SELPLUS_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AD1 */
+#define   ACC_MR_SELPLUS_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AD2 */
+#define   ACC_MR_SELPLUS_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AD3 */
+#define   ACC_MR_SELPLUS_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AD4 */
+#define   ACC_MR_SELPLUS_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AD5 */
+#define   ACC_MR_SELPLUS_AD6 (0x6u << 4) /**< \brief (ACC_MR) Select AD6 */
+#define   ACC_MR_SELPLUS_AD7 (0x7u << 4) /**< \brief (ACC_MR) Select AD7 */
+#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enable */
+#define   ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog comparator disabled. */
+#define   ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog comparator enabled. */
+#define ACC_MR_EDGETYP_Pos 9
+#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) Edge Type */
+#define ACC_MR_EDGETYP(value) ((ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos)))
+#define   ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) Only rising edge of comparator output */
+#define   ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) Falling edge of comparator output */
+#define   ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) Any edge of comparator output */
+#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) Invert Comparator Output */
+#define   ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog comparator output is directly processed. */
+#define   ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog comparator output is inverted prior to being processed. */
+#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) Selection Of Fault Source */
+#define   ACC_MR_SELFS_CE (0x0u << 13) /**< \brief (ACC_MR) The CE flag is used to drive the FAULT output. */
+#define   ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */
+#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */
+#define   ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) The FAULT output is tied to 0. */
+#define   ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */
+/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */
+#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */
+/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */
+#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */
+/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */
+/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */
+#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge (cleared on read) */
+#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */
+#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) Flag Mask */
+/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */
+#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current Selection */
+#define   ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) Low-power option. */
+#define   ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) High-speed option. */
+#define ACC_ACR_HYST_Pos 1
+#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) Hysteresis Selection */
+#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)))
+/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protection Mode Register -------- */
+#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protection Enable */
+#define ACC_WPMR_WPKEY_Pos 8
+#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protection Key */
+#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)))
+#define   ACC_WPMR_WPKEY_PASSWD (0x414343u << 8) /**< \brief (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
+/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protection Status Register -------- */
+#define ACC_WPSR_WPVS (0x1u << 0) /**< \brief (ACC_WPSR) Write Protection Violation Status */
+
+/*@}*/
+
+#endif /* _SAMA5D2_ACC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_adc.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_adc.h
new file mode 100644
index 000000000..49e6b488b
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_adc.h
@@ -0,0 +1,629 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_ADC_COMPONENT_
+#define _SAMA5D2_ADC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Analog-to-Digital Converter */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_ADC Analog-to-Digital Converter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Adc hardware registers */
+typedef struct {
+  __O  uint32_t ADC_CR;       /**< \brief (Adc Offset: 0x00) Control Register */
+  __IO uint32_t ADC_MR;       /**< \brief (Adc Offset: 0x04) Mode Register */
+  __IO uint32_t ADC_SEQR1;    /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */
+  __IO uint32_t ADC_SEQR2;    /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */
+  __O  uint32_t ADC_CHER;     /**< \brief (Adc Offset: 0x10) Channel Enable Register */
+  __O  uint32_t ADC_CHDR;     /**< \brief (Adc Offset: 0x14) Channel Disable Register */
+  __I  uint32_t ADC_CHSR;     /**< \brief (Adc Offset: 0x18) Channel Status Register */
+  __I  uint32_t Reserved1[1];
+  __I  uint32_t ADC_LCDR;     /**< \brief (Adc Offset: 0x20) Last Converted Data Register */
+  __O  uint32_t ADC_IER;      /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */
+  __O  uint32_t ADC_IDR;      /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */
+  __I  uint32_t ADC_IMR;      /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */
+  __I  uint32_t ADC_ISR;      /**< \brief (Adc Offset: 0x30) Interrupt Status Register */
+  __IO uint32_t ADC_LCTMR;    /**< \brief (Adc Offset: 0x34) Last Channel Trigger Mode Register */
+  __IO uint32_t ADC_LCCWR;    /**< \brief (Adc Offset: 0x38) Last Channel Compare Window Register */
+  __I  uint32_t ADC_OVER;     /**< \brief (Adc Offset: 0x3C) Overrun Status Register */
+  __IO uint32_t ADC_EMR;      /**< \brief (Adc Offset: 0x40) Extended Mode Register */
+  __IO uint32_t ADC_CWR;      /**< \brief (Adc Offset: 0x44) Compare Window Register */
+  __IO uint32_t ADC_CGR;      /**< \brief (Adc Offset: 0x48) Channel Gain Register */
+  __IO uint32_t ADC_COR;      /**< \brief (Adc Offset: 0x4C) Channel Offset Register */
+  __I  uint32_t ADC_CDR[12];  /**< \brief (Adc Offset: 0x50) Channel Data Registers */
+  __I  uint32_t Reserved2[5];
+  __IO uint32_t ADC_ACR;      /**< \brief (Adc Offset: 0x94) Analog Control Register */
+  __I  uint32_t Reserved3[6];
+  __IO uint32_t ADC_TSMR;     /**< \brief (Adc Offset: 0xB0) Touchscreen Mode Register */
+  __I  uint32_t ADC_XPOSR;    /**< \brief (Adc Offset: 0xB4) Touchscreen X Position Register */
+  __I  uint32_t ADC_YPOSR;    /**< \brief (Adc Offset: 0xB8) Touchscreen Y Position Register */
+  __I  uint32_t ADC_PRESSR;   /**< \brief (Adc Offset: 0xBC) Touchscreen Pressure Register */
+  __IO uint32_t ADC_TRGR;     /**< \brief (Adc Offset: 0xC0) Trigger Register */
+  __I  uint32_t Reserved4[3];
+  __IO uint32_t ADC_COSR;     /**< \brief (Adc Offset: 0xD0) Correction Select Register */
+  __IO uint32_t ADC_CVR;      /**< \brief (Adc Offset: 0xD4) Correction Values Register */
+  __IO uint32_t ADC_CECR;     /**< \brief (Adc Offset: 0xD8) Channel Error Correction Register */
+  __I  uint32_t Reserved5[2];
+  __IO uint32_t ADC_WPMR;     /**< \brief (Adc Offset: 0xE4) Write Protection Mode Register */
+  __I  uint32_t ADC_WPSR;     /**< \brief (Adc Offset: 0xE8) Write Protection Status Register */
+  __I  uint32_t Reserved6[4];
+  __I  uint32_t ADC_VERSION;  /**< \brief (Adc Offset: 0xFC) Version Register */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
+#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */
+#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */
+#define ADC_CR_TSCALIB (0x1u << 2) /**< \brief (ADC_CR) Touchscreen Calibration */
+#define ADC_CR_CMPRST (0x1u << 4) /**< \brief (ADC_CR) Comparison Restart */
+/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */
+#define ADC_MR_TRGSEL_Pos 1
+#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */
+#define ADC_MR_TRGSEL(value) ((ADC_MR_TRGSEL_Msk & ((value) << ADC_MR_TRGSEL_Pos)))
+#define   ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) ADTRG */
+#define   ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIOA0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIOA1 */
+#define   ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIOA2 */
+#define   ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM event line 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM_even line 1 */
+#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */
+#define   ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC core and reference voltage circuitry are kept ON between conversions. */
+#define   ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The wake-up time can be modified by programming FWUP bit. */
+#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */
+#define   ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) If SLEEP is 1, then both ADC core and reference voltage circuitry are OFF between conversions */
+#define   ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) If SLEEP is 1, then Fast Wake-up Sleep mode: The voltage reference is ON between conversions and ADC core is OFF */
+#define ADC_MR_PRESCAL_Pos 8
+#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */
+#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))
+#define ADC_MR_STARTUP_Pos 16
+#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Startup Time */
+#define ADC_MR_STARTUP(value) ((ADC_MR_STARTUP_Msk & ((value) << ADC_MR_STARTUP_Pos)))
+#define   ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCCLK */
+#define   ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCCLK */
+#define   ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCCLK */
+#define   ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCCLK */
+#define   ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCCLK */
+#define   ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCCLK */
+#define   ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCCLK */
+#define   ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCCLK */
+#define   ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCCLK */
+#define   ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCCLK */
+#define   ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCCLK */
+#define   ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCCLK */
+#define   ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCCLK */
+#define   ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCCLK */
+#define   ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCCLK */
+#define   ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCCLK */
+#define ADC_MR_SETTLING_Pos 20
+#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */
+#define ADC_MR_SETTLING(value) ((ADC_MR_SETTLING_Msk & ((value) << ADC_MR_SETTLING_Pos)))
+#define   ADC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (ADC_MR) 3 periods of ADCCLK */
+#define   ADC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (ADC_MR) 5 periods of ADCCLK */
+#define   ADC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (ADC_MR) 9 periods of ADCCLK */
+#define   ADC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (ADC_MR) 17 periods of ADCCLK */
+#define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */
+#define   ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels. */
+#define   ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_CGR and ADC_COR registers. */
+#define ADC_MR_TRACKTIM_Pos 24
+#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */
+#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))
+#define ADC_MR_TRANSFER_Pos 28
+#define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) /**< \brief (ADC_MR) Hold Time */
+#define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos)))
+#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */
+#define   ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. */
+#define   ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert the same channel several times. */
+/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */
+#define ADC_SEQR1_USCH1_Pos 0
+#define ADC_SEQR1_USCH1_Msk (0xfu << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */
+#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))
+#define ADC_SEQR1_USCH2_Pos 4
+#define ADC_SEQR1_USCH2_Msk (0xfu << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */
+#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))
+#define ADC_SEQR1_USCH3_Pos 8
+#define ADC_SEQR1_USCH3_Msk (0xfu << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */
+#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))
+#define ADC_SEQR1_USCH4_Pos 12
+#define ADC_SEQR1_USCH4_Msk (0xfu << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */
+#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))
+#define ADC_SEQR1_USCH5_Pos 16
+#define ADC_SEQR1_USCH5_Msk (0xfu << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */
+#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))
+#define ADC_SEQR1_USCH6_Pos 20
+#define ADC_SEQR1_USCH6_Msk (0xfu << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */
+#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))
+#define ADC_SEQR1_USCH7_Pos 24
+#define ADC_SEQR1_USCH7_Msk (0xfu << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */
+#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))
+#define ADC_SEQR1_USCH8_Pos 28
+#define ADC_SEQR1_USCH8_Msk (0xfu << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */
+#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))
+/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */
+#define ADC_SEQR2_USCH9_Pos 0
+#define ADC_SEQR2_USCH9_Msk (0xfu << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */
+#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))
+#define ADC_SEQR2_USCH10_Pos 4
+#define ADC_SEQR2_USCH10_Msk (0xfu << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */
+#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))
+#define ADC_SEQR2_USCH11_Pos 8
+#define ADC_SEQR2_USCH11_Msk (0xfu << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */
+#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))
+/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
+#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
+#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
+#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
+#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
+#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
+#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
+#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
+#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
+#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */
+#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */
+#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */
+#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */
+/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
+#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */
+#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */
+#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */
+#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */
+#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */
+#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */
+#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */
+#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */
+#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */
+#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */
+#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */
+#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */
+/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
+#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
+#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
+#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
+#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
+#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
+#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
+#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
+#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
+#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */
+#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */
+#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */
+#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
+#define ADC_LCDR_LDATA_Pos 0
+#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */
+#define ADC_LCDR_CHNB_Pos 12
+#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */
+/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
+#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
+#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
+#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
+#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
+#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
+#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
+#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
+#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
+#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */
+#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */
+#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */
+#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */
+#define ADC_IER_VALUE_ (0x1u << 12) /**< \brief (ADC_IER)  */
+#define ADC_IER_LCCHG (0x1u << 19) /**< \brief (ADC_IER) Last Channel Change Interrupt Enable */
+#define ADC_IER_XRDY (0x1u << 20) /**< \brief (ADC_IER) Touchscreen Measure XPOS Ready Interrupt Enable */
+#define ADC_IER_YRDY (0x1u << 21) /**< \brief (ADC_IER) Touchscreen Measure YPOS Ready Interrupt Enable */
+#define ADC_IER_PRDY (0x1u << 22) /**< \brief (ADC_IER) Touchscreen Measure Pressure Ready Interrupt Enable */
+#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
+#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
+#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */
+#define ADC_IER_PEN (0x1u << 29) /**< \brief (ADC_IER) Pen Contact Interrupt Enable */
+#define ADC_IER_NOPEN (0x1u << 30) /**< \brief (ADC_IER) No Pen Contact Interrupt Enable */
+/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
+#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
+#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
+#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
+#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
+#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
+#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
+#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
+#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
+#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */
+#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */
+#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */
+#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */
+#define ADC_IDR_VALUE_ (0x1u << 12) /**< \brief (ADC_IDR)  */
+#define ADC_IDR_LCCHG (0x1u << 19) /**< \brief (ADC_IDR) Last Channel Change Interrupt Disable */
+#define ADC_IDR_XRDY (0x1u << 20) /**< \brief (ADC_IDR) Touchscreen Measure XPOS Ready Interrupt Disable */
+#define ADC_IDR_YRDY (0x1u << 21) /**< \brief (ADC_IDR) Touchscreen Measure YPOS Ready Interrupt Disable */
+#define ADC_IDR_PRDY (0x1u << 22) /**< \brief (ADC_IDR) Touchscreen Measure Pressure Ready Interrupt Disable */
+#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
+#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
+#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */
+#define ADC_IDR_PEN (0x1u << 29) /**< \brief (ADC_IDR) Pen Contact Interrupt Disable */
+#define ADC_IDR_NOPEN (0x1u << 30) /**< \brief (ADC_IDR) No Pen Contact Interrupt Disable */
+/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
+#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
+#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
+#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
+#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
+#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
+#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
+#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
+#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */
+#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */
+#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */
+#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */
+#define ADC_IMR_VALUE_ (0x1u << 12) /**< \brief (ADC_IMR)  */
+#define ADC_IMR_LCCHG (0x1u << 19) /**< \brief (ADC_IMR) Last Channel Change Interrupt Mask */
+#define ADC_IMR_XRDY (0x1u << 20) /**< \brief (ADC_IMR) Touchscreen Measure XPOS Ready Interrupt Mask */
+#define ADC_IMR_YRDY (0x1u << 21) /**< \brief (ADC_IMR) Touchscreen Measure YPOS Ready Interrupt Mask */
+#define ADC_IMR_PRDY (0x1u << 22) /**< \brief (ADC_IMR) Touchscreen Measure Pressure Ready Interrupt Mask */
+#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
+#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
+#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */
+#define ADC_IMR_PEN (0x1u << 29) /**< \brief (ADC_IMR) Pen Contact Interrupt Mask */
+#define ADC_IMR_NOPEN (0x1u << 30) /**< \brief (ADC_IMR) No Pen Contact Interrupt Mask */
+/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */
+#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 (automatically set / cleared) */
+#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 (automatically set / cleared) */
+#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 (automatically set / cleared) */
+#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 (automatically set / cleared) */
+#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 (automatically set / cleared) */
+#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 (automatically set / cleared) */
+#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 (automatically set / cleared) */
+#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 (automatically set / cleared) */
+#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 (automatically set / cleared) */
+#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 (automatically set / cleared) */
+#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 (automatically set / cleared) */
+#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 (automatically set / cleared) */
+#define ADC_ISR_VALUE_ (0x1u << 12) /**< \brief (ADC_ISR)  */
+#define ADC_ISR_LCCHG (0x1u << 19) /**< \brief (ADC_ISR) Last Channel Change (cleared on read) */
+#define ADC_ISR_XRDY (0x1u << 20) /**< \brief (ADC_ISR) Touchscreen XPOS Measure Ready (cleared on read) */
+#define ADC_ISR_YRDY (0x1u << 21) /**< \brief (ADC_ISR) Touchscreen YPOS Measure Ready (cleared on read) */
+#define ADC_ISR_PRDY (0x1u << 22) /**< \brief (ADC_ISR) Touchscreen Pressure Measure Ready (cleared on read) */
+#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready (automatically set / cleared) */
+#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error (cleared on read) */
+#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Event (cleared on read) */
+#define ADC_ISR_PEN (0x1u << 29) /**< \brief (ADC_ISR) Pen contact (cleared on read) */
+#define ADC_ISR_NOPEN (0x1u << 30) /**< \brief (ADC_ISR) No Pen Contact (cleared on read) */
+#define ADC_ISR_PENS (0x1u << 31) /**< \brief (ADC_ISR) Pen Detect Status */
+/* -------- ADC_LCTMR : (ADC Offset: 0x34) Last Channel Trigger Mode Register -------- */
+#define ADC_LCTMR_DUALTRIG (0x1u << 0) /**< \brief (ADC_LCTMR) Dual Trigger ON */
+#define ADC_LCTMR_CMPMOD_Pos 4
+#define ADC_LCTMR_CMPMOD_Msk (0x3u << ADC_LCTMR_CMPMOD_Pos) /**< \brief (ADC_LCTMR) Last Channel Comparison Mode */
+#define ADC_LCTMR_CMPMOD(value) ((ADC_LCTMR_CMPMOD_Msk & ((value) << ADC_LCTMR_CMPMOD_Pos)))
+#define   ADC_LCTMR_CMPMOD_LOW (0x0u << 4) /**< \brief (ADC_LCTMR) Generates an event when the converted data is lower than the low threshold of the window. */
+#define   ADC_LCTMR_CMPMOD_HIGH (0x1u << 4) /**< \brief (ADC_LCTMR) Generates an event when the converted data is higher than the high threshold of the window. */
+#define   ADC_LCTMR_CMPMOD_IN (0x2u << 4) /**< \brief (ADC_LCTMR) Generates an event when the converted data is in the comparison window. */
+#define   ADC_LCTMR_CMPMOD_OUT (0x3u << 4) /**< \brief (ADC_LCTMR) Generates an event when the converted data is out of the comparison window. */
+/* -------- ADC_LCCWR : (ADC Offset: 0x38) Last Channel Compare Window Register -------- */
+#define ADC_LCCWR_LOWTHRES_Pos 0
+#define ADC_LCCWR_LOWTHRES_Msk (0xfffu << ADC_LCCWR_LOWTHRES_Pos) /**< \brief (ADC_LCCWR) Low Threshold */
+#define ADC_LCCWR_LOWTHRES(value) ((ADC_LCCWR_LOWTHRES_Msk & ((value) << ADC_LCCWR_LOWTHRES_Pos)))
+#define ADC_LCCWR_HIGHTHRES_Pos 16
+#define ADC_LCCWR_HIGHTHRES_Msk (0xfffu << ADC_LCCWR_HIGHTHRES_Pos) /**< \brief (ADC_LCCWR) High Threshold */
+#define ADC_LCCWR_HIGHTHRES(value) ((ADC_LCCWR_HIGHTHRES_Msk & ((value) << ADC_LCCWR_HIGHTHRES_Pos)))
+/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */
+#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */
+#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */
+#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */
+#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */
+#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */
+#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */
+#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */
+#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */
+#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */
+#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */
+#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */
+#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */
+/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */
+#define ADC_EMR_CMPMODE_Pos 0
+#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */
+#define ADC_EMR_CMPMODE(value) ((ADC_EMR_CMPMODE_Msk & ((value) << ADC_EMR_CMPMODE_Pos)))
+#define   ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */
+#define   ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */
+#define   ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */
+#define   ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */
+#define ADC_EMR_CMPTYPE (0x1u << 2) /**< \brief (ADC_EMR) Comparison Type */
+#define   ADC_EMR_CMPTYPE_FLAG_ONLY (0x0u << 2) /**< \brief (ADC_EMR) Any conversion is performed and comparison function drives the COMPE flag. */
+#define   ADC_EMR_CMPTYPE_START_CONDITION (0x1u << 2) /**< \brief (ADC_EMR) Comparison conditions must be met to start the storage of all conversions until the CMPRST bit is set. */
+#define ADC_EMR_CMPSEL_Pos 4
+#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */
+#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))
+#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */
+#define ADC_EMR_CMPFILTER_Pos 12
+#define ADC_EMR_CMPFILTER_Msk (0x3u << ADC_EMR_CMPFILTER_Pos) /**< \brief (ADC_EMR) Compare Event Filtering */
+#define ADC_EMR_CMPFILTER(value) ((ADC_EMR_CMPFILTER_Msk & ((value) << ADC_EMR_CMPFILTER_Pos)))
+#define ADC_EMR_SRCCLK (0x1u << 21) /**< \brief (ADC_EMR) External Clock Selection */
+#define   ADC_EMR_SRCCLK_PERIPH_CLK (0x0u << 21) /**< \brief (ADC_EMR) The peripheral clock is the source for the ADC prescaler. */
+#define   ADC_EMR_SRCCLK_PMC_PCK (0x1u << 21) /**< \brief (ADC_EMR) PMC PCKx is the source clock for the ADC prescaler, thus the ADC clock can be independent of the core/peripheral clock. */
+#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) Tag of the ADC_LCDR */
+#define ADC_EMR_ADCMODE_Pos 28
+#define ADC_EMR_ADCMODE_Msk (0x3u << ADC_EMR_ADCMODE_Pos) /**< \brief (ADC_EMR) ADC Running Mode */
+#define ADC_EMR_ADCMODE(value) ((ADC_EMR_ADCMODE_Msk & ((value) << ADC_EMR_ADCMODE_Pos)))
+#define   ADC_EMR_ADCMODE_NORMAL (0x0u << 28) /**< \brief (ADC_EMR) Normal mode of operation. */
+#define   ADC_EMR_ADCMODE_OFFSET_ERROR (0x1u << 28) /**< \brief (ADC_EMR) Offset Error mode to measure the offset error. See Table 1-8. */
+#define   ADC_EMR_ADCMODE_GAIN_ERROR_HIGH (0x2u << 28) /**< \brief (ADC_EMR) Gain Error mode to measure the gain error. See Table 1-8. */
+#define   ADC_EMR_ADCMODE_GAIN_ERROR_LOW (0x3u << 28) /**< \brief (ADC_EMR) Gain Error mode to measure the gain error. See Table 1-8. */
+/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */
+#define ADC_CWR_LOWTHRES_Pos 0
+#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */
+#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))
+#define ADC_CWR_HIGHTHRES_Pos 16
+#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */
+#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))
+/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */
+#define ADC_CGR_GAIN0_Pos 0
+#define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) /**< \brief (ADC_CGR) Gain for Channel 0 */
+#define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos)))
+#define   ADC_CGR_GAIN0_SE1_DIFF0_5 (0x0u << 0) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN0_SE1_DIFF1 (0x1u << 0) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN0_SE2_DIFF2 (0x2u << 0) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN0_SE4_DIFF2 (0x3u << 0) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define ADC_CGR_GAIN1_Pos 2
+#define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) /**< \brief (ADC_CGR) Gain for Channel 1 */
+#define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos)))
+#define   ADC_CGR_GAIN1_SE1_DIFF0_5 (0x0u << 2) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN1_SE1_DIFF1 (0x1u << 2) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN1_SE2_DIFF2 (0x2u << 2) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN1_SE4_DIFF2 (0x3u << 2) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define ADC_CGR_GAIN2_Pos 4
+#define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) /**< \brief (ADC_CGR) Gain for Channel 2 */
+#define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos)))
+#define   ADC_CGR_GAIN2_SE1_DIFF0_5 (0x0u << 4) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN2_SE1_DIFF1 (0x1u << 4) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN2_SE2_DIFF2 (0x2u << 4) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN2_SE4_DIFF2 (0x3u << 4) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define ADC_CGR_GAIN3_Pos 6
+#define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) /**< \brief (ADC_CGR) Gain for Channel 3 */
+#define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos)))
+#define   ADC_CGR_GAIN3_SE1_DIFF0_5 (0x0u << 6) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN3_SE1_DIFF1 (0x1u << 6) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN3_SE2_DIFF2 (0x2u << 6) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN3_SE4_DIFF2 (0x3u << 6) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define ADC_CGR_GAIN4_Pos 8
+#define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) /**< \brief (ADC_CGR) Gain for Channel 4 */
+#define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos)))
+#define   ADC_CGR_GAIN4_SE1_DIFF0_5 (0x0u << 8) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN4_SE1_DIFF1 (0x1u << 8) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN4_SE2_DIFF2 (0x2u << 8) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN4_SE4_DIFF2 (0x3u << 8) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define ADC_CGR_GAIN5_Pos 10
+#define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) /**< \brief (ADC_CGR) Gain for Channel 5 */
+#define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos)))
+#define   ADC_CGR_GAIN5_SE1_DIFF0_5 (0x0u << 10) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN5_SE1_DIFF1 (0x1u << 10) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN5_SE2_DIFF2 (0x2u << 10) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN5_SE4_DIFF2 (0x3u << 10) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define ADC_CGR_GAIN6_Pos 12
+#define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) /**< \brief (ADC_CGR) Gain for Channel 6 */
+#define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos)))
+#define   ADC_CGR_GAIN6_SE1_DIFF0_5 (0x0u << 12) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN6_SE1_DIFF1 (0x1u << 12) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN6_SE2_DIFF2 (0x2u << 12) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN6_SE4_DIFF2 (0x3u << 12) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define ADC_CGR_GAIN7_Pos 14
+#define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) /**< \brief (ADC_CGR) Gain for Channel 7 */
+#define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos)))
+#define   ADC_CGR_GAIN7_SE1_DIFF0_5 (0x0u << 14) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN7_SE1_DIFF1 (0x1u << 14) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN7_SE2_DIFF2 (0x2u << 14) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN7_SE4_DIFF2 (0x3u << 14) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define ADC_CGR_GAIN8_Pos 16
+#define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) /**< \brief (ADC_CGR) Gain for Channel 8 */
+#define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos)))
+#define   ADC_CGR_GAIN8_SE1_DIFF0_5 (0x0u << 16) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN8_SE1_DIFF1 (0x1u << 16) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN8_SE2_DIFF2 (0x2u << 16) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN8_SE4_DIFF2 (0x3u << 16) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define ADC_CGR_GAIN9_Pos 18
+#define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) /**< \brief (ADC_CGR) Gain for Channel 9 */
+#define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos)))
+#define   ADC_CGR_GAIN9_SE1_DIFF0_5 (0x0u << 18) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN9_SE1_DIFF1 (0x1u << 18) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN9_SE2_DIFF2 (0x2u << 18) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN9_SE4_DIFF2 (0x3u << 18) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define ADC_CGR_GAIN10_Pos 20
+#define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) /**< \brief (ADC_CGR) Gain for Channel 10 */
+#define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos)))
+#define   ADC_CGR_GAIN10_SE1_DIFF0_5 (0x0u << 20) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN10_SE1_DIFF1 (0x1u << 20) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN10_SE2_DIFF2 (0x2u << 20) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN10_SE4_DIFF2 (0x3u << 20) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define ADC_CGR_GAIN11_Pos 22
+#define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) /**< \brief (ADC_CGR) Gain for Channel 11 */
+#define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos)))
+#define   ADC_CGR_GAIN11_SE1_DIFF0_5 (0x0u << 22) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN11_SE1_DIFF1 (0x1u << 22) /**< \brief (ADC_CGR) Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN11_SE2_DIFF2 (0x2u << 22) /**< \brief (ADC_CGR) Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+#define   ADC_CGR_GAIN11_SE4_DIFF2 (0x3u << 22) /**< \brief (ADC_CGR) Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1) */
+/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */
+#define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for Channel 0 */
+#define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for Channel 1 */
+#define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for Channel 2 */
+#define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for Channel 3 */
+#define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for Channel 4 */
+#define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for Channel 5 */
+#define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for Channel 6 */
+#define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for Channel 7 */
+#define ADC_COR_OFF8 (0x1u << 8) /**< \brief (ADC_COR) Offset for Channel 8 */
+#define ADC_COR_OFF9 (0x1u << 9) /**< \brief (ADC_COR) Offset for Channel 9 */
+#define ADC_COR_OFF10 (0x1u << 10) /**< \brief (ADC_COR) Offset for Channel 10 */
+#define ADC_COR_OFF11 (0x1u << 11) /**< \brief (ADC_COR) Offset for Channel 11 */
+#define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential Inputs for Channel 0 */
+#define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential Inputs for Channel 1 */
+#define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential Inputs for Channel 2 */
+#define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential Inputs for Channel 3 */
+#define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential Inputs for Channel 4 */
+#define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential Inputs for Channel 5 */
+#define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential Inputs for Channel 6 */
+#define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential Inputs for Channel 7 */
+#define ADC_COR_DIFF8 (0x1u << 24) /**< \brief (ADC_COR) Differential Inputs for Channel 8 */
+#define ADC_COR_DIFF9 (0x1u << 25) /**< \brief (ADC_COR) Differential Inputs for Channel 9 */
+#define ADC_COR_DIFF10 (0x1u << 26) /**< \brief (ADC_COR) Differential Inputs for Channel 10 */
+#define ADC_COR_DIFF11 (0x1u << 27) /**< \brief (ADC_COR) Differential Inputs for Channel 11 */
+/* -------- ADC_CDR0 : (ADC Offset: 0x50) Channel Data Register 0 -------- */
+#define ADC_CDR0_DATA_Pos 0
+#define ADC_CDR0_DATA_Msk (0xfffu << ADC_CDR0_DATA_Pos) /**< \brief (ADC_CDR0) Converted Data */
+/* -------- ADC_CDR1 : (ADC Offset: 0x54) Channel Data Register 1 -------- */
+#define ADC_CDR1_DATA_Pos 0
+#define ADC_CDR1_DATA_Msk (0xfffu << ADC_CDR1_DATA_Pos) /**< \brief (ADC_CDR1) Converted Data */
+/* -------- ADC_CDR2 : (ADC Offset: 0x58) Channel Data Register 2 -------- */
+#define ADC_CDR2_DATA_Pos 0
+#define ADC_CDR2_DATA_Msk (0xfffu << ADC_CDR2_DATA_Pos) /**< \brief (ADC_CDR2) Converted Data */
+/* -------- ADC_CDR3 : (ADC Offset: 0x5C) Channel Data Register 3 -------- */
+#define ADC_CDR3_DATA_Pos 0
+#define ADC_CDR3_DATA_Msk (0xfffu << ADC_CDR3_DATA_Pos) /**< \brief (ADC_CDR3) Converted Data */
+/* -------- ADC_CDR4 : (ADC Offset: 0x60) Channel Data Register 4 -------- */
+#define ADC_CDR4_DATA_Pos 0
+#define ADC_CDR4_DATA_Msk (0xfffu << ADC_CDR4_DATA_Pos) /**< \brief (ADC_CDR4) Converted Data */
+/* -------- ADC_CDR5 : (ADC Offset: 0x64) Channel Data Register 5 -------- */
+#define ADC_CDR5_DATA_Pos 0
+#define ADC_CDR5_DATA_Msk (0xfffu << ADC_CDR5_DATA_Pos) /**< \brief (ADC_CDR5) Converted Data */
+/* -------- ADC_CDR6 : (ADC Offset: 0x68) Channel Data Register 6 -------- */
+#define ADC_CDR6_DATA_Pos 0
+#define ADC_CDR6_DATA_Msk (0xfffu << ADC_CDR6_DATA_Pos) /**< \brief (ADC_CDR6) Converted Data */
+/* -------- ADC_CDR7 : (ADC Offset: 0x6C) Channel Data Register 7 -------- */
+#define ADC_CDR7_DATA_Pos 0
+#define ADC_CDR7_DATA_Msk (0xfffu << ADC_CDR7_DATA_Pos) /**< \brief (ADC_CDR7) Converted Data */
+/* -------- ADC_CDR8 : (ADC Offset: 0x70) Channel Data Register 8 -------- */
+#define ADC_CDR8_DATA_Pos 0
+#define ADC_CDR8_DATA_Msk (0xfffu << ADC_CDR8_DATA_Pos) /**< \brief (ADC_CDR8) Converted Data */
+/* -------- ADC_CDR9 : (ADC Offset: 0x74) Channel Data Register 9 -------- */
+#define ADC_CDR9_DATA_Pos 0
+#define ADC_CDR9_DATA_Msk (0xfffu << ADC_CDR9_DATA_Pos) /**< \brief (ADC_CDR9) Converted Data */
+/* -------- ADC_CDR10 : (ADC Offset: 0x78) Channel Data Register 10 -------- */
+#define ADC_CDR10_DATA_Pos 0
+#define ADC_CDR10_DATA_Msk (0xfffu << ADC_CDR10_DATA_Pos) /**< \brief (ADC_CDR10) Converted Data */
+/* -------- ADC_CDR11 : (ADC Offset: 0x7C) Channel Data Register 11 -------- */
+#define ADC_CDR11_DATA_Pos 0
+#define ADC_CDR11_DATA_Msk (0xfffu << ADC_CDR11_DATA_Pos) /**< \brief (ADC_CDR11) Converted Data */
+/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */
+#define ADC_ACR_PENDETSENS_Pos 0
+#define ADC_ACR_PENDETSENS_Msk (0x3u << ADC_ACR_PENDETSENS_Pos) /**< \brief (ADC_ACR) Pen Detection Sensitivity */
+#define ADC_ACR_PENDETSENS(value) ((ADC_ACR_PENDETSENS_Msk & ((value) << ADC_ACR_PENDETSENS_Pos)))
+/* -------- ADC_TSMR : (ADC Offset: 0xB0) Touchscreen Mode Register -------- */
+#define ADC_TSMR_TSMODE_Pos 0
+#define ADC_TSMR_TSMODE_Msk (0x3u << ADC_TSMR_TSMODE_Pos) /**< \brief (ADC_TSMR) Touchscreen Mode */
+#define ADC_TSMR_TSMODE(value) ((ADC_TSMR_TSMODE_Msk & ((value) << ADC_TSMR_TSMODE_Pos)))
+#define   ADC_TSMR_TSMODE_NONE (0x0u << 0) /**< \brief (ADC_TSMR) No Touchscreen */
+#define   ADC_TSMR_TSMODE_4_WIRE_NO_PM (0x1u << 0) /**< \brief (ADC_TSMR) 4-wire Touchscreen without pressure measurement */
+#define   ADC_TSMR_TSMODE_4_WIRE (0x2u << 0) /**< \brief (ADC_TSMR) 4-wire Touchscreen with pressure measurement */
+#define   ADC_TSMR_TSMODE_5_WIRE (0x3u << 0) /**< \brief (ADC_TSMR) 5-wire Touchscreen */
+#define ADC_TSMR_TSAV_Pos 4
+#define ADC_TSMR_TSAV_Msk (0x3u << ADC_TSMR_TSAV_Pos) /**< \brief (ADC_TSMR) Touchscreen Average */
+#define ADC_TSMR_TSAV(value) ((ADC_TSMR_TSAV_Msk & ((value) << ADC_TSMR_TSAV_Pos)))
+#define   ADC_TSMR_TSAV_NO_FILTER (0x0u << 4) /**< \brief (ADC_TSMR) No Filtering. Only one ADC conversion per measure */
+#define   ADC_TSMR_TSAV_AVG2CONV (0x1u << 4) /**< \brief (ADC_TSMR) Averages 2 ADC conversions */
+#define   ADC_TSMR_TSAV_AVG4CONV (0x2u << 4) /**< \brief (ADC_TSMR) Averages 4 ADC conversions */
+#define   ADC_TSMR_TSAV_AVG8CONV (0x3u << 4) /**< \brief (ADC_TSMR) Averages 8 ADC conversions */
+#define ADC_TSMR_TSFREQ_Pos 8
+#define ADC_TSMR_TSFREQ_Msk (0xfu << ADC_TSMR_TSFREQ_Pos) /**< \brief (ADC_TSMR) Touchscreen Frequency */
+#define ADC_TSMR_TSFREQ(value) ((ADC_TSMR_TSFREQ_Msk & ((value) << ADC_TSMR_TSFREQ_Pos)))
+#define ADC_TSMR_TSSCTIM_Pos 16
+#define ADC_TSMR_TSSCTIM_Msk (0xfu << ADC_TSMR_TSSCTIM_Pos) /**< \brief (ADC_TSMR) Touchscreen Switches Closure Time */
+#define ADC_TSMR_TSSCTIM(value) ((ADC_TSMR_TSSCTIM_Msk & ((value) << ADC_TSMR_TSSCTIM_Pos)))
+#define ADC_TSMR_NOTSDMA (0x1u << 22) /**< \brief (ADC_TSMR) No TouchScreen DMA */
+#define ADC_TSMR_PENDET (0x1u << 24) /**< \brief (ADC_TSMR) Pen Contact Detection Enable */
+#define ADC_TSMR_PENDBC_Pos 28
+#define ADC_TSMR_PENDBC_Msk (0xfu << ADC_TSMR_PENDBC_Pos) /**< \brief (ADC_TSMR) Pen Detect Debouncing Period */
+#define ADC_TSMR_PENDBC(value) ((ADC_TSMR_PENDBC_Msk & ((value) << ADC_TSMR_PENDBC_Pos)))
+/* -------- ADC_XPOSR : (ADC Offset: 0xB4) Touchscreen X Position Register -------- */
+#define ADC_XPOSR_XPOS_Pos 0
+#define ADC_XPOSR_XPOS_Msk (0xfffu << ADC_XPOSR_XPOS_Pos) /**< \brief (ADC_XPOSR) X Position */
+#define ADC_XPOSR_XSCALE_Pos 16
+#define ADC_XPOSR_XSCALE_Msk (0xfffu << ADC_XPOSR_XSCALE_Pos) /**< \brief (ADC_XPOSR) Scale of XPOS */
+/* -------- ADC_YPOSR : (ADC Offset: 0xB8) Touchscreen Y Position Register -------- */
+#define ADC_YPOSR_YPOS_Pos 0
+#define ADC_YPOSR_YPOS_Msk (0xfffu << ADC_YPOSR_YPOS_Pos) /**< \brief (ADC_YPOSR) Y Position */
+#define ADC_YPOSR_YSCALE_Pos 16
+#define ADC_YPOSR_YSCALE_Msk (0xfffu << ADC_YPOSR_YSCALE_Pos) /**< \brief (ADC_YPOSR) Scale of YPOS */
+/* -------- ADC_PRESSR : (ADC Offset: 0xBC) Touchscreen Pressure Register -------- */
+#define ADC_PRESSR_Z1_Pos 0
+#define ADC_PRESSR_Z1_Msk (0xfffu << ADC_PRESSR_Z1_Pos) /**< \brief (ADC_PRESSR) Data of Z1 Measurement */
+#define ADC_PRESSR_Z2_Pos 16
+#define ADC_PRESSR_Z2_Msk (0xfffu << ADC_PRESSR_Z2_Pos) /**< \brief (ADC_PRESSR) Data of Z2 Measurement */
+/* -------- ADC_TRGR : (ADC Offset: 0xC0) Trigger Register -------- */
+#define ADC_TRGR_TRGMOD_Pos 0
+#define ADC_TRGR_TRGMOD_Msk (0x7u << ADC_TRGR_TRGMOD_Pos) /**< \brief (ADC_TRGR) Trigger Mode */
+#define ADC_TRGR_TRGMOD(value) ((ADC_TRGR_TRGMOD_Msk & ((value) << ADC_TRGR_TRGMOD_Pos)))
+#define   ADC_TRGR_TRGMOD_NO_TRIGGER (0x0u << 0) /**< \brief (ADC_TRGR) No trigger, only software trigger can start conversions */
+#define   ADC_TRGR_TRGMOD_EXT_TRIG_RISE (0x1u << 0) /**< \brief (ADC_TRGR) External trigger rising edge */
+#define   ADC_TRGR_TRGMOD_EXT_TRIG_FALL (0x2u << 0) /**< \brief (ADC_TRGR) External trigger falling edge */
+#define   ADC_TRGR_TRGMOD_EXT_TRIG_ANY (0x3u << 0) /**< \brief (ADC_TRGR) External trigger any edge */
+#define   ADC_TRGR_TRGMOD_PEN_TRIG (0x4u << 0) /**< \brief (ADC_TRGR) Pen Detect Trigger (shall be selected only if PENDET is set and TSAMOD = Touchscreen only mode) */
+#define   ADC_TRGR_TRGMOD_PERIOD_TRIG (0x5u << 0) /**< \brief (ADC_TRGR) ADC internal periodic trigger (see field TRGPER) */
+#define   ADC_TRGR_TRGMOD_CONTINUOUS (0x6u << 0) /**< \brief (ADC_TRGR) Continuous Mode */
+#define ADC_TRGR_TRGPER_Pos 16
+#define ADC_TRGR_TRGPER_Msk (0xffffu << ADC_TRGR_TRGPER_Pos) /**< \brief (ADC_TRGR) Trigger Period */
+#define ADC_TRGR_TRGPER(value) ((ADC_TRGR_TRGPER_Msk & ((value) << ADC_TRGR_TRGPER_Pos)))
+/* -------- ADC_COSR : (ADC Offset: 0xD0) Correction Select Register -------- */
+#define ADC_COSR_CSEL_Pos 0
+#define ADC_COSR_CSEL_Msk (0x1fu << ADC_COSR_CSEL_Pos) /**< \brief (ADC_COSR) CORRECTION_TYPE Correction Select */
+#define ADC_COSR_CSEL(value) ((ADC_COSR_CSEL_Msk & ((value) << ADC_COSR_CSEL_Pos)))
+/* -------- ADC_CVR : (ADC Offset: 0xD4) Correction Values Register -------- */
+#define ADC_CVR_OFFSETCORR_Pos 0
+#define ADC_CVR_OFFSETCORR_Msk (0xffffu << ADC_CVR_OFFSETCORR_Pos) /**< \brief (ADC_CVR) Offset Correction */
+#define ADC_CVR_OFFSETCORR(value) ((ADC_CVR_OFFSETCORR_Msk & ((value) << ADC_CVR_OFFSETCORR_Pos)))
+#define ADC_CVR_GAINCORR_Pos 16
+#define ADC_CVR_GAINCORR_Msk (0xffffu << ADC_CVR_GAINCORR_Pos) /**< \brief (ADC_CVR) Gain Correction */
+#define ADC_CVR_GAINCORR(value) ((ADC_CVR_GAINCORR_Msk & ((value) << ADC_CVR_GAINCORR_Pos)))
+/* -------- ADC_CECR : (ADC Offset: 0xD8) Channel Error Correction Register -------- */
+#define ADC_CECR_ECORR0 (0x1u << 0) /**< \brief (ADC_CECR) Error Correction Enable for channel 0 */
+#define ADC_CECR_ECORR1 (0x1u << 1) /**< \brief (ADC_CECR) Error Correction Enable for channel 1 */
+#define ADC_CECR_ECORR2 (0x1u << 2) /**< \brief (ADC_CECR) Error Correction Enable for channel 2 */
+#define ADC_CECR_ECORR3 (0x1u << 3) /**< \brief (ADC_CECR) Error Correction Enable for channel 3 */
+#define ADC_CECR_ECORR4 (0x1u << 4) /**< \brief (ADC_CECR) Error Correction Enable for channel 4 */
+#define ADC_CECR_ECORR5 (0x1u << 5) /**< \brief (ADC_CECR) Error Correction Enable for channel 5 */
+#define ADC_CECR_ECORR6 (0x1u << 6) /**< \brief (ADC_CECR) Error Correction Enable for channel 6 */
+#define ADC_CECR_ECORR7 (0x1u << 7) /**< \brief (ADC_CECR) Error Correction Enable for channel 7 */
+#define ADC_CECR_ECORR8 (0x1u << 8) /**< \brief (ADC_CECR) Error Correction Enable for channel 8 */
+#define ADC_CECR_ECORR9 (0x1u << 9) /**< \brief (ADC_CECR) Error Correction Enable for channel 9 */
+#define ADC_CECR_ECORR10 (0x1u << 10) /**< \brief (ADC_CECR) Error Correction Enable for channel 10 */
+#define ADC_CECR_ECORR11 (0x1u << 11) /**< \brief (ADC_CECR) Error Correction Enable for channel 11 */
+/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protection Mode Register -------- */
+#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protection Enable */
+#define ADC_WPMR_WPKEY_Pos 8
+#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protection Key */
+#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos)))
+#define   ADC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (ADC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */
+/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protection Status Register -------- */
+#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protection Violation Status */
+#define ADC_WPSR_WPVSRC_Pos 8
+#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protection Violation Source */
+/* -------- ADC_VERSION : (ADC Offset: 0xFC) Version Register -------- */
+#define ADC_VERSION_VERSION_Pos 0
+#define ADC_VERSION_VERSION_Msk (0xfffu << ADC_VERSION_VERSION_Pos) /**< \brief (ADC_VERSION) Version of the Hardware Module */
+#define ADC_VERSION_MFN_Pos 16
+#define ADC_VERSION_MFN_Msk (0x7u << ADC_VERSION_MFN_Pos) /**< \brief (ADC_VERSION) Metal Fix Number */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_ADC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_aes.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_aes.h
new file mode 100644
index 000000000..621329e2f
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_aes.h
@@ -0,0 +1,236 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_AES_COMPONENT_
+#define _SAMA5D2_AES_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Advanced Encryption Standard */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_AES Advanced Encryption Standard */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Aes hardware registers */
+typedef struct {
+  __O  uint32_t AES_CR;        /**< \brief (Aes Offset: 0x00) Control Register */
+  __IO uint32_t AES_MR;        /**< \brief (Aes Offset: 0x04) Mode Register */
+  __I  uint32_t Reserved1[2];
+  __O  uint32_t AES_IER;       /**< \brief (Aes Offset: 0x10) Interrupt Enable Register */
+  __O  uint32_t AES_IDR;       /**< \brief (Aes Offset: 0x14) Interrupt Disable Register */
+  __I  uint32_t AES_IMR;       /**< \brief (Aes Offset: 0x18) Interrupt Mask Register */
+  __I  uint32_t AES_ISR;       /**< \brief (Aes Offset: 0x1C) Interrupt Status Register */
+  __O  uint32_t AES_KEYWR[8];  /**< \brief (Aes Offset: 0x20) Key Word Register */
+  __O  uint32_t AES_IDATAR[4]; /**< \brief (Aes Offset: 0x40) Input Data Register */
+  __I  uint32_t AES_ODATAR[4]; /**< \brief (Aes Offset: 0x50) Output Data Register */
+  __O  uint32_t AES_IVR[4];    /**< \brief (Aes Offset: 0x60) Initialization Vector Register */
+  __IO uint32_t AES_AADLENR;   /**< \brief (Aes Offset: 0x70) Additional Authenticated Data Length Register */
+  __IO uint32_t AES_CLENR;     /**< \brief (Aes Offset: 0x74) Plaintext/Ciphertext Length Register */
+  __IO uint32_t AES_GHASHR[4]; /**< \brief (Aes Offset: 0x78) GCM Intermediate Hash Word Register */
+  __I  uint32_t AES_TAGR[4];   /**< \brief (Aes Offset: 0x88) GCM Authentication Tag Word Register */
+  __I  uint32_t AES_CTRR;      /**< \brief (Aes Offset: 0x98) GCM Encryption Counter Value Register */
+  __IO uint32_t AES_GCMHR[4];  /**< \brief (Aes Offset: 0x9C) GCM H Word Register */
+  __I  uint32_t Reserved2[1];
+  __IO uint32_t AES_EMR;       /**< \brief (Aes Offset: 0xB0) Extended Mode Register */
+  __IO uint32_t AES_BCNT;      /**< \brief (Aes Offset: 0xB4) Byte Counter Register */
+  __I  uint32_t Reserved3[2];
+  __IO uint32_t AES_TWR[4];    /**< \brief (Aes Offset: 0xC0) Tweak Word Register */
+  __O  uint32_t AES_ALPHAR[4]; /**< \brief (Aes Offset: 0xD0) Alpha Word Register */
+  __I  uint32_t Reserved4[7];
+  __I  uint32_t AES_VERSION;   /**< \brief (Aes Offset: 0xFC) Version Register */
+} Aes;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */
+#define AES_CR_START (0x1u << 0) /**< \brief (AES_CR) Start Processing */
+#define AES_CR_SWRST (0x1u << 8) /**< \brief (AES_CR) Software Reset */
+#define AES_CR_LOADSEED (0x1u << 16) /**< \brief (AES_CR) Random Number Generator Seed Loading */
+/* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */
+#define AES_MR_CIPHER (0x1u << 0) /**< \brief (AES_MR) Processing Mode */
+#define AES_MR_GTAGEN (0x1u << 1) /**< \brief (AES_MR) GCM Automatic Tag Generation Enable */
+#define AES_MR_DUALBUFF (0x1u << 3) /**< \brief (AES_MR) Dual Input Buffer */
+#define   AES_MR_DUALBUFF_INACTIVE (0x0u << 3) /**< \brief (AES_MR) AES_IDATARx cannot be written during processing of previous block. */
+#define   AES_MR_DUALBUFF_ACTIVE (0x1u << 3) /**< \brief (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. */
+#define AES_MR_PROCDLY_Pos 4
+#define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos) /**< \brief (AES_MR) Processing Delay */
+#define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos)))
+#define AES_MR_SMOD_Pos 8
+#define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos) /**< \brief (AES_MR) Start Mode */
+#define AES_MR_SMOD(value) ((AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos)))
+#define   AES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AES_MR) Manual Mode */
+#define   AES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AES_MR) Auto Mode */
+#define   AES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */
+#define AES_MR_KEYSIZE_Pos 10
+#define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos) /**< \brief (AES_MR) Key Size */
+#define AES_MR_KEYSIZE(value) ((AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos)))
+#define   AES_MR_KEYSIZE_AES128 (0x0u << 10) /**< \brief (AES_MR) AES Key Size is 128 bits */
+#define   AES_MR_KEYSIZE_AES192 (0x1u << 10) /**< \brief (AES_MR) AES Key Size is 192 bits */
+#define   AES_MR_KEYSIZE_AES256 (0x2u << 10) /**< \brief (AES_MR) AES Key Size is 256 bits */
+#define AES_MR_OPMOD_Pos 12
+#define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos) /**< \brief (AES_MR) Operation Mode */
+#define AES_MR_OPMOD(value) ((AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos)))
+#define   AES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AES_MR) ECB: Electronic Code Book mode */
+#define   AES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AES_MR) CBC: Cipher Block Chaining mode */
+#define   AES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (AES_MR) OFB: Output Feedback mode */
+#define   AES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (AES_MR) CFB: Cipher Feedback mode */
+#define   AES_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AES_MR) CTR: Counter mode (16-bit internal counter) */
+#define   AES_MR_OPMOD_GCM (0x5u << 12) /**< \brief (AES_MR) GCM: Galois/Counter mode */
+#define   AES_MR_OPMOD_XTS (0x6u << 12) /**< \brief (AES_MR) XTS: XEX-based tweaked-codebook mode */
+#define AES_MR_LOD (0x1u << 15) /**< \brief (AES_MR) Last Output Data Mode */
+#define AES_MR_CFBS_Pos 16
+#define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos) /**< \brief (AES_MR) Cipher Feedback Data Size */
+#define AES_MR_CFBS(value) ((AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos)))
+#define   AES_MR_CFBS_SIZE_128BIT (0x0u << 16) /**< \brief (AES_MR) 128-bit */
+#define   AES_MR_CFBS_SIZE_64BIT (0x1u << 16) /**< \brief (AES_MR) 64-bit */
+#define   AES_MR_CFBS_SIZE_32BIT (0x2u << 16) /**< \brief (AES_MR) 32-bit */
+#define   AES_MR_CFBS_SIZE_16BIT (0x3u << 16) /**< \brief (AES_MR) 16-bit */
+#define   AES_MR_CFBS_SIZE_8BIT (0x4u << 16) /**< \brief (AES_MR) 8-bit */
+#define AES_MR_CKEY_Pos 20
+#define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos) /**< \brief (AES_MR) Countermeasure Key */
+#define AES_MR_CKEY(value) ((AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos)))
+#define   AES_MR_CKEY_PASSWD (0xEu << 20) /**< \brief (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. */
+#define AES_MR_CMTYP1 (0x1u << 24) /**< \brief (AES_MR) Countermeasure Type 1 */
+#define   AES_MR_CMTYP1_NOPROT_EXTKEY (0x0u << 24) /**< \brief (AES_MR) Countermeasure type 1 is disabled. */
+#define   AES_MR_CMTYP1_PROT_EXTKEY (0x1u << 24) /**< \brief (AES_MR) Countermeasure type 1 is enabled. */
+#define AES_MR_CMTYP2 (0x1u << 25) /**< \brief (AES_MR) Countermeasure Type 2 */
+#define   AES_MR_CMTYP2_NO_PAUSE (0x0u << 25) /**< \brief (AES_MR) Countermeasure type 2 is disabled. */
+#define   AES_MR_CMTYP2_PAUSE (0x1u << 25) /**< \brief (AES_MR) Countermeasure type 2 is enabled. */
+#define AES_MR_CMTYP3 (0x1u << 26) /**< \brief (AES_MR) Countermeasure Type 3 */
+#define   AES_MR_CMTYP3_NO_DUMMY (0x0u << 26) /**< \brief (AES_MR) Countermeasure type 3 is disabled. */
+#define   AES_MR_CMTYP3_DUMMY (0x1u << 26) /**< \brief (AES_MR) Countermeasure type 3 is enabled. */
+#define AES_MR_CMTYP4 (0x1u << 27) /**< \brief (AES_MR) Countermeasure Type 4 */
+#define   AES_MR_CMTYP4_NO_RESTART (0x0u << 27) /**< \brief (AES_MR) Countermeasure type 4 is disabled. */
+#define   AES_MR_CMTYP4_RESTART (0x1u << 27) /**< \brief (AES_MR) Countermeasure type 4 is enabled. */
+#define AES_MR_CMTYP5 (0x1u << 28) /**< \brief (AES_MR) Countermeasure Type 5 */
+#define   AES_MR_CMTYP5_NO_ADDACCESS (0x0u << 28) /**< \brief (AES_MR) Countermeasure type 5 is disabled. */
+#define   AES_MR_CMTYP5_ADDACCESS (0x1u << 28) /**< \brief (AES_MR) Countermeasure type 5 is enabled. */
+#define AES_MR_CMTYP6 (0x1u << 29) /**< \brief (AES_MR) Countermeasure Type 6 */
+#define   AES_MR_CMTYP6_NO_IDLECURRENT (0x0u << 29) /**< \brief (AES_MR) Countermeasure type 6 is disabled. */
+#define   AES_MR_CMTYP6_IDLECURRENT (0x1u << 29) /**< \brief (AES_MR) Countermeasure type 6 is enabled. */
+/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
+#define AES_IER_DATRDY (0x1u << 0) /**< \brief (AES_IER) Data Ready Interrupt Enable */
+#define AES_IER_URAD (0x1u << 8) /**< \brief (AES_IER) Unspecified Register Access Detection Interrupt Enable */
+#define AES_IER_TAGRDY (0x1u << 16) /**< \brief (AES_IER) GCM Tag Ready Interrupt Enable */
+#define AES_IER_EOPAD (0x1u << 17) /**< \brief (AES_IER) End of Padding Interrupt Enable */
+#define AES_IER_PLENERR (0x1u << 18) /**< \brief (AES_IER) Padding Length Error Interrupt Enable */
+/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
+#define AES_IDR_DATRDY (0x1u << 0) /**< \brief (AES_IDR) Data Ready Interrupt Disable */
+#define AES_IDR_URAD (0x1u << 8) /**< \brief (AES_IDR) Unspecified Register Access Detection Interrupt Disable */
+#define AES_IDR_TAGRDY (0x1u << 16) /**< \brief (AES_IDR) GCM Tag Ready Interrupt Disable */
+#define AES_IDR_EOPAD (0x1u << 17) /**< \brief (AES_IDR) End of Padding Interrupt Disable */
+#define AES_IDR_PLENERR (0x1u << 18) /**< \brief (AES_IDR) Padding Length Error Interrupt Disable */
+/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
+#define AES_IMR_DATRDY (0x1u << 0) /**< \brief (AES_IMR) Data Ready Interrupt Mask */
+#define AES_IMR_URAD (0x1u << 8) /**< \brief (AES_IMR) Unspecified Register Access Detection Interrupt Mask */
+#define AES_IMR_TAGRDY (0x1u << 16) /**< \brief (AES_IMR) GCM Tag Ready Interrupt Mask */
+#define AES_IMR_EOPAD (0x1u << 17) /**< \brief (AES_IMR) End of Padding Interrupt Mask */
+#define AES_IMR_PLENERR (0x1u << 18) /**< \brief (AES_IMR) Padding Length Error Interrupt Mask */
+/* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */
+#define AES_ISR_DATRDY (0x1u << 0) /**< \brief (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) */
+#define AES_ISR_URAD (0x1u << 8) /**< \brief (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) */
+#define AES_ISR_URAT_Pos 12
+#define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos) /**< \brief (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) */
+#define   AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */
+#define   AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AES_ISR) Output Data Register read during the data processing. */
+#define   AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AES_ISR) Mode Register written during the data processing. */
+#define   AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AES_ISR) Output Data Register read during the sub-keys generation. */
+#define   AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AES_ISR) Mode Register written during the sub-keys generation. */
+#define   AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AES_ISR) Write-only register read access. */
+#define AES_ISR_TAGRDY (0x1u << 16) /**< \brief (AES_ISR) GCM Tag Ready */
+#define AES_ISR_EOPAD (0x1u << 17) /**< \brief (AES_ISR) End of Padding */
+#define AES_ISR_PLENERR (0x1u << 18) /**< \brief (AES_ISR) Padding Length Error */
+/* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */
+#define AES_KEYWR_KEYW_Pos 0
+#define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos) /**< \brief (AES_KEYWR[8]) Key Word */
+#define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos)))
+/* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */
+#define AES_IDATAR_IDATA_Pos 0
+#define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos) /**< \brief (AES_IDATAR[4]) Input Data Word */
+#define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos)))
+/* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */
+#define AES_ODATAR_ODATA_Pos 0
+#define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos) /**< \brief (AES_ODATAR[4]) Output Data */
+/* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */
+#define AES_IVR_IV_Pos 0
+#define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos) /**< \brief (AES_IVR[4]) Initialization Vector */
+#define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos)))
+/* -------- AES_AADLENR : (AES Offset: 0x70) Additional Authenticated Data Length Register -------- */
+#define AES_AADLENR_AADLEN_Pos 0
+#define AES_AADLENR_AADLEN_Msk (0xffffffffu << AES_AADLENR_AADLEN_Pos) /**< \brief (AES_AADLENR) Additional Authenticated Data Length */
+#define AES_AADLENR_AADLEN(value) ((AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos)))
+/* -------- AES_CLENR : (AES Offset: 0x74) Plaintext/Ciphertext Length Register -------- */
+#define AES_CLENR_CLEN_Pos 0
+#define AES_CLENR_CLEN_Msk (0xffffffffu << AES_CLENR_CLEN_Pos) /**< \brief (AES_CLENR) Plaintext/Ciphertext Length */
+#define AES_CLENR_CLEN(value) ((AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos)))
+/* -------- AES_GHASHR[4] : (AES Offset: 0x78) GCM Intermediate Hash Word Register -------- */
+#define AES_GHASHR_GHASH_Pos 0
+#define AES_GHASHR_GHASH_Msk (0xffffffffu << AES_GHASHR_GHASH_Pos) /**< \brief (AES_GHASHR[4]) Intermediate GCM Hash Word x */
+#define AES_GHASHR_GHASH(value) ((AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos)))
+/* -------- AES_TAGR[4] : (AES Offset: 0x88) GCM Authentication Tag Word Register -------- */
+#define AES_TAGR_TAG_Pos 0
+#define AES_TAGR_TAG_Msk (0xffffffffu << AES_TAGR_TAG_Pos) /**< \brief (AES_TAGR[4]) GCM Authentication Tag x */
+/* -------- AES_CTRR : (AES Offset: 0x98) GCM Encryption Counter Value Register -------- */
+#define AES_CTRR_CTR_Pos 0
+#define AES_CTRR_CTR_Msk (0xffffffffu << AES_CTRR_CTR_Pos) /**< \brief (AES_CTRR) GCM Encryption Counter */
+/* -------- AES_GCMHR[4] : (AES Offset: 0x9C) GCM H Word Register -------- */
+#define AES_GCMHR_H_Pos 0
+#define AES_GCMHR_H_Msk (0xffffffffu << AES_GCMHR_H_Pos) /**< \brief (AES_GCMHR[4]) GCM H Word x */
+#define AES_GCMHR_H(value) ((AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos)))
+/* -------- AES_EMR : (AES Offset: 0xB0) Extended Mode Register -------- */
+#define AES_EMR_APEN (0x1u << 0) /**< \brief (AES_EMR) Auto Padding Enable */
+#define AES_EMR_APM (0x1u << 1) /**< \brief (AES_EMR) Auto Padding Mode */
+#define AES_EMR_PLIPEN (0x1u << 4) /**< \brief (AES_EMR) Protocol Layer Improved Performance Enable */
+#define AES_EMR_PLIPD (0x1u << 5) /**< \brief (AES_EMR) Protocol Layer Improved Performance Decipher */
+#define AES_EMR_PADLEN_Pos 8
+#define AES_EMR_PADLEN_Msk (0xffu << AES_EMR_PADLEN_Pos) /**< \brief (AES_EMR) Auto Padding Length */
+#define AES_EMR_PADLEN(value) ((AES_EMR_PADLEN_Msk & ((value) << AES_EMR_PADLEN_Pos)))
+#define AES_EMR_NHEAD_Pos 16
+#define AES_EMR_NHEAD_Msk (0xffu << AES_EMR_NHEAD_Pos) /**< \brief (AES_EMR) IPSEC Next Header */
+#define AES_EMR_NHEAD(value) ((AES_EMR_NHEAD_Msk & ((value) << AES_EMR_NHEAD_Pos)))
+/* -------- AES_BCNT : (AES Offset: 0xB4) Byte Counter Register -------- */
+#define AES_BCNT_BCNT_Pos 0
+#define AES_BCNT_BCNT_Msk (0xffffffffu << AES_BCNT_BCNT_Pos) /**< \brief (AES_BCNT) Auto Padding Byte Counter */
+#define AES_BCNT_BCNT(value) ((AES_BCNT_BCNT_Msk & ((value) << AES_BCNT_BCNT_Pos)))
+/* -------- AES_TWR[4] : (AES Offset: 0xC0) Tweak Word Register -------- */
+#define AES_TWR_TWEAK_Pos 0
+#define AES_TWR_TWEAK_Msk (0xffffffffu << AES_TWR_TWEAK_Pos) /**< \brief (AES_TWR[4]) Tweak Word x */
+#define AES_TWR_TWEAK(value) ((AES_TWR_TWEAK_Msk & ((value) << AES_TWR_TWEAK_Pos)))
+/* -------- AES_ALPHAR[4] : (AES Offset: 0xD0) Alpha Word Register -------- */
+#define AES_ALPHAR_ALPHA_Pos 0
+#define AES_ALPHAR_ALPHA_Msk (0xffffffffu << AES_ALPHAR_ALPHA_Pos) /**< \brief (AES_ALPHAR[4]) Alpha Word x */
+#define AES_ALPHAR_ALPHA(value) ((AES_ALPHAR_ALPHA_Msk & ((value) << AES_ALPHAR_ALPHA_Pos)))
+/* -------- AES_VERSION : (AES Offset: 0xFC) Version Register -------- */
+#define AES_VERSION_VERSION_Pos 0
+#define AES_VERSION_VERSION_Msk (0xfffu << AES_VERSION_VERSION_Pos) /**< \brief (AES_VERSION) Version of the Hardware Module */
+#define AES_VERSION_MFN_Pos 16
+#define AES_VERSION_MFN_Msk (0x7u << AES_VERSION_MFN_Pos) /**< \brief (AES_VERSION) Metal Fix Number */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_AES_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_aesb.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_aesb.h
new file mode 100644
index 000000000..db735ef27
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_aesb.h
@@ -0,0 +1,150 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_AESB_COMPONENT_
+#define _SAMA5D2_AESB_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Advanced Encryption Standard Bridge */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_AESB Advanced Encryption Standard Bridge */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Aesb hardware registers */
+typedef struct {
+  __O  uint32_t AESB_CR;        /**< \brief (Aesb Offset: 0x00) Control Register */
+  __IO uint32_t AESB_MR;        /**< \brief (Aesb Offset: 0x04) Mode Register */
+  __I  uint32_t Reserved1[2];
+  __O  uint32_t AESB_IER;       /**< \brief (Aesb Offset: 0x10) Interrupt Enable Register */
+  __O  uint32_t AESB_IDR;       /**< \brief (Aesb Offset: 0x14) Interrupt Disable Register */
+  __I  uint32_t AESB_IMR;       /**< \brief (Aesb Offset: 0x18) Interrupt Mask Register */
+  __I  uint32_t AESB_ISR;       /**< \brief (Aesb Offset: 0x1C) Interrupt Status Register */
+  __O  uint32_t AESB_KEYWR[4];  /**< \brief (Aesb Offset: 0x20) Key Word Register */
+  __I  uint32_t Reserved2[4];
+  __O  uint32_t AESB_IDATAR[4]; /**< \brief (Aesb Offset: 0x40) Input Data Register */
+  __I  uint32_t AESB_ODATAR[4]; /**< \brief (Aesb Offset: 0x50) Output Data Register */
+  __O  uint32_t AESB_IVR[4];    /**< \brief (Aesb Offset: 0x60) Initialization Vector Register */
+  __I  uint32_t Reserved3[35];
+  __I  uint32_t AESB_VERSION;   /**< \brief (Aesb Offset: 0xFC) Version Register */
+} Aesb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- AESB_CR : (AESB Offset: 0x00) Control Register -------- */
+#define AESB_CR_START (0x1u << 0) /**< \brief (AESB_CR) Start Processing */
+#define AESB_CR_SWRST (0x1u << 8) /**< \brief (AESB_CR) Software Reset */
+#define AESB_CR_LOADSEED (0x1u << 16) /**< \brief (AESB_CR) Random Number Generator Seed Loading */
+/* -------- AESB_MR : (AESB Offset: 0x04) Mode Register -------- */
+#define AESB_MR_CIPHER (0x1u << 0) /**< \brief (AESB_MR) Processing Mode */
+#define AESB_MR_AAHB (0x1u << 2) /**< \brief (AESB_MR) Automatic Bridge Mode */
+#define AESB_MR_DUALBUFF (0x1u << 3) /**< \brief (AESB_MR) Dual Input Buffer */
+#define   AESB_MR_DUALBUFF_INACTIVE (0x0u << 3) /**< \brief (AESB_MR) AESB_IDATARx cannot be written during processing of previous block. */
+#define   AESB_MR_DUALBUFF_ACTIVE (0x1u << 3) /**< \brief (AESB_MR) AESB_IDATARx can be written during processing of previous block when SMOD = 0x2. It speeds up the overall runtime of large files. */
+#define AESB_MR_PROCDLY_Pos 4
+#define AESB_MR_PROCDLY_Msk (0xfu << AESB_MR_PROCDLY_Pos) /**< \brief (AESB_MR) Processing Delay */
+#define AESB_MR_PROCDLY(value) ((AESB_MR_PROCDLY_Msk & ((value) << AESB_MR_PROCDLY_Pos)))
+#define AESB_MR_SMOD_Pos 8
+#define AESB_MR_SMOD_Msk (0x3u << AESB_MR_SMOD_Pos) /**< \brief (AESB_MR) Start Mode */
+#define AESB_MR_SMOD(value) ((AESB_MR_SMOD_Msk & ((value) << AESB_MR_SMOD_Pos)))
+#define   AESB_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AESB_MR) Manual Mode */
+#define   AESB_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AESB_MR) Auto Mode */
+#define   AESB_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AESB_MR) AESB_IDATAR0 access only Auto Mode */
+#define AESB_MR_OPMOD_Pos 12
+#define AESB_MR_OPMOD_Msk (0x7u << AESB_MR_OPMOD_Pos) /**< \brief (AESB_MR) Operation Mode */
+#define AESB_MR_OPMOD(value) ((AESB_MR_OPMOD_Msk & ((value) << AESB_MR_OPMOD_Pos)))
+#define   AESB_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AESB_MR) Electronic Code Book mode */
+#define   AESB_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AESB_MR) Cipher Block Chaining mode */
+#define   AESB_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AESB_MR) Counter mode (16-bit internal counter) */
+#define AESB_MR_LOD (0x1u << 15) /**< \brief (AESB_MR) Last Output Data Mode */
+#define AESB_MR_CKEY_Pos 20
+#define AESB_MR_CKEY_Msk (0xfu << AESB_MR_CKEY_Pos) /**< \brief (AESB_MR) Countermeasure Key */
+#define AESB_MR_CKEY(value) ((AESB_MR_CKEY_Msk & ((value) << AESB_MR_CKEY_Pos)))
+#define   AESB_MR_CKEY_PASSWD (0xEu << 20) /**< \brief (AESB_MR) This field must be written with 0xE to allow CMTYPx fields change. Any other values will abort the write operation in CMTYPx fields.Always reads as 0. */
+#define AESB_MR_CMTYP1 (0x1u << 24) /**< \brief (AESB_MR) Countermeasure Type 1 */
+#define   AESB_MR_CMTYP1_NOPROT_EXTKEY (0x0u << 24) /**< \brief (AESB_MR) Countermeasure type 1 is disabled. */
+#define   AESB_MR_CMTYP1_PROT_EXTKEY (0x1u << 24) /**< \brief (AESB_MR) Countermeasure type 1 is enabled. */
+#define AESB_MR_CMTYP2 (0x1u << 25) /**< \brief (AESB_MR) Countermeasure Type 2 */
+#define   AESB_MR_CMTYP2_NO_PAUSE (0x0u << 25) /**< \brief (AESB_MR) Countermeasure type 2 is disabled. */
+#define   AESB_MR_CMTYP2_PAUSE (0x1u << 25) /**< \brief (AESB_MR) Countermeasure type 2 is enabled. */
+#define AESB_MR_CMTYP3 (0x1u << 26) /**< \brief (AESB_MR) Countermeasure Type 3 */
+#define   AESB_MR_CMTYP3_NO_DUMMY (0x0u << 26) /**< \brief (AESB_MR) Countermeasure type 3 is disabled. */
+#define   AESB_MR_CMTYP3_DUMMY (0x1u << 26) /**< \brief (AESB_MR) Countermeasure type 3 is enabled. */
+#define AESB_MR_CMTYP4 (0x1u << 27) /**< \brief (AESB_MR) Countermeasure Type 4 */
+#define   AESB_MR_CMTYP4_NO_RESTART (0x0u << 27) /**< \brief (AESB_MR) Countermeasure type 4 is disabled. */
+#define   AESB_MR_CMTYP4_RESTART (0x1u << 27) /**< \brief (AESB_MR) Countermeasure type 4 is enabled. */
+#define AESB_MR_CMTYP5 (0x1u << 28) /**< \brief (AESB_MR) Countermeasure Type 5 */
+#define   AESB_MR_CMTYP5_NO_ADDACCESS (0x0u << 28) /**< \brief (AESB_MR) Countermeasure type 5 is disabled. */
+#define   AESB_MR_CMTYP5_ADDACCESS (0x1u << 28) /**< \brief (AESB_MR) Countermeasure type 5 is enabled. */
+#define AESB_MR_CMTYP6 (0x1u << 29) /**< \brief (AESB_MR) CounterMeasure Type 6 */
+#define   AESB_MR_CMTYP6_NO_IDLECURRENT (0x0u << 29) /**< \brief (AESB_MR) Countermeasure type 6 is disabled. */
+#define   AESB_MR_CMTYP6_IDLECURRENT (0x1u << 29) /**< \brief (AESB_MR) Countermeasure type 6 is enabled. */
+/* -------- AESB_IER : (AESB Offset: 0x10) Interrupt Enable Register -------- */
+#define AESB_IER_DATRDY (0x1u << 0) /**< \brief (AESB_IER) Data Ready Interrupt Enable */
+#define AESB_IER_URAD (0x1u << 8) /**< \brief (AESB_IER) Unspecified Register Access Detection Interrupt Enable */
+/* -------- AESB_IDR : (AESB Offset: 0x14) Interrupt Disable Register -------- */
+#define AESB_IDR_DATRDY (0x1u << 0) /**< \brief (AESB_IDR) Data Ready Interrupt Disable */
+#define AESB_IDR_URAD (0x1u << 8) /**< \brief (AESB_IDR) Unspecified Register Access Detection Interrupt Disable */
+/* -------- AESB_IMR : (AESB Offset: 0x18) Interrupt Mask Register -------- */
+#define AESB_IMR_DATRDY (0x1u << 0) /**< \brief (AESB_IMR) Data Ready Interrupt Mask */
+#define AESB_IMR_URAD (0x1u << 8) /**< \brief (AESB_IMR) Unspecified Register Access Detection Interrupt Mask */
+/* -------- AESB_ISR : (AESB Offset: 0x1C) Interrupt Status Register -------- */
+#define AESB_ISR_DATRDY (0x1u << 0) /**< \brief (AESB_ISR) Data Ready */
+#define AESB_ISR_URAD (0x1u << 8) /**< \brief (AESB_ISR) Unspecified Register Access Detection Status */
+#define AESB_ISR_URAT_Pos 12
+#define AESB_ISR_URAT_Msk (0xfu << AESB_ISR_URAT_Pos) /**< \brief (AESB_ISR) Unspecified Register Access */
+#define   AESB_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AESB_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode */
+#define   AESB_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AESB_ISR) Output Data Register read during the data processing */
+#define   AESB_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AESB_ISR) Mode Register written during the data processing */
+#define   AESB_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AESB_ISR) Output Data Register read during the sub-keys generation */
+#define   AESB_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AESB_ISR) Mode Register written during the sub-keys generation */
+#define   AESB_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AESB_ISR) Write-only register read access */
+/* -------- AESB_KEYWR[4] : (AESB Offset: 0x20) Key Word Register -------- */
+#define AESB_KEYWR_KEYW_Pos 0
+#define AESB_KEYWR_KEYW_Msk (0xffffffffu << AESB_KEYWR_KEYW_Pos) /**< \brief (AESB_KEYWR[4]) Key Word */
+#define AESB_KEYWR_KEYW(value) ((AESB_KEYWR_KEYW_Msk & ((value) << AESB_KEYWR_KEYW_Pos)))
+/* -------- AESB_IDATAR[4] : (AESB Offset: 0x40) Input Data Register -------- */
+#define AESB_IDATAR_IDATA_Pos 0
+#define AESB_IDATAR_IDATA_Msk (0xffffffffu << AESB_IDATAR_IDATA_Pos) /**< \brief (AESB_IDATAR[4]) Input Data Word */
+#define AESB_IDATAR_IDATA(value) ((AESB_IDATAR_IDATA_Msk & ((value) << AESB_IDATAR_IDATA_Pos)))
+/* -------- AESB_ODATAR[4] : (AESB Offset: 0x50) Output Data Register -------- */
+#define AESB_ODATAR_ODATA_Pos 0
+#define AESB_ODATAR_ODATA_Msk (0xffffffffu << AESB_ODATAR_ODATA_Pos) /**< \brief (AESB_ODATAR[4]) Output Data */
+/* -------- AESB_IVR[4] : (AESB Offset: 0x60) Initialization Vector Register -------- */
+#define AESB_IVR_IV_Pos 0
+#define AESB_IVR_IV_Msk (0xffffffffu << AESB_IVR_IV_Pos) /**< \brief (AESB_IVR[4]) Initialization Vector */
+#define AESB_IVR_IV(value) ((AESB_IVR_IV_Msk & ((value) << AESB_IVR_IV_Pos)))
+/* -------- AESB_VERSION : (AESB Offset: 0xFC) Version Register -------- */
+#define AESB_VERSION_VERSION_Pos 0
+#define AESB_VERSION_VERSION_Msk (0xfffu << AESB_VERSION_VERSION_Pos) /**< \brief (AESB_VERSION) Version of the Hardware Module */
+#define AESB_VERSION_MFN_Pos 16
+#define AESB_VERSION_MFN_Msk (0x7u << AESB_VERSION_MFN_Pos) /**< \brief (AESB_VERSION) Metal Fix Number */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_AESB_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_aic.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_aic.h
new file mode 100644
index 000000000..301b7111c
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_aic.h
@@ -0,0 +1,272 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_AIC_COMPONENT_
+#define _SAMA5D2_AIC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_AIC Advanced Interrupt Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Aic hardware registers */
+typedef struct {
+  __IO uint32_t AIC_SSR;       /**< \brief (Aic Offset: 0x00) Source Select Register */
+  __IO uint32_t AIC_SMR;       /**< \brief (Aic Offset: 0x04) Source Mode Register */
+  __IO uint32_t AIC_SVR;       /**< \brief (Aic Offset: 0x08) Source Vector Register */
+  __I  uint32_t Reserved1[1];
+  __I  uint32_t AIC_IVR;       /**< \brief (Aic Offset: 0x10) Interrupt Vector Register */
+  __I  uint32_t AIC_FVR;       /**< \brief (Aic Offset: 0x14) FIQ Vector Register */
+  __I  uint32_t AIC_ISR;       /**< \brief (Aic Offset: 0x18) Interrupt Status Register */
+  __I  uint32_t Reserved2[1];
+  __I  uint32_t AIC_IPR0;      /**< \brief (Aic Offset: 0x20) Interrupt Pending Register 0 */
+  __I  uint32_t AIC_IPR1;      /**< \brief (Aic Offset: 0x24) Interrupt Pending Register 1 */
+  __I  uint32_t AIC_IPR2;      /**< \brief (Aic Offset: 0x28) Interrupt Pending Register 2 */
+  __I  uint32_t AIC_IPR3;      /**< \brief (Aic Offset: 0x2C) Interrupt Pending Register 3 */
+  __I  uint32_t AIC_IMR;       /**< \brief (Aic Offset: 0x30) Interrupt Mask Register */
+  __I  uint32_t AIC_CISR;      /**< \brief (Aic Offset: 0x34) Core Interrupt Status Register */
+  __O  uint32_t AIC_EOICR;     /**< \brief (Aic Offset: 0x38) End of Interrupt Command Register */
+  __IO uint32_t AIC_SPU;       /**< \brief (Aic Offset: 0x3C) Spurious Interrupt Vector Register */
+  __O  uint32_t AIC_IECR;      /**< \brief (Aic Offset: 0x40) Interrupt Enable Command Register */
+  __O  uint32_t AIC_IDCR;      /**< \brief (Aic Offset: 0x44) Interrupt Disable Command Register */
+  __O  uint32_t AIC_ICCR;      /**< \brief (Aic Offset: 0x48) Interrupt Clear Command Register */
+  __O  uint32_t AIC_ISCR;      /**< \brief (Aic Offset: 0x4C) Interrupt Set Command Register */
+  __I  uint32_t Reserved3[7];
+  __IO uint32_t AIC_DCR;       /**< \brief (Aic Offset: 0x6C) Debug Control Register */
+  __I  uint32_t Reserved4[29];
+  __IO uint32_t AIC_WPMR;      /**< \brief (Aic Offset: 0xE4) Write Protection Mode Register */
+  __I  uint32_t AIC_WPSR;      /**< \brief (Aic Offset: 0xE8) Write Protection Status Register */
+  __I  uint32_t Reserved5[4];
+  __I  uint32_t AIC_VERSION;   /**< \brief (Aic Offset: 0XFC) AIC Version Register */
+} Aic;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- AIC_SSR : (AIC Offset: 0x00) Source Select Register -------- */
+#define AIC_SSR_INTSEL_Pos 0
+#define AIC_SSR_INTSEL_Msk (0x7fu << AIC_SSR_INTSEL_Pos) /**< \brief (AIC_SSR) Interrupt Line Selection */
+#define AIC_SSR_INTSEL(value) ((AIC_SSR_INTSEL_Msk & ((value) << AIC_SSR_INTSEL_Pos)))
+/* -------- AIC_SMR : (AIC Offset: 0x04) Source Mode Register -------- */
+#define AIC_SMR_PRIOR_Pos 0
+#define AIC_SMR_PRIOR_Msk (0x7u << AIC_SMR_PRIOR_Pos) /**< \brief (AIC_SMR) Priority Level */
+#define AIC_SMR_PRIOR(value) ((AIC_SMR_PRIOR_Msk & ((value) << AIC_SMR_PRIOR_Pos)))
+#define AIC_SMR_SRCTYPE_Pos 5
+#define AIC_SMR_SRCTYPE_Msk (0x3u << AIC_SMR_SRCTYPE_Pos) /**< \brief (AIC_SMR) Interrupt Source Type */
+#define AIC_SMR_SRCTYPE(value) ((AIC_SMR_SRCTYPE_Msk & ((value) << AIC_SMR_SRCTYPE_Pos)))
+#define   AIC_SMR_SRCTYPE_INT_LEVEL_SENSITIVE (0x0u << 5) /**< \brief (AIC_SMR) High level Sensitive for internal sourceLow level Sensitive for external source */
+#define   AIC_SMR_SRCTYPE_INT_EDGE_TRIGGERED (0x1u << 5) /**< \brief (AIC_SMR) Positive edge triggered for internal sourceNegative edge triggered for external source */
+#define   AIC_SMR_SRCTYPE_EXT_HIGH_LEVEL (0x2u << 5) /**< \brief (AIC_SMR) High level Sensitive for internal sourceHigh level Sensitive for external source */
+#define   AIC_SMR_SRCTYPE_EXT_POSITIVE_EDGE (0x3u << 5) /**< \brief (AIC_SMR) Positive edge triggered for internal sourcePositive edge triggered for external source */
+/* -------- AIC_SVR : (AIC Offset: 0x08) Source Vector Register -------- */
+#define AIC_SVR_VECTOR_Pos 0
+#define AIC_SVR_VECTOR_Msk (0xffffffffu << AIC_SVR_VECTOR_Pos) /**< \brief (AIC_SVR) Source Vector */
+#define AIC_SVR_VECTOR(value) ((AIC_SVR_VECTOR_Msk & ((value) << AIC_SVR_VECTOR_Pos)))
+/* -------- AIC_IVR : (AIC Offset: 0x10) Interrupt Vector Register -------- */
+#define AIC_IVR_IRQV_Pos 0
+#define AIC_IVR_IRQV_Msk (0xffffffffu << AIC_IVR_IRQV_Pos) /**< \brief (AIC_IVR) Interrupt Vector Register */
+/* -------- AIC_FVR : (AIC Offset: 0x14) FIQ Vector Register -------- */
+#define AIC_FVR_FIQV_Pos 0
+#define AIC_FVR_FIQV_Msk (0xffffffffu << AIC_FVR_FIQV_Pos) /**< \brief (AIC_FVR) FIQ Vector Register */
+/* -------- AIC_ISR : (AIC Offset: 0x18) Interrupt Status Register -------- */
+#define AIC_ISR_IRQID_Pos 0
+#define AIC_ISR_IRQID_Msk (0x7fu << AIC_ISR_IRQID_Pos) /**< \brief (AIC_ISR) Current Interrupt Identifier */
+/* -------- AIC_IPR0 : (AIC Offset: 0x20) Interrupt Pending Register 0 -------- */
+#define AIC_IPR0_FIQ (0x1u << 0) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_SYS (0x1u << 1) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID2 (0x1u << 2) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID3 (0x1u << 3) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID4 (0x1u << 4) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID5 (0x1u << 5) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID6 (0x1u << 6) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID7 (0x1u << 7) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID8 (0x1u << 8) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID9 (0x1u << 9) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID10 (0x1u << 10) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID11 (0x1u << 11) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID12 (0x1u << 12) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID13 (0x1u << 13) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID14 (0x1u << 14) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID15 (0x1u << 15) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID16 (0x1u << 16) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID17 (0x1u << 17) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID18 (0x1u << 18) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID19 (0x1u << 19) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID20 (0x1u << 20) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID21 (0x1u << 21) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID22 (0x1u << 22) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID23 (0x1u << 23) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID24 (0x1u << 24) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID25 (0x1u << 25) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID26 (0x1u << 26) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID27 (0x1u << 27) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID28 (0x1u << 28) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID29 (0x1u << 29) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID30 (0x1u << 30) /**< \brief (AIC_IPR0) Interrupt Pending */
+#define AIC_IPR0_PID31 (0x1u << 31) /**< \brief (AIC_IPR0) Interrupt Pending */
+/* -------- AIC_IPR1 : (AIC Offset: 0x24) Interrupt Pending Register 1 -------- */
+#define AIC_IPR1_PID32 (0x1u << 0) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID33 (0x1u << 1) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID34 (0x1u << 2) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID35 (0x1u << 3) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID36 (0x1u << 4) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID37 (0x1u << 5) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID38 (0x1u << 6) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID39 (0x1u << 7) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID40 (0x1u << 8) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID41 (0x1u << 9) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID42 (0x1u << 10) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID43 (0x1u << 11) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID44 (0x1u << 12) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID45 (0x1u << 13) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID46 (0x1u << 14) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID47 (0x1u << 15) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID48 (0x1u << 16) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID49 (0x1u << 17) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID50 (0x1u << 18) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID51 (0x1u << 19) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID52 (0x1u << 20) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID53 (0x1u << 21) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID54 (0x1u << 22) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID55 (0x1u << 23) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID56 (0x1u << 24) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID57 (0x1u << 25) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID58 (0x1u << 26) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID59 (0x1u << 27) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID60 (0x1u << 28) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID61 (0x1u << 29) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID62 (0x1u << 30) /**< \brief (AIC_IPR1) Interrupt Pending */
+#define AIC_IPR1_PID63 (0x1u << 31) /**< \brief (AIC_IPR1) Interrupt Pending */
+/* -------- AIC_IPR2 : (AIC Offset: 0x28) Interrupt Pending Register 2 -------- */
+#define AIC_IPR2_PID64 (0x1u << 0) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID65 (0x1u << 1) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID66 (0x1u << 2) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID67 (0x1u << 3) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID68 (0x1u << 4) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID69 (0x1u << 5) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID70 (0x1u << 6) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID71 (0x1u << 7) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID72 (0x1u << 8) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID73 (0x1u << 9) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID74 (0x1u << 10) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID75 (0x1u << 11) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID76 (0x1u << 12) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID77 (0x1u << 13) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID78 (0x1u << 14) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID79 (0x1u << 15) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID80 (0x1u << 16) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID81 (0x1u << 17) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID82 (0x1u << 18) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID83 (0x1u << 19) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID84 (0x1u << 20) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID85 (0x1u << 21) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID86 (0x1u << 22) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID87 (0x1u << 23) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID88 (0x1u << 24) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID89 (0x1u << 25) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID90 (0x1u << 26) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID91 (0x1u << 27) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID92 (0x1u << 28) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID93 (0x1u << 29) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID94 (0x1u << 30) /**< \brief (AIC_IPR2) Interrupt Pending */
+#define AIC_IPR2_PID95 (0x1u << 31) /**< \brief (AIC_IPR2) Interrupt Pending */
+/* -------- AIC_IPR3 : (AIC Offset: 0x2C) Interrupt Pending Register 3 -------- */
+#define AIC_IPR3_PID96 (0x1u << 0) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID97 (0x1u << 1) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID98 (0x1u << 2) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID99 (0x1u << 3) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID100 (0x1u << 4) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID101 (0x1u << 5) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID102 (0x1u << 6) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID103 (0x1u << 7) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID104 (0x1u << 8) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID105 (0x1u << 9) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID106 (0x1u << 10) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID107 (0x1u << 11) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID108 (0x1u << 12) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID109 (0x1u << 13) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID110 (0x1u << 14) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID111 (0x1u << 15) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID112 (0x1u << 16) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID113 (0x1u << 17) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID114 (0x1u << 18) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID115 (0x1u << 19) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID116 (0x1u << 20) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID117 (0x1u << 21) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID118 (0x1u << 22) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID119 (0x1u << 23) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID120 (0x1u << 24) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID121 (0x1u << 25) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID122 (0x1u << 26) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID123 (0x1u << 27) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID124 (0x1u << 28) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID125 (0x1u << 29) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID126 (0x1u << 30) /**< \brief (AIC_IPR3) Interrupt Pending */
+#define AIC_IPR3_PID127 (0x1u << 31) /**< \brief (AIC_IPR3) Interrupt Pending */
+/* -------- AIC_IMR : (AIC Offset: 0x30) Interrupt Mask Register -------- */
+#define AIC_IMR_INTM (0x1u << 0) /**< \brief (AIC_IMR) Interrupt Mask */
+/* -------- AIC_CISR : (AIC Offset: 0x34) Core Interrupt Status Register -------- */
+#define AIC_CISR_NFIQ (0x1u << 0) /**< \brief (AIC_CISR) NFIQ Status */
+#define AIC_CISR_NIRQ (0x1u << 1) /**< \brief (AIC_CISR) NIRQ Status */
+/* -------- AIC_EOICR : (AIC Offset: 0x38) End of Interrupt Command Register -------- */
+#define AIC_EOICR_ENDIT (0x1u << 0) /**< \brief (AIC_EOICR) Interrupt Processing Complete Command */
+/* -------- AIC_SPU : (AIC Offset: 0x3C) Spurious Interrupt Vector Register -------- */
+#define AIC_SPU_SIVR_Pos 0
+#define AIC_SPU_SIVR_Msk (0xffffffffu << AIC_SPU_SIVR_Pos) /**< \brief (AIC_SPU) Spurious Interrupt Vector Register */
+#define AIC_SPU_SIVR(value) ((AIC_SPU_SIVR_Msk & ((value) << AIC_SPU_SIVR_Pos)))
+/* -------- AIC_IECR : (AIC Offset: 0x40) Interrupt Enable Command Register -------- */
+#define AIC_IECR_INTEN (0x1u << 0) /**< \brief (AIC_IECR) Interrupt Enable */
+/* -------- AIC_IDCR : (AIC Offset: 0x44) Interrupt Disable Command Register -------- */
+#define AIC_IDCR_INTD (0x1u << 0) /**< \brief (AIC_IDCR) Interrupt Disable */
+/* -------- AIC_ICCR : (AIC Offset: 0x48) Interrupt Clear Command Register -------- */
+#define AIC_ICCR_INTCLR (0x1u << 0) /**< \brief (AIC_ICCR) Interrupt Clear */
+/* -------- AIC_ISCR : (AIC Offset: 0x4C) Interrupt Set Command Register -------- */
+#define AIC_ISCR_INTSET (0x1u << 0) /**< \brief (AIC_ISCR) Interrupt Set */
+/* -------- AIC_DCR : (AIC Offset: 0x6C) Debug Control Register -------- */
+#define AIC_DCR_PROT (0x1u << 0) /**< \brief (AIC_DCR) Protection Mode */
+#define AIC_DCR_GMSK (0x1u << 1) /**< \brief (AIC_DCR) General Interrupt Mask */
+/* -------- AIC_WPMR : (AIC Offset: 0xE4) Write Protection Mode Register -------- */
+#define AIC_WPMR_WPEN (0x1u << 0) /**< \brief (AIC_WPMR) Write Protection Enable */
+#define AIC_WPMR_WPKEY_Pos 8
+#define AIC_WPMR_WPKEY_Msk (0xffffffu << AIC_WPMR_WPKEY_Pos) /**< \brief (AIC_WPMR) Write Protection Key */
+#define AIC_WPMR_WPKEY(value) ((AIC_WPMR_WPKEY_Msk & ((value) << AIC_WPMR_WPKEY_Pos)))
+#define   AIC_WPMR_WPKEY_PASSWD (0x414943u << 8) /**< \brief (AIC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
+/* -------- AIC_WPSR : (AIC Offset: 0xE8) Write Protection Status Register -------- */
+#define AIC_WPSR_WPVS (0x1u << 0) /**< \brief (AIC_WPSR) Write Protection Violation Status */
+#define AIC_WPSR_WPVSRC_Pos 8
+#define AIC_WPSR_WPVSRC_Msk (0xffffu << AIC_WPSR_WPVSRC_Pos) /**< \brief (AIC_WPSR) Write Protection Violation Source */
+/* -------- AIC_VERSION : (AIC Offset: 0XFC) AIC Version Register -------- */
+#define AIC_VERSION_VERSION_Pos 0
+#define AIC_VERSION_VERSION_Msk (0xfffu << AIC_VERSION_VERSION_Pos) /**< \brief (AIC_VERSION) Version of the Hardware Module */
+#define AIC_VERSION_MFN_Pos 16
+#define AIC_VERSION_MFN_Msk (0x7u << AIC_VERSION_MFN_Pos) /**< \brief (AIC_VERSION) Metal Fix Number */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_AIC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_aximx.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_aximx.h
new file mode 100644
index 000000000..d6b70240a
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_aximx.h
@@ -0,0 +1,51 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_AXIMX_COMPONENT_
+#define _SAMA5D2_AXIMX_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR AXI Matrix */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_AXIMX AXI Matrix */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Aximx hardware registers */
+typedef struct {
+  __O uint32_t AXIMX_REMAP; /**< \brief (Aximx Offset: 0x00) AXI Matrix Remap Register */
+} Aximx;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- AXIMX_REMAP : (AXIMX Offset: 0x00) AXI Matrix Remap Register -------- */
+#define AXIMX_REMAP_REMAP0 (0x1u << 0) /**< \brief (AXIMX_REMAP) Remap State 0 */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_AXIMX_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_bsc.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_bsc.h
new file mode 100644
index 000000000..0d4e8cb01
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_bsc.h
@@ -0,0 +1,124 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2016, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_BSC_COMPONENT_
+#define _SAMA5D2_BSC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Boot Sequence Control */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_BSC Boot Sequence Control */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Bsc hardware registers */
+typedef struct {
+  __IO uint32_t BSC_CR; /**< \brief (Bsc Offset: 0x0) Boot Sequence Control Configuration Register */
+} Bsc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- BSC_CR : (BSC Offset: 0x0) Boot Sequence Control Configuration Register -------- */
+#define BSC_CR_BUREG_INDEX_Pos 0
+#define BSC_CR_BUREG_INDEX_Msk (0x3u << BSC_CR_BUREG_INDEX_Pos)
+#define BSC_CR_BUREG_INDEX(value) (BSC_CR_BUREG_INDEX_Msk & ((value) << BSC_CR_BUREG_INDEX_Pos)
+#define   BSC_CR_BUREG_0 (0x0u << 0)
+#define   BSC_CR_BUREG_1 (0x1u << 0)
+#define   BSC_CR_BUREG_2 (0x2u << 0)
+#define   BSC_CR_BUREG_3 (0x3u << 0)
+#define BSC_CR_BUREG_VALID (1 << 2)
+#define BSC_CR_WPKEY_Pos 16
+#define BSC_CR_WPKEY_Msk (0xffffu << BSC_CR_WPKEY_Pos)
+#define BSC_CR_WPKEY (0x6683 << 16)
+
+/* -------- BCW : Boot Control Word -------- */
+#define BCW_QSPI_0_Pos 0
+#define BCW_QSPI_0_Msk (0x3u << BCW_QSPI_0_Pos)
+#define BCW_QSPI_0(value) (BCW_QSPI_0_Msk & ((value) << BCW_QSPI_0_Pos)
+#define   BCW_QSPI_0_IOSET_1 (0x0u << 0)
+#define   BCW_QSPI_0_IOSET_2 (0x1u << 0)
+#define   BCW_QSPI_0_IOSET_3 (0x2u << 0)
+#define   BCW_QSPI_0_DISABLED (0x3u << 0)
+#define BCW_QSPI_1_Pos 2
+#define BCW_QSPI_1_Msk (0x3u << BCW_QSPI_1_Pos)
+#define BCW_QSPI_1(value) (BCW_QSPI_1_Msk & ((value) << BCW_QSPI_1_Pos)
+#define   BCW_QSPI_1_IOSET_1 (0x0u << 2)
+#define   BCW_QSPI_1_IOSET_2 (0x1u << 2)
+#define   BCW_QSPI_1_IOSET_3 (0x2u << 2)
+#define   BCW_QSPI_1_DISABLED (0x3u << 2)
+#define BCW_SPI_0_Pos 4
+#define BCW_SPI_0_Msk (0x3u << BCW_SPI_0_Pos)
+#define BCW_SPI_0(value) (BCW_SPI_0_Msk & ((value) << BCW_SPI_0_Pos)
+#define   BCW_SPI_0_IOSET_1 (0x0u << 4)
+#define   BCW_SPI_0_IOSET_2 (0x1u << 4)
+#define   BCW_SPI_0_DISABLED (0x3u << 4)
+#define BCW_SPI_1_Pos 6
+#define BCW_SPI_1_Msk (0x3u << BCW_SPI_1_Pos)
+#define BCW_SPI_1(value) (BCW_SPI_1_Msk & ((value) << BCW_SPI_1_Pos)
+#define   BCW_SPI_1_IOSET_1 (0x0u << 6)
+#define   BCW_SPI_1_IOSET_2 (0x1u << 6)
+#define   BCW_SPI_1_IOSET_3 (0x2u << 6)
+#define   BCW_SPI_1_DISABLED (0x3u << 6)
+#define BCW_NFC_Pos 8
+#define BCW_NFC_Msk (0x3u << BCW_NFC_Pos)
+#define BCW_NFC(value) (BCW_NFC_Msk & ((value) << BCW_NFC_Pos)
+#define   BCW_NFC_IOSET_1 (0x0u << 8)
+#define   BCW_NFC_IOSET_2 (0x1u << 8)
+#define   BCW_NFC_DISABLED (0x3u << 8)
+#define BCW_SDMMC_0_DISABLED (1 << 10)
+#define BCW_SDMMC_1_DISABLED (1 << 11)
+#define BCW_UART_CONSOLE_Pos 12
+#define BCW_UART_CONSOLE_Msk (0xfu << BCW_UART_CONSOLE_Pos)
+#define BCW_UART_CONSOLE(value) (BCW_UART_CONSOLE_Msk & ((value) << BCW_UART_CONSOLE_Pos)
+#define   BCW_UART_CONSOLE_UART1_IOSET_1 (0x0u << 12)
+#define   BCW_UART_CONSOLE_UART0_IOSET_1 (0x1u << 12)
+#define   BCW_UART_CONSOLE_UART1_IOSET_2 (0x2u << 12)
+#define   BCW_UART_CONSOLE_UART2_IOSET_1 (0x3u << 12)
+#define   BCW_UART_CONSOLE_UART2_IOSET_2 (0x4u << 12)
+#define   BCW_UART_CONSOLE_UART2_IOSET_3 (0x5u << 12)
+#define   BCW_UART_CONSOLE_UART3_IOSET_1 (0x6u << 12)
+#define   BCW_UART_CONSOLE_UART3_IOSET_2 (0x7u << 12)
+#define   BCW_UART_CONSOLE_UART3_IOSET_3 (0x8u << 12)
+#define   BCW_UART_CONSOLE_UART4_IOSET_1 (0x9u << 12)
+#define   BCW_UART_CONSOLE_DISABLED (0xfu << 12)
+#define BCW_JTAG_IO_SET_Pos 16
+#define BCW_JTAG_IO_SET_Msk (0x3u << BCW_JTAG_IO_SET_Pos)
+#define BCW_JTAG_IO_SET(value) (BCW_JTAG_IO_SET_Msk & ((value) << BCW_JTAG_IO_SET_Pos)
+#define   BCW_JTAG_IOSET_1 (0x0u << 16)
+#define   BCW_JTAG_IOSET_2 (0x1u << 16)
+#define   BCW_JTAG_IOSET_3 (0x2u << 16)
+#define   BCW_JTAG_IOSET_4 (0x3u << 16)
+#define BCW_EXT_MEM_BOOT_ENABLE (1 << 18)
+#define BCW_QSPI_XIP_MODE (1 << 21)
+#define BCW_DISABLE_BSCR (1 << 22)
+#define BCW_DISABLE_MONITOR (1 << 24)
+#define BCW_SECURE_MODE (1 << 29)
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_BSC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_chipid.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_chipid.h
new file mode 100644
index 000000000..4d485ccdc
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_chipid.h
@@ -0,0 +1,121 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_CHIPID_COMPONENT_
+#define _SAMA5D2_CHIPID_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Chip Identifier */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_CHIPID Chip Identifier */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Chipid hardware registers */
+typedef struct {
+  __I uint32_t CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
+  __I uint32_t CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
+} Chipid;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
+#define CHIPID_CIDR_VERSION_Pos 0
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */
+#define CHIPID_CIDR_EPROC_Pos 5
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */
+#define   CHIPID_CIDR_EPROC_SAMx7 (0x0u << 5) /**< \brief (CHIPID_CIDR) Cortex-M7 */
+#define   CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */
+#define   CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */
+#define   CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */
+#define   CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */
+#define   CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */
+#define   CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */
+#define   CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */
+#define CHIPID_CIDR_NVPSIZ_Pos 8
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8 Kbytes */
+#define   CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16 Kbytes */
+#define   CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32 Kbytes */
+#define   CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64 Kbytes */
+#define   CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128 Kbytes */
+#define   CHIPID_CIDR_NVPSIZ_160K (0x8u << 8) /**< \brief (CHIPID_CIDR) 160 Kbytes */
+#define   CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256 Kbytes */
+#define   CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512 Kbytes */
+#define   CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024 Kbytes */
+#define   CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048 Kbytes */
+#define CHIPID_CIDR_NVPSIZ2_Pos 12
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8 Kbytes */
+#define   CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16 Kbytes */
+#define   CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32 Kbytes */
+#define   CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64 Kbytes */
+#define   CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128 Kbytes */
+#define   CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256 Kbytes */
+#define   CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512 Kbytes */
+#define   CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024 Kbytes */
+#define   CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048 Kbytes */
+#define CHIPID_CIDR_SRAMSIZ_Pos 16
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
+#define   CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48 Kbytes */
+#define   CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16) /**< \brief (CHIPID_CIDR) 192 Kbytes */
+#define   CHIPID_CIDR_SRAMSIZ_384K (0x2u << 16) /**< \brief (CHIPID_CIDR) 384 Kbytes */
+#define   CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6 Kbytes */
+#define   CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24 Kbytes */
+#define   CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4 Kbytes */
+#define   CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80 Kbytes */
+#define   CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160 Kbytes */
+#define   CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8 Kbytes */
+#define   CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16 Kbytes */
+#define   CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32 Kbytes */
+#define   CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64 Kbytes */
+#define   CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128 Kbytes */
+#define   CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256 Kbytes */
+#define   CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96 Kbytes */
+#define   CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512 Kbytes */
+#define CHIPID_CIDR_ARCH_Pos 20
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */
+#define   CHIPID_CIDR_ARCH_SAM4CxxE (0x66u << 20) /**< \brief (CHIPID_CIDR) SAM4CxE (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAMA5 (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAMA5 */
+#define CHIPID_CIDR_NVPTYP_Pos 28
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
+#define   CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */
+#define   CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */
+#define   CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */
+#define   CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */
+#define   CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
+#define CHIPID_EXID_EXID_Pos 0
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_CHIPID_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_classd.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_classd.h
new file mode 100644
index 000000000..ca1dd2a9c
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_classd.h
@@ -0,0 +1,158 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_CLASSD_COMPONENT_
+#define _SAMA5D2_CLASSD_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Audio Class D Amplifier */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_CLASSD Audio Class D Amplifier */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Classd hardware registers */
+typedef struct {
+  __O  uint32_t CLASSD_CR;      /**< \brief (Classd Offset: 0x00) Control Register */
+  __IO uint32_t CLASSD_MR;      /**< \brief (Classd Offset: 0x04) Mode Register */
+  __IO uint32_t CLASSD_INTPMR;  /**< \brief (Classd Offset: 0x08) Interpolator Mode Register */
+  __I  uint32_t CLASSD_INTSR;   /**< \brief (Classd Offset: 0x0C) Interpolator Status Register */
+  __IO uint32_t CLASSD_THR;     /**< \brief (Classd Offset: 0x10) Transmit Holding Register */
+  __O  uint32_t CLASSD_IER;     /**< \brief (Classd Offset: 0x14) Interrupt Enable Register */
+  __O  uint32_t CLASSD_IDR;     /**< \brief (Classd Offset: 0x18) Interrupt Disable Register */
+  __IO uint32_t CLASSD_IMR;     /**< \brief (Classd Offset: 0x1C) Interrupt Mask Register */
+  __I  uint32_t CLASSD_ISR;     /**< \brief (Classd Offset: 0x20) Interrupt Status Register */
+  __I  uint32_t Reserved1[48];
+  __IO uint32_t CLASSD_WPMR;    /**< \brief (Classd Offset: 0xE4) Write Protection Mode Register */
+  __I  uint32_t Reserved2[5];
+  __I  uint32_t CLASSD_VERSION; /**< \brief (Classd Offset: 0xFC) IP Version Register */
+} Classd;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- CLASSD_CR : (CLASSD Offset: 0x00) Control Register -------- */
+#define CLASSD_CR_SWRST (0x1u << 0) /**< \brief (CLASSD_CR) Software Reset */
+/* -------- CLASSD_MR : (CLASSD Offset: 0x04) Mode Register -------- */
+#define CLASSD_MR_LEN (0x1u << 0) /**< \brief (CLASSD_MR) Left Channel Enable */
+#define CLASSD_MR_LMUTE (0x1u << 1) /**< \brief (CLASSD_MR) Left Channel Mute */
+#define CLASSD_MR_REN (0x1u << 4) /**< \brief (CLASSD_MR) Right Channel Enable */
+#define CLASSD_MR_RMUTE (0x1u << 5) /**< \brief (CLASSD_MR) Right Channel Mute */
+#define CLASSD_MR_PWMTYP (0x1u << 8) /**< \brief (CLASSD_MR) PWM Modulation Type */
+#define CLASSD_MR_NON_OVERLAP (0x1u << 16) /**< \brief (CLASSD_MR) Non-Overlapping Enable */
+#define CLASSD_MR_NOVRVAL_Pos 20
+#define CLASSD_MR_NOVRVAL_Msk (0x3u << CLASSD_MR_NOVRVAL_Pos) /**< \brief (CLASSD_MR) Non-Overlapping Value */
+#define CLASSD_MR_NOVRVAL(value) ((CLASSD_MR_NOVRVAL_Msk & ((value) << CLASSD_MR_NOVRVAL_Pos)))
+#define   CLASSD_MR_NOVRVAL_5NS (0x0u << 20) /**< \brief (CLASSD_MR) Non-overlapping time is 5 ns */
+#define   CLASSD_MR_NOVRVAL_10NS (0x1u << 20) /**< \brief (CLASSD_MR) Non-overlapping time is 10 ns */
+#define   CLASSD_MR_NOVRVAL_15NS (0x2u << 20) /**< \brief (CLASSD_MR) Non-overlapping time is 15 ns */
+#define   CLASSD_MR_NOVRVAL_20NS (0x3u << 20) /**< \brief (CLASSD_MR) Non-overlapping time is 20 ns */
+/* -------- CLASSD_INTPMR : (CLASSD Offset: 0x08) Interpolator Mode Register -------- */
+#define CLASSD_INTPMR_ATTL_Pos 0
+#define CLASSD_INTPMR_ATTL_Msk (0x7fu << CLASSD_INTPMR_ATTL_Pos) /**< \brief (CLASSD_INTPMR) Left Channel Attenuation */
+#define CLASSD_INTPMR_ATTL(value) ((CLASSD_INTPMR_ATTL_Msk & ((value) << CLASSD_INTPMR_ATTL_Pos)))
+#define CLASSD_INTPMR_ATTR_Pos 8
+#define CLASSD_INTPMR_ATTR_Msk (0x7fu << CLASSD_INTPMR_ATTR_Pos) /**< \brief (CLASSD_INTPMR) Right Channel Attenuation */
+#define CLASSD_INTPMR_ATTR(value) ((CLASSD_INTPMR_ATTR_Msk & ((value) << CLASSD_INTPMR_ATTR_Pos)))
+#define CLASSD_INTPMR_DSPCLKFREQ (0x1u << 16) /**< \brief (CLASSD_INTPMR) DSP Clock Frequency */
+#define   CLASSD_INTPMR_DSPCLKFREQ_12M288 (0x0u << 16) /**< \brief (CLASSD_INTPMR) DSP Clock (DSPCLK) is 12.288 MHz */
+#define   CLASSD_INTPMR_DSPCLKFREQ_11M2896 (0x1u << 16) /**< \brief (CLASSD_INTPMR) DSP Clock (DSPCLK) is 11.2896 MHz */
+#define CLASSD_INTPMR_DEEMP (0x1u << 18) /**< \brief (CLASSD_INTPMR) Enable De-emphasis Filter */
+#define   CLASSD_INTPMR_DEEMP_DISABLED (0x0u << 18) /**< \brief (CLASSD_INTPMR) De-emphasis filter is disabled */
+#define   CLASSD_INTPMR_DEEMP_ENABLED (0x1u << 18) /**< \brief (CLASSD_INTPMR) De-emphasis filter is enabled */
+#define CLASSD_INTPMR_SWAP (0x1u << 19) /**< \brief (CLASSD_INTPMR) Swap Left and Right Channels */
+#define   CLASSD_INTPMR_SWAP_LEFT_ON_LSB (0x0u << 19) /**< \brief (CLASSD_INTPMR) Left channel is on CLASSD_THR[15:0], right channel is on CLASSD_THR[31:16] */
+#define   CLASSD_INTPMR_SWAP_RIGHT_ON_LSB (0x1u << 19) /**< \brief (CLASSD_INTPMR) Right channel is on CLASSD_THR[15:0], left channel is on CLASSD_THR[31:16] */
+#define CLASSD_INTPMR_FRAME_Pos 20
+#define CLASSD_INTPMR_FRAME_Msk (0x7u << CLASSD_INTPMR_FRAME_Pos) /**< \brief (CLASSD_INTPMR) CLASSD Incoming Data Sampling Frequency */
+#define CLASSD_INTPMR_FRAME(value) ((CLASSD_INTPMR_FRAME_Msk & ((value) << CLASSD_INTPMR_FRAME_Pos)))
+#define   CLASSD_INTPMR_FRAME_FRAME_8K (0x0u << 20) /**< \brief (CLASSD_INTPMR) 8 kHz */
+#define   CLASSD_INTPMR_FRAME_FRAME_16K (0x1u << 20) /**< \brief (CLASSD_INTPMR) 16 kHz */
+#define   CLASSD_INTPMR_FRAME_FRAME_32K (0x2u << 20) /**< \brief (CLASSD_INTPMR) 32 kHz */
+#define   CLASSD_INTPMR_FRAME_FRAME_48K (0x3u << 20) /**< \brief (CLASSD_INTPMR) 48 kHz */
+#define   CLASSD_INTPMR_FRAME_FRAME_96K (0x4u << 20) /**< \brief (CLASSD_INTPMR) 96 kHz */
+#define   CLASSD_INTPMR_FRAME_FRAME_22K (0x5u << 20) /**< \brief (CLASSD_INTPMR) 22.05 kHz */
+#define   CLASSD_INTPMR_FRAME_FRAME_44K (0x6u << 20) /**< \brief (CLASSD_INTPMR) 44.1 kHz */
+#define   CLASSD_INTPMR_FRAME_FRAME_88K (0x7u << 20) /**< \brief (CLASSD_INTPMR) 88.2 kHz */
+#define CLASSD_INTPMR_EQCFG_Pos 24
+#define CLASSD_INTPMR_EQCFG_Msk (0xfu << CLASSD_INTPMR_EQCFG_Pos) /**< \brief (CLASSD_INTPMR) Equalization Selection */
+#define CLASSD_INTPMR_EQCFG(value) ((CLASSD_INTPMR_EQCFG_Msk & ((value) << CLASSD_INTPMR_EQCFG_Pos)))
+#define   CLASSD_INTPMR_EQCFG_FLAT (0x0u << 24) /**< \brief (CLASSD_INTPMR) Flat Response */
+#define   CLASSD_INTPMR_EQCFG_BBOOST12 (0x1u << 24) /**< \brief (CLASSD_INTPMR) Bass boost +12 dB */
+#define   CLASSD_INTPMR_EQCFG_BBOOST6 (0x2u << 24) /**< \brief (CLASSD_INTPMR) Bass boost +6 dB */
+#define   CLASSD_INTPMR_EQCFG_BCUT12 (0x3u << 24) /**< \brief (CLASSD_INTPMR) Bass cut -12 dB */
+#define   CLASSD_INTPMR_EQCFG_BCUT6 (0x4u << 24) /**< \brief (CLASSD_INTPMR) Bass cut -6 dB */
+#define   CLASSD_INTPMR_EQCFG_MBOOST3 (0x5u << 24) /**< \brief (CLASSD_INTPMR) Medium boost +3 dB */
+#define   CLASSD_INTPMR_EQCFG_MBOOST8 (0x6u << 24) /**< \brief (CLASSD_INTPMR) Medium boost +8 dB */
+#define   CLASSD_INTPMR_EQCFG_MCUT3 (0x7u << 24) /**< \brief (CLASSD_INTPMR) Medium cut -3 dB */
+#define   CLASSD_INTPMR_EQCFG_MCUT8 (0x8u << 24) /**< \brief (CLASSD_INTPMR) Medium cut -8 dB */
+#define   CLASSD_INTPMR_EQCFG_TBOOST12 (0x9u << 24) /**< \brief (CLASSD_INTPMR) Treble boost +12 dB */
+#define   CLASSD_INTPMR_EQCFG_TBOOST6 (0xAu << 24) /**< \brief (CLASSD_INTPMR) Treble boost +6 dB */
+#define   CLASSD_INTPMR_EQCFG_TCUT12 (0xBu << 24) /**< \brief (CLASSD_INTPMR) Treble cut -12 dB */
+#define   CLASSD_INTPMR_EQCFG_TCUT6 (0xCu << 24) /**< \brief (CLASSD_INTPMR) Treble cut -6 dB */
+#define CLASSD_INTPMR_MONO (0x1u << 28) /**< \brief (CLASSD_INTPMR) Mono Signal */
+#define   CLASSD_INTPMR_MONO_DISABLED (0x0u << 28) /**< \brief (CLASSD_INTPMR) The signal is sent stereo to the left and right channels. */
+#define   CLASSD_INTPMR_MONO_ENABLED (0x1u << 28) /**< \brief (CLASSD_INTPMR) The same signal is sent on both left and right channels. The sent signal is defined by the MONOMODE field value. */
+#define CLASSD_INTPMR_MONOMODE_Pos 29
+#define CLASSD_INTPMR_MONOMODE_Msk (0x3u << CLASSD_INTPMR_MONOMODE_Pos) /**< \brief (CLASSD_INTPMR) Mono Mode Selection */
+#define CLASSD_INTPMR_MONOMODE(value) ((CLASSD_INTPMR_MONOMODE_Msk & ((value) << CLASSD_INTPMR_MONOMODE_Pos)))
+#define   CLASSD_INTPMR_MONOMODE_MONOMIX (0x0u << 29) /**< \brief (CLASSD_INTPMR) (left + right) / 2 is sent on both channels */
+#define   CLASSD_INTPMR_MONOMODE_MONOSAT (0x1u << 29) /**< \brief (CLASSD_INTPMR) (left + right) is sent to both channels. If the sum is too high, the result is saturated. */
+#define   CLASSD_INTPMR_MONOMODE_MONOLEFT (0x2u << 29) /**< \brief (CLASSD_INTPMR) THR[15:0] is sent on both left and right channels */
+#define   CLASSD_INTPMR_MONOMODE_MONORIGHT (0x3u << 29) /**< \brief (CLASSD_INTPMR) THR[31:16] is sent on both left and right channels */
+/* -------- CLASSD_INTSR : (CLASSD Offset: 0x0C) Interpolator Status Register -------- */
+#define CLASSD_INTSR_CFGERR (0x1u << 0) /**< \brief (CLASSD_INTSR) Configuration Error */
+/* -------- CLASSD_THR : (CLASSD Offset: 0x10) Transmit Holding Register -------- */
+#define CLASSD_THR_LDATA_Pos 0
+#define CLASSD_THR_LDATA_Msk (0xffffu << CLASSD_THR_LDATA_Pos) /**< \brief (CLASSD_THR) Left Channel Data */
+#define CLASSD_THR_LDATA(value) ((CLASSD_THR_LDATA_Msk & ((value) << CLASSD_THR_LDATA_Pos)))
+#define CLASSD_THR_RDATA_Pos 16
+#define CLASSD_THR_RDATA_Msk (0xffffu << CLASSD_THR_RDATA_Pos) /**< \brief (CLASSD_THR) Right Channel Data */
+#define CLASSD_THR_RDATA(value) ((CLASSD_THR_RDATA_Msk & ((value) << CLASSD_THR_RDATA_Pos)))
+/* -------- CLASSD_IER : (CLASSD Offset: 0x14) Interrupt Enable Register -------- */
+#define CLASSD_IER_DATRDY (0x1u << 0) /**< \brief (CLASSD_IER) Data Ready */
+/* -------- CLASSD_IDR : (CLASSD Offset: 0x18) Interrupt Disable Register -------- */
+#define CLASSD_IDR_DATRDY (0x1u << 0) /**< \brief (CLASSD_IDR) Data Ready */
+/* -------- CLASSD_IMR : (CLASSD Offset: 0x1C) Interrupt Mask Register -------- */
+#define CLASSD_IMR_DATRDY (0x1u << 0) /**< \brief (CLASSD_IMR) Data Ready */
+/* -------- CLASSD_ISR : (CLASSD Offset: 0x20) Interrupt Status Register -------- */
+#define CLASSD_ISR_DATRDY (0x1u << 0) /**< \brief (CLASSD_ISR) Data Ready */
+/* -------- CLASSD_WPMR : (CLASSD Offset: 0xE4) Write Protection Mode Register -------- */
+#define CLASSD_WPMR_WPEN (0x1u << 0) /**< \brief (CLASSD_WPMR) Write Protection Enable */
+#define CLASSD_WPMR_WPKEY_Pos 8
+#define CLASSD_WPMR_WPKEY_Msk (0xffffffu << CLASSD_WPMR_WPKEY_Pos) /**< \brief (CLASSD_WPMR) Write Protection Key */
+#define CLASSD_WPMR_WPKEY(value) ((CLASSD_WPMR_WPKEY_Msk & ((value) << CLASSD_WPMR_WPKEY_Pos)))
+#define   CLASSD_WPMR_WPKEY_PASSWD (0x434C44u << 8) /**< \brief (CLASSD_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
+/* -------- CLASSD_VERSION : (CLASSD Offset: 0xFC) IP Version Register -------- */
+#define CLASSD_VERSION_VERSION_Pos 0
+#define CLASSD_VERSION_VERSION_Msk (0xfffu << CLASSD_VERSION_VERSION_Pos) /**< \brief (CLASSD_VERSION) Version of the Hardware Module */
+#define CLASSD_VERSION_MFN_Pos 16
+#define CLASSD_VERSION_MFN_Msk (0x7u << CLASSD_VERSION_MFN_Pos) /**< \brief (CLASSD_VERSION) Metal Fix Number */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_CLASSD_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_flexcom.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_flexcom.h
new file mode 100644
index 000000000..6eea644da
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_flexcom.h
@@ -0,0 +1,71 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_FLEXCOM_COMPONENT_
+#define _SAMA5D2_FLEXCOM_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Flexible Serial Communication */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_FLEXCOM Flexible Serial Communication */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+
+/** \brief Flexcom hardware registers */
+typedef struct {
+	__IO uint32_t FLEX_MR;          /**< \brief (Flexcom Offset: 0x000) FLEXCOM Mode Register */
+	__I  uint32_t Reserved1[3];
+	__I  uint32_t FLEX_RHR;         /**< \brief (Flexcom Offset: 0x010) FLEXCOM Receive Holding Register */
+	__I  uint32_t Reserved2[3];
+	__IO uint32_t FLEX_THR;         /**< \brief (Flexcom Offset: 0x020) FLEXCOM Transmit Holding Register */
+} Flexcom;
+
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* -------- FLEX_MR : (FLEXCOM Offset: 0x000) FLEXCOM Mode Register -------- */
+#define FLEX_MR_OPMODE_Pos 0
+#define FLEX_MR_OPMODE_Msk (0x3u << FLEX_MR_OPMODE_Pos) /**< \brief (FLEX_MR) FLEXCOM Operating Mode */
+#define FLEX_MR_OPMODE(value) ((FLEX_MR_OPMODE_Msk & ((value) << FLEX_MR_OPMODE_Pos)))
+#define   FLEX_MR_OPMODE_NO_COM (0x0u << 0) /**< \brief (FLEX_MR) No communication */
+#define   FLEX_MR_OPMODE_USART (0x1u << 0) /**< \brief (FLEX_MR) All related UART related protocols are selected (RS232, RS485, IrDA, ISO7816, LIN,)All SPI/TWI related registers are not accessible and have no impact on IOs. */
+#define   FLEX_MR_OPMODE_SPI (0x2u << 0) /**< \brief (FLEX_MR) SPI operating mode is selected.All USART/TWI related registers are not accessible and have no impact on IOs. */
+#define   FLEX_MR_OPMODE_TWI (0x3u << 0) /**< \brief (FLEX_MR) All related TWI protocols are selected (TWI, SMBus). All USART/SPI related registers are not accessible and have no impact on IOs. */
+/* -------- FLEX_RHR : (FLEXCOM Offset: 0x010) FLEXCOM Receive Holding Register -------- */
+#define FLEX_RHR_RXDATA_Pos 0
+#define FLEX_RHR_RXDATA_Msk (0xffffu << FLEX_RHR_RXDATA_Pos) /**< \brief (FLEX_RHR) Receive Data */
+/* -------- FLEX_THR : (FLEXCOM Offset: 0x020) FLEXCOM Transmit Holding Register -------- */
+#define FLEX_THR_TXDATA_Pos 0
+#define FLEX_THR_TXDATA_Msk (0xffffu << FLEX_THR_TXDATA_Pos) /**< \brief (FLEX_THR) Transmit Data */
+#define FLEX_THR_TXDATA(value) ((FLEX_THR_TXDATA_Msk & ((value) << FLEX_THR_TXDATA_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_FLEXCOM_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_gmac.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_gmac.h
new file mode 100644
index 000000000..648173893
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_gmac.h
@@ -0,0 +1,1284 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_GMAC_COMPONENT_
+#define _SAMA5D2_GMAC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Gigabit Ethernet MAC */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_GMAC Gigabit Ethernet MAC */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief GmacSa hardware registers */
+typedef struct {
+  __IO uint32_t GMAC_SAB; /**< \brief (GmacSa Offset: 0x0) Specific Address 1 Bottom Register */
+  __IO uint32_t GMAC_SAT; /**< \brief (GmacSa Offset: 0x4) Specific Address 1 Top Register */
+} GmacSa;
+/** \brief Gmac hardware registers */
+#define GMACSA_NUMBER 4
+typedef struct {
+  __IO uint32_t GMAC_NCR;               /**< \brief (Gmac Offset: 0x000) Network Control Register */
+  __IO uint32_t GMAC_NCFGR;             /**< \brief (Gmac Offset: 0x004) Network Configuration Register */
+  __I  uint32_t GMAC_NSR;               /**< \brief (Gmac Offset: 0x008) Network Status Register */
+  __IO uint32_t GMAC_UR;                /**< \brief (Gmac Offset: 0x00C) User Register */
+  __IO uint32_t GMAC_DCFGR;             /**< \brief (Gmac Offset: 0x010) DMA Configuration Register */
+  __IO uint32_t GMAC_TSR;               /**< \brief (Gmac Offset: 0x014) Transmit Status Register */
+  __IO uint32_t GMAC_RBQB;              /**< \brief (Gmac Offset: 0x018) Receive Buffer Queue Base Address Register */
+  __IO uint32_t GMAC_TBQB;              /**< \brief (Gmac Offset: 0x01C) Transmit Buffer Queue Base Address Register */
+  __IO uint32_t GMAC_RSR;               /**< \brief (Gmac Offset: 0x020) Receive Status Register */
+  __I  uint32_t GMAC_ISR;               /**< \brief (Gmac Offset: 0x024) Interrupt Status Register */
+  __O  uint32_t GMAC_IER;               /**< \brief (Gmac Offset: 0x028) Interrupt Enable Register */
+  __O  uint32_t GMAC_IDR;               /**< \brief (Gmac Offset: 0x02C) Interrupt Disable Register */
+  __IO uint32_t GMAC_IMR;               /**< \brief (Gmac Offset: 0x030) Interrupt Mask Register */
+  __IO uint32_t GMAC_MAN;               /**< \brief (Gmac Offset: 0x034) PHY Maintenance Register */
+  __I  uint32_t GMAC_RPQ;               /**< \brief (Gmac Offset: 0x038) Received Pause Quantum Register */
+  __IO uint32_t GMAC_TPQ;               /**< \brief (Gmac Offset: 0x03C) Transmit Pause Quantum Register */
+  __IO uint32_t GMAC_TPSF;              /**< \brief (Gmac Offset: 0x040) TX Partial Store and Forward Register */
+  __IO uint32_t GMAC_RPSF;              /**< \brief (Gmac Offset: 0x044) RX Partial Store and Forward Register */
+  __IO uint32_t GMAC_RJFML;             /**< \brief (Gmac Offset: 0x048) RX Jumbo Frame Max Length Register */
+  __I  uint32_t Reserved1[13];
+  __IO uint32_t GMAC_HRB;               /**< \brief (Gmac Offset: 0x080) Hash Register Bottom */
+  __IO uint32_t GMAC_HRT;               /**< \brief (Gmac Offset: 0x084) Hash Register Top */
+       GmacSa   GMAC_SA[GMACSA_NUMBER]; /**< \brief (Gmac Offset: 0x088) 1 .. 4 */
+  __IO uint32_t GMAC_TIDM1;             /**< \brief (Gmac Offset: 0x0A8) Type ID Match 1 Register */
+  __IO uint32_t GMAC_TIDM2;             /**< \brief (Gmac Offset: 0x0AC) Type ID Match 2 Register */
+  __IO uint32_t GMAC_TIDM3;             /**< \brief (Gmac Offset: 0x0B0) Type ID Match 3 Register */
+  __IO uint32_t GMAC_TIDM4;             /**< \brief (Gmac Offset: 0x0B4) Type ID Match 4 Register */
+  __IO uint32_t GMAC_WOL;               /**< \brief (Gmac Offset: 0x0B8) Wake on LAN Register */
+  __IO uint32_t GMAC_IPGS;              /**< \brief (Gmac Offset: 0x0BC) IPG Stretch Register */
+  __IO uint32_t GMAC_SVLAN;             /**< \brief (Gmac Offset: 0x0C0) Stacked VLAN Register */
+  __IO uint32_t GMAC_TPFCP;             /**< \brief (Gmac Offset: 0x0C4) Transmit PFC Pause Register */
+  __IO uint32_t GMAC_SAMB1;             /**< \brief (Gmac Offset: 0x0C8) Specific Address 1 Mask Bottom Register */
+  __IO uint32_t GMAC_SAMT1;             /**< \brief (Gmac Offset: 0x0CC) Specific Address 1 Mask Top Register */
+  __I  uint32_t Reserved2[3];
+  __IO uint32_t GMAC_NSC;               /**< \brief (Gmac Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register */
+  __IO uint32_t GMAC_SCL;               /**< \brief (Gmac Offset: 0x0E0) 1588 Timer Second Comparison Low Register */
+  __IO uint32_t GMAC_SCH;               /**< \brief (Gmac Offset: 0x0E4) 1588 Timer Second Comparison High Register */
+  __I  uint32_t GMAC_EFTSH;             /**< \brief (Gmac Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register */
+  __I  uint32_t GMAC_EFRSH;             /**< \brief (Gmac Offset: 0x0EC) PTP Event Frame Received Seconds High Register */
+  __I  uint32_t GMAC_PEFTSH;            /**< \brief (Gmac Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register */
+  __I  uint32_t GMAC_PEFRSH;            /**< \brief (Gmac Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register */
+  __I  uint32_t Reserved3[1];
+  __I  uint32_t GMAC_MID;               /**< \brief (Gmac Offset: 0x0FC) Module ID Register */
+  __I  uint32_t GMAC_OTLO;              /**< \brief (Gmac Offset: 0x100) Octets Transmitted Low Register */
+  __I  uint32_t GMAC_OTHI;              /**< \brief (Gmac Offset: 0x104) Octets Transmitted High Register */
+  __I  uint32_t GMAC_FT;                /**< \brief (Gmac Offset: 0x108) Frames Transmitted Register */
+  __I  uint32_t GMAC_BCFT;              /**< \brief (Gmac Offset: 0x10C) Broadcast Frames Transmitted Register */
+  __I  uint32_t GMAC_MFT;               /**< \brief (Gmac Offset: 0x110) Multicast Frames Transmitted Register */
+  __I  uint32_t GMAC_PFT;               /**< \brief (Gmac Offset: 0x114) Pause Frames Transmitted Register */
+  __I  uint32_t GMAC_BFT64;             /**< \brief (Gmac Offset: 0x118) 64 Byte Frames Transmitted Register */
+  __I  uint32_t GMAC_TBFT127;           /**< \brief (Gmac Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register */
+  __I  uint32_t GMAC_TBFT255;           /**< \brief (Gmac Offset: 0x120) 128 to 255 Byte Frames Transmitted Register */
+  __I  uint32_t GMAC_TBFT511;           /**< \brief (Gmac Offset: 0x124) 256 to 511 Byte Frames Transmitted Register */
+  __I  uint32_t GMAC_TBFT1023;          /**< \brief (Gmac Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register */
+  __I  uint32_t GMAC_TBFT1518;          /**< \brief (Gmac Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register */
+  __I  uint32_t GMAC_GTBFT1518;         /**< \brief (Gmac Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register */
+  __I  uint32_t GMAC_TUR;               /**< \brief (Gmac Offset: 0x134) Transmit Underruns Register */
+  __I  uint32_t GMAC_SCF;               /**< \brief (Gmac Offset: 0x138) Single Collision Frames Register */
+  __I  uint32_t GMAC_MCF;               /**< \brief (Gmac Offset: 0x13C) Multiple Collision Frames Register */
+  __I  uint32_t GMAC_EC;                /**< \brief (Gmac Offset: 0x140) Excessive Collisions Register */
+  __I  uint32_t GMAC_LC;                /**< \brief (Gmac Offset: 0x144) Late Collisions Register */
+  __I  uint32_t GMAC_DTF;               /**< \brief (Gmac Offset: 0x148) Deferred Transmission Frames Register */
+  __I  uint32_t GMAC_CSE;               /**< \brief (Gmac Offset: 0x14C) Carrier Sense Errors Register */
+  __I  uint32_t GMAC_ORLO;              /**< \brief (Gmac Offset: 0x150) Octets Received Low Received Register */
+  __I  uint32_t GMAC_ORHI;              /**< \brief (Gmac Offset: 0x154) Octets Received High Received Register */
+  __I  uint32_t GMAC_FR;                /**< \brief (Gmac Offset: 0x158) Frames Received Register */
+  __I  uint32_t GMAC_BCFR;              /**< \brief (Gmac Offset: 0x15C) Broadcast Frames Received Register */
+  __I  uint32_t GMAC_MFR;               /**< \brief (Gmac Offset: 0x160) Multicast Frames Received Register */
+  __I  uint32_t GMAC_PFR;               /**< \brief (Gmac Offset: 0x164) Pause Frames Received Register */
+  __I  uint32_t GMAC_BFR64;             /**< \brief (Gmac Offset: 0x168) 64 Byte Frames Received Register */
+  __I  uint32_t GMAC_TBFR127;           /**< \brief (Gmac Offset: 0x16C) 65 to 127 Byte Frames Received Register */
+  __I  uint32_t GMAC_TBFR255;           /**< \brief (Gmac Offset: 0x170) 128 to 255 Byte Frames Received Register */
+  __I  uint32_t GMAC_TBFR511;           /**< \brief (Gmac Offset: 0x174) 256 to 511 Byte Frames Received Register */
+  __I  uint32_t GMAC_TBFR1023;          /**< \brief (Gmac Offset: 0x178) 512 to 1023 Byte Frames Received Register */
+  __I  uint32_t GMAC_TBFR1518;          /**< \brief (Gmac Offset: 0x17C) 1024 to 1518 Byte Frames Received Register */
+  __I  uint32_t GMAC_TMXBFR;            /**< \brief (Gmac Offset: 0x180) 1519 to Maximum Byte Frames Received Register */
+  __I  uint32_t GMAC_UFR;               /**< \brief (Gmac Offset: 0x184) Undersize Frames Received Register */
+  __I  uint32_t GMAC_OFR;               /**< \brief (Gmac Offset: 0x188) Oversize Frames Received Register */
+  __I  uint32_t GMAC_JR;                /**< \brief (Gmac Offset: 0x18C) Jabbers Received Register */
+  __I  uint32_t GMAC_FCSE;              /**< \brief (Gmac Offset: 0x190) Frame Check Sequence Errors Register */
+  __I  uint32_t GMAC_LFFE;              /**< \brief (Gmac Offset: 0x194) Length Field Frame Errors Register */
+  __I  uint32_t GMAC_RSE;               /**< \brief (Gmac Offset: 0x198) Receive Symbol Errors Register */
+  __I  uint32_t GMAC_AE;                /**< \brief (Gmac Offset: 0x19C) Alignment Errors Register */
+  __I  uint32_t GMAC_RRE;               /**< \brief (Gmac Offset: 0x1A0) Receive Resource Errors Register */
+  __I  uint32_t GMAC_ROE;               /**< \brief (Gmac Offset: 0x1A4) Receive Overrun Register */
+  __I  uint32_t GMAC_IHCE;              /**< \brief (Gmac Offset: 0x1A8) IP Header Checksum Errors Register */
+  __I  uint32_t GMAC_TCE;               /**< \brief (Gmac Offset: 0x1AC) TCP Checksum Errors Register */
+  __I  uint32_t GMAC_UCE;               /**< \brief (Gmac Offset: 0x1B0) UDP Checksum Errors Register */
+  __I  uint32_t Reserved4[2];
+  __IO uint32_t GMAC_TISUBN;            /**< \brief (Gmac Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register */
+  __IO uint32_t GMAC_TSH;               /**< \brief (Gmac Offset: 0x1C0) 1588 Timer Seconds High Register */
+  __I  uint32_t Reserved5[3];
+  __IO uint32_t GMAC_TSL;               /**< \brief (Gmac Offset: 0x1D0) 1588 Timer Seconds Low Register */
+  __IO uint32_t GMAC_TN;                /**< \brief (Gmac Offset: 0x1D4) 1588 Timer Nanoseconds Register */
+  __O  uint32_t GMAC_TA;                /**< \brief (Gmac Offset: 0x1D8) 1588 Timer Adjust Register */
+  __IO uint32_t GMAC_TI;                /**< \brief (Gmac Offset: 0x1DC) 1588 Timer Increment Register */
+  __I  uint32_t GMAC_EFTSL;             /**< \brief (Gmac Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register */
+  __I  uint32_t GMAC_EFTN;              /**< \brief (Gmac Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register */
+  __I  uint32_t GMAC_EFRSL;             /**< \brief (Gmac Offset: 0x1E8) PTP Event Frame Received Seconds Low Register */
+  __I  uint32_t GMAC_EFRN;              /**< \brief (Gmac Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register */
+  __I  uint32_t GMAC_PEFTSL;            /**< \brief (Gmac Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register */
+  __I  uint32_t GMAC_PEFTN;             /**< \brief (Gmac Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register */
+  __I  uint32_t GMAC_PEFRSL;            /**< \brief (Gmac Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register */
+  __I  uint32_t GMAC_PEFRN;             /**< \brief (Gmac Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register */
+  __I  uint32_t Reserved6[128];
+  __I  uint32_t GMAC_ISRPQ[2];          /**< \brief (Gmac Offset: 0x400) Interrupt Status Register Priority Queue (index = 1) */
+  __I  uint32_t Reserved7[14];
+  __IO uint32_t GMAC_TBQBAPQ[2];        /**< \brief (Gmac Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) */
+  __I  uint32_t Reserved8[14];
+  __IO uint32_t GMAC_RBQBAPQ[2];        /**< \brief (Gmac Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1) */
+  __I  uint32_t Reserved9[6];
+  __IO uint32_t GMAC_RBSRPQ[2];         /**< \brief (Gmac Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1) */
+  __I  uint32_t Reserved10[5];
+  __IO uint32_t GMAC_CBSCR;             /**< \brief (Gmac Offset: 0x4BC) Credit-Based Shaping Control Register */
+  __IO uint32_t GMAC_CBSISQA;           /**< \brief (Gmac Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A */
+  __IO uint32_t GMAC_CBSISQB;           /**< \brief (Gmac Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B */
+  __I  uint32_t Reserved11[14];
+  __IO uint32_t GMAC_ST1RPQ[4];         /**< \brief (Gmac Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0) */
+  __I  uint32_t Reserved12[12];
+  __IO uint32_t GMAC_ST2RPQ[8];         /**< \brief (Gmac Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0) */
+  __I  uint32_t Reserved13[12];
+  __I  uint32_t Reserved14[28];
+  __O  uint32_t GMAC_IERPQ[2];          /**< \brief (Gmac Offset: 0x600) Interrupt Enable Register Priority Queue (index = 1) */
+  __I  uint32_t Reserved15[6];
+  __O  uint32_t GMAC_IDRPQ[2];          /**< \brief (Gmac Offset: 0x620) Interrupt Disable Register Priority Queue (index = 1) */
+  __I  uint32_t Reserved16[6];
+  __IO uint32_t GMAC_IMRPQ[2];          /**< \brief (Gmac Offset: 0x640) Interrupt Mask Register Priority Queue (index = 1) */
+  __I  uint32_t Reserved17[38];
+  __IO uint32_t GMAC_ST2ER[4];          /**< \brief (Gmac Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0) */
+  __I  uint32_t Reserved18[4];
+  __IO uint32_t GMAC_ST2CW00;           /**< \brief (Gmac Offset: 0x700) Screening Type 2 Compare Word 0 Register (index = 0) */
+  __IO uint32_t GMAC_ST2CW10;           /**< \brief (Gmac Offset: 0x704) Screening Type 2 Compare Word 1 Register (index = 0) */
+  __IO uint32_t GMAC_ST2CW01;           /**< \brief (Gmac Offset: 0x708) Screening Type 2 Compare Word 0 Register (index = 1) */
+  __IO uint32_t GMAC_ST2CW11;           /**< \brief (Gmac Offset: 0x70C) Screening Type 2 Compare Word 1 Register (index = 1) */
+  __IO uint32_t GMAC_ST2CW02;           /**< \brief (Gmac Offset: 0x710) Screening Type 2 Compare Word 0 Register (index = 2) */
+  __IO uint32_t GMAC_ST2CW12;           /**< \brief (Gmac Offset: 0x714) Screening Type 2 Compare Word 1 Register (index = 2) */
+  __IO uint32_t GMAC_ST2CW03;           /**< \brief (Gmac Offset: 0x718) Screening Type 2 Compare Word 0 Register (index = 3) */
+  __IO uint32_t GMAC_ST2CW13;           /**< \brief (Gmac Offset: 0x71C) Screening Type 2 Compare Word 1 Register (index = 3) */
+  __IO uint32_t GMAC_ST2CW04;           /**< \brief (Gmac Offset: 0x720) Screening Type 2 Compare Word 0 Register (index = 4) */
+  __IO uint32_t GMAC_ST2CW14;           /**< \brief (Gmac Offset: 0x724) Screening Type 2 Compare Word 1 Register (index = 4) */
+  __IO uint32_t GMAC_ST2CW05;           /**< \brief (Gmac Offset: 0x728) Screening Type 2 Compare Word 0 Register (index = 5) */
+  __IO uint32_t GMAC_ST2CW15;           /**< \brief (Gmac Offset: 0x72C) Screening Type 2 Compare Word 1 Register (index = 5) */
+  __IO uint32_t GMAC_ST2CW06;           /**< \brief (Gmac Offset: 0x730) Screening Type 2 Compare Word 0 Register (index = 6) */
+  __IO uint32_t GMAC_ST2CW16;           /**< \brief (Gmac Offset: 0x734) Screening Type 2 Compare Word 1 Register (index = 6) */
+  __IO uint32_t GMAC_ST2CW07;           /**< \brief (Gmac Offset: 0x738) Screening Type 2 Compare Word 0 Register (index = 7) */
+  __IO uint32_t GMAC_ST2CW17;           /**< \brief (Gmac Offset: 0x73C) Screening Type 2 Compare Word 1 Register (index = 7) */
+  __IO uint32_t GMAC_ST2CW08;           /**< \brief (Gmac Offset: 0x740) Screening Type 2 Compare Word 0 Register (index = 8) */
+  __IO uint32_t GMAC_ST2CW18;           /**< \brief (Gmac Offset: 0x744) Screening Type 2 Compare Word 1 Register (index = 8) */
+  __IO uint32_t GMAC_ST2CW09;           /**< \brief (Gmac Offset: 0x748) Screening Type 2 Compare Word 0 Register (index = 9) */
+  __IO uint32_t GMAC_ST2CW19;           /**< \brief (Gmac Offset: 0x74C) Screening Type 2 Compare Word 1 Register (index = 9) */
+  __IO uint32_t GMAC_ST2CW010;          /**< \brief (Gmac Offset: 0x750) Screening Type 2 Compare Word 0 Register (index = 10) */
+  __IO uint32_t GMAC_ST2CW110;          /**< \brief (Gmac Offset: 0x754) Screening Type 2 Compare Word 1 Register (index = 10) */
+  __IO uint32_t GMAC_ST2CW011;          /**< \brief (Gmac Offset: 0x758) Screening Type 2 Compare Word 0 Register (index = 11) */
+  __IO uint32_t GMAC_ST2CW111;          /**< \brief (Gmac Offset: 0x75C) Screening Type 2 Compare Word 1 Register (index = 11) */
+  __IO uint32_t GMAC_ST2CW012;          /**< \brief (Gmac Offset: 0x760) Screening Type 2 Compare Word 0 Register (index = 12) */
+  __IO uint32_t GMAC_ST2CW112;          /**< \brief (Gmac Offset: 0x764) Screening Type 2 Compare Word 1 Register (index = 12) */
+  __IO uint32_t GMAC_ST2CW013;          /**< \brief (Gmac Offset: 0x768) Screening Type 2 Compare Word 0 Register (index = 13) */
+  __IO uint32_t GMAC_ST2CW113;          /**< \brief (Gmac Offset: 0x76C) Screening Type 2 Compare Word 1 Register (index = 13) */
+  __IO uint32_t GMAC_ST2CW014;          /**< \brief (Gmac Offset: 0x770) Screening Type 2 Compare Word 0 Register (index = 14) */
+  __IO uint32_t GMAC_ST2CW114;          /**< \brief (Gmac Offset: 0x774) Screening Type 2 Compare Word 1 Register (index = 14) */
+  __IO uint32_t GMAC_ST2CW015;          /**< \brief (Gmac Offset: 0x778) Screening Type 2 Compare Word 0 Register (index = 15) */
+  __IO uint32_t GMAC_ST2CW115;          /**< \brief (Gmac Offset: 0x77C) Screening Type 2 Compare Word 1 Register (index = 15) */
+  __IO uint32_t GMAC_ST2CW016;          /**< \brief (Gmac Offset: 0x780) Screening Type 2 Compare Word 0 Register (index = 16) */
+  __IO uint32_t GMAC_ST2CW116;          /**< \brief (Gmac Offset: 0x784) Screening Type 2 Compare Word 1 Register (index = 16) */
+  __IO uint32_t GMAC_ST2CW017;          /**< \brief (Gmac Offset: 0x788) Screening Type 2 Compare Word 0 Register (index = 17) */
+  __IO uint32_t GMAC_ST2CW117;          /**< \brief (Gmac Offset: 0x78C) Screening Type 2 Compare Word 1 Register (index = 17) */
+  __IO uint32_t GMAC_ST2CW018;          /**< \brief (Gmac Offset: 0x790) Screening Type 2 Compare Word 0 Register (index = 18) */
+  __IO uint32_t GMAC_ST2CW118;          /**< \brief (Gmac Offset: 0x794) Screening Type 2 Compare Word 1 Register (index = 18) */
+  __IO uint32_t GMAC_ST2CW019;          /**< \brief (Gmac Offset: 0x798) Screening Type 2 Compare Word 0 Register (index = 19) */
+  __IO uint32_t GMAC_ST2CW119;          /**< \brief (Gmac Offset: 0x79C) Screening Type 2 Compare Word 1 Register (index = 19) */
+  __IO uint32_t GMAC_ST2CW020;          /**< \brief (Gmac Offset: 0x7A0) Screening Type 2 Compare Word 0 Register (index = 20) */
+  __IO uint32_t GMAC_ST2CW120;          /**< \brief (Gmac Offset: 0x7A4) Screening Type 2 Compare Word 1 Register (index = 20) */
+  __IO uint32_t GMAC_ST2CW021;          /**< \brief (Gmac Offset: 0x7A8) Screening Type 2 Compare Word 0 Register (index = 21) */
+  __IO uint32_t GMAC_ST2CW121;          /**< \brief (Gmac Offset: 0x7AC) Screening Type 2 Compare Word 1 Register (index = 21) */
+  __IO uint32_t GMAC_ST2CW022;          /**< \brief (Gmac Offset: 0x7B0) Screening Type 2 Compare Word 0 Register (index = 22) */
+  __IO uint32_t GMAC_ST2CW122;          /**< \brief (Gmac Offset: 0x7B4) Screening Type 2 Compare Word 1 Register (index = 22) */
+  __IO uint32_t GMAC_ST2CW023;          /**< \brief (Gmac Offset: 0x7B8) Screening Type 2 Compare Word 0 Register (index = 23) */
+  __IO uint32_t GMAC_ST2CW123;          /**< \brief (Gmac Offset: 0x7BC) Screening Type 2 Compare Word 1 Register (index = 23) */
+} Gmac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- GMAC_NCR : (GMAC Offset: 0x000) Network Control Register -------- */
+#define GMAC_NCR_LBL (0x1u << 1) /**< \brief (GMAC_NCR) Loop Back Local */
+#define GMAC_NCR_RXEN (0x1u << 2) /**< \brief (GMAC_NCR) Receive Enable */
+#define GMAC_NCR_TXEN (0x1u << 3) /**< \brief (GMAC_NCR) Transmit Enable */
+#define GMAC_NCR_MPE (0x1u << 4) /**< \brief (GMAC_NCR) Management Port Enable */
+#define GMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (GMAC_NCR) Clear Statistics Registers */
+#define GMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (GMAC_NCR) Increment Statistics Registers */
+#define GMAC_NCR_WESTAT (0x1u << 7) /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */
+#define GMAC_NCR_BP (0x1u << 8) /**< \brief (GMAC_NCR) Back pressure */
+#define GMAC_NCR_TSTART (0x1u << 9) /**< \brief (GMAC_NCR) Start Transmission */
+#define GMAC_NCR_THALT (0x1u << 10) /**< \brief (GMAC_NCR) Transmit Halt */
+#define GMAC_NCR_TXPF (0x1u << 11) /**< \brief (GMAC_NCR) Transmit Pause Frame */
+#define GMAC_NCR_TXZQPF (0x1u << 12) /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */
+#define GMAC_NCR_SRTSM (0x1u << 15) /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */
+#define GMAC_NCR_ENPBPR (0x1u << 16) /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */
+#define GMAC_NCR_TXPBPF (0x1u << 17) /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */
+#define GMAC_NCR_FNP (0x1u << 18) /**< \brief (GMAC_NCR) Flush Next Packet */
+/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) Network Configuration Register -------- */
+#define GMAC_NCFGR_SPD (0x1u << 0) /**< \brief (GMAC_NCFGR) Speed */
+#define GMAC_NCFGR_FD (0x1u << 1) /**< \brief (GMAC_NCFGR) Full Duplex */
+#define GMAC_NCFGR_DNVLAN (0x1u << 2) /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */
+#define GMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (GMAC_NCFGR) Jumbo Frame Size */
+#define GMAC_NCFGR_CAF (0x1u << 4) /**< \brief (GMAC_NCFGR) Copy All Frames */
+#define GMAC_NCFGR_NBC (0x1u << 5) /**< \brief (GMAC_NCFGR) No Broadcast */
+#define GMAC_NCFGR_MTIHEN (0x1u << 6) /**< \brief (GMAC_NCFGR) Multicast Hash Enable */
+#define GMAC_NCFGR_UNIHEN (0x1u << 7) /**< \brief (GMAC_NCFGR) Unicast Hash Enable */
+#define GMAC_NCFGR_MAXFS (0x1u << 8) /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */
+#define GMAC_NCFGR_RTY (0x1u << 12) /**< \brief (GMAC_NCFGR) Retry Test */
+#define GMAC_NCFGR_PEN (0x1u << 13) /**< \brief (GMAC_NCFGR) Pause Enable */
+#define GMAC_NCFGR_RXBUFO_Pos 14
+#define GMAC_NCFGR_RXBUFO_Msk (0x3u << GMAC_NCFGR_RXBUFO_Pos) /**< \brief (GMAC_NCFGR) Receive Buffer Offset */
+#define GMAC_NCFGR_RXBUFO(value) ((GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos)))
+#define GMAC_NCFGR_LFERD (0x1u << 16) /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */
+#define GMAC_NCFGR_RFCS (0x1u << 17) /**< \brief (GMAC_NCFGR) Remove FCS */
+#define GMAC_NCFGR_CLK_Pos 18
+#define GMAC_NCFGR_CLK_Msk (0x7u << GMAC_NCFGR_CLK_Pos) /**< \brief (GMAC_NCFGR) MDC CLock Division */
+#define GMAC_NCFGR_CLK(value) ((GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos)))
+#define   GMAC_NCFGR_CLK_MCK_8 (0x0u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */
+#define   GMAC_NCFGR_CLK_MCK_16 (0x1u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */
+#define   GMAC_NCFGR_CLK_MCK_32 (0x2u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */
+#define   GMAC_NCFGR_CLK_MCK_48 (0x3u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz) */
+#define   GMAC_NCFGR_CLK_MCK_64 (0x4u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */
+#define   GMAC_NCFGR_CLK_MCK_96 (0x5u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */
+#define GMAC_NCFGR_DBW_Pos 21
+#define GMAC_NCFGR_DBW_Msk (0x3u << GMAC_NCFGR_DBW_Pos) /**< \brief (GMAC_NCFGR) Data Bus Width */
+#define GMAC_NCFGR_DBW(value) ((GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos)))
+#define GMAC_NCFGR_DCPF (0x1u << 23) /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */
+#define GMAC_NCFGR_RXCOEN (0x1u << 24) /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */
+#define GMAC_NCFGR_EFRHD (0x1u << 25) /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */
+#define GMAC_NCFGR_IRXFCS (0x1u << 26) /**< \brief (GMAC_NCFGR) Ignore RX FCS */
+#define GMAC_NCFGR_IPGSEN (0x1u << 28) /**< \brief (GMAC_NCFGR) IP Stretch Enable */
+#define GMAC_NCFGR_RXBP (0x1u << 29) /**< \brief (GMAC_NCFGR) Receive Bad Preamble */
+#define GMAC_NCFGR_IRXER (0x1u << 30) /**< \brief (GMAC_NCFGR) Ignore IPG GRXER */
+/* -------- GMAC_NSR : (GMAC Offset: 0x008) Network Status Register -------- */
+#define GMAC_NSR_MDIO (0x1u << 1) /**< \brief (GMAC_NSR) MDIO Input Status */
+#define GMAC_NSR_IDLE (0x1u << 2) /**< \brief (GMAC_NSR) PHY Management Logic Idle */
+/* -------- GMAC_UR : (GMAC Offset: 0x00C) User Register -------- */
+#define GMAC_UR_RMII (0x1u << 0) /**< \brief (GMAC_UR) Reduced MII Mode */
+/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) DMA Configuration Register -------- */
+#define GMAC_DCFGR_FBLDO_Pos 0
+#define GMAC_DCFGR_FBLDO_Msk (0x1fu << GMAC_DCFGR_FBLDO_Pos) /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */
+#define GMAC_DCFGR_FBLDO(value) ((GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos)))
+#define   GMAC_DCFGR_FBLDO_SINGLE (0x1u << 0) /**< \brief (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */
+#define   GMAC_DCFGR_FBLDO_INCR4 (0x4u << 0) /**< \brief (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */
+#define   GMAC_DCFGR_FBLDO_INCR8 (0x8u << 0) /**< \brief (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */
+#define   GMAC_DCFGR_FBLDO_INCR16 (0x10u << 0) /**< \brief (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */
+#define GMAC_DCFGR_ESMA (0x1u << 6) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */
+#define GMAC_DCFGR_ESPA (0x1u << 7) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */
+#define GMAC_DCFGR_RXBMS_Pos 8
+#define GMAC_DCFGR_RXBMS_Msk (0x3u << GMAC_DCFGR_RXBMS_Pos) /**< \brief (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select */
+#define GMAC_DCFGR_RXBMS(value) ((GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos)))
+#define   GMAC_DCFGR_RXBMS_EIGHTH (0x0u << 8) /**< \brief (GMAC_DCFGR) 4/8 Kbyte Memory Size */
+#define   GMAC_DCFGR_RXBMS_QUARTER (0x1u << 8) /**< \brief (GMAC_DCFGR) 4/4 Kbytes Memory Size */
+#define   GMAC_DCFGR_RXBMS_HALF (0x2u << 8) /**< \brief (GMAC_DCFGR) 4/2 Kbytes Memory Size */
+#define   GMAC_DCFGR_RXBMS_FULL (0x3u << 8) /**< \brief (GMAC_DCFGR) 4 Kbytes Memory Size */
+#define GMAC_DCFGR_TXPBMS (0x1u << 10) /**< \brief (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select */
+#define GMAC_DCFGR_TXCOEN (0x1u << 11) /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */
+#define GMAC_DCFGR_DRBS_Pos 16
+#define GMAC_DCFGR_DRBS_Msk (0xffu << GMAC_DCFGR_DRBS_Pos) /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */
+#define GMAC_DCFGR_DRBS(value) ((GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos)))
+#define GMAC_DCFGR_DDRP (0x1u << 24) /**< \brief (GMAC_DCFGR) DMA Discard Receive Packets */
+/* -------- GMAC_TSR : (GMAC Offset: 0x014) Transmit Status Register -------- */
+#define GMAC_TSR_UBR (0x1u << 0) /**< \brief (GMAC_TSR) Used Bit Read */
+#define GMAC_TSR_COL (0x1u << 1) /**< \brief (GMAC_TSR) Collision Occurred */
+#define GMAC_TSR_RLE (0x1u << 2) /**< \brief (GMAC_TSR) Retry Limit Exceeded */
+#define GMAC_TSR_TXGO (0x1u << 3) /**< \brief (GMAC_TSR) Transmit Go */
+#define GMAC_TSR_TFC (0x1u << 4) /**< \brief (GMAC_TSR) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_TSR_TXCOMP (0x1u << 5) /**< \brief (GMAC_TSR) Transmit Complete */
+#define GMAC_TSR_HRESP (0x1u << 8) /**< \brief (GMAC_TSR) HRESP Not OK */
+/* -------- GMAC_RBQB : (GMAC Offset: 0x018) Receive Buffer Queue Base Address Register -------- */
+#define GMAC_RBQB_ADDR_Pos 2
+#define GMAC_RBQB_ADDR_Msk (0x3fffffffu << GMAC_RBQB_ADDR_Pos) /**< \brief (GMAC_RBQB) Receive Buffer Queue Base Address */
+#define GMAC_RBQB_ADDR(value) ((GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos)))
+/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) Transmit Buffer Queue Base Address Register -------- */
+#define GMAC_TBQB_ADDR_Pos 2
+#define GMAC_TBQB_ADDR_Msk (0x3fffffffu << GMAC_TBQB_ADDR_Pos) /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */
+#define GMAC_TBQB_ADDR(value) ((GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos)))
+/* -------- GMAC_RSR : (GMAC Offset: 0x020) Receive Status Register -------- */
+#define GMAC_RSR_BNA (0x1u << 0) /**< \brief (GMAC_RSR) Buffer Not Available */
+#define GMAC_RSR_REC (0x1u << 1) /**< \brief (GMAC_RSR) Frame Received */
+#define GMAC_RSR_RXOVR (0x1u << 2) /**< \brief (GMAC_RSR) Receive Overrun */
+#define GMAC_RSR_HNO (0x1u << 3) /**< \brief (GMAC_RSR) HRESP Not OK */
+/* -------- GMAC_ISR : (GMAC Offset: 0x024) Interrupt Status Register -------- */
+#define GMAC_ISR_MFS (0x1u << 0) /**< \brief (GMAC_ISR) Management Frame Sent */
+#define GMAC_ISR_RCOMP (0x1u << 1) /**< \brief (GMAC_ISR) Receive Complete */
+#define GMAC_ISR_RXUBR (0x1u << 2) /**< \brief (GMAC_ISR) RX Used Bit Read */
+#define GMAC_ISR_TXUBR (0x1u << 3) /**< \brief (GMAC_ISR) TX Used Bit Read */
+#define GMAC_ISR_TUR (0x1u << 4) /**< \brief (GMAC_ISR) Transmit Underrun */
+#define GMAC_ISR_RLEX (0x1u << 5) /**< \brief (GMAC_ISR) Retry Limit Exceeded */
+#define GMAC_ISR_TFC (0x1u << 6) /**< \brief (GMAC_ISR) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_ISR_TCOMP (0x1u << 7) /**< \brief (GMAC_ISR) Transmit Complete */
+#define GMAC_ISR_ROVR (0x1u << 10) /**< \brief (GMAC_ISR) Receive Overrun */
+#define GMAC_ISR_HRESP (0x1u << 11) /**< \brief (GMAC_ISR) HRESP Not OK */
+#define GMAC_ISR_PFNZ (0x1u << 12) /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */
+#define GMAC_ISR_PTZ (0x1u << 13) /**< \brief (GMAC_ISR) Pause Time Zero */
+#define GMAC_ISR_PFTR (0x1u << 14) /**< \brief (GMAC_ISR) Pause Frame Transmitted */
+#define GMAC_ISR_DRQFR (0x1u << 18) /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */
+#define GMAC_ISR_SFR (0x1u << 19) /**< \brief (GMAC_ISR) PTP Sync Frame Received */
+#define GMAC_ISR_DRQFT (0x1u << 20) /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */
+#define GMAC_ISR_SFT (0x1u << 21) /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */
+#define GMAC_ISR_PDRQFR (0x1u << 22) /**< \brief (GMAC_ISR) PDelay Request Frame Received */
+#define GMAC_ISR_PDRSFR (0x1u << 23) /**< \brief (GMAC_ISR) PDelay Response Frame Received */
+#define GMAC_ISR_PDRQFT (0x1u << 24) /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */
+#define GMAC_ISR_PDRSFT (0x1u << 25) /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */
+#define GMAC_ISR_SRI (0x1u << 26) /**< \brief (GMAC_ISR) TSU Seconds Register Increment */
+#define GMAC_ISR_WOL (0x1u << 28) /**< \brief (GMAC_ISR) Wake On LAN */
+/* -------- GMAC_IER : (GMAC Offset: 0x028) Interrupt Enable Register -------- */
+#define GMAC_IER_MFS (0x1u << 0) /**< \brief (GMAC_IER) Management Frame Sent */
+#define GMAC_IER_RCOMP (0x1u << 1) /**< \brief (GMAC_IER) Receive Complete */
+#define GMAC_IER_RXUBR (0x1u << 2) /**< \brief (GMAC_IER) RX Used Bit Read */
+#define GMAC_IER_TXUBR (0x1u << 3) /**< \brief (GMAC_IER) TX Used Bit Read */
+#define GMAC_IER_TUR (0x1u << 4) /**< \brief (GMAC_IER) Transmit Underrun */
+#define GMAC_IER_RLEX (0x1u << 5) /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */
+#define GMAC_IER_TFC (0x1u << 6) /**< \brief (GMAC_IER) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_IER_TCOMP (0x1u << 7) /**< \brief (GMAC_IER) Transmit Complete */
+#define GMAC_IER_ROVR (0x1u << 10) /**< \brief (GMAC_IER) Receive Overrun */
+#define GMAC_IER_HRESP (0x1u << 11) /**< \brief (GMAC_IER) HRESP Not OK */
+#define GMAC_IER_PFNZ (0x1u << 12) /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */
+#define GMAC_IER_PTZ (0x1u << 13) /**< \brief (GMAC_IER) Pause Time Zero */
+#define GMAC_IER_PFTR (0x1u << 14) /**< \brief (GMAC_IER) Pause Frame Transmitted */
+#define GMAC_IER_EXINT (0x1u << 15) /**< \brief (GMAC_IER) External Interrupt */
+#define GMAC_IER_DRQFR (0x1u << 18) /**< \brief (GMAC_IER) PTP Delay Request Frame Received */
+#define GMAC_IER_SFR (0x1u << 19) /**< \brief (GMAC_IER) PTP Sync Frame Received */
+#define GMAC_IER_DRQFT (0x1u << 20) /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */
+#define GMAC_IER_SFT (0x1u << 21) /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */
+#define GMAC_IER_PDRQFR (0x1u << 22) /**< \brief (GMAC_IER) PDelay Request Frame Received */
+#define GMAC_IER_PDRSFR (0x1u << 23) /**< \brief (GMAC_IER) PDelay Response Frame Received */
+#define GMAC_IER_PDRQFT (0x1u << 24) /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */
+#define GMAC_IER_PDRSFT (0x1u << 25) /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */
+#define GMAC_IER_SRI (0x1u << 26) /**< \brief (GMAC_IER) TSU Seconds Register Increment */
+#define GMAC_IER_WOL (0x1u << 28) /**< \brief (GMAC_IER) Wake On LAN */
+/* -------- GMAC_IDR : (GMAC Offset: 0x02C) Interrupt Disable Register -------- */
+#define GMAC_IDR_MFS (0x1u << 0) /**< \brief (GMAC_IDR) Management Frame Sent */
+#define GMAC_IDR_RCOMP (0x1u << 1) /**< \brief (GMAC_IDR) Receive Complete */
+#define GMAC_IDR_RXUBR (0x1u << 2) /**< \brief (GMAC_IDR) RX Used Bit Read */
+#define GMAC_IDR_TXUBR (0x1u << 3) /**< \brief (GMAC_IDR) TX Used Bit Read */
+#define GMAC_IDR_TUR (0x1u << 4) /**< \brief (GMAC_IDR) Transmit Underrun */
+#define GMAC_IDR_RLEX (0x1u << 5) /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */
+#define GMAC_IDR_TFC (0x1u << 6) /**< \brief (GMAC_IDR) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_IDR_TCOMP (0x1u << 7) /**< \brief (GMAC_IDR) Transmit Complete */
+#define GMAC_IDR_ROVR (0x1u << 10) /**< \brief (GMAC_IDR) Receive Overrun */
+#define GMAC_IDR_HRESP (0x1u << 11) /**< \brief (GMAC_IDR) HRESP Not OK */
+#define GMAC_IDR_PFNZ (0x1u << 12) /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */
+#define GMAC_IDR_PTZ (0x1u << 13) /**< \brief (GMAC_IDR) Pause Time Zero */
+#define GMAC_IDR_PFTR (0x1u << 14) /**< \brief (GMAC_IDR) Pause Frame Transmitted */
+#define GMAC_IDR_EXINT (0x1u << 15) /**< \brief (GMAC_IDR) External Interrupt */
+#define GMAC_IDR_DRQFR (0x1u << 18) /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */
+#define GMAC_IDR_SFR (0x1u << 19) /**< \brief (GMAC_IDR) PTP Sync Frame Received */
+#define GMAC_IDR_DRQFT (0x1u << 20) /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */
+#define GMAC_IDR_SFT (0x1u << 21) /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */
+#define GMAC_IDR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IDR) PDelay Request Frame Received */
+#define GMAC_IDR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IDR) PDelay Response Frame Received */
+#define GMAC_IDR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */
+#define GMAC_IDR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */
+#define GMAC_IDR_SRI (0x1u << 26) /**< \brief (GMAC_IDR) TSU Seconds Register Increment */
+#define GMAC_IDR_WOL (0x1u << 28) /**< \brief (GMAC_IDR) Wake On LAN */
+/* -------- GMAC_IMR : (GMAC Offset: 0x030) Interrupt Mask Register -------- */
+#define GMAC_IMR_MFS (0x1u << 0) /**< \brief (GMAC_IMR) Management Frame Sent */
+#define GMAC_IMR_RCOMP (0x1u << 1) /**< \brief (GMAC_IMR) Receive Complete */
+#define GMAC_IMR_RXUBR (0x1u << 2) /**< \brief (GMAC_IMR) RX Used Bit Read */
+#define GMAC_IMR_TXUBR (0x1u << 3) /**< \brief (GMAC_IMR) TX Used Bit Read */
+#define GMAC_IMR_TUR (0x1u << 4) /**< \brief (GMAC_IMR) Transmit Underrun */
+#define GMAC_IMR_RLEX (0x1u << 5) /**< \brief (GMAC_IMR) Retry Limit Exceeded */
+#define GMAC_IMR_TFC (0x1u << 6) /**< \brief (GMAC_IMR) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_IMR_TCOMP (0x1u << 7) /**< \brief (GMAC_IMR) Transmit Complete */
+#define GMAC_IMR_ROVR (0x1u << 10) /**< \brief (GMAC_IMR) Receive Overrun */
+#define GMAC_IMR_HRESP (0x1u << 11) /**< \brief (GMAC_IMR) HRESP Not OK */
+#define GMAC_IMR_PFNZ (0x1u << 12) /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */
+#define GMAC_IMR_PTZ (0x1u << 13) /**< \brief (GMAC_IMR) Pause Time Zero */
+#define GMAC_IMR_PFTR (0x1u << 14) /**< \brief (GMAC_IMR) Pause Frame Transmitted */
+#define GMAC_IMR_EXINT (0x1u << 15) /**< \brief (GMAC_IMR) External Interrupt */
+#define GMAC_IMR_DRQFR (0x1u << 18) /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */
+#define GMAC_IMR_SFR (0x1u << 19) /**< \brief (GMAC_IMR) PTP Sync Frame Received */
+#define GMAC_IMR_DRQFT (0x1u << 20) /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */
+#define GMAC_IMR_SFT (0x1u << 21) /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */
+#define GMAC_IMR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IMR) PDelay Request Frame Received */
+#define GMAC_IMR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IMR) PDelay Response Frame Received */
+#define GMAC_IMR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */
+#define GMAC_IMR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */
+/* -------- GMAC_MAN : (GMAC Offset: 0x034) PHY Maintenance Register -------- */
+#define GMAC_MAN_DATA_Pos 0
+#define GMAC_MAN_DATA_Msk (0xffffu << GMAC_MAN_DATA_Pos) /**< \brief (GMAC_MAN) PHY Data */
+#define GMAC_MAN_DATA(value) ((GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos)))
+#define GMAC_MAN_WTN_Pos 16
+#define GMAC_MAN_WTN_Msk (0x3u << GMAC_MAN_WTN_Pos) /**< \brief (GMAC_MAN) Write Ten */
+#define GMAC_MAN_WTN(value) ((GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos)))
+#define GMAC_MAN_REGA_Pos 18
+#define GMAC_MAN_REGA_Msk (0x1fu << GMAC_MAN_REGA_Pos) /**< \brief (GMAC_MAN) Register Address */
+#define GMAC_MAN_REGA(value) ((GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos)))
+#define GMAC_MAN_PHYA_Pos 23
+#define GMAC_MAN_PHYA_Msk (0x1fu << GMAC_MAN_PHYA_Pos) /**< \brief (GMAC_MAN) PHY Address */
+#define GMAC_MAN_PHYA(value) ((GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos)))
+#define GMAC_MAN_OP_Pos 28
+#define GMAC_MAN_OP_Msk (0x3u << GMAC_MAN_OP_Pos) /**< \brief (GMAC_MAN) Operation */
+#define GMAC_MAN_OP(value) ((GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos)))
+#define GMAC_MAN_CLTTO (0x1u << 30) /**< \brief (GMAC_MAN) Clause 22 Operation */
+#define GMAC_MAN_WZO (0x1u << 31) /**< \brief (GMAC_MAN) Write ZERO */
+/* -------- GMAC_RPQ : (GMAC Offset: 0x038) Received Pause Quantum Register -------- */
+#define GMAC_RPQ_RPQ_Pos 0
+#define GMAC_RPQ_RPQ_Msk (0xffffu << GMAC_RPQ_RPQ_Pos) /**< \brief (GMAC_RPQ) Received Pause Quantum */
+/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) Transmit Pause Quantum Register -------- */
+#define GMAC_TPQ_TPQ_Pos 0
+#define GMAC_TPQ_TPQ_Msk (0xffffu << GMAC_TPQ_TPQ_Pos) /**< \brief (GMAC_TPQ) Transmit Pause Quantum */
+#define GMAC_TPQ_TPQ(value) ((GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos)))
+/* -------- GMAC_TPSF : (GMAC Offset: 0x040) TX Partial Store and Forward Register -------- */
+#define GMAC_TPSF_TPB1ADR_Pos 0
+#define GMAC_TPSF_TPB1ADR_Msk (0xfffu << GMAC_TPSF_TPB1ADR_Pos) /**< \brief (GMAC_TPSF) Transmit Partial Store and Forward Address */
+#define GMAC_TPSF_TPB1ADR(value) ((GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos)))
+#define GMAC_TPSF_ENTXP (0x1u << 31) /**< \brief (GMAC_TPSF) Enable TX Partial Store and Forward Operation */
+/* -------- GMAC_RPSF : (GMAC Offset: 0x044) RX Partial Store and Forward Register -------- */
+#define GMAC_RPSF_RPB1ADR_Pos 0
+#define GMAC_RPSF_RPB1ADR_Msk (0xfffu << GMAC_RPSF_RPB1ADR_Pos) /**< \brief (GMAC_RPSF) Receive Partial Store and Forward Address */
+#define GMAC_RPSF_RPB1ADR(value) ((GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos)))
+#define GMAC_RPSF_ENRXP (0x1u << 31) /**< \brief (GMAC_RPSF) Enable RX Partial Store and Forward Operation */
+/* -------- GMAC_RJFML : (GMAC Offset: 0x048) RX Jumbo Frame Max Length Register -------- */
+#define GMAC_RJFML_FML_Pos 0
+#define GMAC_RJFML_FML_Msk (0x3fffu << GMAC_RJFML_FML_Pos) /**< \brief (GMAC_RJFML) Frame Max Length */
+#define GMAC_RJFML_FML(value) ((GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos)))
+/* -------- GMAC_HRB : (GMAC Offset: 0x080) Hash Register Bottom -------- */
+#define GMAC_HRB_ADDR_Pos 0
+#define GMAC_HRB_ADDR_Msk (0xffffffffu << GMAC_HRB_ADDR_Pos) /**< \brief (GMAC_HRB) Hash Address */
+#define GMAC_HRB_ADDR(value) ((GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos)))
+/* -------- GMAC_HRT : (GMAC Offset: 0x084) Hash Register Top -------- */
+#define GMAC_HRT_ADDR_Pos 0
+#define GMAC_HRT_ADDR_Msk (0xffffffffu << GMAC_HRT_ADDR_Pos) /**< \brief (GMAC_HRT) Hash Address */
+#define GMAC_HRT_ADDR(value) ((GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos)))
+/* -------- GMAC_SAB : (GMAC Offset: N/A) Specific Address 1 Bottom Register -------- */
+#define GMAC_SAB_ADDR_Pos 0
+#define GMAC_SAB_ADDR_Msk (0xffffffffu << GMAC_SAB_ADDR_Pos) /**< \brief (GMAC_SAB) Specific Address 1 */
+#define GMAC_SAB_ADDR(value) ((GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos)))
+/* -------- GMAC_SAT : (GMAC Offset: N/A) Specific Address 1 Top Register -------- */
+#define GMAC_SAT_ADDR_Pos 0
+#define GMAC_SAT_ADDR_Msk (0xffffu << GMAC_SAT_ADDR_Pos) /**< \brief (GMAC_SAT) Specific Address 1 */
+#define GMAC_SAT_ADDR(value) ((GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos)))
+/* -------- GMAC_TIDM1 : (GMAC Offset: 0x0A8) Type ID Match 1 Register -------- */
+#define GMAC_TIDM1_TID_Pos 0
+#define GMAC_TIDM1_TID_Msk (0xffffu << GMAC_TIDM1_TID_Pos) /**< \brief (GMAC_TIDM1) Type ID Match 1 */
+#define GMAC_TIDM1_TID(value) ((GMAC_TIDM1_TID_Msk & ((value) << GMAC_TIDM1_TID_Pos)))
+#define GMAC_TIDM1_ENID1 (0x1u << 31) /**< \brief (GMAC_TIDM1) Enable Copying of TID Matched Frames */
+/* -------- GMAC_TIDM2 : (GMAC Offset: 0x0AC) Type ID Match 2 Register -------- */
+#define GMAC_TIDM2_TID_Pos 0
+#define GMAC_TIDM2_TID_Msk (0xffffu << GMAC_TIDM2_TID_Pos) /**< \brief (GMAC_TIDM2) Type ID Match 2 */
+#define GMAC_TIDM2_TID(value) ((GMAC_TIDM2_TID_Msk & ((value) << GMAC_TIDM2_TID_Pos)))
+#define GMAC_TIDM2_ENID2 (0x1u << 31) /**< \brief (GMAC_TIDM2) Enable Copying of TID Matched Frames */
+/* -------- GMAC_TIDM3 : (GMAC Offset: 0x0B0) Type ID Match 3 Register -------- */
+#define GMAC_TIDM3_TID_Pos 0
+#define GMAC_TIDM3_TID_Msk (0xffffu << GMAC_TIDM3_TID_Pos) /**< \brief (GMAC_TIDM3) Type ID Match 3 */
+#define GMAC_TIDM3_TID(value) ((GMAC_TIDM3_TID_Msk & ((value) << GMAC_TIDM3_TID_Pos)))
+#define GMAC_TIDM3_ENID3 (0x1u << 31) /**< \brief (GMAC_TIDM3) Enable Copying of TID Matched Frames */
+/* -------- GMAC_TIDM4 : (GMAC Offset: 0x0B4) Type ID Match 4 Register -------- */
+#define GMAC_TIDM4_TID_Pos 0
+#define GMAC_TIDM4_TID_Msk (0xffffu << GMAC_TIDM4_TID_Pos) /**< \brief (GMAC_TIDM4) Type ID Match 4 */
+#define GMAC_TIDM4_TID(value) ((GMAC_TIDM4_TID_Msk & ((value) << GMAC_TIDM4_TID_Pos)))
+#define GMAC_TIDM4_ENID4 (0x1u << 31) /**< \brief (GMAC_TIDM4) Enable Copying of TID Matched Frames */
+/* -------- GMAC_WOL : (GMAC Offset: 0x0B8) Wake on LAN Register -------- */
+#define GMAC_WOL_IP_Pos 0
+#define GMAC_WOL_IP_Msk (0xffffu << GMAC_WOL_IP_Pos) /**< \brief (GMAC_WOL) ARP Request IP Address */
+#define GMAC_WOL_IP(value) ((GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos)))
+#define GMAC_WOL_MAG (0x1u << 16) /**< \brief (GMAC_WOL) Magic Packet Event Enable */
+#define GMAC_WOL_ARP (0x1u << 17) /**< \brief (GMAC_WOL) ARP Request IP Address */
+#define GMAC_WOL_SA1 (0x1u << 18) /**< \brief (GMAC_WOL) Specific Address Register 1 Event Enable */
+#define GMAC_WOL_MTI (0x1u << 19) /**< \brief (GMAC_WOL) Multicast Hash Event Enable */
+/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) IPG Stretch Register -------- */
+#define GMAC_IPGS_FL_Pos 0
+#define GMAC_IPGS_FL_Msk (0xffffu << GMAC_IPGS_FL_Pos) /**< \brief (GMAC_IPGS) Frame Length */
+#define GMAC_IPGS_FL(value) ((GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos)))
+/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) Stacked VLAN Register -------- */
+#define GMAC_SVLAN_VLAN_TYPE_Pos 0
+#define GMAC_SVLAN_VLAN_TYPE_Msk (0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos) /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */
+#define GMAC_SVLAN_VLAN_TYPE(value) ((GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos)))
+#define GMAC_SVLAN_ESVLAN (0x1u << 31) /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */
+/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) Transmit PFC Pause Register -------- */
+#define GMAC_TPFCP_PEV_Pos 0
+#define GMAC_TPFCP_PEV_Msk (0xffu << GMAC_TPFCP_PEV_Pos) /**< \brief (GMAC_TPFCP) Priority Enable Vector */
+#define GMAC_TPFCP_PEV(value) ((GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos)))
+#define GMAC_TPFCP_PQ_Pos 8
+#define GMAC_TPFCP_PQ_Msk (0xffu << GMAC_TPFCP_PQ_Pos) /**< \brief (GMAC_TPFCP) Pause Quantum */
+#define GMAC_TPFCP_PQ(value) ((GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos)))
+/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) Specific Address 1 Mask Bottom Register -------- */
+#define GMAC_SAMB1_ADDR_Pos 0
+#define GMAC_SAMB1_ADDR_Msk (0xffffffffu << GMAC_SAMB1_ADDR_Pos) /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */
+#define GMAC_SAMB1_ADDR(value) ((GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos)))
+/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) Specific Address 1 Mask Top Register -------- */
+#define GMAC_SAMT1_ADDR_Pos 0
+#define GMAC_SAMT1_ADDR_Msk (0xffffu << GMAC_SAMT1_ADDR_Pos) /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */
+#define GMAC_SAMT1_ADDR(value) ((GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos)))
+/* -------- GMAC_NSC : (GMAC Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register -------- */
+#define GMAC_NSC_NANOSEC_Pos 0
+#define GMAC_NSC_NANOSEC_Msk (0x3fffffu << GMAC_NSC_NANOSEC_Pos) /**< \brief (GMAC_NSC) 1588 Timer Nanosecond Comparison Value */
+#define GMAC_NSC_NANOSEC(value) ((GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos)))
+/* -------- GMAC_SCL : (GMAC Offset: 0x0E0) 1588 Timer Second Comparison Low Register -------- */
+#define GMAC_SCL_SEC_Pos 0
+#define GMAC_SCL_SEC_Msk (0xffffffffu << GMAC_SCL_SEC_Pos) /**< \brief (GMAC_SCL) 1588 Timer Second Comparison Value */
+#define GMAC_SCL_SEC(value) ((GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos)))
+/* -------- GMAC_SCH : (GMAC Offset: 0x0E4) 1588 Timer Second Comparison High Register -------- */
+#define GMAC_SCH_SEC_Pos 0
+#define GMAC_SCH_SEC_Msk (0xffffu << GMAC_SCH_SEC_Pos) /**< \brief (GMAC_SCH) 1588 Timer Second Comparison Value */
+#define GMAC_SCH_SEC(value) ((GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos)))
+/* -------- GMAC_EFTSH : (GMAC Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register -------- */
+#define GMAC_EFTSH_RUD_Pos 0
+#define GMAC_EFTSH_RUD_Msk (0xffffu << GMAC_EFTSH_RUD_Pos) /**< \brief (GMAC_EFTSH) Register Update */
+/* -------- GMAC_EFRSH : (GMAC Offset: 0x0EC) PTP Event Frame Received Seconds High Register -------- */
+#define GMAC_EFRSH_RUD_Pos 0
+#define GMAC_EFRSH_RUD_Msk (0xffffu << GMAC_EFRSH_RUD_Pos) /**< \brief (GMAC_EFRSH) Register Update */
+/* -------- GMAC_PEFTSH : (GMAC Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register -------- */
+#define GMAC_PEFTSH_RUD_Pos 0
+#define GMAC_PEFTSH_RUD_Msk (0xffffu << GMAC_PEFTSH_RUD_Pos) /**< \brief (GMAC_PEFTSH) Register Update */
+/* -------- GMAC_PEFRSH : (GMAC Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register -------- */
+#define GMAC_PEFRSH_RUD_Pos 0
+#define GMAC_PEFRSH_RUD_Msk (0xffffu << GMAC_PEFRSH_RUD_Pos) /**< \brief (GMAC_PEFRSH) Register Update */
+/* -------- GMAC_MID : (GMAC Offset: 0x0FC) Module ID Register -------- */
+#define GMAC_MID_MREV_Pos 0
+#define GMAC_MID_MREV_Msk (0xffffu << GMAC_MID_MREV_Pos) /**< \brief (GMAC_MID) Module Revision */
+#define GMAC_MID_MID_Pos 16
+#define GMAC_MID_MID_Msk (0xffffu << GMAC_MID_MID_Pos) /**< \brief (GMAC_MID) Module Identification Number */
+/* -------- GMAC_OTLO : (GMAC Offset: 0x100) Octets Transmitted Low Register -------- */
+#define GMAC_OTLO_TXO_Pos 0
+#define GMAC_OTLO_TXO_Msk (0xffffffffu << GMAC_OTLO_TXO_Pos) /**< \brief (GMAC_OTLO) Transmitted Octets */
+/* -------- GMAC_OTHI : (GMAC Offset: 0x104) Octets Transmitted High Register -------- */
+#define GMAC_OTHI_TXO_Pos 0
+#define GMAC_OTHI_TXO_Msk (0xffffu << GMAC_OTHI_TXO_Pos) /**< \brief (GMAC_OTHI) Transmitted Octets */
+/* -------- GMAC_FT : (GMAC Offset: 0x108) Frames Transmitted Register -------- */
+#define GMAC_FT_FTX_Pos 0
+#define GMAC_FT_FTX_Msk (0xffffffffu << GMAC_FT_FTX_Pos) /**< \brief (GMAC_FT) Frames Transmitted without Error */
+/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register -------- */
+#define GMAC_BCFT_BFTX_Pos 0
+#define GMAC_BCFT_BFTX_Msk (0xffffffffu << GMAC_BCFT_BFTX_Pos) /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */
+/* -------- GMAC_MFT : (GMAC Offset: 0x110) Multicast Frames Transmitted Register -------- */
+#define GMAC_MFT_MFTX_Pos 0
+#define GMAC_MFT_MFTX_Msk (0xffffffffu << GMAC_MFT_MFTX_Pos) /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */
+/* -------- GMAC_PFT : (GMAC Offset: 0x114) Pause Frames Transmitted Register -------- */
+#define GMAC_PFT_PFTX_Pos 0
+#define GMAC_PFT_PFTX_Msk (0xffffu << GMAC_PFT_PFTX_Pos) /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */
+/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register -------- */
+#define GMAC_BFT64_NFTX_Pos 0
+#define GMAC_BFT64_NFTX_Msk (0xffffffffu << GMAC_BFT64_NFTX_Pos) /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */
+/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register -------- */
+#define GMAC_TBFT127_NFTX_Pos 0
+#define GMAC_TBFT127_NFTX_Msk (0xffffffffu << GMAC_TBFT127_NFTX_Pos) /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */
+/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register -------- */
+#define GMAC_TBFT255_NFTX_Pos 0
+#define GMAC_TBFT255_NFTX_Msk (0xffffffffu << GMAC_TBFT255_NFTX_Pos) /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */
+/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register -------- */
+#define GMAC_TBFT511_NFTX_Pos 0
+#define GMAC_TBFT511_NFTX_Msk (0xffffffffu << GMAC_TBFT511_NFTX_Pos) /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */
+/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register -------- */
+#define GMAC_TBFT1023_NFTX_Pos 0
+#define GMAC_TBFT1023_NFTX_Msk (0xffffffffu << GMAC_TBFT1023_NFTX_Pos) /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */
+/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register -------- */
+#define GMAC_TBFT1518_NFTX_Pos 0
+#define GMAC_TBFT1518_NFTX_Msk (0xffffffffu << GMAC_TBFT1518_NFTX_Pos) /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */
+/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register -------- */
+#define GMAC_GTBFT1518_NFTX_Pos 0
+#define GMAC_GTBFT1518_NFTX_Msk (0xffffffffu << GMAC_GTBFT1518_NFTX_Pos) /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */
+/* -------- GMAC_TUR : (GMAC Offset: 0x134) Transmit Underruns Register -------- */
+#define GMAC_TUR_TXUNR_Pos 0
+#define GMAC_TUR_TXUNR_Msk (0x3ffu << GMAC_TUR_TXUNR_Pos) /**< \brief (GMAC_TUR) Transmit Underruns */
+/* -------- GMAC_SCF : (GMAC Offset: 0x138) Single Collision Frames Register -------- */
+#define GMAC_SCF_SCOL_Pos 0
+#define GMAC_SCF_SCOL_Msk (0x3ffffu << GMAC_SCF_SCOL_Pos) /**< \brief (GMAC_SCF) Single Collision */
+/* -------- GMAC_MCF : (GMAC Offset: 0x13C) Multiple Collision Frames Register -------- */
+#define GMAC_MCF_MCOL_Pos 0
+#define GMAC_MCF_MCOL_Msk (0x3ffffu << GMAC_MCF_MCOL_Pos) /**< \brief (GMAC_MCF) Multiple Collision */
+/* -------- GMAC_EC : (GMAC Offset: 0x140) Excessive Collisions Register -------- */
+#define GMAC_EC_XCOL_Pos 0
+#define GMAC_EC_XCOL_Msk (0x3ffu << GMAC_EC_XCOL_Pos) /**< \brief (GMAC_EC) Excessive Collisions */
+/* -------- GMAC_LC : (GMAC Offset: 0x144) Late Collisions Register -------- */
+#define GMAC_LC_LCOL_Pos 0
+#define GMAC_LC_LCOL_Msk (0x3ffu << GMAC_LC_LCOL_Pos) /**< \brief (GMAC_LC) Late Collisions */
+/* -------- GMAC_DTF : (GMAC Offset: 0x148) Deferred Transmission Frames Register -------- */
+#define GMAC_DTF_DEFT_Pos 0
+#define GMAC_DTF_DEFT_Msk (0x3ffffu << GMAC_DTF_DEFT_Pos) /**< \brief (GMAC_DTF) Deferred Transmission */
+/* -------- GMAC_CSE : (GMAC Offset: 0x14C) Carrier Sense Errors Register -------- */
+#define GMAC_CSE_CSR_Pos 0
+#define GMAC_CSE_CSR_Msk (0x3ffu << GMAC_CSE_CSR_Pos) /**< \brief (GMAC_CSE) Carrier Sense Error */
+/* -------- GMAC_ORLO : (GMAC Offset: 0x150) Octets Received Low Received Register -------- */
+#define GMAC_ORLO_RXO_Pos 0
+#define GMAC_ORLO_RXO_Msk (0xffffffffu << GMAC_ORLO_RXO_Pos) /**< \brief (GMAC_ORLO) Received Octets */
+/* -------- GMAC_ORHI : (GMAC Offset: 0x154) Octets Received High Received Register -------- */
+#define GMAC_ORHI_RXO_Pos 0
+#define GMAC_ORHI_RXO_Msk (0xffffu << GMAC_ORHI_RXO_Pos) /**< \brief (GMAC_ORHI) Received Octets */
+/* -------- GMAC_FR : (GMAC Offset: 0x158) Frames Received Register -------- */
+#define GMAC_FR_FRX_Pos 0
+#define GMAC_FR_FRX_Msk (0xffffffffu << GMAC_FR_FRX_Pos) /**< \brief (GMAC_FR) Frames Received without Error */
+/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) Broadcast Frames Received Register -------- */
+#define GMAC_BCFR_BFRX_Pos 0
+#define GMAC_BCFR_BFRX_Msk (0xffffffffu << GMAC_BCFR_BFRX_Pos) /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */
+/* -------- GMAC_MFR : (GMAC Offset: 0x160) Multicast Frames Received Register -------- */
+#define GMAC_MFR_MFRX_Pos 0
+#define GMAC_MFR_MFRX_Msk (0xffffffffu << GMAC_MFR_MFRX_Pos) /**< \brief (GMAC_MFR) Multicast Frames Received without Error */
+/* -------- GMAC_PFR : (GMAC Offset: 0x164) Pause Frames Received Register -------- */
+#define GMAC_PFR_PFRX_Pos 0
+#define GMAC_PFR_PFRX_Msk (0xffffu << GMAC_PFR_PFRX_Pos) /**< \brief (GMAC_PFR) Pause Frames Received Register */
+/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) 64 Byte Frames Received Register -------- */
+#define GMAC_BFR64_NFRX_Pos 0
+#define GMAC_BFR64_NFRX_Msk (0xffffffffu << GMAC_BFR64_NFRX_Pos) /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */
+/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register -------- */
+#define GMAC_TBFR127_NFRX_Pos 0
+#define GMAC_TBFR127_NFRX_Msk (0xffffffffu << GMAC_TBFR127_NFRX_Pos) /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */
+/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register -------- */
+#define GMAC_TBFR255_NFRX_Pos 0
+#define GMAC_TBFR255_NFRX_Msk (0xffffffffu << GMAC_TBFR255_NFRX_Pos) /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */
+/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) 256 to 511 Byte Frames Received Register -------- */
+#define GMAC_TBFR511_NFRX_Pos 0
+#define GMAC_TBFR511_NFRX_Msk (0xffffffffu << GMAC_TBFR511_NFRX_Pos) /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */
+/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register -------- */
+#define GMAC_TBFR1023_NFRX_Pos 0
+#define GMAC_TBFR1023_NFRX_Msk (0xffffffffu << GMAC_TBFR1023_NFRX_Pos) /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */
+/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register -------- */
+#define GMAC_TBFR1518_NFRX_Pos 0
+#define GMAC_TBFR1518_NFRX_Msk (0xffffffffu << GMAC_TBFR1518_NFRX_Pos) /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */
+/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register -------- */
+#define GMAC_TMXBFR_NFRX_Pos 0
+#define GMAC_TMXBFR_NFRX_Msk (0xffffffffu << GMAC_TMXBFR_NFRX_Pos) /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */
+/* -------- GMAC_UFR : (GMAC Offset: 0x184) Undersize Frames Received Register -------- */
+#define GMAC_UFR_UFRX_Pos 0
+#define GMAC_UFR_UFRX_Msk (0x3ffu << GMAC_UFR_UFRX_Pos) /**< \brief (GMAC_UFR) Undersize Frames Received */
+/* -------- GMAC_OFR : (GMAC Offset: 0x188) Oversize Frames Received Register -------- */
+#define GMAC_OFR_OFRX_Pos 0
+#define GMAC_OFR_OFRX_Msk (0x3ffu << GMAC_OFR_OFRX_Pos) /**< \brief (GMAC_OFR) Oversized Frames Received */
+/* -------- GMAC_JR : (GMAC Offset: 0x18C) Jabbers Received Register -------- */
+#define GMAC_JR_JRX_Pos 0
+#define GMAC_JR_JRX_Msk (0x3ffu << GMAC_JR_JRX_Pos) /**< \brief (GMAC_JR) Jabbers Received */
+/* -------- GMAC_FCSE : (GMAC Offset: 0x190) Frame Check Sequence Errors Register -------- */
+#define GMAC_FCSE_FCKR_Pos 0
+#define GMAC_FCSE_FCKR_Msk (0x3ffu << GMAC_FCSE_FCKR_Pos) /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */
+/* -------- GMAC_LFFE : (GMAC Offset: 0x194) Length Field Frame Errors Register -------- */
+#define GMAC_LFFE_LFER_Pos 0
+#define GMAC_LFFE_LFER_Msk (0x3ffu << GMAC_LFFE_LFER_Pos) /**< \brief (GMAC_LFFE) Length Field Frame Errors */
+/* -------- GMAC_RSE : (GMAC Offset: 0x198) Receive Symbol Errors Register -------- */
+#define GMAC_RSE_RXSE_Pos 0
+#define GMAC_RSE_RXSE_Msk (0x3ffu << GMAC_RSE_RXSE_Pos) /**< \brief (GMAC_RSE) Receive Symbol Errors */
+/* -------- GMAC_AE : (GMAC Offset: 0x19C) Alignment Errors Register -------- */
+#define GMAC_AE_AER_Pos 0
+#define GMAC_AE_AER_Msk (0x3ffu << GMAC_AE_AER_Pos) /**< \brief (GMAC_AE) Alignment Errors */
+/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) Receive Resource Errors Register -------- */
+#define GMAC_RRE_RXRER_Pos 0
+#define GMAC_RRE_RXRER_Msk (0x3ffffu << GMAC_RRE_RXRER_Pos) /**< \brief (GMAC_RRE) Receive Resource Errors */
+/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) Receive Overrun Register -------- */
+#define GMAC_ROE_RXOVR_Pos 0
+#define GMAC_ROE_RXOVR_Msk (0x3ffu << GMAC_ROE_RXOVR_Pos) /**< \brief (GMAC_ROE) Receive Overruns */
+/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) IP Header Checksum Errors Register -------- */
+#define GMAC_IHCE_HCKER_Pos 0
+#define GMAC_IHCE_HCKER_Msk (0xffu << GMAC_IHCE_HCKER_Pos) /**< \brief (GMAC_IHCE) IP Header Checksum Errors */
+/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) TCP Checksum Errors Register -------- */
+#define GMAC_TCE_TCKER_Pos 0
+#define GMAC_TCE_TCKER_Msk (0xffu << GMAC_TCE_TCKER_Pos) /**< \brief (GMAC_TCE) TCP Checksum Errors */
+/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) UDP Checksum Errors Register -------- */
+#define GMAC_UCE_UCKER_Pos 0
+#define GMAC_UCE_UCKER_Msk (0xffu << GMAC_UCE_UCKER_Pos) /**< \brief (GMAC_UCE) UDP Checksum Errors */
+/* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register -------- */
+#define GMAC_TISUBN_LSBTIR_Pos 0
+#define GMAC_TISUBN_LSBTIR_Msk (0xffffu << GMAC_TISUBN_LSBTIR_Pos) /**< \brief (GMAC_TISUBN) Lower Significant Bits of Timer Increment Register */
+#define GMAC_TISUBN_LSBTIR(value) ((GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos)))
+/* -------- GMAC_TSH : (GMAC Offset: 0x1C0) 1588 Timer Seconds High Register -------- */
+#define GMAC_TSH_TCS_Pos 0
+#define GMAC_TSH_TCS_Msk (0xffffu << GMAC_TSH_TCS_Pos) /**< \brief (GMAC_TSH) Timer Count in Seconds */
+#define GMAC_TSH_TCS(value) ((GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos)))
+/* -------- GMAC_TSL : (GMAC Offset: 0x1D0) 1588 Timer Seconds Low Register -------- */
+#define GMAC_TSL_TCS_Pos 0
+#define GMAC_TSL_TCS_Msk (0xffffffffu << GMAC_TSL_TCS_Pos) /**< \brief (GMAC_TSL) Timer Count in Seconds */
+#define GMAC_TSL_TCS(value) ((GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos)))
+/* -------- GMAC_TN : (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register -------- */
+#define GMAC_TN_TNS_Pos 0
+#define GMAC_TN_TNS_Msk (0x3fffffffu << GMAC_TN_TNS_Pos) /**< \brief (GMAC_TN) Timer Count in Nanoseconds */
+#define GMAC_TN_TNS(value) ((GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos)))
+/* -------- GMAC_TA : (GMAC Offset: 0x1D8) 1588 Timer Adjust Register -------- */
+#define GMAC_TA_ITDT_Pos 0
+#define GMAC_TA_ITDT_Msk (0x3fffffffu << GMAC_TA_ITDT_Pos) /**< \brief (GMAC_TA) Increment/Decrement */
+#define GMAC_TA_ITDT(value) ((GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos)))
+#define GMAC_TA_ADJ (0x1u << 31) /**< \brief (GMAC_TA) Adjust 1588 Timer */
+/* -------- GMAC_TI : (GMAC Offset: 0x1DC) 1588 Timer Increment Register -------- */
+#define GMAC_TI_CNS_Pos 0
+#define GMAC_TI_CNS_Msk (0xffu << GMAC_TI_CNS_Pos) /**< \brief (GMAC_TI) Count Nanoseconds */
+#define GMAC_TI_CNS(value) ((GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos)))
+#define GMAC_TI_ACNS_Pos 8
+#define GMAC_TI_ACNS_Msk (0xffu << GMAC_TI_ACNS_Pos) /**< \brief (GMAC_TI) Alternative Count Nanoseconds */
+#define GMAC_TI_ACNS(value) ((GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos)))
+#define GMAC_TI_NIT_Pos 16
+#define GMAC_TI_NIT_Msk (0xffu << GMAC_TI_NIT_Pos) /**< \brief (GMAC_TI) Number of Increments */
+#define GMAC_TI_NIT(value) ((GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos)))
+/* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register -------- */
+#define GMAC_EFTSL_RUD_Pos 0
+#define GMAC_EFTSL_RUD_Msk (0xffffffffu << GMAC_EFTSL_RUD_Pos) /**< \brief (GMAC_EFTSL) Register Update */
+/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register -------- */
+#define GMAC_EFTN_RUD_Pos 0
+#define GMAC_EFTN_RUD_Msk (0x3fffffffu << GMAC_EFTN_RUD_Pos) /**< \brief (GMAC_EFTN) Register Update */
+/* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds Low Register -------- */
+#define GMAC_EFRSL_RUD_Pos 0
+#define GMAC_EFRSL_RUD_Msk (0xffffffffu << GMAC_EFRSL_RUD_Pos) /**< \brief (GMAC_EFRSL) Register Update */
+/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register -------- */
+#define GMAC_EFRN_RUD_Pos 0
+#define GMAC_EFRN_RUD_Msk (0x3fffffffu << GMAC_EFRN_RUD_Pos) /**< \brief (GMAC_EFRN) Register Update */
+/* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register -------- */
+#define GMAC_PEFTSL_RUD_Pos 0
+#define GMAC_PEFTSL_RUD_Msk (0xffffffffu << GMAC_PEFTSL_RUD_Pos) /**< \brief (GMAC_PEFTSL) Register Update */
+/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register -------- */
+#define GMAC_PEFTN_RUD_Pos 0
+#define GMAC_PEFTN_RUD_Msk (0x3fffffffu << GMAC_PEFTN_RUD_Pos) /**< \brief (GMAC_PEFTN) Register Update */
+/* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register -------- */
+#define GMAC_PEFRSL_RUD_Pos 0
+#define GMAC_PEFRSL_RUD_Msk (0xffffffffu << GMAC_PEFRSL_RUD_Pos) /**< \brief (GMAC_PEFRSL) Register Update */
+/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register -------- */
+#define GMAC_PEFRN_RUD_Pos 0
+#define GMAC_PEFRN_RUD_Msk (0x3fffffffu << GMAC_PEFRN_RUD_Pos) /**< \brief (GMAC_PEFRN) Register Update */
+/* -------- GMAC_ISRPQ[2] : (GMAC Offset: 0x400) Interrupt Status Register Priority Queue  (index = 1) -------- */
+#define GMAC_ISRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_ISRPQ[2]) Receive Complete */
+#define GMAC_ISRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_ISRPQ[2]) RX Used Bit Read */
+#define GMAC_ISRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_ISRPQ[2]) Retry Limit Exceeded or Late Collision */
+#define GMAC_ISRPQ_TFC (0x1u << 6) /**< \brief (GMAC_ISRPQ[2]) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_ISRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_ISRPQ[2]) Transmit Complete */
+#define GMAC_ISRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_ISRPQ[2]) Receive Overrun */
+#define GMAC_ISRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_ISRPQ[2]) HRESP Not OK */
+/* -------- GMAC_TBQBAPQ[2] : (GMAC Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue  (index = 1) -------- */
+#define GMAC_TBQBAPQ_TXBQBA_Pos 2
+#define GMAC_TBQBAPQ_TXBQBA_Msk (0x3fffffffu << GMAC_TBQBAPQ_TXBQBA_Pos) /**< \brief (GMAC_TBQBAPQ[2]) Transmit Buffer Queue Base Address */
+#define GMAC_TBQBAPQ_TXBQBA(value) ((GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos)))
+/* -------- GMAC_RBQBAPQ[2] : (GMAC Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue  (index = 1) -------- */
+#define GMAC_RBQBAPQ_RXBQBA_Pos 2
+#define GMAC_RBQBAPQ_RXBQBA_Msk (0x3fffffffu << GMAC_RBQBAPQ_RXBQBA_Pos) /**< \brief (GMAC_RBQBAPQ[2]) Receive Buffer Queue Base Address */
+#define GMAC_RBQBAPQ_RXBQBA(value) ((GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos)))
+/* -------- GMAC_RBSRPQ[2] : (GMAC Offset: 0x4A0) Receive Buffer Size Register Priority Queue  (index = 1) -------- */
+#define GMAC_RBSRPQ_RBS_Pos 0
+#define GMAC_RBSRPQ_RBS_Msk (0xffffu << GMAC_RBSRPQ_RBS_Pos) /**< \brief (GMAC_RBSRPQ[2]) Receive Buffer Size */
+#define GMAC_RBSRPQ_RBS(value) ((GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos)))
+/* -------- GMAC_CBSCR : (GMAC Offset: 0x4BC) Credit-Based Shaping Control Register -------- */
+#define GMAC_CBSCR_QBE (0x1u << 0) /**< \brief (GMAC_CBSCR) Queue B CBS Enable */
+#define GMAC_CBSCR_QAE (0x1u << 1) /**< \brief (GMAC_CBSCR) Queue A CBS Enable */
+/* -------- GMAC_CBSISQA : (GMAC Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A -------- */
+#define GMAC_CBSISQA_IS_Pos 0
+#define GMAC_CBSISQA_IS_Msk (0xffffffffu << GMAC_CBSISQA_IS_Pos) /**< \brief (GMAC_CBSISQA) IdleSlope */
+#define GMAC_CBSISQA_IS(value) ((GMAC_CBSISQA_IS_Msk & ((value) << GMAC_CBSISQA_IS_Pos)))
+/* -------- GMAC_CBSISQB : (GMAC Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B -------- */
+#define GMAC_CBSISQB_IS_Pos 0
+#define GMAC_CBSISQB_IS_Msk (0xffffffffu << GMAC_CBSISQB_IS_Pos) /**< \brief (GMAC_CBSISQB) IdleSlope */
+#define GMAC_CBSISQB_IS(value) ((GMAC_CBSISQB_IS_Msk & ((value) << GMAC_CBSISQB_IS_Pos)))
+/* -------- GMAC_ST1RPQ[4] : (GMAC Offset: 0x500) Screening Type 1 Register Priority Queue  (index = 0) -------- */
+#define GMAC_ST1RPQ_QNB_Pos 0
+#define GMAC_ST1RPQ_QNB_Msk (0x7u << GMAC_ST1RPQ_QNB_Pos) /**< \brief (GMAC_ST1RPQ[4]) Queue Number (0-2) */
+#define GMAC_ST1RPQ_QNB(value) ((GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos)))
+#define GMAC_ST1RPQ_DSTCM_Pos 4
+#define GMAC_ST1RPQ_DSTCM_Msk (0xffu << GMAC_ST1RPQ_DSTCM_Pos) /**< \brief (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match */
+#define GMAC_ST1RPQ_DSTCM(value) ((GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos)))
+#define GMAC_ST1RPQ_UDPM_Pos 12
+#define GMAC_ST1RPQ_UDPM_Msk (0xffffu << GMAC_ST1RPQ_UDPM_Pos) /**< \brief (GMAC_ST1RPQ[4]) UDP Port Match */
+#define GMAC_ST1RPQ_UDPM(value) ((GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos)))
+#define GMAC_ST1RPQ_DSTCE (0x1u << 28) /**< \brief (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match Enable */
+#define GMAC_ST1RPQ_UDPE (0x1u << 29) /**< \brief (GMAC_ST1RPQ[4]) UDP Port Match Enable */
+/* -------- GMAC_ST2RPQ[8] : (GMAC Offset: 0x540) Screening Type 2 Register Priority Queue  (index = 0) -------- */
+#define GMAC_ST2RPQ_QNB_Pos 0
+#define GMAC_ST2RPQ_QNB_Msk (0x7u << GMAC_ST2RPQ_QNB_Pos) /**< \brief (GMAC_ST2RPQ[8]) Queue Number (0-2) */
+#define GMAC_ST2RPQ_QNB(value) ((GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos)))
+#define GMAC_ST2RPQ_VLANP_Pos 4
+#define GMAC_ST2RPQ_VLANP_Msk (0x7u << GMAC_ST2RPQ_VLANP_Pos) /**< \brief (GMAC_ST2RPQ[8]) VLAN Priority */
+#define GMAC_ST2RPQ_VLANP(value) ((GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos)))
+#define GMAC_ST2RPQ_VLANE (0x1u << 8) /**< \brief (GMAC_ST2RPQ[8]) VLAN Enable */
+#define GMAC_ST2RPQ_I2ETH_Pos 9
+#define GMAC_ST2RPQ_I2ETH_Msk (0x7u << GMAC_ST2RPQ_I2ETH_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 EtherType register x */
+#define GMAC_ST2RPQ_I2ETH(value) ((GMAC_ST2RPQ_I2ETH_Msk & ((value) << GMAC_ST2RPQ_I2ETH_Pos)))
+#define GMAC_ST2RPQ_ETHE (0x1u << 12) /**< \brief (GMAC_ST2RPQ[8]) EtherType Enable */
+#define GMAC_ST2RPQ_COMPA_Pos 13
+#define GMAC_ST2RPQ_COMPA_Msk (0x1fu << GMAC_ST2RPQ_COMPA_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */
+#define GMAC_ST2RPQ_COMPA(value) ((GMAC_ST2RPQ_COMPA_Msk & ((value) << GMAC_ST2RPQ_COMPA_Pos)))
+#define GMAC_ST2RPQ_COMPAE (0x1u << 18) /**< \brief (GMAC_ST2RPQ[8]) Compare A Enable */
+#define GMAC_ST2RPQ_COMPB_Pos 19
+#define GMAC_ST2RPQ_COMPB_Msk (0x1fu << GMAC_ST2RPQ_COMPB_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */
+#define GMAC_ST2RPQ_COMPB(value) ((GMAC_ST2RPQ_COMPB_Msk & ((value) << GMAC_ST2RPQ_COMPB_Pos)))
+#define GMAC_ST2RPQ_COMPBE (0x1u << 24) /**< \brief (GMAC_ST2RPQ[8]) Compare B Enable */
+#define GMAC_ST2RPQ_COMPC_Pos 25
+#define GMAC_ST2RPQ_COMPC_Msk (0x1fu << GMAC_ST2RPQ_COMPC_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */
+#define GMAC_ST2RPQ_COMPC(value) ((GMAC_ST2RPQ_COMPC_Msk & ((value) << GMAC_ST2RPQ_COMPC_Pos)))
+#define GMAC_ST2RPQ_COMPCE (0x1u << 30) /**< \brief (GMAC_ST2RPQ[8]) Compare C Enable */
+/* -------- GMAC_IERPQ[2] : (GMAC Offset: 0x600) Interrupt Enable Register Priority Queue  (index = 1) -------- */
+#define GMAC_IERPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IERPQ[2]) Receive Complete */
+#define GMAC_IERPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IERPQ[2]) RX Used Bit Read */
+#define GMAC_IERPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IERPQ[2]) Retry Limit Exceeded or Late Collision */
+#define GMAC_IERPQ_TFC (0x1u << 6) /**< \brief (GMAC_IERPQ[2]) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_IERPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IERPQ[2]) Transmit Complete */
+#define GMAC_IERPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IERPQ[2]) Receive Overrun */
+#define GMAC_IERPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IERPQ[2]) HRESP Not OK */
+/* -------- GMAC_IDRPQ[2] : (GMAC Offset: 0x620) Interrupt Disable Register Priority Queue  (index = 1) -------- */
+#define GMAC_IDRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IDRPQ[2]) Receive Complete */
+#define GMAC_IDRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IDRPQ[2]) RX Used Bit Read */
+#define GMAC_IDRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IDRPQ[2]) Retry Limit Exceeded or Late Collision */
+#define GMAC_IDRPQ_TFC (0x1u << 6) /**< \brief (GMAC_IDRPQ[2]) Transmit Frame Corruption Due to AHB Error */
+#define GMAC_IDRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IDRPQ[2]) Transmit Complete */
+#define GMAC_IDRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IDRPQ[2]) Receive Overrun */
+#define GMAC_IDRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IDRPQ[2]) HRESP Not OK */
+/* -------- GMAC_IMRPQ[2] : (GMAC Offset: 0x640) Interrupt Mask Register Priority Queue  (index = 1) -------- */
+#define GMAC_IMRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IMRPQ[2]) Receive Complete */
+#define GMAC_IMRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IMRPQ[2]) RX Used Bit Read */
+#define GMAC_IMRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IMRPQ[2]) Retry Limit Exceeded or Late Collision */
+#define GMAC_IMRPQ_AHB (0x1u << 6) /**< \brief (GMAC_IMRPQ[2]) AHB Error */
+#define GMAC_IMRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IMRPQ[2]) Transmit Complete */
+#define GMAC_IMRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IMRPQ[2]) Receive Overrun */
+#define GMAC_IMRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IMRPQ[2]) HRESP Not OK */
+/* -------- GMAC_ST2ER[4] : (GMAC Offset: 0x6E0) Screening Type 2 Ethertype Register  (index = 0) -------- */
+#define GMAC_ST2ER_COMPVAL_Pos 0
+#define GMAC_ST2ER_COMPVAL_Msk (0xffffu << GMAC_ST2ER_COMPVAL_Pos) /**< \brief (GMAC_ST2ER[4]) Ethertype Compare Value */
+#define GMAC_ST2ER_COMPVAL(value) ((GMAC_ST2ER_COMPVAL_Msk & ((value) << GMAC_ST2ER_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW00 : (GMAC Offset: 0x700) Screening Type 2 Compare Word 0 Register  (index = 0) -------- */
+#define GMAC_ST2CW00_MASKVAL_Pos 0
+#define GMAC_ST2CW00_MASKVAL_Msk (0xffffu << GMAC_ST2CW00_MASKVAL_Pos) /**< \brief (GMAC_ST2CW00) Mask Value */
+#define GMAC_ST2CW00_MASKVAL(value) ((GMAC_ST2CW00_MASKVAL_Msk & ((value) << GMAC_ST2CW00_MASKVAL_Pos)))
+#define GMAC_ST2CW00_COMPVAL_Pos 16
+#define GMAC_ST2CW00_COMPVAL_Msk (0xffffu << GMAC_ST2CW00_COMPVAL_Pos) /**< \brief (GMAC_ST2CW00) Compare Value */
+#define GMAC_ST2CW00_COMPVAL(value) ((GMAC_ST2CW00_COMPVAL_Msk & ((value) << GMAC_ST2CW00_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW10 : (GMAC Offset: 0x704) Screening Type 2 Compare Word 1 Register  (index = 0) -------- */
+#define GMAC_ST2CW10_OFFSVAL_Pos 0
+#define GMAC_ST2CW10_OFFSVAL_Msk (0x7fu << GMAC_ST2CW10_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW10) Offset Value in Bytes */
+#define GMAC_ST2CW10_OFFSVAL(value) ((GMAC_ST2CW10_OFFSVAL_Msk & ((value) << GMAC_ST2CW10_OFFSVAL_Pos)))
+#define GMAC_ST2CW10_OFFSSTRT_Pos 7
+#define GMAC_ST2CW10_OFFSSTRT_Msk (0x3u << GMAC_ST2CW10_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW10) Ethernet Frame Offset Start */
+#define GMAC_ST2CW10_OFFSSTRT(value) ((GMAC_ST2CW10_OFFSSTRT_Msk & ((value) << GMAC_ST2CW10_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW10_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW10) Offset from the start of the frame */
+#define   GMAC_ST2CW10_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW10_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW10_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW10) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW01 : (GMAC Offset: 0x708) Screening Type 2 Compare Word 0 Register  (index = 1) -------- */
+#define GMAC_ST2CW01_MASKVAL_Pos 0
+#define GMAC_ST2CW01_MASKVAL_Msk (0xffffu << GMAC_ST2CW01_MASKVAL_Pos) /**< \brief (GMAC_ST2CW01) Mask Value */
+#define GMAC_ST2CW01_MASKVAL(value) ((GMAC_ST2CW01_MASKVAL_Msk & ((value) << GMAC_ST2CW01_MASKVAL_Pos)))
+#define GMAC_ST2CW01_COMPVAL_Pos 16
+#define GMAC_ST2CW01_COMPVAL_Msk (0xffffu << GMAC_ST2CW01_COMPVAL_Pos) /**< \brief (GMAC_ST2CW01) Compare Value */
+#define GMAC_ST2CW01_COMPVAL(value) ((GMAC_ST2CW01_COMPVAL_Msk & ((value) << GMAC_ST2CW01_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW11 : (GMAC Offset: 0x70C) Screening Type 2 Compare Word 1 Register  (index = 1) -------- */
+#define GMAC_ST2CW11_OFFSVAL_Pos 0
+#define GMAC_ST2CW11_OFFSVAL_Msk (0x7fu << GMAC_ST2CW11_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW11) Offset Value in Bytes */
+#define GMAC_ST2CW11_OFFSVAL(value) ((GMAC_ST2CW11_OFFSVAL_Msk & ((value) << GMAC_ST2CW11_OFFSVAL_Pos)))
+#define GMAC_ST2CW11_OFFSSTRT_Pos 7
+#define GMAC_ST2CW11_OFFSSTRT_Msk (0x3u << GMAC_ST2CW11_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW11) Ethernet Frame Offset Start */
+#define GMAC_ST2CW11_OFFSSTRT(value) ((GMAC_ST2CW11_OFFSSTRT_Msk & ((value) << GMAC_ST2CW11_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW11_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW11) Offset from the start of the frame */
+#define   GMAC_ST2CW11_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW11_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW11_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW11) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW02 : (GMAC Offset: 0x710) Screening Type 2 Compare Word 0 Register  (index = 2) -------- */
+#define GMAC_ST2CW02_MASKVAL_Pos 0
+#define GMAC_ST2CW02_MASKVAL_Msk (0xffffu << GMAC_ST2CW02_MASKVAL_Pos) /**< \brief (GMAC_ST2CW02) Mask Value */
+#define GMAC_ST2CW02_MASKVAL(value) ((GMAC_ST2CW02_MASKVAL_Msk & ((value) << GMAC_ST2CW02_MASKVAL_Pos)))
+#define GMAC_ST2CW02_COMPVAL_Pos 16
+#define GMAC_ST2CW02_COMPVAL_Msk (0xffffu << GMAC_ST2CW02_COMPVAL_Pos) /**< \brief (GMAC_ST2CW02) Compare Value */
+#define GMAC_ST2CW02_COMPVAL(value) ((GMAC_ST2CW02_COMPVAL_Msk & ((value) << GMAC_ST2CW02_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW12 : (GMAC Offset: 0x714) Screening Type 2 Compare Word 1 Register  (index = 2) -------- */
+#define GMAC_ST2CW12_OFFSVAL_Pos 0
+#define GMAC_ST2CW12_OFFSVAL_Msk (0x7fu << GMAC_ST2CW12_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW12) Offset Value in Bytes */
+#define GMAC_ST2CW12_OFFSVAL(value) ((GMAC_ST2CW12_OFFSVAL_Msk & ((value) << GMAC_ST2CW12_OFFSVAL_Pos)))
+#define GMAC_ST2CW12_OFFSSTRT_Pos 7
+#define GMAC_ST2CW12_OFFSSTRT_Msk (0x3u << GMAC_ST2CW12_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW12) Ethernet Frame Offset Start */
+#define GMAC_ST2CW12_OFFSSTRT(value) ((GMAC_ST2CW12_OFFSSTRT_Msk & ((value) << GMAC_ST2CW12_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW12_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW12) Offset from the start of the frame */
+#define   GMAC_ST2CW12_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW12_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW12_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW12) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW03 : (GMAC Offset: 0x718) Screening Type 2 Compare Word 0 Register  (index = 3) -------- */
+#define GMAC_ST2CW03_MASKVAL_Pos 0
+#define GMAC_ST2CW03_MASKVAL_Msk (0xffffu << GMAC_ST2CW03_MASKVAL_Pos) /**< \brief (GMAC_ST2CW03) Mask Value */
+#define GMAC_ST2CW03_MASKVAL(value) ((GMAC_ST2CW03_MASKVAL_Msk & ((value) << GMAC_ST2CW03_MASKVAL_Pos)))
+#define GMAC_ST2CW03_COMPVAL_Pos 16
+#define GMAC_ST2CW03_COMPVAL_Msk (0xffffu << GMAC_ST2CW03_COMPVAL_Pos) /**< \brief (GMAC_ST2CW03) Compare Value */
+#define GMAC_ST2CW03_COMPVAL(value) ((GMAC_ST2CW03_COMPVAL_Msk & ((value) << GMAC_ST2CW03_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW13 : (GMAC Offset: 0x71C) Screening Type 2 Compare Word 1 Register  (index = 3) -------- */
+#define GMAC_ST2CW13_OFFSVAL_Pos 0
+#define GMAC_ST2CW13_OFFSVAL_Msk (0x7fu << GMAC_ST2CW13_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW13) Offset Value in Bytes */
+#define GMAC_ST2CW13_OFFSVAL(value) ((GMAC_ST2CW13_OFFSVAL_Msk & ((value) << GMAC_ST2CW13_OFFSVAL_Pos)))
+#define GMAC_ST2CW13_OFFSSTRT_Pos 7
+#define GMAC_ST2CW13_OFFSSTRT_Msk (0x3u << GMAC_ST2CW13_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW13) Ethernet Frame Offset Start */
+#define GMAC_ST2CW13_OFFSSTRT(value) ((GMAC_ST2CW13_OFFSSTRT_Msk & ((value) << GMAC_ST2CW13_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW13_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW13) Offset from the start of the frame */
+#define   GMAC_ST2CW13_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW13_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW13_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW13) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW04 : (GMAC Offset: 0x720) Screening Type 2 Compare Word 0 Register  (index = 4) -------- */
+#define GMAC_ST2CW04_MASKVAL_Pos 0
+#define GMAC_ST2CW04_MASKVAL_Msk (0xffffu << GMAC_ST2CW04_MASKVAL_Pos) /**< \brief (GMAC_ST2CW04) Mask Value */
+#define GMAC_ST2CW04_MASKVAL(value) ((GMAC_ST2CW04_MASKVAL_Msk & ((value) << GMAC_ST2CW04_MASKVAL_Pos)))
+#define GMAC_ST2CW04_COMPVAL_Pos 16
+#define GMAC_ST2CW04_COMPVAL_Msk (0xffffu << GMAC_ST2CW04_COMPVAL_Pos) /**< \brief (GMAC_ST2CW04) Compare Value */
+#define GMAC_ST2CW04_COMPVAL(value) ((GMAC_ST2CW04_COMPVAL_Msk & ((value) << GMAC_ST2CW04_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW14 : (GMAC Offset: 0x724) Screening Type 2 Compare Word 1 Register  (index = 4) -------- */
+#define GMAC_ST2CW14_OFFSVAL_Pos 0
+#define GMAC_ST2CW14_OFFSVAL_Msk (0x7fu << GMAC_ST2CW14_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW14) Offset Value in Bytes */
+#define GMAC_ST2CW14_OFFSVAL(value) ((GMAC_ST2CW14_OFFSVAL_Msk & ((value) << GMAC_ST2CW14_OFFSVAL_Pos)))
+#define GMAC_ST2CW14_OFFSSTRT_Pos 7
+#define GMAC_ST2CW14_OFFSSTRT_Msk (0x3u << GMAC_ST2CW14_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW14) Ethernet Frame Offset Start */
+#define GMAC_ST2CW14_OFFSSTRT(value) ((GMAC_ST2CW14_OFFSSTRT_Msk & ((value) << GMAC_ST2CW14_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW14_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW14) Offset from the start of the frame */
+#define   GMAC_ST2CW14_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW14_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW14_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW14) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW05 : (GMAC Offset: 0x728) Screening Type 2 Compare Word 0 Register  (index = 5) -------- */
+#define GMAC_ST2CW05_MASKVAL_Pos 0
+#define GMAC_ST2CW05_MASKVAL_Msk (0xffffu << GMAC_ST2CW05_MASKVAL_Pos) /**< \brief (GMAC_ST2CW05) Mask Value */
+#define GMAC_ST2CW05_MASKVAL(value) ((GMAC_ST2CW05_MASKVAL_Msk & ((value) << GMAC_ST2CW05_MASKVAL_Pos)))
+#define GMAC_ST2CW05_COMPVAL_Pos 16
+#define GMAC_ST2CW05_COMPVAL_Msk (0xffffu << GMAC_ST2CW05_COMPVAL_Pos) /**< \brief (GMAC_ST2CW05) Compare Value */
+#define GMAC_ST2CW05_COMPVAL(value) ((GMAC_ST2CW05_COMPVAL_Msk & ((value) << GMAC_ST2CW05_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW15 : (GMAC Offset: 0x72C) Screening Type 2 Compare Word 1 Register  (index = 5) -------- */
+#define GMAC_ST2CW15_OFFSVAL_Pos 0
+#define GMAC_ST2CW15_OFFSVAL_Msk (0x7fu << GMAC_ST2CW15_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW15) Offset Value in Bytes */
+#define GMAC_ST2CW15_OFFSVAL(value) ((GMAC_ST2CW15_OFFSVAL_Msk & ((value) << GMAC_ST2CW15_OFFSVAL_Pos)))
+#define GMAC_ST2CW15_OFFSSTRT_Pos 7
+#define GMAC_ST2CW15_OFFSSTRT_Msk (0x3u << GMAC_ST2CW15_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW15) Ethernet Frame Offset Start */
+#define GMAC_ST2CW15_OFFSSTRT(value) ((GMAC_ST2CW15_OFFSSTRT_Msk & ((value) << GMAC_ST2CW15_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW15_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW15) Offset from the start of the frame */
+#define   GMAC_ST2CW15_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW15_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW15_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW15) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW06 : (GMAC Offset: 0x730) Screening Type 2 Compare Word 0 Register  (index = 6) -------- */
+#define GMAC_ST2CW06_MASKVAL_Pos 0
+#define GMAC_ST2CW06_MASKVAL_Msk (0xffffu << GMAC_ST2CW06_MASKVAL_Pos) /**< \brief (GMAC_ST2CW06) Mask Value */
+#define GMAC_ST2CW06_MASKVAL(value) ((GMAC_ST2CW06_MASKVAL_Msk & ((value) << GMAC_ST2CW06_MASKVAL_Pos)))
+#define GMAC_ST2CW06_COMPVAL_Pos 16
+#define GMAC_ST2CW06_COMPVAL_Msk (0xffffu << GMAC_ST2CW06_COMPVAL_Pos) /**< \brief (GMAC_ST2CW06) Compare Value */
+#define GMAC_ST2CW06_COMPVAL(value) ((GMAC_ST2CW06_COMPVAL_Msk & ((value) << GMAC_ST2CW06_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW16 : (GMAC Offset: 0x734) Screening Type 2 Compare Word 1 Register  (index = 6) -------- */
+#define GMAC_ST2CW16_OFFSVAL_Pos 0
+#define GMAC_ST2CW16_OFFSVAL_Msk (0x7fu << GMAC_ST2CW16_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW16) Offset Value in Bytes */
+#define GMAC_ST2CW16_OFFSVAL(value) ((GMAC_ST2CW16_OFFSVAL_Msk & ((value) << GMAC_ST2CW16_OFFSVAL_Pos)))
+#define GMAC_ST2CW16_OFFSSTRT_Pos 7
+#define GMAC_ST2CW16_OFFSSTRT_Msk (0x3u << GMAC_ST2CW16_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW16) Ethernet Frame Offset Start */
+#define GMAC_ST2CW16_OFFSSTRT(value) ((GMAC_ST2CW16_OFFSSTRT_Msk & ((value) << GMAC_ST2CW16_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW16_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW16) Offset from the start of the frame */
+#define   GMAC_ST2CW16_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW16_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW16_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW16) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW07 : (GMAC Offset: 0x738) Screening Type 2 Compare Word 0 Register  (index = 7) -------- */
+#define GMAC_ST2CW07_MASKVAL_Pos 0
+#define GMAC_ST2CW07_MASKVAL_Msk (0xffffu << GMAC_ST2CW07_MASKVAL_Pos) /**< \brief (GMAC_ST2CW07) Mask Value */
+#define GMAC_ST2CW07_MASKVAL(value) ((GMAC_ST2CW07_MASKVAL_Msk & ((value) << GMAC_ST2CW07_MASKVAL_Pos)))
+#define GMAC_ST2CW07_COMPVAL_Pos 16
+#define GMAC_ST2CW07_COMPVAL_Msk (0xffffu << GMAC_ST2CW07_COMPVAL_Pos) /**< \brief (GMAC_ST2CW07) Compare Value */
+#define GMAC_ST2CW07_COMPVAL(value) ((GMAC_ST2CW07_COMPVAL_Msk & ((value) << GMAC_ST2CW07_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW17 : (GMAC Offset: 0x73C) Screening Type 2 Compare Word 1 Register  (index = 7) -------- */
+#define GMAC_ST2CW17_OFFSVAL_Pos 0
+#define GMAC_ST2CW17_OFFSVAL_Msk (0x7fu << GMAC_ST2CW17_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW17) Offset Value in Bytes */
+#define GMAC_ST2CW17_OFFSVAL(value) ((GMAC_ST2CW17_OFFSVAL_Msk & ((value) << GMAC_ST2CW17_OFFSVAL_Pos)))
+#define GMAC_ST2CW17_OFFSSTRT_Pos 7
+#define GMAC_ST2CW17_OFFSSTRT_Msk (0x3u << GMAC_ST2CW17_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW17) Ethernet Frame Offset Start */
+#define GMAC_ST2CW17_OFFSSTRT(value) ((GMAC_ST2CW17_OFFSSTRT_Msk & ((value) << GMAC_ST2CW17_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW17_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW17) Offset from the start of the frame */
+#define   GMAC_ST2CW17_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW17_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW17_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW17) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW08 : (GMAC Offset: 0x740) Screening Type 2 Compare Word 0 Register  (index = 8) -------- */
+#define GMAC_ST2CW08_MASKVAL_Pos 0
+#define GMAC_ST2CW08_MASKVAL_Msk (0xffffu << GMAC_ST2CW08_MASKVAL_Pos) /**< \brief (GMAC_ST2CW08) Mask Value */
+#define GMAC_ST2CW08_MASKVAL(value) ((GMAC_ST2CW08_MASKVAL_Msk & ((value) << GMAC_ST2CW08_MASKVAL_Pos)))
+#define GMAC_ST2CW08_COMPVAL_Pos 16
+#define GMAC_ST2CW08_COMPVAL_Msk (0xffffu << GMAC_ST2CW08_COMPVAL_Pos) /**< \brief (GMAC_ST2CW08) Compare Value */
+#define GMAC_ST2CW08_COMPVAL(value) ((GMAC_ST2CW08_COMPVAL_Msk & ((value) << GMAC_ST2CW08_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW18 : (GMAC Offset: 0x744) Screening Type 2 Compare Word 1 Register  (index = 8) -------- */
+#define GMAC_ST2CW18_OFFSVAL_Pos 0
+#define GMAC_ST2CW18_OFFSVAL_Msk (0x7fu << GMAC_ST2CW18_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW18) Offset Value in Bytes */
+#define GMAC_ST2CW18_OFFSVAL(value) ((GMAC_ST2CW18_OFFSVAL_Msk & ((value) << GMAC_ST2CW18_OFFSVAL_Pos)))
+#define GMAC_ST2CW18_OFFSSTRT_Pos 7
+#define GMAC_ST2CW18_OFFSSTRT_Msk (0x3u << GMAC_ST2CW18_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW18) Ethernet Frame Offset Start */
+#define GMAC_ST2CW18_OFFSSTRT(value) ((GMAC_ST2CW18_OFFSSTRT_Msk & ((value) << GMAC_ST2CW18_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW18_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW18) Offset from the start of the frame */
+#define   GMAC_ST2CW18_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW18_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW18_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW18) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW09 : (GMAC Offset: 0x748) Screening Type 2 Compare Word 0 Register  (index = 9) -------- */
+#define GMAC_ST2CW09_MASKVAL_Pos 0
+#define GMAC_ST2CW09_MASKVAL_Msk (0xffffu << GMAC_ST2CW09_MASKVAL_Pos) /**< \brief (GMAC_ST2CW09) Mask Value */
+#define GMAC_ST2CW09_MASKVAL(value) ((GMAC_ST2CW09_MASKVAL_Msk & ((value) << GMAC_ST2CW09_MASKVAL_Pos)))
+#define GMAC_ST2CW09_COMPVAL_Pos 16
+#define GMAC_ST2CW09_COMPVAL_Msk (0xffffu << GMAC_ST2CW09_COMPVAL_Pos) /**< \brief (GMAC_ST2CW09) Compare Value */
+#define GMAC_ST2CW09_COMPVAL(value) ((GMAC_ST2CW09_COMPVAL_Msk & ((value) << GMAC_ST2CW09_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW19 : (GMAC Offset: 0x74C) Screening Type 2 Compare Word 1 Register  (index = 9) -------- */
+#define GMAC_ST2CW19_OFFSVAL_Pos 0
+#define GMAC_ST2CW19_OFFSVAL_Msk (0x7fu << GMAC_ST2CW19_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW19) Offset Value in Bytes */
+#define GMAC_ST2CW19_OFFSVAL(value) ((GMAC_ST2CW19_OFFSVAL_Msk & ((value) << GMAC_ST2CW19_OFFSVAL_Pos)))
+#define GMAC_ST2CW19_OFFSSTRT_Pos 7
+#define GMAC_ST2CW19_OFFSSTRT_Msk (0x3u << GMAC_ST2CW19_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW19) Ethernet Frame Offset Start */
+#define GMAC_ST2CW19_OFFSSTRT(value) ((GMAC_ST2CW19_OFFSSTRT_Msk & ((value) << GMAC_ST2CW19_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW19_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW19) Offset from the start of the frame */
+#define   GMAC_ST2CW19_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW19_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW19_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW19) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW010 : (GMAC Offset: 0x750) Screening Type 2 Compare Word 0 Register  (index = 10) -------- */
+#define GMAC_ST2CW010_MASKVAL_Pos 0
+#define GMAC_ST2CW010_MASKVAL_Msk (0xffffu << GMAC_ST2CW010_MASKVAL_Pos) /**< \brief (GMAC_ST2CW010) Mask Value */
+#define GMAC_ST2CW010_MASKVAL(value) ((GMAC_ST2CW010_MASKVAL_Msk & ((value) << GMAC_ST2CW010_MASKVAL_Pos)))
+#define GMAC_ST2CW010_COMPVAL_Pos 16
+#define GMAC_ST2CW010_COMPVAL_Msk (0xffffu << GMAC_ST2CW010_COMPVAL_Pos) /**< \brief (GMAC_ST2CW010) Compare Value */
+#define GMAC_ST2CW010_COMPVAL(value) ((GMAC_ST2CW010_COMPVAL_Msk & ((value) << GMAC_ST2CW010_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW110 : (GMAC Offset: 0x754) Screening Type 2 Compare Word 1 Register  (index = 10) -------- */
+#define GMAC_ST2CW110_OFFSVAL_Pos 0
+#define GMAC_ST2CW110_OFFSVAL_Msk (0x7fu << GMAC_ST2CW110_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW110) Offset Value in Bytes */
+#define GMAC_ST2CW110_OFFSVAL(value) ((GMAC_ST2CW110_OFFSVAL_Msk & ((value) << GMAC_ST2CW110_OFFSVAL_Pos)))
+#define GMAC_ST2CW110_OFFSSTRT_Pos 7
+#define GMAC_ST2CW110_OFFSSTRT_Msk (0x3u << GMAC_ST2CW110_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW110) Ethernet Frame Offset Start */
+#define GMAC_ST2CW110_OFFSSTRT(value) ((GMAC_ST2CW110_OFFSSTRT_Msk & ((value) << GMAC_ST2CW110_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW110_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW110) Offset from the start of the frame */
+#define   GMAC_ST2CW110_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW110_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW110_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW110) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW011 : (GMAC Offset: 0x758) Screening Type 2 Compare Word 0 Register  (index = 11) -------- */
+#define GMAC_ST2CW011_MASKVAL_Pos 0
+#define GMAC_ST2CW011_MASKVAL_Msk (0xffffu << GMAC_ST2CW011_MASKVAL_Pos) /**< \brief (GMAC_ST2CW011) Mask Value */
+#define GMAC_ST2CW011_MASKVAL(value) ((GMAC_ST2CW011_MASKVAL_Msk & ((value) << GMAC_ST2CW011_MASKVAL_Pos)))
+#define GMAC_ST2CW011_COMPVAL_Pos 16
+#define GMAC_ST2CW011_COMPVAL_Msk (0xffffu << GMAC_ST2CW011_COMPVAL_Pos) /**< \brief (GMAC_ST2CW011) Compare Value */
+#define GMAC_ST2CW011_COMPVAL(value) ((GMAC_ST2CW011_COMPVAL_Msk & ((value) << GMAC_ST2CW011_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW111 : (GMAC Offset: 0x75C) Screening Type 2 Compare Word 1 Register  (index = 11) -------- */
+#define GMAC_ST2CW111_OFFSVAL_Pos 0
+#define GMAC_ST2CW111_OFFSVAL_Msk (0x7fu << GMAC_ST2CW111_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW111) Offset Value in Bytes */
+#define GMAC_ST2CW111_OFFSVAL(value) ((GMAC_ST2CW111_OFFSVAL_Msk & ((value) << GMAC_ST2CW111_OFFSVAL_Pos)))
+#define GMAC_ST2CW111_OFFSSTRT_Pos 7
+#define GMAC_ST2CW111_OFFSSTRT_Msk (0x3u << GMAC_ST2CW111_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW111) Ethernet Frame Offset Start */
+#define GMAC_ST2CW111_OFFSSTRT(value) ((GMAC_ST2CW111_OFFSSTRT_Msk & ((value) << GMAC_ST2CW111_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW111_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW111) Offset from the start of the frame */
+#define   GMAC_ST2CW111_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW111_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW111_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW111) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW012 : (GMAC Offset: 0x760) Screening Type 2 Compare Word 0 Register  (index = 12) -------- */
+#define GMAC_ST2CW012_MASKVAL_Pos 0
+#define GMAC_ST2CW012_MASKVAL_Msk (0xffffu << GMAC_ST2CW012_MASKVAL_Pos) /**< \brief (GMAC_ST2CW012) Mask Value */
+#define GMAC_ST2CW012_MASKVAL(value) ((GMAC_ST2CW012_MASKVAL_Msk & ((value) << GMAC_ST2CW012_MASKVAL_Pos)))
+#define GMAC_ST2CW012_COMPVAL_Pos 16
+#define GMAC_ST2CW012_COMPVAL_Msk (0xffffu << GMAC_ST2CW012_COMPVAL_Pos) /**< \brief (GMAC_ST2CW012) Compare Value */
+#define GMAC_ST2CW012_COMPVAL(value) ((GMAC_ST2CW012_COMPVAL_Msk & ((value) << GMAC_ST2CW012_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW112 : (GMAC Offset: 0x764) Screening Type 2 Compare Word 1 Register  (index = 12) -------- */
+#define GMAC_ST2CW112_OFFSVAL_Pos 0
+#define GMAC_ST2CW112_OFFSVAL_Msk (0x7fu << GMAC_ST2CW112_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW112) Offset Value in Bytes */
+#define GMAC_ST2CW112_OFFSVAL(value) ((GMAC_ST2CW112_OFFSVAL_Msk & ((value) << GMAC_ST2CW112_OFFSVAL_Pos)))
+#define GMAC_ST2CW112_OFFSSTRT_Pos 7
+#define GMAC_ST2CW112_OFFSSTRT_Msk (0x3u << GMAC_ST2CW112_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW112) Ethernet Frame Offset Start */
+#define GMAC_ST2CW112_OFFSSTRT(value) ((GMAC_ST2CW112_OFFSSTRT_Msk & ((value) << GMAC_ST2CW112_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW112_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW112) Offset from the start of the frame */
+#define   GMAC_ST2CW112_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW112_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW112_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW112) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW013 : (GMAC Offset: 0x768) Screening Type 2 Compare Word 0 Register  (index = 13) -------- */
+#define GMAC_ST2CW013_MASKVAL_Pos 0
+#define GMAC_ST2CW013_MASKVAL_Msk (0xffffu << GMAC_ST2CW013_MASKVAL_Pos) /**< \brief (GMAC_ST2CW013) Mask Value */
+#define GMAC_ST2CW013_MASKVAL(value) ((GMAC_ST2CW013_MASKVAL_Msk & ((value) << GMAC_ST2CW013_MASKVAL_Pos)))
+#define GMAC_ST2CW013_COMPVAL_Pos 16
+#define GMAC_ST2CW013_COMPVAL_Msk (0xffffu << GMAC_ST2CW013_COMPVAL_Pos) /**< \brief (GMAC_ST2CW013) Compare Value */
+#define GMAC_ST2CW013_COMPVAL(value) ((GMAC_ST2CW013_COMPVAL_Msk & ((value) << GMAC_ST2CW013_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW113 : (GMAC Offset: 0x76C) Screening Type 2 Compare Word 1 Register  (index = 13) -------- */
+#define GMAC_ST2CW113_OFFSVAL_Pos 0
+#define GMAC_ST2CW113_OFFSVAL_Msk (0x7fu << GMAC_ST2CW113_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW113) Offset Value in Bytes */
+#define GMAC_ST2CW113_OFFSVAL(value) ((GMAC_ST2CW113_OFFSVAL_Msk & ((value) << GMAC_ST2CW113_OFFSVAL_Pos)))
+#define GMAC_ST2CW113_OFFSSTRT_Pos 7
+#define GMAC_ST2CW113_OFFSSTRT_Msk (0x3u << GMAC_ST2CW113_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW113) Ethernet Frame Offset Start */
+#define GMAC_ST2CW113_OFFSSTRT(value) ((GMAC_ST2CW113_OFFSSTRT_Msk & ((value) << GMAC_ST2CW113_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW113_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW113) Offset from the start of the frame */
+#define   GMAC_ST2CW113_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW113_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW113_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW113) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW014 : (GMAC Offset: 0x770) Screening Type 2 Compare Word 0 Register  (index = 14) -------- */
+#define GMAC_ST2CW014_MASKVAL_Pos 0
+#define GMAC_ST2CW014_MASKVAL_Msk (0xffffu << GMAC_ST2CW014_MASKVAL_Pos) /**< \brief (GMAC_ST2CW014) Mask Value */
+#define GMAC_ST2CW014_MASKVAL(value) ((GMAC_ST2CW014_MASKVAL_Msk & ((value) << GMAC_ST2CW014_MASKVAL_Pos)))
+#define GMAC_ST2CW014_COMPVAL_Pos 16
+#define GMAC_ST2CW014_COMPVAL_Msk (0xffffu << GMAC_ST2CW014_COMPVAL_Pos) /**< \brief (GMAC_ST2CW014) Compare Value */
+#define GMAC_ST2CW014_COMPVAL(value) ((GMAC_ST2CW014_COMPVAL_Msk & ((value) << GMAC_ST2CW014_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW114 : (GMAC Offset: 0x774) Screening Type 2 Compare Word 1 Register  (index = 14) -------- */
+#define GMAC_ST2CW114_OFFSVAL_Pos 0
+#define GMAC_ST2CW114_OFFSVAL_Msk (0x7fu << GMAC_ST2CW114_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW114) Offset Value in Bytes */
+#define GMAC_ST2CW114_OFFSVAL(value) ((GMAC_ST2CW114_OFFSVAL_Msk & ((value) << GMAC_ST2CW114_OFFSVAL_Pos)))
+#define GMAC_ST2CW114_OFFSSTRT_Pos 7
+#define GMAC_ST2CW114_OFFSSTRT_Msk (0x3u << GMAC_ST2CW114_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW114) Ethernet Frame Offset Start */
+#define GMAC_ST2CW114_OFFSSTRT(value) ((GMAC_ST2CW114_OFFSSTRT_Msk & ((value) << GMAC_ST2CW114_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW114_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW114) Offset from the start of the frame */
+#define   GMAC_ST2CW114_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW114_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW114_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW114) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW015 : (GMAC Offset: 0x778) Screening Type 2 Compare Word 0 Register  (index = 15) -------- */
+#define GMAC_ST2CW015_MASKVAL_Pos 0
+#define GMAC_ST2CW015_MASKVAL_Msk (0xffffu << GMAC_ST2CW015_MASKVAL_Pos) /**< \brief (GMAC_ST2CW015) Mask Value */
+#define GMAC_ST2CW015_MASKVAL(value) ((GMAC_ST2CW015_MASKVAL_Msk & ((value) << GMAC_ST2CW015_MASKVAL_Pos)))
+#define GMAC_ST2CW015_COMPVAL_Pos 16
+#define GMAC_ST2CW015_COMPVAL_Msk (0xffffu << GMAC_ST2CW015_COMPVAL_Pos) /**< \brief (GMAC_ST2CW015) Compare Value */
+#define GMAC_ST2CW015_COMPVAL(value) ((GMAC_ST2CW015_COMPVAL_Msk & ((value) << GMAC_ST2CW015_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW115 : (GMAC Offset: 0x77C) Screening Type 2 Compare Word 1 Register  (index = 15) -------- */
+#define GMAC_ST2CW115_OFFSVAL_Pos 0
+#define GMAC_ST2CW115_OFFSVAL_Msk (0x7fu << GMAC_ST2CW115_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW115) Offset Value in Bytes */
+#define GMAC_ST2CW115_OFFSVAL(value) ((GMAC_ST2CW115_OFFSVAL_Msk & ((value) << GMAC_ST2CW115_OFFSVAL_Pos)))
+#define GMAC_ST2CW115_OFFSSTRT_Pos 7
+#define GMAC_ST2CW115_OFFSSTRT_Msk (0x3u << GMAC_ST2CW115_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW115) Ethernet Frame Offset Start */
+#define GMAC_ST2CW115_OFFSSTRT(value) ((GMAC_ST2CW115_OFFSSTRT_Msk & ((value) << GMAC_ST2CW115_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW115_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW115) Offset from the start of the frame */
+#define   GMAC_ST2CW115_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW115_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW115_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW115) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW016 : (GMAC Offset: 0x780) Screening Type 2 Compare Word 0 Register  (index = 16) -------- */
+#define GMAC_ST2CW016_MASKVAL_Pos 0
+#define GMAC_ST2CW016_MASKVAL_Msk (0xffffu << GMAC_ST2CW016_MASKVAL_Pos) /**< \brief (GMAC_ST2CW016) Mask Value */
+#define GMAC_ST2CW016_MASKVAL(value) ((GMAC_ST2CW016_MASKVAL_Msk & ((value) << GMAC_ST2CW016_MASKVAL_Pos)))
+#define GMAC_ST2CW016_COMPVAL_Pos 16
+#define GMAC_ST2CW016_COMPVAL_Msk (0xffffu << GMAC_ST2CW016_COMPVAL_Pos) /**< \brief (GMAC_ST2CW016) Compare Value */
+#define GMAC_ST2CW016_COMPVAL(value) ((GMAC_ST2CW016_COMPVAL_Msk & ((value) << GMAC_ST2CW016_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW116 : (GMAC Offset: 0x784) Screening Type 2 Compare Word 1 Register  (index = 16) -------- */
+#define GMAC_ST2CW116_OFFSVAL_Pos 0
+#define GMAC_ST2CW116_OFFSVAL_Msk (0x7fu << GMAC_ST2CW116_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW116) Offset Value in Bytes */
+#define GMAC_ST2CW116_OFFSVAL(value) ((GMAC_ST2CW116_OFFSVAL_Msk & ((value) << GMAC_ST2CW116_OFFSVAL_Pos)))
+#define GMAC_ST2CW116_OFFSSTRT_Pos 7
+#define GMAC_ST2CW116_OFFSSTRT_Msk (0x3u << GMAC_ST2CW116_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW116) Ethernet Frame Offset Start */
+#define GMAC_ST2CW116_OFFSSTRT(value) ((GMAC_ST2CW116_OFFSSTRT_Msk & ((value) << GMAC_ST2CW116_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW116_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW116) Offset from the start of the frame */
+#define   GMAC_ST2CW116_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW116_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW116_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW116) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW017 : (GMAC Offset: 0x788) Screening Type 2 Compare Word 0 Register  (index = 17) -------- */
+#define GMAC_ST2CW017_MASKVAL_Pos 0
+#define GMAC_ST2CW017_MASKVAL_Msk (0xffffu << GMAC_ST2CW017_MASKVAL_Pos) /**< \brief (GMAC_ST2CW017) Mask Value */
+#define GMAC_ST2CW017_MASKVAL(value) ((GMAC_ST2CW017_MASKVAL_Msk & ((value) << GMAC_ST2CW017_MASKVAL_Pos)))
+#define GMAC_ST2CW017_COMPVAL_Pos 16
+#define GMAC_ST2CW017_COMPVAL_Msk (0xffffu << GMAC_ST2CW017_COMPVAL_Pos) /**< \brief (GMAC_ST2CW017) Compare Value */
+#define GMAC_ST2CW017_COMPVAL(value) ((GMAC_ST2CW017_COMPVAL_Msk & ((value) << GMAC_ST2CW017_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW117 : (GMAC Offset: 0x78C) Screening Type 2 Compare Word 1 Register  (index = 17) -------- */
+#define GMAC_ST2CW117_OFFSVAL_Pos 0
+#define GMAC_ST2CW117_OFFSVAL_Msk (0x7fu << GMAC_ST2CW117_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW117) Offset Value in Bytes */
+#define GMAC_ST2CW117_OFFSVAL(value) ((GMAC_ST2CW117_OFFSVAL_Msk & ((value) << GMAC_ST2CW117_OFFSVAL_Pos)))
+#define GMAC_ST2CW117_OFFSSTRT_Pos 7
+#define GMAC_ST2CW117_OFFSSTRT_Msk (0x3u << GMAC_ST2CW117_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW117) Ethernet Frame Offset Start */
+#define GMAC_ST2CW117_OFFSSTRT(value) ((GMAC_ST2CW117_OFFSSTRT_Msk & ((value) << GMAC_ST2CW117_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW117_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW117) Offset from the start of the frame */
+#define   GMAC_ST2CW117_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW117_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW117_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW117) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW018 : (GMAC Offset: 0x790) Screening Type 2 Compare Word 0 Register  (index = 18) -------- */
+#define GMAC_ST2CW018_MASKVAL_Pos 0
+#define GMAC_ST2CW018_MASKVAL_Msk (0xffffu << GMAC_ST2CW018_MASKVAL_Pos) /**< \brief (GMAC_ST2CW018) Mask Value */
+#define GMAC_ST2CW018_MASKVAL(value) ((GMAC_ST2CW018_MASKVAL_Msk & ((value) << GMAC_ST2CW018_MASKVAL_Pos)))
+#define GMAC_ST2CW018_COMPVAL_Pos 16
+#define GMAC_ST2CW018_COMPVAL_Msk (0xffffu << GMAC_ST2CW018_COMPVAL_Pos) /**< \brief (GMAC_ST2CW018) Compare Value */
+#define GMAC_ST2CW018_COMPVAL(value) ((GMAC_ST2CW018_COMPVAL_Msk & ((value) << GMAC_ST2CW018_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW118 : (GMAC Offset: 0x794) Screening Type 2 Compare Word 1 Register  (index = 18) -------- */
+#define GMAC_ST2CW118_OFFSVAL_Pos 0
+#define GMAC_ST2CW118_OFFSVAL_Msk (0x7fu << GMAC_ST2CW118_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW118) Offset Value in Bytes */
+#define GMAC_ST2CW118_OFFSVAL(value) ((GMAC_ST2CW118_OFFSVAL_Msk & ((value) << GMAC_ST2CW118_OFFSVAL_Pos)))
+#define GMAC_ST2CW118_OFFSSTRT_Pos 7
+#define GMAC_ST2CW118_OFFSSTRT_Msk (0x3u << GMAC_ST2CW118_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW118) Ethernet Frame Offset Start */
+#define GMAC_ST2CW118_OFFSSTRT(value) ((GMAC_ST2CW118_OFFSSTRT_Msk & ((value) << GMAC_ST2CW118_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW118_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW118) Offset from the start of the frame */
+#define   GMAC_ST2CW118_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW118_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW118_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW118) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW019 : (GMAC Offset: 0x798) Screening Type 2 Compare Word 0 Register  (index = 19) -------- */
+#define GMAC_ST2CW019_MASKVAL_Pos 0
+#define GMAC_ST2CW019_MASKVAL_Msk (0xffffu << GMAC_ST2CW019_MASKVAL_Pos) /**< \brief (GMAC_ST2CW019) Mask Value */
+#define GMAC_ST2CW019_MASKVAL(value) ((GMAC_ST2CW019_MASKVAL_Msk & ((value) << GMAC_ST2CW019_MASKVAL_Pos)))
+#define GMAC_ST2CW019_COMPVAL_Pos 16
+#define GMAC_ST2CW019_COMPVAL_Msk (0xffffu << GMAC_ST2CW019_COMPVAL_Pos) /**< \brief (GMAC_ST2CW019) Compare Value */
+#define GMAC_ST2CW019_COMPVAL(value) ((GMAC_ST2CW019_COMPVAL_Msk & ((value) << GMAC_ST2CW019_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW119 : (GMAC Offset: 0x79C) Screening Type 2 Compare Word 1 Register  (index = 19) -------- */
+#define GMAC_ST2CW119_OFFSVAL_Pos 0
+#define GMAC_ST2CW119_OFFSVAL_Msk (0x7fu << GMAC_ST2CW119_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW119) Offset Value in Bytes */
+#define GMAC_ST2CW119_OFFSVAL(value) ((GMAC_ST2CW119_OFFSVAL_Msk & ((value) << GMAC_ST2CW119_OFFSVAL_Pos)))
+#define GMAC_ST2CW119_OFFSSTRT_Pos 7
+#define GMAC_ST2CW119_OFFSSTRT_Msk (0x3u << GMAC_ST2CW119_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW119) Ethernet Frame Offset Start */
+#define GMAC_ST2CW119_OFFSSTRT(value) ((GMAC_ST2CW119_OFFSSTRT_Msk & ((value) << GMAC_ST2CW119_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW119_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW119) Offset from the start of the frame */
+#define   GMAC_ST2CW119_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW119_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW119_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW119) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW020 : (GMAC Offset: 0x7A0) Screening Type 2 Compare Word 0 Register  (index = 20) -------- */
+#define GMAC_ST2CW020_MASKVAL_Pos 0
+#define GMAC_ST2CW020_MASKVAL_Msk (0xffffu << GMAC_ST2CW020_MASKVAL_Pos) /**< \brief (GMAC_ST2CW020) Mask Value */
+#define GMAC_ST2CW020_MASKVAL(value) ((GMAC_ST2CW020_MASKVAL_Msk & ((value) << GMAC_ST2CW020_MASKVAL_Pos)))
+#define GMAC_ST2CW020_COMPVAL_Pos 16
+#define GMAC_ST2CW020_COMPVAL_Msk (0xffffu << GMAC_ST2CW020_COMPVAL_Pos) /**< \brief (GMAC_ST2CW020) Compare Value */
+#define GMAC_ST2CW020_COMPVAL(value) ((GMAC_ST2CW020_COMPVAL_Msk & ((value) << GMAC_ST2CW020_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW120 : (GMAC Offset: 0x7A4) Screening Type 2 Compare Word 1 Register  (index = 20) -------- */
+#define GMAC_ST2CW120_OFFSVAL_Pos 0
+#define GMAC_ST2CW120_OFFSVAL_Msk (0x7fu << GMAC_ST2CW120_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW120) Offset Value in Bytes */
+#define GMAC_ST2CW120_OFFSVAL(value) ((GMAC_ST2CW120_OFFSVAL_Msk & ((value) << GMAC_ST2CW120_OFFSVAL_Pos)))
+#define GMAC_ST2CW120_OFFSSTRT_Pos 7
+#define GMAC_ST2CW120_OFFSSTRT_Msk (0x3u << GMAC_ST2CW120_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW120) Ethernet Frame Offset Start */
+#define GMAC_ST2CW120_OFFSSTRT(value) ((GMAC_ST2CW120_OFFSSTRT_Msk & ((value) << GMAC_ST2CW120_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW120_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW120) Offset from the start of the frame */
+#define   GMAC_ST2CW120_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW120_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW120_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW120) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW021 : (GMAC Offset: 0x7A8) Screening Type 2 Compare Word 0 Register  (index = 21) -------- */
+#define GMAC_ST2CW021_MASKVAL_Pos 0
+#define GMAC_ST2CW021_MASKVAL_Msk (0xffffu << GMAC_ST2CW021_MASKVAL_Pos) /**< \brief (GMAC_ST2CW021) Mask Value */
+#define GMAC_ST2CW021_MASKVAL(value) ((GMAC_ST2CW021_MASKVAL_Msk & ((value) << GMAC_ST2CW021_MASKVAL_Pos)))
+#define GMAC_ST2CW021_COMPVAL_Pos 16
+#define GMAC_ST2CW021_COMPVAL_Msk (0xffffu << GMAC_ST2CW021_COMPVAL_Pos) /**< \brief (GMAC_ST2CW021) Compare Value */
+#define GMAC_ST2CW021_COMPVAL(value) ((GMAC_ST2CW021_COMPVAL_Msk & ((value) << GMAC_ST2CW021_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW121 : (GMAC Offset: 0x7AC) Screening Type 2 Compare Word 1 Register  (index = 21) -------- */
+#define GMAC_ST2CW121_OFFSVAL_Pos 0
+#define GMAC_ST2CW121_OFFSVAL_Msk (0x7fu << GMAC_ST2CW121_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW121) Offset Value in Bytes */
+#define GMAC_ST2CW121_OFFSVAL(value) ((GMAC_ST2CW121_OFFSVAL_Msk & ((value) << GMAC_ST2CW121_OFFSVAL_Pos)))
+#define GMAC_ST2CW121_OFFSSTRT_Pos 7
+#define GMAC_ST2CW121_OFFSSTRT_Msk (0x3u << GMAC_ST2CW121_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW121) Ethernet Frame Offset Start */
+#define GMAC_ST2CW121_OFFSSTRT(value) ((GMAC_ST2CW121_OFFSSTRT_Msk & ((value) << GMAC_ST2CW121_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW121_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW121) Offset from the start of the frame */
+#define   GMAC_ST2CW121_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW121_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW121_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW121) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW022 : (GMAC Offset: 0x7B0) Screening Type 2 Compare Word 0 Register  (index = 22) -------- */
+#define GMAC_ST2CW022_MASKVAL_Pos 0
+#define GMAC_ST2CW022_MASKVAL_Msk (0xffffu << GMAC_ST2CW022_MASKVAL_Pos) /**< \brief (GMAC_ST2CW022) Mask Value */
+#define GMAC_ST2CW022_MASKVAL(value) ((GMAC_ST2CW022_MASKVAL_Msk & ((value) << GMAC_ST2CW022_MASKVAL_Pos)))
+#define GMAC_ST2CW022_COMPVAL_Pos 16
+#define GMAC_ST2CW022_COMPVAL_Msk (0xffffu << GMAC_ST2CW022_COMPVAL_Pos) /**< \brief (GMAC_ST2CW022) Compare Value */
+#define GMAC_ST2CW022_COMPVAL(value) ((GMAC_ST2CW022_COMPVAL_Msk & ((value) << GMAC_ST2CW022_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW122 : (GMAC Offset: 0x7B4) Screening Type 2 Compare Word 1 Register  (index = 22) -------- */
+#define GMAC_ST2CW122_OFFSVAL_Pos 0
+#define GMAC_ST2CW122_OFFSVAL_Msk (0x7fu << GMAC_ST2CW122_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW122) Offset Value in Bytes */
+#define GMAC_ST2CW122_OFFSVAL(value) ((GMAC_ST2CW122_OFFSVAL_Msk & ((value) << GMAC_ST2CW122_OFFSVAL_Pos)))
+#define GMAC_ST2CW122_OFFSSTRT_Pos 7
+#define GMAC_ST2CW122_OFFSSTRT_Msk (0x3u << GMAC_ST2CW122_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW122) Ethernet Frame Offset Start */
+#define GMAC_ST2CW122_OFFSSTRT(value) ((GMAC_ST2CW122_OFFSSTRT_Msk & ((value) << GMAC_ST2CW122_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW122_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW122) Offset from the start of the frame */
+#define   GMAC_ST2CW122_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW122_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW122_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW122) Offset from the byte after the TCP/UDP header field */
+/* -------- GMAC_ST2CW023 : (GMAC Offset: 0x7B8) Screening Type 2 Compare Word 0 Register  (index = 23) -------- */
+#define GMAC_ST2CW023_MASKVAL_Pos 0
+#define GMAC_ST2CW023_MASKVAL_Msk (0xffffu << GMAC_ST2CW023_MASKVAL_Pos) /**< \brief (GMAC_ST2CW023) Mask Value */
+#define GMAC_ST2CW023_MASKVAL(value) ((GMAC_ST2CW023_MASKVAL_Msk & ((value) << GMAC_ST2CW023_MASKVAL_Pos)))
+#define GMAC_ST2CW023_COMPVAL_Pos 16
+#define GMAC_ST2CW023_COMPVAL_Msk (0xffffu << GMAC_ST2CW023_COMPVAL_Pos) /**< \brief (GMAC_ST2CW023) Compare Value */
+#define GMAC_ST2CW023_COMPVAL(value) ((GMAC_ST2CW023_COMPVAL_Msk & ((value) << GMAC_ST2CW023_COMPVAL_Pos)))
+/* -------- GMAC_ST2CW123 : (GMAC Offset: 0x7BC) Screening Type 2 Compare Word 1 Register  (index = 23) -------- */
+#define GMAC_ST2CW123_OFFSVAL_Pos 0
+#define GMAC_ST2CW123_OFFSVAL_Msk (0x7fu << GMAC_ST2CW123_OFFSVAL_Pos) /**< \brief (GMAC_ST2CW123) Offset Value in Bytes */
+#define GMAC_ST2CW123_OFFSVAL(value) ((GMAC_ST2CW123_OFFSVAL_Msk & ((value) << GMAC_ST2CW123_OFFSVAL_Pos)))
+#define GMAC_ST2CW123_OFFSSTRT_Pos 7
+#define GMAC_ST2CW123_OFFSSTRT_Msk (0x3u << GMAC_ST2CW123_OFFSSTRT_Pos) /**< \brief (GMAC_ST2CW123) Ethernet Frame Offset Start */
+#define GMAC_ST2CW123_OFFSSTRT(value) ((GMAC_ST2CW123_OFFSSTRT_Msk & ((value) << GMAC_ST2CW123_OFFSSTRT_Pos)))
+#define   GMAC_ST2CW123_OFFSSTRT_FRAMESTART (0x0u << 7) /**< \brief (GMAC_ST2CW123) Offset from the start of the frame */
+#define   GMAC_ST2CW123_OFFSSTRT_ETHERTYPE (0x1u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the EtherType field */
+#define   GMAC_ST2CW123_OFFSSTRT_IP (0x2u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the IP header field */
+#define   GMAC_ST2CW123_OFFSSTRT_TCP_UDP (0x3u << 7) /**< \brief (GMAC_ST2CW123) Offset from the byte after the TCP/UDP header field */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_GMAC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_i2sc.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_i2sc.h
new file mode 100644
index 000000000..2d66551a5
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_i2sc.h
@@ -0,0 +1,185 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_I2SC_COMPONENT_
+#define _SAMA5D2_I2SC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Inter-IC Sound Controller */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_I2SC Inter-IC Sound Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief I2sc hardware registers */
+typedef struct {
+  __O  uint32_t I2SC_CR;      /**< \brief (I2sc Offset: 0x00) Control Register */
+  __IO uint32_t I2SC_MR;      /**< \brief (I2sc Offset: 0x04) Mode Register */
+  __I  uint32_t I2SC_SR;      /**< \brief (I2sc Offset: 0x08) Status Register */
+  __O  uint32_t I2SC_SCR;     /**< \brief (I2sc Offset: 0x0C) Status Clear Register */
+  __O  uint32_t I2SC_SSR;     /**< \brief (I2sc Offset: 0x10) Status Set Register */
+  __O  uint32_t I2SC_IER;     /**< \brief (I2sc Offset: 0x14) Interrupt Enable Register */
+  __O  uint32_t I2SC_IDR;     /**< \brief (I2sc Offset: 0x18) Interrupt Disable Register */
+  __I  uint32_t I2SC_IMR;     /**< \brief (I2sc Offset: 0x1C) Interrupt Mask Register */
+  __I  uint32_t I2SC_RHR;     /**< \brief (I2sc Offset: 0x20) Receiver Holding Register */
+  __O  uint32_t I2SC_THR;     /**< \brief (I2sc Offset: 0x24) Transmitter Holding Register */
+  __I  uint32_t I2SC_VERSION; /**< \brief (I2sc Offset: 0x28) Version Register */
+} I2sc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- I2SC_CR : (I2SC Offset: 0x00) Control Register -------- */
+#define I2SC_CR_RXEN (0x1u << 0) /**< \brief (I2SC_CR) Receiver Enable */
+#define I2SC_CR_RXDIS (0x1u << 1) /**< \brief (I2SC_CR) Receiver Disable */
+#define I2SC_CR_CKEN (0x1u << 2) /**< \brief (I2SC_CR) Clocks Enable */
+#define I2SC_CR_CKDIS (0x1u << 3) /**< \brief (I2SC_CR) Clocks Disable */
+#define I2SC_CR_TXEN (0x1u << 4) /**< \brief (I2SC_CR) Transmitter Enable */
+#define I2SC_CR_TXDIS (0x1u << 5) /**< \brief (I2SC_CR) Transmitter Disable */
+#define I2SC_CR_SWRST (0x1u << 7) /**< \brief (I2SC_CR) Software Reset */
+/* -------- I2SC_MR : (I2SC Offset: 0x04) Mode Register -------- */
+#define I2SC_MR_MODE (0x1u << 0) /**< \brief (I2SC_MR) Inter-IC Sound Controller Mode */
+#define   I2SC_MR_MODE_SLAVE (0x0u << 0) /**< \brief (I2SC_MR) I2SCK and i2SWS pin inputs used as bit clock and word select/frame synchronization. */
+#define   I2SC_MR_MODE_MASTER (0x1u << 0) /**< \brief (I2SC_MR) Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SCK and I2SWS pins. MCK is output as master clock on I2SMCK if I2SC_MR.IMCKMODE is set. */
+#define I2SC_MR_DATALENGTH_Pos 2
+#define I2SC_MR_DATALENGTH_Msk (0x7u << I2SC_MR_DATALENGTH_Pos) /**< \brief (I2SC_MR) Data Word Length */
+#define I2SC_MR_DATALENGTH(value) ((I2SC_MR_DATALENGTH_Msk & ((value) << I2SC_MR_DATALENGTH_Pos)))
+#define   I2SC_MR_DATALENGTH_32_BITS (0x0u << 2) /**< \brief (I2SC_MR) Data length is set to 32 bits */
+#define   I2SC_MR_DATALENGTH_24_BITS (0x1u << 2) /**< \brief (I2SC_MR) Data length is set to 24 bits */
+#define   I2SC_MR_DATALENGTH_20_BITS (0x2u << 2) /**< \brief (I2SC_MR) Data length is set to 20 bits */
+#define   I2SC_MR_DATALENGTH_18_BITS (0x3u << 2) /**< \brief (I2SC_MR) Data length is set to 18 bits */
+#define   I2SC_MR_DATALENGTH_16_BITS (0x4u << 2) /**< \brief (I2SC_MR) Data length is set to 16 bits */
+#define   I2SC_MR_DATALENGTH_16_BITS_COMPACT (0x5u << 2) /**< \brief (I2SC_MR) Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word. */
+#define   I2SC_MR_DATALENGTH_8_BITS (0x6u << 2) /**< \brief (I2SC_MR) Data length is set to 8 bits */
+#define   I2SC_MR_DATALENGTH_8_BITS_COMPACT (0x7u << 2) /**< \brief (I2SC_MR) Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word. */
+#define I2SC_MR_FORMAT_Pos 6
+#define I2SC_MR_FORMAT_Msk (0x3u << I2SC_MR_FORMAT_Pos) /**< \brief (I2SC_MR) Data Format */
+#define I2SC_MR_FORMAT(value) ((I2SC_MR_FORMAT_Msk & ((value) << I2SC_MR_FORMAT_Pos)))
+#define   I2SC_MR_FORMAT_I2S (0x0u << 6) /**< \brief (I2SC_MR) I2S format, stereo with I2SWS low for left channel, and MSB of sample starting one I2SCK period after I2SWS edge */
+#define   I2SC_MR_FORMAT_LJ (0x1u << 6) /**< \brief (I2SC_MR) Left-justified format, stereo with I2SWS high for left channel, and MSB of sample starting on I2SWS edge */
+#define   I2SC_MR_FORMAT_TDM (0x2u << 6) /**< \brief (I2SC_MR) TDM format, with (NBCHAN + 1) channels, I2SWS high at beginning of first channel, and MSB of sample starting one ISCK period after I2SWS edge */
+#define   I2SC_MR_FORMAT_TDMLJ (0x3u << 6) /**< \brief (I2SC_MR) TDM format, left-justified, with (NBCHAN + 1) channels, I2SWS high at beginning of first channel, and MSB of sample starting on I2SWS edge */
+#define I2SC_MR_RXMONO (0x1u << 8) /**< \brief (I2SC_MR) Receive Mono */
+#define I2SC_MR_RXDMA (0x1u << 9) /**< \brief (I2SC_MR) Single or Multiple DMA Controller Channels for Receiver */
+#define I2SC_MR_RXLOOP (0x1u << 10) /**< \brief (I2SC_MR) Loop-back Test Mode */
+#define I2SC_MR_TXMONO (0x1u << 12) /**< \brief (I2SC_MR) Transmit Mono */
+#define I2SC_MR_TXDMA (0x1u << 13) /**< \brief (I2SC_MR) Single or Multiple DMA Controller Channels for Transmitter */
+#define I2SC_MR_TXSAME (0x1u << 14) /**< \brief (I2SC_MR) Transmit Data when Underrun */
+#define I2SC_MR_NBCHAN_Pos 16
+#define I2SC_MR_NBCHAN_Msk (0x7u << I2SC_MR_NBCHAN_Pos) /**< \brief (I2SC_MR) Number of TDM Channels-1 */
+#define I2SC_MR_NBCHAN(value) ((I2SC_MR_NBCHAN_Msk & ((value) << I2SC_MR_NBCHAN_Pos)))
+#define I2SC_MR_TDMFS_Pos 22
+#define I2SC_MR_TDMFS_Msk (0x3u << I2SC_MR_TDMFS_Pos) /**< \brief (I2SC_MR) TDM Frame Synchronization */
+#define I2SC_MR_TDMFS(value) ((I2SC_MR_TDMFS_Msk & ((value) << I2SC_MR_TDMFS_Pos)))
+#define   I2SC_MR_TDMFS_SLOT (0x0u << 22) /**< \brief (I2SC_MR) I2SWS pulse is high for one time slot at beginning of frame */
+#define   I2SC_MR_TDMFS_HALF (0x1u << 22) /**< \brief (I2SC_MR) I2SWS pulse is high for half the time slots at beginning of frame, i.e., half the IWS period */
+#define   I2SC_MR_TDMFS_BIT (0x2u << 22) /**< \brief (I2SC_MR) I2SWS pulse is high for one bit period at beginning of frame, i.e., one ISCK period */
+#define I2SC_MR_IMCKFS_Pos 24
+#define I2SC_MR_IMCKFS_Msk (0x3fu << I2SC_MR_IMCKFS_Pos) /**< \brief (I2SC_MR) Master Clock to fs Ratio */
+#define I2SC_MR_IMCKFS(value) ((I2SC_MR_IMCKFS_Msk & ((value) << I2SC_MR_IMCKFS_Pos)))
+#define   I2SC_MR_IMCKFS_M2SF32_64_96_128 (0x0u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 32 for two channels, set to 64 for 4 channels, set to 96 for 6 channels and set to 128 for 8 channels. */
+#define   I2SC_MR_IMCKFS_M2SF64_128_192_256 (0x1u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 64 for two channels, set to 128 for 4 channels, set to 192 for 6 channels and set to 256 for 8 channels. */
+#define   I2SC_MR_IMCKFS_M2SF96_192_384 (0x2u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 96 for two channels, set to 192 for 4 channels and set to 384 for 8 channels */
+#define   I2SC_MR_IMCKFS_M2SF128_256_384_512 (0x3u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 128 for two channels, set to 256 for 4 channels set to 384 for 6 channels and set to 512 for 8 channels. */
+#define   I2SC_MR_IMCKFS_M2SF192_384_768 (0x5u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 192 for two channels, set to 384 for 4 channels and set to 768 for 8 channels. */
+#define   I2SC_MR_IMCKFS_M2SF256_512_768_1024 (0x7u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 256 for two channels, set to 512 for 4 channels, set to 768 for 6 channels and set to 1024 for 8 channels. */
+#define   I2SC_MR_IMCKFS_M2SF384_768_1536 (0xBu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 384 for two channels, set to 768 for 4 channels and set to 1536 for 8 channels. */
+#define   I2SC_MR_IMCKFS_M2SF512_1024_1536_2048 (0xFu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 512 for two channels, set to 1024 for 4 channels, set to 1536 for 6 channels and set to 2048 for 8 channels. */
+#define   I2SC_MR_IMCKFS_M2SF768_1536 (0x17u << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 768 for two channels and set to 1536 for 4 channels. */
+#define   I2SC_MR_IMCKFS_M2SF1024_2048 (0x1Fu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 1024 for two channels and set to 2048 for 4 channels. */
+#define   I2SC_MR_IMCKFS_M2SF1536 (0x2Fu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 1536. */
+#define   I2SC_MR_IMCKFS_M2SF2048 (0x3Fu << 24) /**< \brief (I2SC_MR) Sample frequency ratio set to 2048. */
+#define I2SC_MR_IMCKMODE (0x1u << 30) /**< \brief (I2SC_MR) Master Clock Mode */
+#define I2SC_MR_IWS (0x1u << 31) /**< \brief (I2SC_MR) I2SWS Slot Width */
+/* -------- I2SC_SR : (I2SC Offset: 0x08) Status Register -------- */
+#define I2SC_SR_RXEN (0x1u << 0) /**< \brief (I2SC_SR) Receiver Enabled */
+#define I2SC_SR_RXRDY (0x1u << 1) /**< \brief (I2SC_SR) Receive Ready */
+#define I2SC_SR_RXOR (0x1u << 2) /**< \brief (I2SC_SR) Receive Overrun */
+#define I2SC_SR_TXEN (0x1u << 4) /**< \brief (I2SC_SR) Transmitter Enabled */
+#define I2SC_SR_TXRDY (0x1u << 5) /**< \brief (I2SC_SR) Transmit Ready */
+#define I2SC_SR_TXUR (0x1u << 6) /**< \brief (I2SC_SR) Transmit Underrun */
+#define I2SC_SR_RXORCH_Pos 8
+#define I2SC_SR_RXORCH_Msk (0xffu << I2SC_SR_RXORCH_Pos) /**< \brief (I2SC_SR) Receive Overrun Channel */
+#define I2SC_SR_TXURCH30_Pos 20
+#define I2SC_SR_TXURCH30_Msk (0xfu << I2SC_SR_TXURCH30_Pos) /**< \brief (I2SC_SR) Transmit Underrun Channel */
+#define I2SC_SR_TXURCH74_Pos 24
+#define I2SC_SR_TXURCH74_Msk (0xfu << I2SC_SR_TXURCH74_Pos) /**< \brief (I2SC_SR) Transmit Underrun Channel */
+/* -------- I2SC_SCR : (I2SC Offset: 0x0C) Status Clear Register -------- */
+#define I2SC_SCR_RXOR (0x1u << 2) /**< \brief (I2SC_SCR) Receive Overrun Status Clear */
+#define I2SC_SCR_TXUR (0x1u << 6) /**< \brief (I2SC_SCR) Transmit Underrun Status Clear */
+#define I2SC_SCR_RXORCH_Pos 8
+#define I2SC_SCR_RXORCH_Msk (0xffu << I2SC_SCR_RXORCH_Pos) /**< \brief (I2SC_SCR) Receive Overrun Per Channel Status Clear */
+#define I2SC_SCR_RXORCH(value) ((I2SC_SCR_RXORCH_Msk & ((value) << I2SC_SCR_RXORCH_Pos)))
+#define I2SC_SCR_TXURCH30_Pos 20
+#define I2SC_SCR_TXURCH30_Msk (0xfu << I2SC_SCR_TXURCH30_Pos) /**< \brief (I2SC_SCR) Transmit Underrun Per Channel for Channel 30 Status Clear */
+#define I2SC_SCR_TXURCH30(value) ((I2SC_SCR_TXURCH30_Msk & ((value) << I2SC_SCR_TXURCH30_Pos)))
+#define I2SC_SCR_TXURCH74_Pos 24
+#define I2SC_SCR_TXURCH74_Msk (0xfu << I2SC_SCR_TXURCH74_Pos) /**< \brief (I2SC_SCR) Transmit Underrun Per Channel for Channel 74 Status Clear */
+#define I2SC_SCR_TXURCH74(value) ((I2SC_SCR_TXURCH74_Msk & ((value) << I2SC_SCR_TXURCH74_Pos)))
+/* -------- I2SC_SSR : (I2SC Offset: 0x10) Status Set Register -------- */
+#define I2SC_SSR_RXOR (0x1u << 2) /**< \brief (I2SC_SSR) Receive Overrun Status Set */
+#define I2SC_SSR_TXUR (0x1u << 6) /**< \brief (I2SC_SSR) Transmit Underrun Status Set */
+#define I2SC_SSR_RXORCH_Pos 8
+#define I2SC_SSR_RXORCH_Msk (0xffu << I2SC_SSR_RXORCH_Pos) /**< \brief (I2SC_SSR) Receive Overrun Per Channel Status Set */
+#define I2SC_SSR_RXORCH(value) ((I2SC_SSR_RXORCH_Msk & ((value) << I2SC_SSR_RXORCH_Pos)))
+#define I2SC_SSR_TXURCH30_Pos 20
+#define I2SC_SSR_TXURCH30_Msk (0xfu << I2SC_SSR_TXURCH30_Pos) /**< \brief (I2SC_SSR) Transmit Underrun Per Channel for Channel 30 Status Set */
+#define I2SC_SSR_TXURCH30(value) ((I2SC_SSR_TXURCH30_Msk & ((value) << I2SC_SSR_TXURCH30_Pos)))
+#define I2SC_SSR_TXURCH74_Pos 24
+#define I2SC_SSR_TXURCH74_Msk (0xfu << I2SC_SSR_TXURCH74_Pos) /**< \brief (I2SC_SSR) Transmit Underrun Per Channel for Channel 74 Status Set */
+#define I2SC_SSR_TXURCH74(value) ((I2SC_SSR_TXURCH74_Msk & ((value) << I2SC_SSR_TXURCH74_Pos)))
+/* -------- I2SC_IER : (I2SC Offset: 0x14) Interrupt Enable Register -------- */
+#define I2SC_IER_RXRDY (0x1u << 1) /**< \brief (I2SC_IER) Receiver Ready Interrupt Enable */
+#define I2SC_IER_RXOR (0x1u << 2) /**< \brief (I2SC_IER) Receiver Overrun Interrupt Enable */
+#define I2SC_IER_TXRDY (0x1u << 5) /**< \brief (I2SC_IER) Transmit Ready Interrupt Enable */
+#define I2SC_IER_TXUR (0x1u << 6) /**< \brief (I2SC_IER) Transmit Underflow Interrupt Enable */
+/* -------- I2SC_IDR : (I2SC Offset: 0x18) Interrupt Disable Register -------- */
+#define I2SC_IDR_RXRDY (0x1u << 1) /**< \brief (I2SC_IDR) Receiver Ready Interrupt Disable */
+#define I2SC_IDR_RXOR (0x1u << 2) /**< \brief (I2SC_IDR) Receiver Overrun Interrupt Disable */
+#define I2SC_IDR_TXRDY (0x1u << 5) /**< \brief (I2SC_IDR) Transmit Ready Interrupt Disable */
+#define I2SC_IDR_TXUR (0x1u << 6) /**< \brief (I2SC_IDR) Transmit Underflow Interrupt Disable */
+/* -------- I2SC_IMR : (I2SC Offset: 0x1C) Interrupt Mask Register -------- */
+#define I2SC_IMR_RXRDY (0x1u << 1) /**< \brief (I2SC_IMR) Receiver Ready Interrupt Disable */
+#define I2SC_IMR_RXOR (0x1u << 2) /**< \brief (I2SC_IMR) Receiver Overrun Interrupt Disable */
+#define I2SC_IMR_TXRDY (0x1u << 5) /**< \brief (I2SC_IMR) Transmit Ready Interrupt Disable */
+#define I2SC_IMR_TXUR (0x1u << 6) /**< \brief (I2SC_IMR) Transmit Underflow Interrupt Disable */
+/* -------- I2SC_RHR : (I2SC Offset: 0x20) Receiver Holding Register -------- */
+#define I2SC_RHR_RHR_Pos 0
+#define I2SC_RHR_RHR_Msk (0xffffffffu << I2SC_RHR_RHR_Pos) /**< \brief (I2SC_RHR) Receiver Holding Register */
+/* -------- I2SC_THR : (I2SC Offset: 0x24) Transmitter Holding Register -------- */
+#define I2SC_THR_THR_Pos 0
+#define I2SC_THR_THR_Msk (0xffffffffu << I2SC_THR_THR_Pos) /**< \brief (I2SC_THR) Transmitter Holding Register */
+#define I2SC_THR_THR(value) ((I2SC_THR_THR_Msk & ((value) << I2SC_THR_THR_Pos)))
+/* -------- I2SC_VERSION : (I2SC Offset: 0x28) Version Register -------- */
+#define I2SC_VERSION_VERSION_Pos 0
+#define I2SC_VERSION_VERSION_Msk (0xfffu << I2SC_VERSION_VERSION_Pos) /**< \brief (I2SC_VERSION) Version of the Hardware Module */
+#define I2SC_VERSION_MFN_Pos 16
+#define I2SC_VERSION_MFN_Msk (0x7u << I2SC_VERSION_MFN_Pos) /**< \brief (I2SC_VERSION) Metal Fix Number */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_I2SC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_icm.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_icm.h
new file mode 100644
index 000000000..4adfc8e6c
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_icm.h
@@ -0,0 +1,226 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_ICM_COMPONENT_
+#define _SAMA5D2_ICM_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Integrity Check Monitor */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_ICM Integrity Check Monitor */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Icm hardware registers */
+typedef struct {
+  __IO uint32_t ICM_CFG;        /**< \brief (Icm Offset: 0x00) Configuration Register */
+  __O  uint32_t ICM_CTRL;       /**< \brief (Icm Offset: 0x04) Control Register */
+  __O  uint32_t ICM_SR;         /**< \brief (Icm Offset: 0x08) Status Register */
+  __I  uint32_t Reserved1[1];
+  __O  uint32_t ICM_IER;        /**< \brief (Icm Offset: 0x10) Interrupt Enable Register */
+  __O  uint32_t ICM_IDR;        /**< \brief (Icm Offset: 0x14) Interrupt Disable Register */
+  __I  uint32_t ICM_IMR;        /**< \brief (Icm Offset: 0x18) Interrupt Mask Register */
+  __I  uint32_t ICM_ISR;        /**< \brief (Icm Offset: 0x1C) Interrupt Status Register */
+  __I  uint32_t ICM_UASR;       /**< \brief (Icm Offset: 0x20) Undefined Access Status Register */
+  __I  uint32_t Reserved2[3];
+  __IO uint32_t ICM_DSCR;       /**< \brief (Icm Offset: 0x30) Region Descriptor Area Start Address Register */
+  __IO uint32_t ICM_HASH;       /**< \brief (Icm Offset: 0x34) Region Hash Area Start Address Register */
+  __O  uint32_t ICM_UIHVAL[16]; /**< \brief (Icm Offset: 0x38) User Initial Hash Value 0 Register */
+  __I  uint32_t Reserved3[29];
+  __I  uint32_t ICM_ADDRSIZE;   /**< \brief (Icm Offset: 0xEC) Address Size Register */
+  __I  uint32_t ICM_IPNAME[2];  /**< \brief (Icm Offset: 0xF0) IP Name 1 Register */
+  __I  uint32_t ICM_FEATURES;   /**< \brief (Icm Offset: 0xF8) Feature Register */
+  __I  uint32_t ICM_VERSION;    /**< \brief (Icm Offset: 0xFC) Version Register */
+} Icm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- ICM_CFG : (ICM Offset: 0x00) Configuration Register -------- */
+#define ICM_CFG_WBDIS (0x1u << 0) /**< \brief (ICM_CFG) Write Back Disable */
+#define ICM_CFG_EOMDIS (0x1u << 1) /**< \brief (ICM_CFG) End of Monitoring Disable */
+#define ICM_CFG_SLBDIS (0x1u << 2) /**< \brief (ICM_CFG) Secondary List Branching Disable */
+#define ICM_CFG_BBC_Pos 4
+#define ICM_CFG_BBC_Msk (0xfu << ICM_CFG_BBC_Pos) /**< \brief (ICM_CFG) Bus Burden Control */
+#define ICM_CFG_BBC(value) ((ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos)))
+#define ICM_CFG_ASCD (0x1u << 8) /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */
+#define ICM_CFG_DUALBUFF (0x1u << 9) /**< \brief (ICM_CFG) Dual Input Buffer */
+#define ICM_CFG_UIHASH (0x1u << 12) /**< \brief (ICM_CFG) User Initial Hash Value */
+#define ICM_CFG_UALGO_Pos 13
+#define ICM_CFG_UALGO_Msk (0x7u << ICM_CFG_UALGO_Pos) /**< \brief (ICM_CFG) User SHA Algorithm */
+#define ICM_CFG_UALGO(value) ((ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos)))
+#define   ICM_CFG_UALGO_SHA1 (0x0u << 13) /**< \brief (ICM_CFG) SHA1 algorithm processed */
+#define   ICM_CFG_UALGO_SHA256 (0x1u << 13) /**< \brief (ICM_CFG) SHA256 algorithm processed */
+#define   ICM_CFG_UALGO_SHA384 (0x2u << 13) /**< \brief (ICM_CFG) SHA384 algorithm processed */
+#define   ICM_CFG_UALGO_SHA512 (0x3u << 13) /**< \brief (ICM_CFG) SHA512 algorithm processed */
+#define   ICM_CFG_UALGO_SHA224 (0x4u << 13) /**< \brief (ICM_CFG) SHA224 algorithm processed */
+#define ICM_CFG_HAPROT_Pos 16
+#define ICM_CFG_HAPROT_Msk (0x3fu << ICM_CFG_HAPROT_Pos) /**< \brief (ICM_CFG) Region Hash Area Protection */
+#define ICM_CFG_HAPROT(value) ((ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos)))
+#define ICM_CFG_DAPROT_Pos 24
+#define ICM_CFG_DAPROT_Msk (0x3fu << ICM_CFG_DAPROT_Pos) /**< \brief (ICM_CFG) Region Descriptor Area Protection */
+#define ICM_CFG_DAPROT(value) ((ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos)))
+/* -------- ICM_CTRL : (ICM Offset: 0x04) Control Register -------- */
+#define ICM_CTRL_ENABLE (0x1u << 0) /**< \brief (ICM_CTRL) ICM Enable */
+#define ICM_CTRL_DISABLE (0x1u << 1) /**< \brief (ICM_CTRL) ICM Disable Register */
+#define ICM_CTRL_SWRST (0x1u << 2) /**< \brief (ICM_CTRL) Software Reset */
+#define ICM_CTRL_REHASH_Pos 4
+#define ICM_CTRL_REHASH_Msk (0xfu << ICM_CTRL_REHASH_Pos) /**< \brief (ICM_CTRL) Recompute Internal Hash */
+#define ICM_CTRL_REHASH(value) ((ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos)))
+#define ICM_CTRL_RMDIS_Pos 8
+#define ICM_CTRL_RMDIS_Msk (0xfu << ICM_CTRL_RMDIS_Pos) /**< \brief (ICM_CTRL) Region Monitoring Disable */
+#define ICM_CTRL_RMDIS(value) ((ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos)))
+#define ICM_CTRL_RMEN_Pos 12
+#define ICM_CTRL_RMEN_Msk (0xfu << ICM_CTRL_RMEN_Pos) /**< \brief (ICM_CTRL) Region Monitoring Enable */
+#define ICM_CTRL_RMEN(value) ((ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos)))
+/* -------- ICM_SR : (ICM Offset: 0x08) Status Register -------- */
+#define ICM_SR_ENABLE (0x1u << 0) /**< \brief (ICM_SR) ICM Controller Enable Register */
+#define ICM_SR_RAWRMDIS_Pos 8
+#define ICM_SR_RAWRMDIS_Msk (0xfu << ICM_SR_RAWRMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Raw Status */
+#define ICM_SR_RAWRMDIS(value) ((ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos)))
+#define ICM_SR_RMDIS_Pos 12
+#define ICM_SR_RMDIS_Msk (0xfu << ICM_SR_RMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Status */
+#define ICM_SR_RMDIS(value) ((ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos)))
+/* -------- ICM_IER : (ICM Offset: 0x10) Interrupt Enable Register -------- */
+#define ICM_IER_RHC_Pos 0
+#define ICM_IER_RHC_Msk (0xfu << ICM_IER_RHC_Pos) /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */
+#define ICM_IER_RHC(value) ((ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos)))
+#define ICM_IER_RDM_Pos 4
+#define ICM_IER_RDM_Msk (0xfu << ICM_IER_RDM_Pos) /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */
+#define ICM_IER_RDM(value) ((ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos)))
+#define ICM_IER_RBE_Pos 8
+#define ICM_IER_RBE_Msk (0xfu << ICM_IER_RBE_Pos) /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */
+#define ICM_IER_RBE(value) ((ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos)))
+#define ICM_IER_RWC_Pos 12
+#define ICM_IER_RWC_Msk (0xfu << ICM_IER_RWC_Pos) /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */
+#define ICM_IER_RWC(value) ((ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos)))
+#define ICM_IER_REC_Pos 16
+#define ICM_IER_REC_Msk (0xfu << ICM_IER_REC_Pos) /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */
+#define ICM_IER_REC(value) ((ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos)))
+#define ICM_IER_RSU_Pos 20
+#define ICM_IER_RSU_Msk (0xfu << ICM_IER_RSU_Pos) /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */
+#define ICM_IER_RSU(value) ((ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos)))
+#define ICM_IER_URAD (0x1u << 24) /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */
+/* -------- ICM_IDR : (ICM Offset: 0x14) Interrupt Disable Register -------- */
+#define ICM_IDR_RHC_Pos 0
+#define ICM_IDR_RHC_Msk (0xfu << ICM_IDR_RHC_Pos) /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */
+#define ICM_IDR_RHC(value) ((ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos)))
+#define ICM_IDR_RDM_Pos 4
+#define ICM_IDR_RDM_Msk (0xfu << ICM_IDR_RDM_Pos) /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */
+#define ICM_IDR_RDM(value) ((ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos)))
+#define ICM_IDR_RBE_Pos 8
+#define ICM_IDR_RBE_Msk (0xfu << ICM_IDR_RBE_Pos) /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */
+#define ICM_IDR_RBE(value) ((ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos)))
+#define ICM_IDR_RWC_Pos 12
+#define ICM_IDR_RWC_Msk (0xfu << ICM_IDR_RWC_Pos) /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */
+#define ICM_IDR_RWC(value) ((ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos)))
+#define ICM_IDR_REC_Pos 16
+#define ICM_IDR_REC_Msk (0xfu << ICM_IDR_REC_Pos) /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */
+#define ICM_IDR_REC(value) ((ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos)))
+#define ICM_IDR_RSU_Pos 20
+#define ICM_IDR_RSU_Msk (0xfu << ICM_IDR_RSU_Pos) /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */
+#define ICM_IDR_RSU(value) ((ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos)))
+#define ICM_IDR_URAD (0x1u << 24) /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */
+/* -------- ICM_IMR : (ICM Offset: 0x18) Interrupt Mask Register -------- */
+#define ICM_IMR_RHC_Pos 0
+#define ICM_IMR_RHC_Msk (0xfu << ICM_IMR_RHC_Pos) /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */
+#define ICM_IMR_RDM_Pos 4
+#define ICM_IMR_RDM_Msk (0xfu << ICM_IMR_RDM_Pos) /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */
+#define ICM_IMR_RBE_Pos 8
+#define ICM_IMR_RBE_Msk (0xfu << ICM_IMR_RBE_Pos) /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */
+#define ICM_IMR_RWC_Pos 12
+#define ICM_IMR_RWC_Msk (0xfu << ICM_IMR_RWC_Pos) /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */
+#define ICM_IMR_REC_Pos 16
+#define ICM_IMR_REC_Msk (0xfu << ICM_IMR_REC_Pos) /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */
+#define ICM_IMR_RSU_Pos 20
+#define ICM_IMR_RSU_Msk (0xfu << ICM_IMR_RSU_Pos) /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */
+#define ICM_IMR_URAD (0x1u << 24) /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */
+/* -------- ICM_ISR : (ICM Offset: 0x1C) Interrupt Status Register -------- */
+#define ICM_ISR_RHC_Pos 0
+#define ICM_ISR_RHC_Msk (0xfu << ICM_ISR_RHC_Pos) /**< \brief (ICM_ISR) Region Hash Completed */
+#define ICM_ISR_RDM_Pos 4
+#define ICM_ISR_RDM_Msk (0xfu << ICM_ISR_RDM_Pos) /**< \brief (ICM_ISR) Region Digest Mismatch */
+#define ICM_ISR_RBE_Pos 8
+#define ICM_ISR_RBE_Msk (0xfu << ICM_ISR_RBE_Pos) /**< \brief (ICM_ISR) Region Bus Error */
+#define ICM_ISR_RWC_Pos 12
+#define ICM_ISR_RWC_Msk (0xfu << ICM_ISR_RWC_Pos) /**< \brief (ICM_ISR) Region Wrap Condition Detected */
+#define ICM_ISR_REC_Pos 16
+#define ICM_ISR_REC_Msk (0xfu << ICM_ISR_REC_Pos) /**< \brief (ICM_ISR) Region End bit Condition Detected */
+#define ICM_ISR_RSU_Pos 20
+#define ICM_ISR_RSU_Msk (0xfu << ICM_ISR_RSU_Pos) /**< \brief (ICM_ISR) Region Status Updated Detected */
+#define ICM_ISR_URAD (0x1u << 24) /**< \brief (ICM_ISR) Undefined Register Access Detection Status */
+/* -------- ICM_UASR : (ICM Offset: 0x20) Undefined Access Status Register -------- */
+#define ICM_UASR_URAT_Pos 0
+#define ICM_UASR_URAT_Msk (0x7u << ICM_UASR_URAT_Pos) /**< \brief (ICM_UASR) Undefined Register Access Trace */
+#define   ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (0x0u << 0) /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */
+#define   ICM_UASR_URAT_ICM_CFG_MODIFIED (0x1u << 0) /**< \brief (ICM_UASR) ICM_CFG modified during active monitoring. */
+#define   ICM_UASR_URAT_ICM_DSCR_MODIFIED (0x2u << 0) /**< \brief (ICM_UASR) ICM_DSCR modified during active monitoring. */
+#define   ICM_UASR_URAT_ICM_HASH_MODIFIED (0x3u << 0) /**< \brief (ICM_UASR) ICM_HASH modified during active monitoring */
+#define   ICM_UASR_URAT_READ_ACCESS (0x4u << 0) /**< \brief (ICM_UASR) Write-only register read access */
+/* -------- ICM_DSCR : (ICM Offset: 0x30) Region Descriptor Area Start Address Register -------- */
+#define ICM_DSCR_DASA_Pos 6
+#define ICM_DSCR_DASA_Msk (0x3ffffffu << ICM_DSCR_DASA_Pos) /**< \brief (ICM_DSCR) Descriptor Area Start Address */
+#define ICM_DSCR_DASA(value) ((ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos)))
+/* -------- ICM_HASH : (ICM Offset: 0x34) Region Hash Area Start Address Register -------- */
+#define ICM_HASH_HASA_Pos 8
+#define ICM_HASH_HASA_Msk (0xffffffu << ICM_HASH_HASA_Pos) /**< \brief (ICM_HASH) Hash Area Start Address */
+#define ICM_HASH_HASA(value) ((ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos)))
+/* -------- ICM_UIHVAL[16] : (ICM Offset: 0x38) User Initial Hash Value 0 Register -------- */
+#define ICM_UIHVAL_VAL_Pos 0
+#define ICM_UIHVAL_VAL_Msk (0xffffffffu << ICM_UIHVAL_VAL_Pos) /**< \brief (ICM_UIHVAL[16]) Initial Hash Value */
+#define ICM_UIHVAL_VAL(value) ((ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos)))
+/* -------- ICM_ADDRSIZE : (ICM Offset: 0xEC) Address Size Register -------- */
+#define ICM_ADDRSIZE_ADDRSIZE_Pos 0
+#define ICM_ADDRSIZE_ADDRSIZE_Msk (0xffffu << ICM_ADDRSIZE_ADDRSIZE_Pos) /**< \brief (ICM_ADDRSIZE) Peripheral Bus Address Area Size */
+/* -------- ICM_IPNAME[2] : (ICM Offset: 0xF0) IP Name 1 Register -------- */
+#define ICM_IPNAME_IPNAME_Pos 0
+#define ICM_IPNAME_IPNAME_Msk (0xffffffffu << ICM_IPNAME_IPNAME_Pos) /**< \brief (ICM_IPNAME[2]) IP Name in ASCII Format */
+/* -------- ICM_FEATURES : (ICM Offset: 0xF8) Feature Register -------- */
+#define ICM_FEATURES_CFGALGO (0x1u << 0) /**< \brief (ICM_FEATURES) Configurable Algorithms */
+#define ICM_FEATURES_RFU (0x1u << 1) /**< \brief (ICM_FEATURES) Reserved for Future Use */
+#define ICM_FEATURES_CFGPP (0x1u << 2) /**< \brief (ICM_FEATURES) Configurable Processing Period */
+#define ICM_FEATURES_HDPP (0x1u << 3) /**< \brief (ICM_FEATURES) Hardcoded Processing Period */
+#define ICM_FEATURES_PDC (0x1u << 4) /**< \brief (ICM_FEATURES) Peripheral DMA Logic */
+#define ICM_FEATURES_NAIS (0x1u << 5) /**< \brief (ICM_FEATURES) No Access to Intermediate State */
+#define ICM_FEATURES_EF (0x1u << 6) /**< \brief (ICM_FEATURES) Embedded LFSR */
+#define ICM_FEATURES_SI (0x1u << 7) /**< \brief (ICM_FEATURES) Scan Intrusion */
+#define ICM_FEATURES_BTYP (0x1u << 8) /**< \brief (ICM_FEATURES) Bridge Type */
+#define ICM_FEATURES_PDCOFF0C (0x1u << 9) /**< \brief (ICM_FEATURES) PDC Offset is 0x0C */
+#define ICM_FEATURES_HSHA1 (0x1u << 16) /**< \brief (ICM_FEATURES) SHA1 Hardcoded Mode */
+#define ICM_FEATURES_HSHA224 (0x1u << 17) /**< \brief (ICM_FEATURES) SHA224 Hardcoded Mode */
+#define ICM_FEATURES_HSHA256 (0x1u << 18) /**< \brief (ICM_FEATURES) SHA256 Hardcoded Mode */
+#define ICM_FEATURES_HSHA384 (0x1u << 19) /**< \brief (ICM_FEATURES) SHA384 Hardcoded Mode */
+#define ICM_FEATURES_HSHA512 (0x1u << 20) /**< \brief (ICM_FEATURES) SHA512 Hardcoded Mode */
+/* -------- ICM_VERSION : (ICM Offset: 0xFC) Version Register -------- */
+#define ICM_VERSION_VERSION_Pos 0
+#define ICM_VERSION_VERSION_Msk (0xfffu << ICM_VERSION_VERSION_Pos) /**< \brief (ICM_VERSION) Version of the Hardware Module */
+#define ICM_VERSION_MFN_Pos 16
+#define ICM_VERSION_MFN_Msk (0x7u << ICM_VERSION_MFN_Pos) /**< \brief (ICM_VERSION) Metal Fix Number */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_ICM_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_isc.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_isc.h
new file mode 100644
index 000000000..f0a5575fb
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_isc.h
@@ -0,0 +1,568 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_ISC_COMPONENT_
+#define _SAMA5D2_ISC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Image Sensor Controller */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_ISC Image Sensor Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief IscSub0 hardware registers */
+typedef struct {
+  __IO uint32_t ISC_DAD; /**< \brief (IscSub0 Offset: 0x0) DMA Address 0 Register */
+  __IO uint32_t ISC_DST; /**< \brief (IscSub0 Offset: 0x4) DMA Stride 0 Register */
+} IscSub0;
+/** \brief Isc hardware registers */
+#define ISCSUB0_NUMBER 3
+typedef struct {
+  __O  uint32_t ISC_CTRLEN;               /**< \brief (Isc Offset: 0x00) Control Enable Register */
+  __O  uint32_t ISC_CTRLDIS;              /**< \brief (Isc Offset: 0x04) Control Disable Register */
+  __I  uint32_t ISC_CTRLSR;               /**< \brief (Isc Offset: 0x08) Control Status Register */
+  __IO uint32_t ISC_PFE_CFG0;             /**< \brief (Isc Offset: 0x0C) Parallel Front End Configuration 0 Register */
+  __IO uint32_t ISC_PFE_CFG1;             /**< \brief (Isc Offset: 0x10) Parallel Front End Configuration 1 Register */
+  __IO uint32_t ISC_PFE_CFG2;             /**< \brief (Isc Offset: 0x14) Parallel Front End Configuration 2 Register */
+  __O  uint32_t ISC_CLKEN;                /**< \brief (Isc Offset: 0x18) Clock Enable Register */
+  __O  uint32_t ISC_CLKDIS;               /**< \brief (Isc Offset: 0x1C) Clock Disable Register */
+  __I  uint32_t ISC_CLKSR;                /**< \brief (Isc Offset: 0x20) Clock Status Register */
+  __IO uint32_t ISC_CLKCFG;               /**< \brief (Isc Offset: 0x24) Clock Configuration Register */
+  __O  uint32_t ISC_INTEN;                /**< \brief (Isc Offset: 0x28) Interrupt Enable Register */
+  __O  uint32_t ISC_INTDIS;               /**< \brief (Isc Offset: 0x2C) Interrupt Disable Register */
+  __I  uint32_t ISC_INTMASK;              /**< \brief (Isc Offset: 0x30) Interrupt Mask Register */
+  __I  uint32_t ISC_INTSR;                /**< \brief (Isc Offset: 0x34) Interrupt Status Register */
+  __I  uint32_t Reserved1[8];
+  __IO uint32_t ISC_WB_CTRL;              /**< \brief (Isc Offset: 0x58) White Balance Control Register */
+  __IO uint32_t ISC_WB_CFG;               /**< \brief (Isc Offset: 0x5C) White Balance Configuration Register */
+  __IO uint32_t ISC_WB_O_RGR;             /**< \brief (Isc Offset: 0x60) White Balance Offset for R, GR Register */
+  __IO uint32_t ISC_WB_O_BGB;             /**< \brief (Isc Offset: 0x64) White Balance Offset for B, GB Register */
+  __IO uint32_t ISC_WB_G_RGR;             /**< \brief (Isc Offset: 0x68) White Balance Gain for R, GR Register */
+  __IO uint32_t ISC_WB_G_BGB;             /**< \brief (Isc Offset: 0x6C) White Balance Gain for B, GB Register */
+  __IO uint32_t ISC_CFA_CTRL;             /**< \brief (Isc Offset: 0x70) Color Filter Array Control Register */
+  __IO uint32_t ISC_CFA_CFG;              /**< \brief (Isc Offset: 0x74) Color Filter Array Configuration Register */
+  __IO uint32_t ISC_CC_CTRL;              /**< \brief (Isc Offset: 0x78) Color Correction Control Register */
+  __IO uint32_t ISC_CC_RR_RG;             /**< \brief (Isc Offset: 0x7C) Color Correction RR RG Register */
+  __IO uint32_t ISC_CC_RB_OR;             /**< \brief (Isc Offset: 0x80) Color Correction RB OR Register */
+  __IO uint32_t ISC_CC_GR_GG;             /**< \brief (Isc Offset: 0x84) Color Correction GR GG Register */
+  __IO uint32_t ISC_CC_GB_OG;             /**< \brief (Isc Offset: 0x88) Color Correction GB OG Register */
+  __IO uint32_t ISC_CC_BR_BG;             /**< \brief (Isc Offset: 0x8C) Color Correction BR BG Register */
+  __IO uint32_t ISC_CC_BB_OB;             /**< \brief (Isc Offset: 0x90) Color Correction BB OB Register */
+  __IO uint32_t ISC_GAM_CTRL;             /**< \brief (Isc Offset: 0x94) Gamma Correction Control Register */
+  __IO uint32_t ISC_GAM_BENTRY[64];       /**< \brief (Isc Offset: 0x98) Gamma Correction Blue Entry */
+  __IO uint32_t ISC_GAM_GENTRY[64];       /**< \brief (Isc Offset: 0x198) Gamma Correction Green Entry */
+  __IO uint32_t ISC_GAM_RENTRY[64];       /**< \brief (Isc Offset: 0x298) Gamma Correction Red Entry */
+  __IO uint32_t ISC_CSC_CTRL;             /**< \brief (Isc Offset: 0x398) Color Space Conversion Control Register */
+  __IO uint32_t ISC_CSC_YR_YG;            /**< \brief (Isc Offset: 0x39C) Color Space Conversion YR, YG Register */
+  __IO uint32_t ISC_CSC_YB_OY;            /**< \brief (Isc Offset: 0x3A0) Color Space Conversion YB, OY Register */
+  __IO uint32_t ISC_CSC_CBR_CBG;          /**< \brief (Isc Offset: 0x3A4) Color Space Conversion CBR CBG Register */
+  __IO uint32_t ISC_CSC_CBB_OCB;          /**< \brief (Isc Offset: 0x3A8) Color Space Conversion CBB OCB Register */
+  __IO uint32_t ISC_CSC_CRR_CRG;          /**< \brief (Isc Offset: 0x3AC) Color Space Conversion CRR CRG Register */
+  __IO uint32_t ISC_CSC_CRB_OCR;          /**< \brief (Isc Offset: 0x3B0) Color Space Conversion CRB OCR Register */
+  __IO uint32_t ISC_CBC_CTRL;             /**< \brief (Isc Offset: 0x3B4) Contrast and Brightness Control Register */
+  __IO uint32_t ISC_CBC_CFG;              /**< \brief (Isc Offset: 0x3B8) Contrast and Brightness Configuration Register */
+  __IO uint32_t ISC_CBC_BRIGHT;           /**< \brief (Isc Offset: 0x3BC) Contrast and Brightness, Brightness Register */
+  __IO uint32_t ISC_CBC_CONTRAST;         /**< \brief (Isc Offset: 0x3C0) Contrast and Brightness, Contrast Register */
+  __IO uint32_t ISC_SUB422_CTRL;          /**< \brief (Isc Offset: 0x3C4) Subsampling 4:4:4 to 4:2:2 Control Register */
+  __IO uint32_t ISC_SUB422_CFG;           /**< \brief (Isc Offset: 0x3C8) Subsampling 4:4:4 to 4:2:2 Configuration Register */
+  __IO uint32_t ISC_SUB420_CTRL;          /**< \brief (Isc Offset: 0x3CC) Subsampling 4:2:2 to 4:2:0 Control Register */
+  __IO uint32_t ISC_RLP_CFG;              /**< \brief (Isc Offset: 0x3D0) Rounding, Limiting and Packing Config Register */
+  __IO uint32_t ISC_HIS_CTRL;             /**< \brief (Isc Offset: 0x3D4) Histogram Control Register */
+  __IO uint32_t ISC_HIS_CFG;              /**< \brief (Isc Offset: 0x3D8) Histogram Configuration Register */
+  __I  uint32_t Reserved2[1];
+  __IO uint32_t ISC_DCFG;                 /**< \brief (Isc Offset: 0x3E0) DMA Configuration Register */
+  __IO uint32_t ISC_DCTRL;                /**< \brief (Isc Offset: 0x3E4) DMA Control Register */
+  __IO uint32_t ISC_DNDA;                 /**< \brief (Isc Offset: 0x3E8) DMA Descriptor Address Register */
+       IscSub0  ISC_SUB0[ISCSUB0_NUMBER]; /**< \brief (Isc Offset: 0x3EC) 0 .. 2 */
+  __I  uint32_t Reserved3[2];
+  __I  uint32_t IPB_VERSION;              /**< \brief (Isc Offset: 0x40C) Version Register */
+  __I  uint32_t ISC_HIS_ENTRY[512];       /**< \brief (Isc Offset: 0x410) Histogram Entry */
+} Isc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- ISC_CTRLEN : (ISC Offset: 0x00) Control Enable Register -------- */
+#define ISC_CTRLEN_CAPTURE (0x1u << 0) /**< \brief (ISC_CTRLEN) Capture Input Stream Command */
+#define ISC_CTRLEN_UPPRO (0x1u << 1) /**< \brief (ISC_CTRLEN) Update Profile */
+#define ISC_CTRLEN_HISREQ (0x1u << 2) /**< \brief (ISC_CTRLEN) Histogram Request */
+#define ISC_CTRLEN_HISCLR (0x1u << 3) /**< \brief (ISC_CTRLEN) Histogram Clear */
+/* -------- ISC_CTRLDIS : (ISC Offset: 0x04) Control Disable Register -------- */
+#define ISC_CTRLDIS_DISABLE (0x1u << 0) /**< \brief (ISC_CTRLDIS) Capture Disable */
+#define ISC_CTRLDIS_SWRST (0x1u << 8) /**< \brief (ISC_CTRLDIS) Software Reset */
+/* -------- ISC_CTRLSR : (ISC Offset: 0x08) Control Status Register -------- */
+#define ISC_CTRLSR_CAPTURE (0x1u << 0) /**< \brief (ISC_CTRLSR) Capture pending */
+#define ISC_CTRLSR_UPPRO (0x1u << 1) /**< \brief (ISC_CTRLSR) Profile Update Pending */
+#define ISC_CTRLSR_HISREQ (0x1u << 2) /**< \brief (ISC_CTRLSR) Histogram Request Pending */
+#define ISC_CTRLSR_FIELD (0x1u << 4) /**< \brief (ISC_CTRLSR) Field Status (only relevant when the video stream is interlaced) */
+#define ISC_CTRLSR_SIP (0x1u << 31) /**< \brief (ISC_CTRLSR) Synchronization In Progress */
+/* -------- ISC_PFE_CFG0 : (ISC Offset: 0x0C) Parallel Front End Configuration 0 Register -------- */
+#define ISC_PFE_CFG0_HPOL (0x1u << 0) /**< \brief (ISC_PFE_CFG0) Horizontal Synchronization Polarity */
+#define ISC_PFE_CFG0_VPOL (0x1u << 1) /**< \brief (ISC_PFE_CFG0) Vertical Synchronization Polarity */
+#define ISC_PFE_CFG0_PPOL (0x1u << 2) /**< \brief (ISC_PFE_CFG0) Pixel Clock Polarity */
+#define ISC_PFE_CFG0_FPOL (0x1u << 3) /**< \brief (ISC_PFE_CFG0) Field Polarity */
+#define ISC_PFE_CFG0_MODE_Pos 4
+#define ISC_PFE_CFG0_MODE_Msk (0x7u << ISC_PFE_CFG0_MODE_Pos) /**< \brief (ISC_PFE_CFG0) Parallel Front End Mode */
+#define ISC_PFE_CFG0_MODE(value) ((ISC_PFE_CFG0_MODE_Msk & ((value) << ISC_PFE_CFG0_MODE_Pos)))
+#define   ISC_PFE_CFG0_MODE_PROGRESSIVE (0x0u << 4) /**< \brief (ISC_PFE_CFG0) Video source is progressive. */
+#define   ISC_PFE_CFG0_MODE_DF_TOP (0x1u << 4) /**< \brief (ISC_PFE_CFG0) Video source is interlaced, two fields are captured starting with top field. */
+#define   ISC_PFE_CFG0_MODE_DF_BOTTOM (0x2u << 4) /**< \brief (ISC_PFE_CFG0) Video source is interlaced, two fields are captured starting with bottom field. */
+#define   ISC_PFE_CFG0_MODE_DF_IMMEDIATE (0x3u << 4) /**< \brief (ISC_PFE_CFG0) Video source is interlaced, two fields are captured immediately. */
+#define   ISC_PFE_CFG0_MODE_SF_TOP (0x4u << 4) /**< \brief (ISC_PFE_CFG0) Video source is interlaced, one field is captured starting with the top field. */
+#define   ISC_PFE_CFG0_MODE_SF_BOTTOM (0x5u << 4) /**< \brief (ISC_PFE_CFG0) Video source is interlaced, one field is captured starting with the bottom field. */
+#define   ISC_PFE_CFG0_MODE_SF_IMMEDIATE (0x6u << 4) /**< \brief (ISC_PFE_CFG0) Video source is interlaced, one field is captured starting immediately. */
+#define ISC_PFE_CFG0_CONT (0x1u << 7) /**< \brief (ISC_PFE_CFG0) Continuous Acquisition */
+#define ISC_PFE_CFG0_GATED (0x1u << 8) /**< \brief (ISC_PFE_CFG0) Gated input clock */
+#define ISC_PFE_CFG0_CCIR656 (0x1u << 9) /**< \brief (ISC_PFE_CFG0) CCIR656 input mode */
+#define ISC_PFE_CFG0_CCIR_CRC (0x1u << 10) /**< \brief (ISC_PFE_CFG0) CCIR656 CRC Decoder */
+#define ISC_PFE_CFG0_CCIR10_8N (0x1u << 11) /**< \brief (ISC_PFE_CFG0) CCIR 10 bits or 8 bits */
+#define ISC_PFE_CFG0_COLEN (0x1u << 12) /**< \brief (ISC_PFE_CFG0) Column Cropping Enable */
+#define ISC_PFE_CFG0_ROWEN (0x1u << 13) /**< \brief (ISC_PFE_CFG0) Row Cropping Enable */
+#define ISC_PFE_CFG0_SKIPCNT_Pos 16
+#define ISC_PFE_CFG0_SKIPCNT_Msk (0xffu << ISC_PFE_CFG0_SKIPCNT_Pos) /**< \brief (ISC_PFE_CFG0) Frame Skipping Counter */
+#define ISC_PFE_CFG0_SKIPCNT(value) ((ISC_PFE_CFG0_SKIPCNT_Msk & ((value) << ISC_PFE_CFG0_SKIPCNT_Pos)))
+#define ISC_PFE_CFG0_CCIR_REP (0x1u << 27) /**< \brief (ISC_PFE_CFG0) CCIR Replication */
+#define ISC_PFE_CFG0_BPS_Pos 28
+#define ISC_PFE_CFG0_BPS_Msk (0x7u << ISC_PFE_CFG0_BPS_Pos) /**< \brief (ISC_PFE_CFG0) Bits Per Sample */
+#define ISC_PFE_CFG0_BPS(value) ((ISC_PFE_CFG0_BPS_Msk & ((value) << ISC_PFE_CFG0_BPS_Pos)))
+#define   ISC_PFE_CFG0_BPS_TWELVE (0x0u << 28) /**< \brief (ISC_PFE_CFG0) 12-bit input */
+#define   ISC_PFE_CFG0_BPS_ELEVEN (0x1u << 28) /**< \brief (ISC_PFE_CFG0) 11-bit input */
+#define   ISC_PFE_CFG0_BPS_TEN (0x2u << 28) /**< \brief (ISC_PFE_CFG0) 10-bit input */
+#define   ISC_PFE_CFG0_BPS_NINE (0x3u << 28) /**< \brief (ISC_PFE_CFG0) 9-bit input */
+#define   ISC_PFE_CFG0_BPS_EIGHT (0x4u << 28) /**< \brief (ISC_PFE_CFG0) 8-bit input */
+#define ISC_PFE_CFG0_REP (0x1u << 31) /**< \brief (ISC_PFE_CFG0) Up Multiply with Replication */
+/* -------- ISC_PFE_CFG1 : (ISC Offset: 0x10) Parallel Front End Configuration 1 Register -------- */
+#define ISC_PFE_CFG1_COLMIN_Pos 0
+#define ISC_PFE_CFG1_COLMIN_Msk (0xffffu << ISC_PFE_CFG1_COLMIN_Pos) /**< \brief (ISC_PFE_CFG1) Column Minimum Limit */
+#define ISC_PFE_CFG1_COLMIN(value) ((ISC_PFE_CFG1_COLMIN_Msk & ((value) << ISC_PFE_CFG1_COLMIN_Pos)))
+#define ISC_PFE_CFG1_COLMAX_Pos 16
+#define ISC_PFE_CFG1_COLMAX_Msk (0xffffu << ISC_PFE_CFG1_COLMAX_Pos) /**< \brief (ISC_PFE_CFG1) Column Maximum Limit */
+#define ISC_PFE_CFG1_COLMAX(value) ((ISC_PFE_CFG1_COLMAX_Msk & ((value) << ISC_PFE_CFG1_COLMAX_Pos)))
+/* -------- ISC_PFE_CFG2 : (ISC Offset: 0x14) Parallel Front End Configuration 2 Register -------- */
+#define ISC_PFE_CFG2_ROWMIN_Pos 0
+#define ISC_PFE_CFG2_ROWMIN_Msk (0xffffu << ISC_PFE_CFG2_ROWMIN_Pos) /**< \brief (ISC_PFE_CFG2) Row Minimum Limit */
+#define ISC_PFE_CFG2_ROWMIN(value) ((ISC_PFE_CFG2_ROWMIN_Msk & ((value) << ISC_PFE_CFG2_ROWMIN_Pos)))
+#define ISC_PFE_CFG2_ROWMAX_Pos 16
+#define ISC_PFE_CFG2_ROWMAX_Msk (0xffffu << ISC_PFE_CFG2_ROWMAX_Pos) /**< \brief (ISC_PFE_CFG2) Row Maximum Limit */
+#define ISC_PFE_CFG2_ROWMAX(value) ((ISC_PFE_CFG2_ROWMAX_Msk & ((value) << ISC_PFE_CFG2_ROWMAX_Pos)))
+/* -------- ISC_CLKEN : (ISC Offset: 0x18) Clock Enable Register -------- */
+#define ISC_CLKEN_ICEN (0x1u << 0) /**< \brief (ISC_CLKEN) ISP Clock Enable */
+#define ISC_CLKEN_MCEN (0x1u << 1) /**< \brief (ISC_CLKEN) Master Clock Enable */
+/* -------- ISC_CLKDIS : (ISC Offset: 0x1C) Clock Disable Register -------- */
+#define ISC_CLKDIS_ICDIS (0x1u << 0) /**< \brief (ISC_CLKDIS) ISP Clock Disable */
+#define ISC_CLKDIS_MCDIS (0x1u << 1) /**< \brief (ISC_CLKDIS) Master Clock Disable */
+#define ISC_CLKDIS_ICSWRST (0x1u << 8) /**< \brief (ISC_CLKDIS) ISP Clock Software Reset */
+#define ISC_CLKDIS_MCSWRST (0x1u << 9) /**< \brief (ISC_CLKDIS) Master Clock Software Reset */
+/* -------- ISC_CLKSR : (ISC Offset: 0x20) Clock Status Register -------- */
+#define ISC_CLKSR_ICSR (0x1u << 0) /**< \brief (ISC_CLKSR) ISP Clock Status Register */
+#define ISC_CLKSR_MCSR (0x1u << 1) /**< \brief (ISC_CLKSR) Master Clock Status Register */
+#define ISC_CLKSR_SIP (0x1u << 31) /**< \brief (ISC_CLKSR) Synchronization In Progress */
+/* -------- ISC_CLKCFG : (ISC Offset: 0x24) Clock Configuration Register -------- */
+#define ISC_CLKCFG_ICDIV_Pos 0
+#define ISC_CLKCFG_ICDIV_Msk (0xffu << ISC_CLKCFG_ICDIV_Pos) /**< \brief (ISC_CLKCFG) ISP Clock Divider */
+#define ISC_CLKCFG_ICDIV(value) ((ISC_CLKCFG_ICDIV_Msk & ((value) << ISC_CLKCFG_ICDIV_Pos)))
+#define ISC_CLKCFG_ICSEL (0x1u << 8) /**< \brief (ISC_CLKCFG) ISP Clock Selection */
+#define ISC_CLKCFG_MCDIV_Pos 16
+#define ISC_CLKCFG_MCDIV_Msk (0xffu << ISC_CLKCFG_MCDIV_Pos) /**< \brief (ISC_CLKCFG) Master Clock Divider */
+#define ISC_CLKCFG_MCDIV(value) ((ISC_CLKCFG_MCDIV_Msk & ((value) << ISC_CLKCFG_MCDIV_Pos)))
+#define ISC_CLKCFG_MCSEL_Pos 24
+#define ISC_CLKCFG_MCSEL_Msk (0x3u << ISC_CLKCFG_MCSEL_Pos) /**< \brief (ISC_CLKCFG) Master Clock Reference Clock Selection */
+#define ISC_CLKCFG_MCSEL(value) ((ISC_CLKCFG_MCSEL_Msk & ((value) << ISC_CLKCFG_MCSEL_Pos)))
+/* -------- ISC_INTEN : (ISC Offset: 0x28) Interrupt Enable Register -------- */
+#define ISC_INTEN_VD (0x1u << 0) /**< \brief (ISC_INTEN) Vertical Synchronization Detection Interrupt Enable */
+#define ISC_INTEN_HD (0x1u << 1) /**< \brief (ISC_INTEN) Horizontal Synchronization Detection Interrupt Enable */
+#define ISC_INTEN_SWRST (0x1u << 4) /**< \brief (ISC_INTEN) Software Reset Completed Interrupt Enable */
+#define ISC_INTEN_DIS (0x1u << 5) /**< \brief (ISC_INTEN) Disable Completed Interrupt Enable */
+#define ISC_INTEN_DDONE (0x1u << 8) /**< \brief (ISC_INTEN) DMA Done Interrupt Enable */
+#define ISC_INTEN_LDONE (0x1u << 9) /**< \brief (ISC_INTEN) DMA List Done Interrupt Enable */
+#define ISC_INTEN_HISDONE (0x1u << 12) /**< \brief (ISC_INTEN) Histogram Completed Interrupt Enable */
+#define ISC_INTEN_HISCLR (0x1u << 13) /**< \brief (ISC_INTEN) Histogram Clear Interrupt Enable */
+#define ISC_INTEN_WERR (0x1u << 16) /**< \brief (ISC_INTEN) Write Channel Error Interrupt Enable */
+#define ISC_INTEN_RERR (0x1u << 20) /**< \brief (ISC_INTEN) Read Channel Error Interrupt Enable */
+#define ISC_INTEN_VFPOV (0x1u << 24) /**< \brief (ISC_INTEN) Vertical Front Porch Overflow Interrupt Enable */
+#define ISC_INTEN_DAOV (0x1u << 25) /**< \brief (ISC_INTEN) Data Overflow Interrupt Enable */
+#define ISC_INTEN_VDTO (0x1u << 26) /**< \brief (ISC_INTEN) Vertical Synchronization Timeout Interrupt Enable */
+#define ISC_INTEN_HDTO (0x1u << 27) /**< \brief (ISC_INTEN) Horizontal Synchronization Timeout Interrupt Enable */
+#define ISC_INTEN_CCIRERR (0x1u << 28) /**< \brief (ISC_INTEN) CCIR Decoder Error Interrupt Enable */
+/* -------- ISC_INTDIS : (ISC Offset: 0x2C) Interrupt Disable Register -------- */
+#define ISC_INTDIS_VD (0x1u << 0) /**< \brief (ISC_INTDIS) Vertical Synchronization Detection Interrupt Disable */
+#define ISC_INTDIS_HD (0x1u << 1) /**< \brief (ISC_INTDIS) Horizontal Synchronization Detection Interrupt Disable */
+#define ISC_INTDIS_SWRST (0x1u << 4) /**< \brief (ISC_INTDIS) Software Reset Completed Interrupt Disable */
+#define ISC_INTDIS_DIS (0x1u << 5) /**< \brief (ISC_INTDIS) Disable Completed Interrupt Disable */
+#define ISC_INTDIS_DDONE (0x1u << 8) /**< \brief (ISC_INTDIS) DMA Done Interrupt Disable */
+#define ISC_INTDIS_LDONE (0x1u << 9) /**< \brief (ISC_INTDIS) DMA List Done Interrupt Disable */
+#define ISC_INTDIS_HISDONE (0x1u << 12) /**< \brief (ISC_INTDIS) Histogram Completed Interrupt Disable */
+#define ISC_INTDIS_HISCLR (0x1u << 13) /**< \brief (ISC_INTDIS) Histogram Clear Interrupt Disable */
+#define ISC_INTDIS_WERR (0x1u << 16) /**< \brief (ISC_INTDIS) Write Channel Error Interrupt Disable */
+#define ISC_INTDIS_RERR (0x1u << 20) /**< \brief (ISC_INTDIS) Read Channel Error Interrupt Disable */
+#define ISC_INTDIS_VFPOV (0x1u << 24) /**< \brief (ISC_INTDIS) Vertical Front Porch Overflow Interrupt Disable */
+#define ISC_INTDIS_DAOV (0x1u << 25) /**< \brief (ISC_INTDIS) Data Overflow Interrupt Disable */
+#define ISC_INTDIS_VDTO (0x1u << 26) /**< \brief (ISC_INTDIS) Vertical Synchronization Timeout Interrupt Disable */
+#define ISC_INTDIS_HDTO (0x1u << 27) /**< \brief (ISC_INTDIS) Horizontal Synchronization Timeout Interrupt Disable */
+#define ISC_INTDIS_CCIRERR (0x1u << 28) /**< \brief (ISC_INTDIS) CCIR Decoder Error Interrupt Disable */
+/* -------- ISC_INTMASK : (ISC Offset: 0x30) Interrupt Mask Register -------- */
+#define ISC_INTMASK_VD (0x1u << 0) /**< \brief (ISC_INTMASK) Vertical Synchronization Detection Interrupt Mask */
+#define ISC_INTMASK_HD (0x1u << 1) /**< \brief (ISC_INTMASK) Horizontal Synchronization Detection Interrupt Mask */
+#define ISC_INTMASK_SWRST (0x1u << 4) /**< \brief (ISC_INTMASK) Software Reset Completed Interrupt Mask */
+#define ISC_INTMASK_DIS (0x1u << 5) /**< \brief (ISC_INTMASK) Disable Completed Interrupt Mask */
+#define ISC_INTMASK_DDONE (0x1u << 8) /**< \brief (ISC_INTMASK) DMA Done Interrupt Mask */
+#define ISC_INTMASK_LDONE (0x1u << 9) /**< \brief (ISC_INTMASK) DMA List Done Interrupt Mask */
+#define ISC_INTMASK_HISDONE (0x1u << 12) /**< \brief (ISC_INTMASK) Histogram Completed Interrupt Mask */
+#define ISC_INTMASK_HISCLR (0x1u << 13) /**< \brief (ISC_INTMASK) Histogram Clear Interrupt Mask */
+#define ISC_INTMASK_WERR (0x1u << 16) /**< \brief (ISC_INTMASK) Write Channel Error Interrupt Mask */
+#define ISC_INTMASK_RERR (0x1u << 20) /**< \brief (ISC_INTMASK) Read Channel Error Interrupt Mask */
+#define ISC_INTMASK_VFPOV (0x1u << 24) /**< \brief (ISC_INTMASK) Vertical Front Porch Overflow Interrupt Mask */
+#define ISC_INTMASK_DAOV (0x1u << 25) /**< \brief (ISC_INTMASK) Data Overflow Interrupt Mask */
+#define ISC_INTMASK_VDTO (0x1u << 26) /**< \brief (ISC_INTMASK) Vertical Synchronization Timeout Interrupt Mask */
+#define ISC_INTMASK_HDTO (0x1u << 27) /**< \brief (ISC_INTMASK) Horizontal Synchronization Timeout Interrupt Mask */
+#define ISC_INTMASK_CCIRERR (0x1u << 28) /**< \brief (ISC_INTMASK) CCIR Decoder Error Interrupt Mask */
+/* -------- ISC_INTSR : (ISC Offset: 0x34) Interrupt Status Register -------- */
+#define ISC_INTSR_VD (0x1u << 0) /**< \brief (ISC_INTSR) Vertical Synchronization Detected Interrupt */
+#define ISC_INTSR_HD (0x1u << 1) /**< \brief (ISC_INTSR) Horizontal Synchronization Detected Interrupt */
+#define ISC_INTSR_SWRST (0x1u << 4) /**< \brief (ISC_INTSR) Software Reset Completed Interrupt */
+#define ISC_INTSR_DIS (0x1u << 5) /**< \brief (ISC_INTSR) Disable Completed Interrupt */
+#define ISC_INTSR_DDONE (0x1u << 8) /**< \brief (ISC_INTSR) DMA Done Interrupt */
+#define ISC_INTSR_LDONE (0x1u << 9) /**< \brief (ISC_INTSR) DMA List Done Interrupt */
+#define ISC_INTSR_HISDONE (0x1u << 12) /**< \brief (ISC_INTSR) Histogram Completed Interrupt */
+#define ISC_INTSR_HISCLR (0x1u << 13) /**< \brief (ISC_INTSR) Histogram Clear Interrupt */
+#define ISC_INTSR_WERR (0x1u << 16) /**< \brief (ISC_INTSR) Write Channel Error Interrupt */
+#define ISC_INTSR_WERRID_Pos 17
+#define ISC_INTSR_WERRID_Msk (0x3u << ISC_INTSR_WERRID_Pos) /**< \brief (ISC_INTSR) Write Channel Error Identifier */
+#define   ISC_INTSR_WERRID_CH0 (0x0u << 17) /**< \brief (ISC_INTSR) An error occurred for Channel 0 (RAW/RGB/Y) */
+#define   ISC_INTSR_WERRID_CH1 (0x1u << 17) /**< \brief (ISC_INTSR) An error occurred for Channel 1 (CbCr/Cb) */
+#define   ISC_INTSR_WERRID_CH2 (0x2u << 17) /**< \brief (ISC_INTSR) An error occurred for Channel 2 (Cr) */
+#define   ISC_INTSR_WERRID_WB (0x3u << 17) /**< \brief (ISC_INTSR) Write back channel error */
+#define ISC_INTSR_RERR (0x1u << 20) /**< \brief (ISC_INTSR) Read Channel Error Interrupt */
+#define ISC_INTSR_VFPOV (0x1u << 24) /**< \brief (ISC_INTSR) Vertical Front Porch Overflow Interrupt */
+#define ISC_INTSR_DAOV (0x1u << 25) /**< \brief (ISC_INTSR) Data Overflow Interrupt */
+#define ISC_INTSR_VDTO (0x1u << 26) /**< \brief (ISC_INTSR) Vertical Synchronization Timeout Interrupt */
+#define ISC_INTSR_HDTO (0x1u << 27) /**< \brief (ISC_INTSR) Horizontal Synchronization Timeout Interrupt */
+#define ISC_INTSR_CCIRERR (0x1u << 28) /**< \brief (ISC_INTSR) CCIR Decoder Error Interrupt */
+/* -------- ISC_WB_CTRL : (ISC Offset: 0x58) White Balance Control Register -------- */
+#define ISC_WB_CTRL_ENABLE (0x1u << 0) /**< \brief (ISC_WB_CTRL) White Balance Enable */
+/* -------- ISC_WB_CFG : (ISC Offset: 0x5C) White Balance Configuration Register -------- */
+#define ISC_WB_CFG_BAYCFG_Pos 0
+#define ISC_WB_CFG_BAYCFG_Msk (0x3u << ISC_WB_CFG_BAYCFG_Pos) /**< \brief (ISC_WB_CFG) White Balance Bayer Configuration (Pixel Color Pattern) */
+#define ISC_WB_CFG_BAYCFG(value) ((ISC_WB_CFG_BAYCFG_Msk & ((value) << ISC_WB_CFG_BAYCFG_Pos)))
+#define   ISC_WB_CFG_BAYCFG_GRGR (0x0u << 0) /**< \brief (ISC_WB_CFG) Starting Row configuration is G R G R (Red Row) */
+#define   ISC_WB_CFG_BAYCFG_RGRG (0x1u << 0) /**< \brief (ISC_WB_CFG) Starting Row configuration is R G R G (Red Row */
+#define   ISC_WB_CFG_BAYCFG_GBGB (0x2u << 0) /**< \brief (ISC_WB_CFG) Starting Row configuration is G B G B (Blue Row */
+#define   ISC_WB_CFG_BAYCFG_BGBG (0x3u << 0) /**< \brief (ISC_WB_CFG) Starting Row configuration is B G B G (Blue Row) */
+/* -------- ISC_WB_O_RGR : (ISC Offset: 0x60) White Balance Offset for R, GR Register -------- */
+#define ISC_WB_O_RGR_ROFST_Pos 0
+#define ISC_WB_O_RGR_ROFST_Msk (0x1fffu << ISC_WB_O_RGR_ROFST_Pos) /**< \brief (ISC_WB_O_RGR) Offset Red Component (signed 13 bits 1:12:0) */
+#define ISC_WB_O_RGR_ROFST(value) ((ISC_WB_O_RGR_ROFST_Msk & ((value) << ISC_WB_O_RGR_ROFST_Pos)))
+#define ISC_WB_O_RGR_GROFST_Pos 16
+#define ISC_WB_O_RGR_GROFST_Msk (0x1fffu << ISC_WB_O_RGR_GROFST_Pos) /**< \brief (ISC_WB_O_RGR) Offset Green Component for Red Row (signed 13 bits 1:12:0) */
+#define ISC_WB_O_RGR_GROFST(value) ((ISC_WB_O_RGR_GROFST_Msk & ((value) << ISC_WB_O_RGR_GROFST_Pos)))
+/* -------- ISC_WB_O_BGB : (ISC Offset: 0x64) White Balance Offset for B, GB Register -------- */
+#define ISC_WB_O_BGB_BOFST_Pos 0
+#define ISC_WB_O_BGB_BOFST_Msk (0x1fffu << ISC_WB_O_BGB_BOFST_Pos) /**< \brief (ISC_WB_O_BGB) Offset Blue Component (signed 13 bits, 1:12:0) */
+#define ISC_WB_O_BGB_BOFST(value) ((ISC_WB_O_BGB_BOFST_Msk & ((value) << ISC_WB_O_BGB_BOFST_Pos)))
+#define ISC_WB_O_BGB_GBOFST_Pos 16
+#define ISC_WB_O_BGB_GBOFST_Msk (0x1fffu << ISC_WB_O_BGB_GBOFST_Pos) /**< \brief (ISC_WB_O_BGB) Offset Green Component for Blue Row (signed 13 bits, 1:12:0) */
+#define ISC_WB_O_BGB_GBOFST(value) ((ISC_WB_O_BGB_GBOFST_Msk & ((value) << ISC_WB_O_BGB_GBOFST_Pos)))
+/* -------- ISC_WB_G_RGR : (ISC Offset: 0x68) White Balance Gain for R, GR Register -------- */
+#define ISC_WB_G_RGR_RGAIN_Pos 0
+#define ISC_WB_G_RGR_RGAIN_Msk (0x1fffu << ISC_WB_G_RGR_RGAIN_Pos) /**< \brief (ISC_WB_G_RGR) Red Component Gain (unsigned 13 bits, 0:4:9) */
+#define ISC_WB_G_RGR_RGAIN(value) ((ISC_WB_G_RGR_RGAIN_Msk & ((value) << ISC_WB_G_RGR_RGAIN_Pos)))
+#define ISC_WB_G_RGR_GRGAIN_Pos 16
+#define ISC_WB_G_RGR_GRGAIN_Msk (0x1fffu << ISC_WB_G_RGR_GRGAIN_Pos) /**< \brief (ISC_WB_G_RGR) Green Component (Red row) Gain (unsigned 13 bits, 0:4:9) */
+#define ISC_WB_G_RGR_GRGAIN(value) ((ISC_WB_G_RGR_GRGAIN_Msk & ((value) << ISC_WB_G_RGR_GRGAIN_Pos)))
+/* -------- ISC_WB_G_BGB : (ISC Offset: 0x6C) White Balance Gain for B, GB Register -------- */
+#define ISC_WB_G_BGB_BGAIN_Pos 0
+#define ISC_WB_G_BGB_BGAIN_Msk (0x1fffu << ISC_WB_G_BGB_BGAIN_Pos) /**< \brief (ISC_WB_G_BGB) Blue Component Gain (unsigned 13 bits, 0:4:9) */
+#define ISC_WB_G_BGB_BGAIN(value) ((ISC_WB_G_BGB_BGAIN_Msk & ((value) << ISC_WB_G_BGB_BGAIN_Pos)))
+#define ISC_WB_G_BGB_GBGAIN_Pos 16
+#define ISC_WB_G_BGB_GBGAIN_Msk (0x1fffu << ISC_WB_G_BGB_GBGAIN_Pos) /**< \brief (ISC_WB_G_BGB) Green Component (Blue row) Gain (unsigned 13 bits, 0:4:9) */
+#define ISC_WB_G_BGB_GBGAIN(value) ((ISC_WB_G_BGB_GBGAIN_Msk & ((value) << ISC_WB_G_BGB_GBGAIN_Pos)))
+/* -------- ISC_CFA_CTRL : (ISC Offset: 0x70) Color Filter Array Control Register -------- */
+#define ISC_CFA_CTRL_ENABLE (0x1u << 0) /**< \brief (ISC_CFA_CTRL) Color Filter Array Interpolation Enable */
+/* -------- ISC_CFA_CFG : (ISC Offset: 0x74) Color Filter Array Configuration Register -------- */
+#define ISC_CFA_CFG_BAYCFG_Pos 0
+#define ISC_CFA_CFG_BAYCFG_Msk (0x3u << ISC_CFA_CFG_BAYCFG_Pos) /**< \brief (ISC_CFA_CFG) Color Filter Array Pattern */
+#define ISC_CFA_CFG_BAYCFG(value) ((ISC_CFA_CFG_BAYCFG_Msk & ((value) << ISC_CFA_CFG_BAYCFG_Pos)))
+#define   ISC_CFA_CFG_BAYCFG_GRGR (0x0u << 0) /**< \brief (ISC_CFA_CFG) Starting row configuration is G R G R (red row) */
+#define   ISC_CFA_CFG_BAYCFG_RGRG (0x1u << 0) /**< \brief (ISC_CFA_CFG) Starting row configuration is R G R G (red row */
+#define   ISC_CFA_CFG_BAYCFG_GBGB (0x2u << 0) /**< \brief (ISC_CFA_CFG) Starting row configuration is G B G B (blue row */
+#define   ISC_CFA_CFG_BAYCFG_BGBG (0x3u << 0) /**< \brief (ISC_CFA_CFG) Starting row configuration is B G B G (blue row) */
+#define ISC_CFA_CFG_EITPOL (0x1u << 4) /**< \brief (ISC_CFA_CFG) Edge Interpolation */
+/* -------- ISC_CC_CTRL : (ISC Offset: 0x78) Color Correction Control Register -------- */
+#define ISC_CC_CTRL_ENABLE (0x1u << 0) /**< \brief (ISC_CC_CTRL) Color Correction Enable */
+/* -------- ISC_CC_RR_RG : (ISC Offset: 0x7C) Color Correction RR RG Register -------- */
+#define ISC_CC_RR_RG_RRGAIN_Pos 0
+#define ISC_CC_RR_RG_RRGAIN_Msk (0xfffu << ISC_CC_RR_RG_RRGAIN_Pos) /**< \brief (ISC_CC_RR_RG) Red Gain for Red Component (signed 12 bits, 1:3:8) */
+#define ISC_CC_RR_RG_RRGAIN(value) ((ISC_CC_RR_RG_RRGAIN_Msk & ((value) << ISC_CC_RR_RG_RRGAIN_Pos)))
+#define ISC_CC_RR_RG_RGGAIN_Pos 16
+#define ISC_CC_RR_RG_RGGAIN_Msk (0xfffu << ISC_CC_RR_RG_RGGAIN_Pos) /**< \brief (ISC_CC_RR_RG) Green Gain for Red Component (signed 12 bits, 1:3:8) */
+#define ISC_CC_RR_RG_RGGAIN(value) ((ISC_CC_RR_RG_RGGAIN_Msk & ((value) << ISC_CC_RR_RG_RGGAIN_Pos)))
+/* -------- ISC_CC_RB_OR : (ISC Offset: 0x80) Color Correction RB OR Register -------- */
+#define ISC_CC_RB_OR_RBGAIN_Pos 0
+#define ISC_CC_RB_OR_RBGAIN_Msk (0xfffu << ISC_CC_RB_OR_RBGAIN_Pos) /**< \brief (ISC_CC_RB_OR) Blue Gain for Red Component (signed 12 bits, 1:3:8) */
+#define ISC_CC_RB_OR_RBGAIN(value) ((ISC_CC_RB_OR_RBGAIN_Msk & ((value) << ISC_CC_RB_OR_RBGAIN_Pos)))
+#define ISC_CC_RB_OR_ROFST_Pos 16
+#define ISC_CC_RB_OR_ROFST_Msk (0x1fffu << ISC_CC_RB_OR_ROFST_Pos) /**< \brief (ISC_CC_RB_OR) Red Component Offset (signed 13 bits, 1:12:0) */
+#define ISC_CC_RB_OR_ROFST(value) ((ISC_CC_RB_OR_ROFST_Msk & ((value) << ISC_CC_RB_OR_ROFST_Pos)))
+/* -------- ISC_CC_GR_GG : (ISC Offset: 0x84) Color Correction GR GG Register -------- */
+#define ISC_CC_GR_GG_GRGAIN_Pos 0
+#define ISC_CC_GR_GG_GRGAIN_Msk (0xfffu << ISC_CC_GR_GG_GRGAIN_Pos) /**< \brief (ISC_CC_GR_GG) Red Gain for Green Component (signed 12 bits, 1:3:8) */
+#define ISC_CC_GR_GG_GRGAIN(value) ((ISC_CC_GR_GG_GRGAIN_Msk & ((value) << ISC_CC_GR_GG_GRGAIN_Pos)))
+#define ISC_CC_GR_GG_GGGAIN_Pos 16
+#define ISC_CC_GR_GG_GGGAIN_Msk (0xfffu << ISC_CC_GR_GG_GGGAIN_Pos) /**< \brief (ISC_CC_GR_GG) Green Gain for Green Component (signed 12 bits, 1:3:8) */
+#define ISC_CC_GR_GG_GGGAIN(value) ((ISC_CC_GR_GG_GGGAIN_Msk & ((value) << ISC_CC_GR_GG_GGGAIN_Pos)))
+/* -------- ISC_CC_GB_OG : (ISC Offset: 0x88) Color Correction GB OG Register -------- */
+#define ISC_CC_GB_OG_GBGAIN_Pos 0
+#define ISC_CC_GB_OG_GBGAIN_Msk (0xfffu << ISC_CC_GB_OG_GBGAIN_Pos) /**< \brief (ISC_CC_GB_OG) Blue Gain for Green Component (signed 12 bits, 1:3:8) */
+#define ISC_CC_GB_OG_GBGAIN(value) ((ISC_CC_GB_OG_GBGAIN_Msk & ((value) << ISC_CC_GB_OG_GBGAIN_Pos)))
+#define ISC_CC_GB_OG_ROFST_Pos 16
+#define ISC_CC_GB_OG_ROFST_Msk (0x1fffu << ISC_CC_GB_OG_ROFST_Pos) /**< \brief (ISC_CC_GB_OG) Green Component Offset (signed 13 bits, 1:12:0) */
+#define ISC_CC_GB_OG_ROFST(value) ((ISC_CC_GB_OG_ROFST_Msk & ((value) << ISC_CC_GB_OG_ROFST_Pos)))
+/* -------- ISC_CC_BR_BG : (ISC Offset: 0x8C) Color Correction BR BG Register -------- */
+#define ISC_CC_BR_BG_BRGAIN_Pos 0
+#define ISC_CC_BR_BG_BRGAIN_Msk (0xfffu << ISC_CC_BR_BG_BRGAIN_Pos) /**< \brief (ISC_CC_BR_BG) Red Gain for Blue Component (signed 12 bits, 1:3:8) */
+#define ISC_CC_BR_BG_BRGAIN(value) ((ISC_CC_BR_BG_BRGAIN_Msk & ((value) << ISC_CC_BR_BG_BRGAIN_Pos)))
+#define ISC_CC_BR_BG_BGGAIN_Pos 16
+#define ISC_CC_BR_BG_BGGAIN_Msk (0xfffu << ISC_CC_BR_BG_BGGAIN_Pos) /**< \brief (ISC_CC_BR_BG) Green Gain for Blue Component (signed 12 bits, 1:3:8) */
+#define ISC_CC_BR_BG_BGGAIN(value) ((ISC_CC_BR_BG_BGGAIN_Msk & ((value) << ISC_CC_BR_BG_BGGAIN_Pos)))
+/* -------- ISC_CC_BB_OB : (ISC Offset: 0x90) Color Correction BB OB Register -------- */
+#define ISC_CC_BB_OB_BBGAIN_Pos 0
+#define ISC_CC_BB_OB_BBGAIN_Msk (0xfffu << ISC_CC_BB_OB_BBGAIN_Pos) /**< \brief (ISC_CC_BB_OB) Blue Gain for Blue Component (signed 12 bits, 1:3:8) */
+#define ISC_CC_BB_OB_BBGAIN(value) ((ISC_CC_BB_OB_BBGAIN_Msk & ((value) << ISC_CC_BB_OB_BBGAIN_Pos)))
+#define ISC_CC_BB_OB_BOFST_Pos 16
+#define ISC_CC_BB_OB_BOFST_Msk (0x1fffu << ISC_CC_BB_OB_BOFST_Pos) /**< \brief (ISC_CC_BB_OB) Blue Component Offset (signed 13 bits, 1:12:0) */
+#define ISC_CC_BB_OB_BOFST(value) ((ISC_CC_BB_OB_BOFST_Msk & ((value) << ISC_CC_BB_OB_BOFST_Pos)))
+/* -------- ISC_GAM_CTRL : (ISC Offset: 0x94) Gamma Correction Control Register -------- */
+#define ISC_GAM_CTRL_ENABLE (0x1u << 0) /**< \brief (ISC_GAM_CTRL) Gamma Correction Enable */
+#define ISC_GAM_CTRL_BENABLE (0x1u << 1) /**< \brief (ISC_GAM_CTRL) Gamma Correction Enable for B Channel */
+#define ISC_GAM_CTRL_GENABLE (0x1u << 2) /**< \brief (ISC_GAM_CTRL) Gamma Correction Enable for G Channel */
+#define ISC_GAM_CTRL_RENABLE (0x1u << 3) /**< \brief (ISC_GAM_CTRL) Gamma Correction Enable for R Channel */
+/* -------- ISC_GAM_BENTRY[64] : (ISC Offset: 0x98) Gamma Correction Blue Entry -------- */
+#define ISC_GAM_BENTRY_BSLOPE_Pos 0
+#define ISC_GAM_BENTRY_BSLOPE_Msk (0x3ffu << ISC_GAM_BENTRY_BSLOPE_Pos) /**< \brief (ISC_GAM_BENTRY[64]) Blue Color Slope for Piecewise Interpolation (signed 10 bits 1:3:6) */
+#define ISC_GAM_BENTRY_BSLOPE(value) ((ISC_GAM_BENTRY_BSLOPE_Msk & ((value) << ISC_GAM_BENTRY_BSLOPE_Pos)))
+#define ISC_GAM_BENTRY_BCONSTANT_Pos 16
+#define ISC_GAM_BENTRY_BCONSTANT_Msk (0x3ffu << ISC_GAM_BENTRY_BCONSTANT_Pos) /**< \brief (ISC_GAM_BENTRY[64]) Blue Color Constant for Piecewise Interpolation (unsigned 10 bits 0:10:0) */
+#define ISC_GAM_BENTRY_BCONSTANT(value) ((ISC_GAM_BENTRY_BCONSTANT_Msk & ((value) << ISC_GAM_BENTRY_BCONSTANT_Pos)))
+/* -------- ISC_GAM_GENTRY[64] : (ISC Offset: 0x198) Gamma Correction Green Entry -------- */
+#define ISC_GAM_GENTRY_GSLOPE_Pos 0
+#define ISC_GAM_GENTRY_GSLOPE_Msk (0x3ffu << ISC_GAM_GENTRY_GSLOPE_Pos) /**< \brief (ISC_GAM_GENTRY[64]) Green Color Slope for Piecewise Interpolation (signed 10 bits 1:3:6) */
+#define ISC_GAM_GENTRY_GSLOPE(value) ((ISC_GAM_GENTRY_GSLOPE_Msk & ((value) << ISC_GAM_GENTRY_GSLOPE_Pos)))
+#define ISC_GAM_GENTRY_GCONSTANT_Pos 16
+#define ISC_GAM_GENTRY_GCONSTANT_Msk (0x3ffu << ISC_GAM_GENTRY_GCONSTANT_Pos) /**< \brief (ISC_GAM_GENTRY[64]) Green Color Constant for Piecewise Interpolation (unsigned 10 bits 0:10:0) */
+#define ISC_GAM_GENTRY_GCONSTANT(value) ((ISC_GAM_GENTRY_GCONSTANT_Msk & ((value) << ISC_GAM_GENTRY_GCONSTANT_Pos)))
+/* -------- ISC_GAM_RENTRY[64] : (ISC Offset: 0x298) Gamma Correction Red Entry -------- */
+#define ISC_GAM_RENTRY_RSLOPE_Pos 0
+#define ISC_GAM_RENTRY_RSLOPE_Msk (0x3ffu << ISC_GAM_RENTRY_RSLOPE_Pos) /**< \brief (ISC_GAM_RENTRY[64]) Red Color Slope for Piecewise Interpolation (signed 10 bits 1:3:6) */
+#define ISC_GAM_RENTRY_RSLOPE(value) ((ISC_GAM_RENTRY_RSLOPE_Msk & ((value) << ISC_GAM_RENTRY_RSLOPE_Pos)))
+#define ISC_GAM_RENTRY_RCONSTANT_Pos 16
+#define ISC_GAM_RENTRY_RCONSTANT_Msk (0x3ffu << ISC_GAM_RENTRY_RCONSTANT_Pos) /**< \brief (ISC_GAM_RENTRY[64]) Red Color Constant for Piecewise Interpolation (unsigned 10 bits 0:10:0) */
+#define ISC_GAM_RENTRY_RCONSTANT(value) ((ISC_GAM_RENTRY_RCONSTANT_Msk & ((value) << ISC_GAM_RENTRY_RCONSTANT_Pos)))
+/* -------- ISC_CSC_CTRL : (ISC Offset: 0x398) Color Space Conversion Control Register -------- */
+#define ISC_CSC_CTRL_ENABLE (0x1u << 0) /**< \brief (ISC_CSC_CTRL) RGB to YCbCr Color Space Conversion Enable */
+/* -------- ISC_CSC_YR_YG : (ISC Offset: 0x39C) Color Space Conversion YR, YG Register -------- */
+#define ISC_CSC_YR_YG_YRGAIN_Pos 0
+#define ISC_CSC_YR_YG_YRGAIN_Msk (0xfffu << ISC_CSC_YR_YG_YRGAIN_Pos) /**< \brief (ISC_CSC_YR_YG) Reg Gain for Luminance (signed 12 bits 1:3:8) */
+#define ISC_CSC_YR_YG_YRGAIN(value) ((ISC_CSC_YR_YG_YRGAIN_Msk & ((value) << ISC_CSC_YR_YG_YRGAIN_Pos)))
+#define ISC_CSC_YR_YG_YGGAIN_Pos 16
+#define ISC_CSC_YR_YG_YGGAIN_Msk (0xfffu << ISC_CSC_YR_YG_YGGAIN_Pos) /**< \brief (ISC_CSC_YR_YG) Green Gain for Luminance (signed 12 bits 1:3:8) */
+#define ISC_CSC_YR_YG_YGGAIN(value) ((ISC_CSC_YR_YG_YGGAIN_Msk & ((value) << ISC_CSC_YR_YG_YGGAIN_Pos)))
+/* -------- ISC_CSC_YB_OY : (ISC Offset: 0x3A0) Color Space Conversion YB, OY Register -------- */
+#define ISC_CSC_YB_OY_YBGAIN_Pos 0
+#define ISC_CSC_YB_OY_YBGAIN_Msk (0xfffu << ISC_CSC_YB_OY_YBGAIN_Pos) /**< \brief (ISC_CSC_YB_OY) Blue Gain for Luminance Component (12 bits signed 1:3:8) */
+#define ISC_CSC_YB_OY_YBGAIN(value) ((ISC_CSC_YB_OY_YBGAIN_Msk & ((value) << ISC_CSC_YB_OY_YBGAIN_Pos)))
+#define ISC_CSC_YB_OY_YOFST_Pos 16
+#define ISC_CSC_YB_OY_YOFST_Msk (0x7ffu << ISC_CSC_YB_OY_YOFST_Pos) /**< \brief (ISC_CSC_YB_OY) Luminance Offset (11 bits signed 1:10:0) */
+#define ISC_CSC_YB_OY_YOFST(value) ((ISC_CSC_YB_OY_YOFST_Msk & ((value) << ISC_CSC_YB_OY_YOFST_Pos)))
+/* -------- ISC_CSC_CBR_CBG : (ISC Offset: 0x3A4) Color Space Conversion CBR CBG Register -------- */
+#define ISC_CSC_CBR_CBG_CBRGAIN_Pos 0
+#define ISC_CSC_CBR_CBG_CBRGAIN_Msk (0xfffu << ISC_CSC_CBR_CBG_CBRGAIN_Pos) /**< \brief (ISC_CSC_CBR_CBG) Red Gain for Blue Chrominance (signed 12 bits, 1:3:8) */
+#define ISC_CSC_CBR_CBG_CBRGAIN(value) ((ISC_CSC_CBR_CBG_CBRGAIN_Msk & ((value) << ISC_CSC_CBR_CBG_CBRGAIN_Pos)))
+#define ISC_CSC_CBR_CBG_CBGGAIN_Pos 16
+#define ISC_CSC_CBR_CBG_CBGGAIN_Msk (0xfffu << ISC_CSC_CBR_CBG_CBGGAIN_Pos) /**< \brief (ISC_CSC_CBR_CBG) Green Gain for Blue Chrominance (signed 12 bits 1:3:8) */
+#define ISC_CSC_CBR_CBG_CBGGAIN(value) ((ISC_CSC_CBR_CBG_CBGGAIN_Msk & ((value) << ISC_CSC_CBR_CBG_CBGGAIN_Pos)))
+/* -------- ISC_CSC_CBB_OCB : (ISC Offset: 0x3A8) Color Space Conversion CBB OCB Register -------- */
+#define ISC_CSC_CBB_OCB_CBBGAIN_Pos 0
+#define ISC_CSC_CBB_OCB_CBBGAIN_Msk (0xfffu << ISC_CSC_CBB_OCB_CBBGAIN_Pos) /**< \brief (ISC_CSC_CBB_OCB) Blue Gain for Blue Chrominance (signed 12 bits 1:3:8) */
+#define ISC_CSC_CBB_OCB_CBBGAIN(value) ((ISC_CSC_CBB_OCB_CBBGAIN_Msk & ((value) << ISC_CSC_CBB_OCB_CBBGAIN_Pos)))
+#define ISC_CSC_CBB_OCB_CBOFST_Pos 16
+#define ISC_CSC_CBB_OCB_CBOFST_Msk (0x7ffu << ISC_CSC_CBB_OCB_CBOFST_Pos) /**< \brief (ISC_CSC_CBB_OCB) Blue Chrominance Offset (signed 11 bits 1:10:0) */
+#define ISC_CSC_CBB_OCB_CBOFST(value) ((ISC_CSC_CBB_OCB_CBOFST_Msk & ((value) << ISC_CSC_CBB_OCB_CBOFST_Pos)))
+/* -------- ISC_CSC_CRR_CRG : (ISC Offset: 0x3AC) Color Space Conversion CRR CRG Register -------- */
+#define ISC_CSC_CRR_CRG_CRRGAIN_Pos 0
+#define ISC_CSC_CRR_CRG_CRRGAIN_Msk (0xfffu << ISC_CSC_CRR_CRG_CRRGAIN_Pos) /**< \brief (ISC_CSC_CRR_CRG) Red Gain for Red Chrominance (signed 12 bits 1:3:8) */
+#define ISC_CSC_CRR_CRG_CRRGAIN(value) ((ISC_CSC_CRR_CRG_CRRGAIN_Msk & ((value) << ISC_CSC_CRR_CRG_CRRGAIN_Pos)))
+#define ISC_CSC_CRR_CRG_CRGGAIN_Pos 16
+#define ISC_CSC_CRR_CRG_CRGGAIN_Msk (0xfffu << ISC_CSC_CRR_CRG_CRGGAIN_Pos) /**< \brief (ISC_CSC_CRR_CRG) Green Gain for Red Chrominance (signed 12 bits 1:3:8) */
+#define ISC_CSC_CRR_CRG_CRGGAIN(value) ((ISC_CSC_CRR_CRG_CRGGAIN_Msk & ((value) << ISC_CSC_CRR_CRG_CRGGAIN_Pos)))
+/* -------- ISC_CSC_CRB_OCR : (ISC Offset: 0x3B0) Color Space Conversion CRB OCR Register -------- */
+#define ISC_CSC_CRB_OCR_CRBGAIN_Pos 0
+#define ISC_CSC_CRB_OCR_CRBGAIN_Msk (0xfffu << ISC_CSC_CRB_OCR_CRBGAIN_Pos) /**< \brief (ISC_CSC_CRB_OCR) Blue Gain for Red Chrominance (signed 12 bits 1:3:8) */
+#define ISC_CSC_CRB_OCR_CRBGAIN(value) ((ISC_CSC_CRB_OCR_CRBGAIN_Msk & ((value) << ISC_CSC_CRB_OCR_CRBGAIN_Pos)))
+#define ISC_CSC_CRB_OCR_CROFST_Pos 16
+#define ISC_CSC_CRB_OCR_CROFST_Msk (0x7ffu << ISC_CSC_CRB_OCR_CROFST_Pos) /**< \brief (ISC_CSC_CRB_OCR) Red Chrominance Offset (signed 11 bits 1:10:0) */
+#define ISC_CSC_CRB_OCR_CROFST(value) ((ISC_CSC_CRB_OCR_CROFST_Msk & ((value) << ISC_CSC_CRB_OCR_CROFST_Pos)))
+/* -------- ISC_CBC_CTRL : (ISC Offset: 0x3B4) Contrast and Brightness Control Register -------- */
+#define ISC_CBC_CTRL_ENABLE (0x1u << 0) /**< \brief (ISC_CBC_CTRL) Contrast and Brightness Control Enable */
+/* -------- ISC_CBC_CFG : (ISC Offset: 0x3B8) Contrast and Brightness Configuration Register -------- */
+#define ISC_CBC_CFG_CCIR (0x1u << 0) /**< \brief (ISC_CBC_CFG) CCIR656 Stream Enable */
+#define ISC_CBC_CFG_CCIRMODE_Pos 1
+#define ISC_CBC_CFG_CCIRMODE_Msk (0x3u << ISC_CBC_CFG_CCIRMODE_Pos) /**< \brief (ISC_CBC_CFG) CCIR656 Byte Ordering */
+#define ISC_CBC_CFG_CCIRMODE(value) ((ISC_CBC_CFG_CCIRMODE_Msk & ((value) << ISC_CBC_CFG_CCIRMODE_Pos)))
+#define   ISC_CBC_CFG_CCIRMODE_CBY (0x0u << 1) /**< \brief (ISC_CBC_CFG) Byte ordering Cb0, Y0, Cr0, Y1 */
+#define   ISC_CBC_CFG_CCIRMODE_CRY (0x1u << 1) /**< \brief (ISC_CBC_CFG) Byte ordering Cr0, Y0, Cb0, Y1 */
+#define   ISC_CBC_CFG_CCIRMODE_YCB (0x2u << 1) /**< \brief (ISC_CBC_CFG) Byte ordering Y0, Cb0, Y1, Cr0 */
+#define   ISC_CBC_CFG_CCIRMODE_YCR (0x3u << 1) /**< \brief (ISC_CBC_CFG) Byte ordering Y0, Cr0, Y1, Cb0 */
+/* -------- ISC_CBC_BRIGHT : (ISC Offset: 0x3BC) Contrast and Brightness, Brightness Register -------- */
+#define ISC_CBC_BRIGHT_BRIGHT_Pos 0
+#define ISC_CBC_BRIGHT_BRIGHT_Msk (0x7ffu << ISC_CBC_BRIGHT_BRIGHT_Pos) /**< \brief (ISC_CBC_BRIGHT) Brightness Control (signed 11 bits 1:10:0) */
+#define ISC_CBC_BRIGHT_BRIGHT(value) ((ISC_CBC_BRIGHT_BRIGHT_Msk & ((value) << ISC_CBC_BRIGHT_BRIGHT_Pos)))
+/* -------- ISC_CBC_CONTRAST : (ISC Offset: 0x3C0) Contrast and Brightness, Contrast Register -------- */
+#define ISC_CBC_CONTRAST_CONTRAST_Pos 0
+#define ISC_CBC_CONTRAST_CONTRAST_Msk (0xfffu << ISC_CBC_CONTRAST_CONTRAST_Pos) /**< \brief (ISC_CBC_CONTRAST) Contrast (signed 12 bits 1:3:8) */
+#define ISC_CBC_CONTRAST_CONTRAST(value) ((ISC_CBC_CONTRAST_CONTRAST_Msk & ((value) << ISC_CBC_CONTRAST_CONTRAST_Pos)))
+/* -------- ISC_SUB422_CTRL : (ISC Offset: 0x3C4) Subsampling 4:4:4 to 4:2:2 Control Register -------- */
+#define ISC_SUB422_CTRL_ENABLE (0x1u << 0) /**< \brief (ISC_SUB422_CTRL) 4:4:4 to 4:2:2 Chrominance Horizontal Subsampling Filter Enable */
+/* -------- ISC_SUB422_CFG : (ISC Offset: 0x3C8) Subsampling 4:4:4 to 4:2:2 Configuration Register -------- */
+#define ISC_SUB422_CFG_CCIR (0x1u << 0) /**< \brief (ISC_SUB422_CFG) CCIR656 Input Stream */
+#define ISC_SUB422_CFG_CCIRMODE_Pos 1
+#define ISC_SUB422_CFG_CCIRMODE_Msk (0x3u << ISC_SUB422_CFG_CCIRMODE_Pos) /**< \brief (ISC_SUB422_CFG) CCIR656 Byte Ordering */
+#define ISC_SUB422_CFG_CCIRMODE(value) ((ISC_SUB422_CFG_CCIRMODE_Msk & ((value) << ISC_SUB422_CFG_CCIRMODE_Pos)))
+#define   ISC_SUB422_CFG_CCIRMODE_CBY (0x0u << 1) /**< \brief (ISC_SUB422_CFG) Byte ordering Cb0, Y0, Cr0, Y1 */
+#define   ISC_SUB422_CFG_CCIRMODE_CRY (0x1u << 1) /**< \brief (ISC_SUB422_CFG) Byte ordering Cr0, Y0, Cb0, Y1 */
+#define   ISC_SUB422_CFG_CCIRMODE_YCB (0x2u << 1) /**< \brief (ISC_SUB422_CFG) Byte ordering Y0, Cb0, Y1, Cr0 */
+#define   ISC_SUB422_CFG_CCIRMODE_YCR (0x3u << 1) /**< \brief (ISC_SUB422_CFG) Byte ordering Y0, Cr0, Y1, Cb0 */
+#define ISC_SUB422_CFG_FILTER_Pos 4
+#define ISC_SUB422_CFG_FILTER_Msk (0x3u << ISC_SUB422_CFG_FILTER_Pos) /**< \brief (ISC_SUB422_CFG) Low Pass Filter Selection */
+#define ISC_SUB422_CFG_FILTER(value) ((ISC_SUB422_CFG_FILTER_Msk & ((value) << ISC_SUB422_CFG_FILTER_Pos)))
+#define   ISC_SUB422_CFG_FILTER_FILT0CO (0x0u << 4) /**< \brief (ISC_SUB422_CFG) Cosited, {1} */
+#define   ISC_SUB422_CFG_FILTER_FILT1CE (0x1u << 4) /**< \brief (ISC_SUB422_CFG) Centered {1, 1} */
+#define   ISC_SUB422_CFG_FILTER_FILT2CO (0x2u << 4) /**< \brief (ISC_SUB422_CFG) Cosited {1,2,1} */
+#define   ISC_SUB422_CFG_FILTER_FILT3CE (0x3u << 4) /**< \brief (ISC_SUB422_CFG) Centered {1, 3, 3, 1} */
+/* -------- ISC_SUB420_CTRL : (ISC Offset: 0x3CC) Subsampling 4:2:2 to 4:2:0 Control Register -------- */
+#define ISC_SUB420_CTRL_ENABLE (0x1u << 0) /**< \brief (ISC_SUB420_CTRL) 4:2:2 to 4:2:0 Vertical Subsampling Filter Enable (Center Aligned) */
+#define ISC_SUB420_CTRL_FILTER (0x1u << 4) /**< \brief (ISC_SUB420_CTRL) Interlaced or Progressive Chrominance Filter */
+/* -------- ISC_RLP_CFG : (ISC Offset: 0x3D0) Rounding, Limiting and Packing Config Register -------- */
+#define ISC_RLP_CFG_MODE_Pos 0
+#define ISC_RLP_CFG_MODE_Msk (0xfu << ISC_RLP_CFG_MODE_Pos) /**< \brief (ISC_RLP_CFG) Rounding, Limiting and Packing Mode */
+#define ISC_RLP_CFG_MODE(value) ((ISC_RLP_CFG_MODE_Msk & ((value) << ISC_RLP_CFG_MODE_Pos)))
+#define   ISC_RLP_CFG_MODE_DAT8 (0x0u << 0) /**< \brief (ISC_RLP_CFG) 8-bit data */
+#define   ISC_RLP_CFG_MODE_DAT9 (0x1u << 0) /**< \brief (ISC_RLP_CFG) 9-bit data */
+#define   ISC_RLP_CFG_MODE_DAT10 (0x2u << 0) /**< \brief (ISC_RLP_CFG) 10-bit data */
+#define   ISC_RLP_CFG_MODE_DAT11 (0x3u << 0) /**< \brief (ISC_RLP_CFG) 11-bit data */
+#define   ISC_RLP_CFG_MODE_DAT12 (0x4u << 0) /**< \brief (ISC_RLP_CFG) 12-bit data */
+#define   ISC_RLP_CFG_MODE_DATY8 (0x5u << 0) /**< \brief (ISC_RLP_CFG) 8-bit luminance only */
+#define   ISC_RLP_CFG_MODE_DATY10 (0x6u << 0) /**< \brief (ISC_RLP_CFG) 10-bit luminance only */
+#define   ISC_RLP_CFG_MODE_ARGB444 (0x7u << 0) /**< \brief (ISC_RLP_CFG) 12-bit RGB+4-bit Alpha (MSB) */
+#define   ISC_RLP_CFG_MODE_ARGB555 (0x8u << 0) /**< \brief (ISC_RLP_CFG) 15-bit RGB+1-bit Alpha (MSB) */
+#define   ISC_RLP_CFG_MODE_RGB565 (0x9u << 0) /**< \brief (ISC_RLP_CFG) 16-bit RGB */
+#define   ISC_RLP_CFG_MODE_ARGB32 (0xAu << 0) /**< \brief (ISC_RLP_CFG) 24-bits RGB mode+8-bit Alpha */
+#define   ISC_RLP_CFG_MODE_YYCC (0xBu << 0) /**< \brief (ISC_RLP_CFG) YCbCr mode (full range, [0-255]) */
+#define   ISC_RLP_CFG_MODE_YYCC_LIMITED (0xCu << 0) /**< \brief (ISC_RLP_CFG) YCbCr mode (limited range) */
+#define ISC_RLP_CFG_ALPHA_Pos 8
+#define ISC_RLP_CFG_ALPHA_Msk (0xffu << ISC_RLP_CFG_ALPHA_Pos) /**< \brief (ISC_RLP_CFG) Alpha Value for Alpha-enabled RGB Mode */
+#define ISC_RLP_CFG_ALPHA(value) ((ISC_RLP_CFG_ALPHA_Msk & ((value) << ISC_RLP_CFG_ALPHA_Pos)))
+/* -------- ISC_HIS_CTRL : (ISC Offset: 0x3D4) Histogram Control Register -------- */
+#define ISC_HIS_CTRL_ENABLE (0x1u << 0) /**< \brief (ISC_HIS_CTRL) Histogram Sub Module Enable */
+/* -------- ISC_HIS_CFG : (ISC Offset: 0x3D8) Histogram Configuration Register -------- */
+#define ISC_HIS_CFG_MODE_Pos 0
+#define ISC_HIS_CFG_MODE_Msk (0x7u << ISC_HIS_CFG_MODE_Pos) /**< \brief (ISC_HIS_CFG) Histogram Operating Mode */
+#define ISC_HIS_CFG_MODE(value) ((ISC_HIS_CFG_MODE_Msk & ((value) << ISC_HIS_CFG_MODE_Pos)))
+#define   ISC_HIS_CFG_MODE_Gr (0x0u << 0) /**< \brief (ISC_HIS_CFG) Gr sampling */
+#define   ISC_HIS_CFG_MODE_R (0x1u << 0) /**< \brief (ISC_HIS_CFG) R sampling */
+#define   ISC_HIS_CFG_MODE_Gb (0x2u << 0) /**< \brief (ISC_HIS_CFG) Gb sampling */
+#define   ISC_HIS_CFG_MODE_B (0x3u << 0) /**< \brief (ISC_HIS_CFG) B sampling */
+#define   ISC_HIS_CFG_MODE_Y (0x4u << 0) /**< \brief (ISC_HIS_CFG) Luminance-only mode */
+#define   ISC_HIS_CFG_MODE_RAW (0x5u << 0) /**< \brief (ISC_HIS_CFG) Raw sampling */
+#define   ISC_HIS_CFG_MODE_YCCIR656 (0x6u << 0) /**< \brief (ISC_HIS_CFG) Luminance only with CCIR656 10-bit or 8-bit mode */
+#define ISC_HIS_CFG_BAYSEL_Pos 4
+#define ISC_HIS_CFG_BAYSEL_Msk (0x3u << ISC_HIS_CFG_BAYSEL_Pos) /**< \brief (ISC_HIS_CFG) Bayer Color Component Selection */
+#define ISC_HIS_CFG_BAYSEL(value) ((ISC_HIS_CFG_BAYSEL_Msk & ((value) << ISC_HIS_CFG_BAYSEL_Pos)))
+#define   ISC_HIS_CFG_BAYSEL_GRGR (0x0u << 4) /**< \brief (ISC_HIS_CFG) Starting row configuration is G R G R (red row) */
+#define   ISC_HIS_CFG_BAYSEL_RGRG (0x1u << 4) /**< \brief (ISC_HIS_CFG) Starting row configuration is R G R G (red row */
+#define   ISC_HIS_CFG_BAYSEL_GBGB (0x2u << 4) /**< \brief (ISC_HIS_CFG) Starting row configuration is G B G B (blue row */
+#define   ISC_HIS_CFG_BAYSEL_BGBG (0x3u << 4) /**< \brief (ISC_HIS_CFG) Starting row configuration is B G B G (blue row) */
+#define ISC_HIS_CFG_RAR (0x1u << 8) /**< \brief (ISC_HIS_CFG) Histogram Reset After Read */
+/* -------- ISC_DCFG : (ISC Offset: 0x3E0) DMA Configuration Register -------- */
+#define ISC_DCFG_IMODE_Pos 0
+#define ISC_DCFG_IMODE_Msk (0x7u << ISC_DCFG_IMODE_Pos) /**< \brief (ISC_DCFG) DMA Input Mode Selection */
+#define ISC_DCFG_IMODE(value) ((ISC_DCFG_IMODE_Msk & ((value) << ISC_DCFG_IMODE_Pos)))
+#define   ISC_DCFG_IMODE_PACKED8 (0x0u << 0) /**< \brief (ISC_DCFG) 8 bits, single channel packed */
+#define   ISC_DCFG_IMODE_PACKED16 (0x1u << 0) /**< \brief (ISC_DCFG) 16 bits, single channel packed */
+#define   ISC_DCFG_IMODE_PACKED32 (0x2u << 0) /**< \brief (ISC_DCFG) 32 bits, single channel packed */
+#define   ISC_DCFG_IMODE_YC422SP (0x3u << 0) /**< \brief (ISC_DCFG) 32 bits, dual channel */
+#define   ISC_DCFG_IMODE_YC422P (0x4u << 0) /**< \brief (ISC_DCFG) 32 bits, triple channel */
+#define   ISC_DCFG_IMODE_YC420SP (0x5u << 0) /**< \brief (ISC_DCFG) 32 bits, dual channel */
+#define   ISC_DCFG_IMODE_YC420P (0x6u << 0) /**< \brief (ISC_DCFG) 32 bits, triple channel */
+#define ISC_DCFG_YMBSIZE_Pos 4
+#define ISC_DCFG_YMBSIZE_Msk (0x3u << ISC_DCFG_YMBSIZE_Pos) /**< \brief (ISC_DCFG) DMA Memory Burst Size Y channel */
+#define ISC_DCFG_YMBSIZE(value) ((ISC_DCFG_YMBSIZE_Msk & ((value) << ISC_DCFG_YMBSIZE_Pos)))
+#define   ISC_DCFG_YMBSIZE_SINGLE (0x0u << 4) /**< \brief (ISC_DCFG) DMA single access */
+#define   ISC_DCFG_YMBSIZE_BEATS4 (0x1u << 4) /**< \brief (ISC_DCFG) 4-beat burst access */
+#define   ISC_DCFG_YMBSIZE_BEATS8 (0x2u << 4) /**< \brief (ISC_DCFG) 8-beat burst access */
+#define   ISC_DCFG_YMBSIZE_BEATS16 (0x3u << 4) /**< \brief (ISC_DCFG) 16-beat burst access */
+#define ISC_DCFG_CMBSIZE_Pos 8
+#define ISC_DCFG_CMBSIZE_Msk (0x3u << ISC_DCFG_CMBSIZE_Pos) /**< \brief (ISC_DCFG) DMA Memory Burst Size C channel */
+#define ISC_DCFG_CMBSIZE(value) ((ISC_DCFG_CMBSIZE_Msk & ((value) << ISC_DCFG_CMBSIZE_Pos)))
+#define   ISC_DCFG_CMBSIZE_SINGLE (0x0u << 8) /**< \brief (ISC_DCFG) DMA single access */
+#define   ISC_DCFG_CMBSIZE_BEATS4 (0x1u << 8) /**< \brief (ISC_DCFG) 4-beat burst access */
+#define   ISC_DCFG_CMBSIZE_BEATS8 (0x2u << 8) /**< \brief (ISC_DCFG) 8-beat burst access */
+#define   ISC_DCFG_CMBSIZE_BEATS16 (0x3u << 8) /**< \brief (ISC_DCFG) 16-beat burst access */
+/* -------- ISC_DCTRL : (ISC Offset: 0x3E4) DMA Control Register -------- */
+#define ISC_DCTRL_DE (0x1u << 0) /**< \brief (ISC_DCTRL) Descriptor Enable */
+#define ISC_DCTRL_DVIEW_Pos 1
+#define ISC_DCTRL_DVIEW_Msk (0x3u << ISC_DCTRL_DVIEW_Pos) /**< \brief (ISC_DCTRL) Descriptor View */
+#define ISC_DCTRL_DVIEW(value) ((ISC_DCTRL_DVIEW_Msk & ((value) << ISC_DCTRL_DVIEW_Pos)))
+#define   ISC_DCTRL_DVIEW_PACKED (0x0u << 1) /**< \brief (ISC_DCTRL) Address {0} Stride {0} are updated */
+#define   ISC_DCTRL_DVIEW_SEMIPLANAR (0x1u << 1) /**< \brief (ISC_DCTRL) Address {0,1} Stride {0,1} are updated */
+#define   ISC_DCTRL_DVIEW_PLANAR (0x2u << 1) /**< \brief (ISC_DCTRL) Address {0,1,2} Stride {0,1,2} are updated */
+#define ISC_DCTRL_IE (0x1u << 4) /**< \brief (ISC_DCTRL) Interrupt Enable */
+#define ISC_DCTRL_WB (0x1u << 5) /**< \brief (ISC_DCTRL) Write Back Operation Enable */
+/* -------- ISC_DNDA : (ISC Offset: 0x3E8) DMA Descriptor Address Register -------- */
+#define ISC_DNDA_NDA_Pos 2
+#define ISC_DNDA_NDA_Msk (0x3fffffffu << ISC_DNDA_NDA_Pos) /**< \brief (ISC_DNDA) Next Descriptor Address Register */
+#define ISC_DNDA_NDA(value) ((ISC_DNDA_NDA_Msk & ((value) << ISC_DNDA_NDA_Pos)))
+/* -------- ISC_DAD : (ISC Offset: N/A) DMA Address 0 Register -------- */
+#define ISC_DAD_AD0_Pos 0
+#define ISC_DAD_AD0_Msk (0xffffffffu << ISC_DAD_AD0_Pos) /**< \brief (ISC_DAD) Channel 0 Address */
+#define ISC_DAD_AD0(value) ((ISC_DAD_AD0_Msk & ((value) << ISC_DAD_AD0_Pos)))
+/* -------- ISC_DST : (ISC Offset: N/A) DMA Stride 0 Register -------- */
+#define ISC_DST_ST0_Pos 0
+#define ISC_DST_ST0_Msk (0xffffffffu << ISC_DST_ST0_Pos) /**< \brief (ISC_DST) Channel 0 Stride */
+#define ISC_DST_ST0(value) ((ISC_DST_ST0_Msk & ((value) << ISC_DST_ST0_Pos)))
+/* -------- IPB_VERSION : (ISC Offset: 0x40C) Version Register -------- */
+#define IPB_VERSION_VERSION_Pos 0
+#define IPB_VERSION_VERSION_Msk (0xfffu << IPB_VERSION_VERSION_Pos) /**< \brief (IPB_VERSION)  */
+#define IPB_VERSION_MFN_Pos 16
+#define IPB_VERSION_MFN_Msk (0x7u << IPB_VERSION_MFN_Pos) /**< \brief (IPB_VERSION)  */
+/* -------- ISC_HIS_ENTRY[512] : (ISC Offset: 0x410) Histogram Entry -------- */
+#define ISC_HIS_ENTRY_COUNT_Pos 0
+#define ISC_HIS_ENTRY_COUNT_Msk (0xfffffu << ISC_HIS_ENTRY_COUNT_Pos) /**< \brief (ISC_HIS_ENTRY[512]) Entry Counter */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_ISC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_l2cc.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_l2cc.h
new file mode 100644
index 000000000..2526c57d5
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_l2cc.h
@@ -0,0 +1,354 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_L2CC_COMPONENT_
+#define _SAMA5D2_L2CC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR L2 Cache Controller */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_L2CC L2 Cache Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief L2cc hardware registers */
+typedef struct {
+  __I  uint32_t L2CC_IDR;        /**< \brief (L2cc Offset: 0x000) Cache ID Register */
+  __I  uint32_t L2CC_TYPR;       /**< \brief (L2cc Offset: 0x004) Cache Type Register */
+  __I  uint32_t Reserved1[62];
+  __IO uint32_t L2CC_CR;         /**< \brief (L2cc Offset: 0x100) Control Register */
+  __IO uint32_t L2CC_ACR;        /**< \brief (L2cc Offset: 0x104) Auxiliary Control Register */
+  __IO uint32_t L2CC_TRCR;       /**< \brief (L2cc Offset: 0x108) Tag RAM Control Register */
+  __IO uint32_t L2CC_DRCR;       /**< \brief (L2cc Offset: 0x10C) Data RAM Control Register */
+  __I  uint32_t Reserved2[60];
+  __IO uint32_t L2CC_ECR;        /**< \brief (L2cc Offset: 0x200) Event Counter Control Register */
+  __IO uint32_t L2CC_ECFGR1;     /**< \brief (L2cc Offset: 0x204) Event Counter 1 Configuration Register */
+  __IO uint32_t L2CC_ECFGR0;     /**< \brief (L2cc Offset: 0x208) Event Counter 0 Configuration Register */
+  __IO uint32_t L2CC_EVR1;       /**< \brief (L2cc Offset: 0x20C) Event Counter 1 Value Register */
+  __IO uint32_t L2CC_EVR0;       /**< \brief (L2cc Offset: 0x210) Event Counter 0 Value Register */
+  __IO uint32_t L2CC_IMR;        /**< \brief (L2cc Offset: 0x214) Interrupt Mask Register */
+  __I  uint32_t L2CC_MISR;       /**< \brief (L2cc Offset: 0x218) Masked Interrupt Status Register */
+  __I  uint32_t L2CC_RISR;       /**< \brief (L2cc Offset: 0x21C) Raw Interrupt Status Register */
+  __IO uint32_t L2CC_ICR;        /**< \brief (L2cc Offset: 0x220) Interrupt Clear Register */
+  __I  uint32_t Reserved3[323];
+  __IO uint32_t L2CC_CSR;        /**< \brief (L2cc Offset: 0x730) Cache Synchronization Register */
+  __I  uint32_t Reserved4[15];
+  __IO uint32_t L2CC_IPALR;      /**< \brief (L2cc Offset: 0x770) Invalidate Physical Address Line Register */
+  __I  uint32_t Reserved5[2];
+  __IO uint32_t L2CC_IWR;        /**< \brief (L2cc Offset: 0x77C) Invalidate Way Register */
+  __I  uint32_t Reserved6[12];
+  __IO uint32_t L2CC_CPALR;      /**< \brief (L2cc Offset: 0x7B0) Clean Physical Address Line Register */
+  __I  uint32_t Reserved7[1];
+  __IO uint32_t L2CC_CIR;        /**< \brief (L2cc Offset: 0x7B8) Clean Index Register */
+  __IO uint32_t L2CC_CWR;        /**< \brief (L2cc Offset: 0x7BC) Clean Way Register */
+  __I  uint32_t Reserved8[12];
+  __IO uint32_t L2CC_CIPALR;     /**< \brief (L2cc Offset: 0x7F0) Clean Invalidate Physical Address Line Register */
+  __I  uint32_t Reserved9[1];
+  __IO uint32_t L2CC_CIIR;       /**< \brief (L2cc Offset: 0x7F8) Clean Invalidate Index Register */
+  __IO uint32_t L2CC_CIWR;       /**< \brief (L2cc Offset: 0x7FC) Clean Invalidate Way Register */
+  __I  uint32_t Reserved10[64];
+  __IO uint32_t L2CC_DLKR;       /**< \brief (L2cc Offset: 0x900) Data Lockdown Register */
+  __IO uint32_t L2CC_ILKR;       /**< \brief (L2cc Offset: 0x904) Instruction Lockdown Register */
+  __I  uint32_t Reserved11[398];
+  __IO uint32_t L2CC_DCR;        /**< \brief (L2cc Offset: 0xF40) Debug Control Register */
+  __I  uint32_t Reserved12[7];
+  __IO uint32_t L2CC_PCR;        /**< \brief (L2cc Offset: 0xF60) Prefetch Control Register */
+  __I  uint32_t Reserved13[7];
+  __IO uint32_t L2CC_POWCR;      /**< \brief (L2cc Offset: 0xF80) Power Control Register */
+} L2cc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- L2CC_IDR : (L2CC Offset: 0x000) Cache ID Register -------- */
+#define L2CC_IDR_ID_Pos 0
+#define L2CC_IDR_ID_Msk (0xffffffffu << L2CC_IDR_ID_Pos) /**< \brief (L2CC_IDR) Cache Controller ID */
+/* -------- L2CC_TYPR : (L2CC Offset: 0x004) Cache Type Register -------- */
+#define L2CC_TYPR_IL2ASS (0x1u << 6) /**< \brief (L2CC_TYPR) Instruction L2 Cache Associativity */
+#define L2CC_TYPR_IL2WSIZE_Pos 8
+#define L2CC_TYPR_IL2WSIZE_Msk (0x7u << L2CC_TYPR_IL2WSIZE_Pos) /**< \brief (L2CC_TYPR) Instruction L2 Cache Way Size */
+#define L2CC_TYPR_DL2ASS (0x1u << 18) /**< \brief (L2CC_TYPR) Data L2 Cache Associativity */
+#define L2CC_TYPR_DL2WSIZE_Pos 20
+#define L2CC_TYPR_DL2WSIZE_Msk (0x7u << L2CC_TYPR_DL2WSIZE_Pos) /**< \brief (L2CC_TYPR) Data L2 Cache Way Size */
+/* -------- L2CC_CR : (L2CC Offset: 0x100) Control Register -------- */
+#define L2CC_CR_L2CEN (0x1u << 0) /**< \brief (L2CC_CR) L2 Cache Enable */
+/* -------- L2CC_ACR : (L2CC Offset: 0x104) Auxiliary Control Register -------- */
+#define L2CC_ACR_HPSO (0x1u << 10) /**< \brief (L2CC_ACR) High Priority for SO and Dev Reads Enable */
+#define L2CC_ACR_SBDLE (0x1u << 11) /**< \brief (L2CC_ACR) Store Buffer Device Limitation Enable */
+#define L2CC_ACR_EXCC (0x1u << 12) /**< \brief (L2CC_ACR) Exclusive Cache Configuration */
+#define L2CC_ACR_SAIE (0x1u << 13) /**< \brief (L2CC_ACR) Shared Attribute Invalidate Enable */
+#define L2CC_ACR_ASS (0x1u << 16) /**< \brief (L2CC_ACR) Associativity */
+#define L2CC_ACR_WAYSIZE_Pos 17
+#define L2CC_ACR_WAYSIZE_Msk (0x7u << L2CC_ACR_WAYSIZE_Pos) /**< \brief (L2CC_ACR) Way Size */
+#define L2CC_ACR_WAYSIZE(value) ((L2CC_ACR_WAYSIZE_Msk & ((value) << L2CC_ACR_WAYSIZE_Pos)))
+#define   L2CC_ACR_WAYSIZE_16KB_WAY (0x1u << 17) /**< \brief (L2CC_ACR) 16-Kbyte way set associative */
+#define L2CC_ACR_EMBEN (0x1u << 20) /**< \brief (L2CC_ACR) Event Monitor Bus Enable */
+#define L2CC_ACR_PEN (0x1u << 21) /**< \brief (L2CC_ACR) Parity Enable */
+#define L2CC_ACR_SAOEN (0x1u << 22) /**< \brief (L2CC_ACR) Shared Attribute Override Enable */
+#define L2CC_ACR_FWA_Pos 23
+#define L2CC_ACR_FWA_Msk (0x3u << L2CC_ACR_FWA_Pos) /**< \brief (L2CC_ACR) Force Write Allocate */
+#define L2CC_ACR_FWA(value) ((L2CC_ACR_FWA_Msk & ((value) << L2CC_ACR_FWA_Pos)))
+#define L2CC_ACR_CRPOL (0x1u << 25) /**< \brief (L2CC_ACR) Cache Replacement Policy */
+#define L2CC_ACR_NSLEN (0x1u << 26) /**< \brief (L2CC_ACR) Non-Secure Lockdown Enable */
+#define L2CC_ACR_NSIAC (0x1u << 27) /**< \brief (L2CC_ACR) Non-Secure Interrupt Access Control */
+#define L2CC_ACR_DPEN (0x1u << 28) /**< \brief (L2CC_ACR) Data Prefetch Enable */
+#define L2CC_ACR_IPEN (0x1u << 29) /**< \brief (L2CC_ACR) Instruction Prefetch Enable */
+/* -------- L2CC_TRCR : (L2CC Offset: 0x108) Tag RAM Control Register -------- */
+#define L2CC_TRCR_TSETLAT_Pos 0
+#define L2CC_TRCR_TSETLAT_Msk (0x7u << L2CC_TRCR_TSETLAT_Pos) /**< \brief (L2CC_TRCR) Setup Latency */
+#define L2CC_TRCR_TSETLAT(value) ((L2CC_TRCR_TSETLAT_Msk & ((value) << L2CC_TRCR_TSETLAT_Pos)))
+#define L2CC_TRCR_TRDLAT_Pos 4
+#define L2CC_TRCR_TRDLAT_Msk (0x7u << L2CC_TRCR_TRDLAT_Pos) /**< \brief (L2CC_TRCR) Read Access Latency */
+#define L2CC_TRCR_TRDLAT(value) ((L2CC_TRCR_TRDLAT_Msk & ((value) << L2CC_TRCR_TRDLAT_Pos)))
+#define L2CC_TRCR_TWRLAT_Pos 8
+#define L2CC_TRCR_TWRLAT_Msk (0x7u << L2CC_TRCR_TWRLAT_Pos) /**< \brief (L2CC_TRCR) Write Access Latency */
+#define L2CC_TRCR_TWRLAT(value) ((L2CC_TRCR_TWRLAT_Msk & ((value) << L2CC_TRCR_TWRLAT_Pos)))
+/* -------- L2CC_DRCR : (L2CC Offset: 0x10C) Data RAM Control Register -------- */
+#define L2CC_DRCR_DSETLAT_Pos 0
+#define L2CC_DRCR_DSETLAT_Msk (0x7u << L2CC_DRCR_DSETLAT_Pos) /**< \brief (L2CC_DRCR) Setup Latency */
+#define L2CC_DRCR_DSETLAT(value) ((L2CC_DRCR_DSETLAT_Msk & ((value) << L2CC_DRCR_DSETLAT_Pos)))
+#define L2CC_DRCR_DRDLAT_Pos 4
+#define L2CC_DRCR_DRDLAT_Msk (0x7u << L2CC_DRCR_DRDLAT_Pos) /**< \brief (L2CC_DRCR) Read Access Latency */
+#define L2CC_DRCR_DRDLAT(value) ((L2CC_DRCR_DRDLAT_Msk & ((value) << L2CC_DRCR_DRDLAT_Pos)))
+#define L2CC_DRCR_DWRLAT_Pos 8
+#define L2CC_DRCR_DWRLAT_Msk (0x7u << L2CC_DRCR_DWRLAT_Pos) /**< \brief (L2CC_DRCR) Write Access Latency */
+#define L2CC_DRCR_DWRLAT(value) ((L2CC_DRCR_DWRLAT_Msk & ((value) << L2CC_DRCR_DWRLAT_Pos)))
+/* -------- L2CC_ECR : (L2CC Offset: 0x200) Event Counter Control Register -------- */
+#define L2CC_ECR_EVCEN (0x1u << 0) /**< \brief (L2CC_ECR) Event Counter Enable */
+#define L2CC_ECR_EVC0RST (0x1u << 1) /**< \brief (L2CC_ECR) Event Counter 0 Reset */
+#define L2CC_ECR_EVC1RST (0x1u << 2) /**< \brief (L2CC_ECR) Event Counter 1 Reset */
+/* -------- L2CC_ECFGR1 : (L2CC Offset: 0x204) Event Counter 1 Configuration Register -------- */
+#define L2CC_ECFGR1_EIGEN_Pos 0
+#define L2CC_ECFGR1_EIGEN_Msk (0x3u << L2CC_ECFGR1_EIGEN_Pos) /**< \brief (L2CC_ECFGR1) Event Counter Interrupt Generation */
+#define L2CC_ECFGR1_EIGEN(value) ((L2CC_ECFGR1_EIGEN_Msk & ((value) << L2CC_ECFGR1_EIGEN_Pos)))
+#define   L2CC_ECFGR1_EIGEN_INT_DIS (0x0u << 0) /**< \brief (L2CC_ECFGR1) Disables (default) */
+#define   L2CC_ECFGR1_EIGEN_INT_EN_INCR (0x1u << 0) /**< \brief (L2CC_ECFGR1) Enables with Increment condition */
+#define   L2CC_ECFGR1_EIGEN_INT_EN_OVER (0x2u << 0) /**< \brief (L2CC_ECFGR1) Enables with Overflow condition */
+#define   L2CC_ECFGR1_EIGEN_INT_GEN_DIS (0x3u << 0) /**< \brief (L2CC_ECFGR1) Disables Interrupt generation */
+#define L2CC_ECFGR1_ESRC_Pos 2
+#define L2CC_ECFGR1_ESRC_Msk (0xfu << L2CC_ECFGR1_ESRC_Pos) /**< \brief (L2CC_ECFGR1) Event Counter Source */
+#define L2CC_ECFGR1_ESRC(value) ((L2CC_ECFGR1_ESRC_Msk & ((value) << L2CC_ECFGR1_ESRC_Pos)))
+#define   L2CC_ECFGR1_ESRC_CNT_DIS (0x0u << 2) /**< \brief (L2CC_ECFGR1) Counter Disabled */
+#define   L2CC_ECFGR1_ESRC_SRC_CO (0x1u << 2) /**< \brief (L2CC_ECFGR1) Source is CO */
+#define   L2CC_ECFGR1_ESRC_SRC_DRHIT (0x2u << 2) /**< \brief (L2CC_ECFGR1) Source is DRHIT */
+#define   L2CC_ECFGR1_ESRC_SRC_DRREQ (0x3u << 2) /**< \brief (L2CC_ECFGR1) Source is DRREQ */
+#define   L2CC_ECFGR1_ESRC_SRC_DWHIT (0x4u << 2) /**< \brief (L2CC_ECFGR1) Source is DWHIT */
+#define   L2CC_ECFGR1_ESRC_SRC_DWREQ (0x5u << 2) /**< \brief (L2CC_ECFGR1) Source is DWREQ */
+#define   L2CC_ECFGR1_ESRC_SRC_DWTREQ (0x6u << 2) /**< \brief (L2CC_ECFGR1) Source is DWTREQ */
+#define   L2CC_ECFGR1_ESRC_SRC_IRHIT (0x7u << 2) /**< \brief (L2CC_ECFGR1) Source is IRHIT */
+#define   L2CC_ECFGR1_ESRC_SRC_IRREQ (0x8u << 2) /**< \brief (L2CC_ECFGR1) Source is IRREQ */
+#define   L2CC_ECFGR1_ESRC_SRC_WA (0x9u << 2) /**< \brief (L2CC_ECFGR1) Source is WA */
+#define   L2CC_ECFGR1_ESRC_SRC_IPFALLOC (0xAu << 2) /**< \brief (L2CC_ECFGR1) Source is IPFALLOC */
+#define   L2CC_ECFGR1_ESRC_SRC_EPFHIT (0xBu << 2) /**< \brief (L2CC_ECFGR1) Source is EPFHIT */
+#define   L2CC_ECFGR1_ESRC_SRC_EPFALLOC (0xCu << 2) /**< \brief (L2CC_ECFGR1) Source is EPFALLOC */
+#define   L2CC_ECFGR1_ESRC_SRC_SRRCVD (0xDu << 2) /**< \brief (L2CC_ECFGR1) Source is SRRCVD */
+#define   L2CC_ECFGR1_ESRC_SRC_SRCONF (0xEu << 2) /**< \brief (L2CC_ECFGR1) Source is SRCONF */
+#define   L2CC_ECFGR1_ESRC_SRC_EPFRCVD (0xFu << 2) /**< \brief (L2CC_ECFGR1) Source is EPFRCVD */
+/* -------- L2CC_ECFGR0 : (L2CC Offset: 0x208) Event Counter 0 Configuration Register -------- */
+#define L2CC_ECFGR0_EIGEN_Pos 0
+#define L2CC_ECFGR0_EIGEN_Msk (0x3u << L2CC_ECFGR0_EIGEN_Pos) /**< \brief (L2CC_ECFGR0) Event Counter Interrupt Generation */
+#define L2CC_ECFGR0_EIGEN(value) ((L2CC_ECFGR0_EIGEN_Msk & ((value) << L2CC_ECFGR0_EIGEN_Pos)))
+#define   L2CC_ECFGR0_EIGEN_INT_DIS (0x0u << 0) /**< \brief (L2CC_ECFGR0) Disables (default) */
+#define   L2CC_ECFGR0_EIGEN_INT_EN_INCR (0x1u << 0) /**< \brief (L2CC_ECFGR0) Enables with Increment condition */
+#define   L2CC_ECFGR0_EIGEN_INT_EN_OVER (0x2u << 0) /**< \brief (L2CC_ECFGR0) Enables with Overflow condition */
+#define   L2CC_ECFGR0_EIGEN_INT_GEN_DIS (0x3u << 0) /**< \brief (L2CC_ECFGR0) Disables Interrupt generation */
+#define L2CC_ECFGR0_ESRC_Pos 2
+#define L2CC_ECFGR0_ESRC_Msk (0xfu << L2CC_ECFGR0_ESRC_Pos) /**< \brief (L2CC_ECFGR0) Event Counter Source */
+#define L2CC_ECFGR0_ESRC(value) ((L2CC_ECFGR0_ESRC_Msk & ((value) << L2CC_ECFGR0_ESRC_Pos)))
+#define   L2CC_ECFGR0_ESRC_CNT_DIS (0x0u << 2) /**< \brief (L2CC_ECFGR0) Counter Disabled */
+#define   L2CC_ECFGR0_ESRC_SRC_CO (0x1u << 2) /**< \brief (L2CC_ECFGR0) Source is CO */
+#define   L2CC_ECFGR0_ESRC_SRC_DRHIT (0x2u << 2) /**< \brief (L2CC_ECFGR0) Source is DRHIT */
+#define   L2CC_ECFGR0_ESRC_SRC_DRREQ (0x3u << 2) /**< \brief (L2CC_ECFGR0) Source is DRREQ */
+#define   L2CC_ECFGR0_ESRC_SRC_DWHIT (0x4u << 2) /**< \brief (L2CC_ECFGR0) Source is DWHIT */
+#define   L2CC_ECFGR0_ESRC_SRC_DWREQ (0x5u << 2) /**< \brief (L2CC_ECFGR0) Source is DWREQ */
+#define   L2CC_ECFGR0_ESRC_SRC_DWTREQ (0x6u << 2) /**< \brief (L2CC_ECFGR0) Source is DWTREQ */
+#define   L2CC_ECFGR0_ESRC_SRC_IRHIT (0x7u << 2) /**< \brief (L2CC_ECFGR0) Source is IRHIT */
+#define   L2CC_ECFGR0_ESRC_SRC_IRREQ (0x8u << 2) /**< \brief (L2CC_ECFGR0) Source is IRREQ */
+#define   L2CC_ECFGR0_ESRC_SRC_WA (0x9u << 2) /**< \brief (L2CC_ECFGR0) Source is WA */
+#define   L2CC_ECFGR0_ESRC_SRC_IPFALLOC (0xAu << 2) /**< \brief (L2CC_ECFGR0) Source is IPFALLOC */
+#define   L2CC_ECFGR0_ESRC_SRC_EPFHIT (0xBu << 2) /**< \brief (L2CC_ECFGR0) Source is EPFHIT */
+#define   L2CC_ECFGR0_ESRC_SRC_EPFALLOC (0xCu << 2) /**< \brief (L2CC_ECFGR0) Source is EPFALLOC */
+#define   L2CC_ECFGR0_ESRC_SRC_SRRCVD (0xDu << 2) /**< \brief (L2CC_ECFGR0) Source is SRRCVD */
+#define   L2CC_ECFGR0_ESRC_SRC_SRCONF (0xEu << 2) /**< \brief (L2CC_ECFGR0) Source is SRCONF */
+#define   L2CC_ECFGR0_ESRC_SRC_EPFRCVD (0xFu << 2) /**< \brief (L2CC_ECFGR0) Source is EPFRCVD */
+/* -------- L2CC_EVR1 : (L2CC Offset: 0x20C) Event Counter 1 Value Register -------- */
+#define L2CC_EVR1_VALUE_Pos 0
+#define L2CC_EVR1_VALUE_Msk (0xffffffffu << L2CC_EVR1_VALUE_Pos) /**< \brief (L2CC_EVR1) Event Counter Value */
+#define L2CC_EVR1_VALUE(value) ((L2CC_EVR1_VALUE_Msk & ((value) << L2CC_EVR1_VALUE_Pos)))
+/* -------- L2CC_EVR0 : (L2CC Offset: 0x210) Event Counter 0 Value Register -------- */
+#define L2CC_EVR0_VALUE_Pos 0
+#define L2CC_EVR0_VALUE_Msk (0xffffffffu << L2CC_EVR0_VALUE_Pos) /**< \brief (L2CC_EVR0) Event Counter Value */
+#define L2CC_EVR0_VALUE(value) ((L2CC_EVR0_VALUE_Msk & ((value) << L2CC_EVR0_VALUE_Pos)))
+/* -------- L2CC_IMR : (L2CC Offset: 0x214) Interrupt Mask Register -------- */
+#define L2CC_IMR_ECNTR (0x1u << 0) /**< \brief (L2CC_IMR) Event Counter 1/0 Overflow Increment */
+#define L2CC_IMR_PARRT (0x1u << 1) /**< \brief (L2CC_IMR) Parity Error on L2 Tag RAM, Read */
+#define L2CC_IMR_PARRD (0x1u << 2) /**< \brief (L2CC_IMR) Parity Error on L2 Data RAM, Read */
+#define L2CC_IMR_ERRWT (0x1u << 3) /**< \brief (L2CC_IMR) Error on L2 Tag RAM, Write */
+#define L2CC_IMR_ERRWD (0x1u << 4) /**< \brief (L2CC_IMR) Error on L2 Data RAM, Write */
+#define L2CC_IMR_ERRRT (0x1u << 5) /**< \brief (L2CC_IMR) Error on L2 Tag RAM, Read */
+#define L2CC_IMR_ERRRD (0x1u << 6) /**< \brief (L2CC_IMR) Error on L2 Data RAM, Read */
+#define L2CC_IMR_SLVERR (0x1u << 7) /**< \brief (L2CC_IMR) SLVERR from L3 Memory */
+#define L2CC_IMR_DECERR (0x1u << 8) /**< \brief (L2CC_IMR) DECERR from L3 Memory */
+/* -------- L2CC_MISR : (L2CC Offset: 0x218) Masked Interrupt Status Register -------- */
+#define L2CC_MISR_ECNTR (0x1u << 0) /**< \brief (L2CC_MISR) Event Counter 1/0 Overflow Increment */
+#define L2CC_MISR_PARRT (0x1u << 1) /**< \brief (L2CC_MISR) Parity Error on L2 Tag RAM, Read */
+#define L2CC_MISR_PARRD (0x1u << 2) /**< \brief (L2CC_MISR) Parity Error on L2 Data RAM, Read */
+#define L2CC_MISR_ERRWT (0x1u << 3) /**< \brief (L2CC_MISR) Error on L2 Tag RAM, Write */
+#define L2CC_MISR_ERRWD (0x1u << 4) /**< \brief (L2CC_MISR) Error on L2 Data RAM, Write */
+#define L2CC_MISR_ERRRT (0x1u << 5) /**< \brief (L2CC_MISR) Error on L2 Tag RAM, Read */
+#define L2CC_MISR_ERRRD (0x1u << 6) /**< \brief (L2CC_MISR) Error on L2 Data RAM, Read */
+#define L2CC_MISR_SLVERR (0x1u << 7) /**< \brief (L2CC_MISR) SLVERR from L3 memory */
+#define L2CC_MISR_DECERR (0x1u << 8) /**< \brief (L2CC_MISR) DECERR from L3 memory */
+/* -------- L2CC_RISR : (L2CC Offset: 0x21C) Raw Interrupt Status Register -------- */
+#define L2CC_RISR_ECNTR (0x1u << 0) /**< \brief (L2CC_RISR) Event Counter 1/0 Overflow Increment */
+#define L2CC_RISR_PARRT (0x1u << 1) /**< \brief (L2CC_RISR) Parity Error on L2 Tag RAM, Read */
+#define L2CC_RISR_PARRD (0x1u << 2) /**< \brief (L2CC_RISR) Parity Error on L2 Data RAM, Read */
+#define L2CC_RISR_ERRWT (0x1u << 3) /**< \brief (L2CC_RISR) Error on L2 Tag RAM, Write */
+#define L2CC_RISR_ERRWD (0x1u << 4) /**< \brief (L2CC_RISR) Error on L2 Data RAM, Write */
+#define L2CC_RISR_ERRRT (0x1u << 5) /**< \brief (L2CC_RISR) Error on L2 Tag RAM, Read */
+#define L2CC_RISR_ERRRD (0x1u << 6) /**< \brief (L2CC_RISR) Error on L2 Data RAM, Read */
+#define L2CC_RISR_SLVERR (0x1u << 7) /**< \brief (L2CC_RISR) SLVERR from L3 memory */
+#define L2CC_RISR_DECERR (0x1u << 8) /**< \brief (L2CC_RISR) DECERR from L3 memory */
+/* -------- L2CC_ICR : (L2CC Offset: 0x220) Interrupt Clear Register -------- */
+#define L2CC_ICR_ECNTR (0x1u << 0) /**< \brief (L2CC_ICR) Event Counter 1/0 Overflow Increment */
+#define L2CC_ICR_PARRT (0x1u << 1) /**< \brief (L2CC_ICR) Parity Error on L2 Tag RAM, Read */
+#define L2CC_ICR_PARRD (0x1u << 2) /**< \brief (L2CC_ICR) Parity Error on L2 Data RAM, Read */
+#define L2CC_ICR_ERRWT (0x1u << 3) /**< \brief (L2CC_ICR) Error on L2 Tag RAM, Write */
+#define L2CC_ICR_ERRWD (0x1u << 4) /**< \brief (L2CC_ICR) Error on L2 Data RAM, Write */
+#define L2CC_ICR_ERRRT (0x1u << 5) /**< \brief (L2CC_ICR) Error on L2 Tag RAM, Read */
+#define L2CC_ICR_ERRRD (0x1u << 6) /**< \brief (L2CC_ICR) Error on L2 Data RAM, Read */
+#define L2CC_ICR_SLVERR (0x1u << 7) /**< \brief (L2CC_ICR) SLVERR from L3 memory */
+#define L2CC_ICR_DECERR (0x1u << 8) /**< \brief (L2CC_ICR) DECERR from L3 memory */
+/* -------- L2CC_CSR : (L2CC Offset: 0x730) Cache Synchronization Register -------- */
+#define L2CC_CSR_C (0x1u << 0) /**< \brief (L2CC_CSR) Cache Synchronization Status */
+/* -------- L2CC_IPALR : (L2CC Offset: 0x770) Invalidate Physical Address Line Register -------- */
+#define L2CC_IPALR_C (0x1u << 0) /**< \brief (L2CC_IPALR) Cache Synchronization Status */
+#define L2CC_IPALR_IDX_Pos 5
+#define L2CC_IPALR_IDX_Msk (0x1ffu << L2CC_IPALR_IDX_Pos) /**< \brief (L2CC_IPALR) Index Number */
+#define L2CC_IPALR_IDX(value) ((L2CC_IPALR_IDX_Msk & ((value) << L2CC_IPALR_IDX_Pos)))
+#define L2CC_IPALR_TAG_Pos 14
+#define L2CC_IPALR_TAG_Msk (0x3ffffu << L2CC_IPALR_TAG_Pos) /**< \brief (L2CC_IPALR) Tag Number */
+#define L2CC_IPALR_TAG(value) ((L2CC_IPALR_TAG_Msk & ((value) << L2CC_IPALR_TAG_Pos)))
+/* -------- L2CC_IWR : (L2CC Offset: 0x77C) Invalidate Way Register -------- */
+#define L2CC_IWR_WAY0 (0x1u << 0) /**< \brief (L2CC_IWR) Invalidate Way Number 0 */
+#define L2CC_IWR_WAY1 (0x1u << 1) /**< \brief (L2CC_IWR) Invalidate Way Number 1 */
+#define L2CC_IWR_WAY2 (0x1u << 2) /**< \brief (L2CC_IWR) Invalidate Way Number 2 */
+#define L2CC_IWR_WAY3 (0x1u << 3) /**< \brief (L2CC_IWR) Invalidate Way Number 3 */
+#define L2CC_IWR_WAY4 (0x1u << 4) /**< \brief (L2CC_IWR) Invalidate Way Number 4 */
+#define L2CC_IWR_WAY5 (0x1u << 5) /**< \brief (L2CC_IWR) Invalidate Way Number 5 */
+#define L2CC_IWR_WAY6 (0x1u << 6) /**< \brief (L2CC_IWR) Invalidate Way Number 6 */
+#define L2CC_IWR_WAY7 (0x1u << 7) /**< \brief (L2CC_IWR) Invalidate Way Number 7 */
+/* -------- L2CC_CPALR : (L2CC Offset: 0x7B0) Clean Physical Address Line Register -------- */
+#define L2CC_CPALR_C (0x1u << 0) /**< \brief (L2CC_CPALR) Cache Synchronization Status */
+#define L2CC_CPALR_IDX_Pos 5
+#define L2CC_CPALR_IDX_Msk (0x1ffu << L2CC_CPALR_IDX_Pos) /**< \brief (L2CC_CPALR) Index number */
+#define L2CC_CPALR_IDX(value) ((L2CC_CPALR_IDX_Msk & ((value) << L2CC_CPALR_IDX_Pos)))
+#define L2CC_CPALR_TAG_Pos 14
+#define L2CC_CPALR_TAG_Msk (0x3ffffu << L2CC_CPALR_TAG_Pos) /**< \brief (L2CC_CPALR) Tag number */
+#define L2CC_CPALR_TAG(value) ((L2CC_CPALR_TAG_Msk & ((value) << L2CC_CPALR_TAG_Pos)))
+/* -------- L2CC_CIR : (L2CC Offset: 0x7B8) Clean Index Register -------- */
+#define L2CC_CIR_C (0x1u << 0) /**< \brief (L2CC_CIR) Cache Synchronization Status */
+#define L2CC_CIR_IDX_Pos 5
+#define L2CC_CIR_IDX_Msk (0x1ffu << L2CC_CIR_IDX_Pos) /**< \brief (L2CC_CIR) Index number */
+#define L2CC_CIR_IDX(value) ((L2CC_CIR_IDX_Msk & ((value) << L2CC_CIR_IDX_Pos)))
+#define L2CC_CIR_WAY_Pos 28
+#define L2CC_CIR_WAY_Msk (0x7u << L2CC_CIR_WAY_Pos) /**< \brief (L2CC_CIR) Way number */
+#define L2CC_CIR_WAY(value) ((L2CC_CIR_WAY_Msk & ((value) << L2CC_CIR_WAY_Pos)))
+/* -------- L2CC_CWR : (L2CC Offset: 0x7BC) Clean Way Register -------- */
+#define L2CC_CWR_WAY0 (0x1u << 0) /**< \brief (L2CC_CWR) Clean Way Number 0 */
+#define L2CC_CWR_WAY1 (0x1u << 1) /**< \brief (L2CC_CWR) Clean Way Number 1 */
+#define L2CC_CWR_WAY2 (0x1u << 2) /**< \brief (L2CC_CWR) Clean Way Number 2 */
+#define L2CC_CWR_WAY3 (0x1u << 3) /**< \brief (L2CC_CWR) Clean Way Number 3 */
+#define L2CC_CWR_WAY4 (0x1u << 4) /**< \brief (L2CC_CWR) Clean Way Number 4 */
+#define L2CC_CWR_WAY5 (0x1u << 5) /**< \brief (L2CC_CWR) Clean Way Number 5 */
+#define L2CC_CWR_WAY6 (0x1u << 6) /**< \brief (L2CC_CWR) Clean Way Number 6 */
+#define L2CC_CWR_WAY7 (0x1u << 7) /**< \brief (L2CC_CWR) Clean Way Number 7 */
+/* -------- L2CC_CIPALR : (L2CC Offset: 0x7F0) Clean Invalidate Physical Address Line Register -------- */
+#define L2CC_CIPALR_C (0x1u << 0) /**< \brief (L2CC_CIPALR) Cache Synchronization Status */
+#define L2CC_CIPALR_IDX_Pos 5
+#define L2CC_CIPALR_IDX_Msk (0x1ffu << L2CC_CIPALR_IDX_Pos) /**< \brief (L2CC_CIPALR) Index Number */
+#define L2CC_CIPALR_IDX(value) ((L2CC_CIPALR_IDX_Msk & ((value) << L2CC_CIPALR_IDX_Pos)))
+#define L2CC_CIPALR_TAG_Pos 14
+#define L2CC_CIPALR_TAG_Msk (0x3ffffu << L2CC_CIPALR_TAG_Pos) /**< \brief (L2CC_CIPALR) Tag Number */
+#define L2CC_CIPALR_TAG(value) ((L2CC_CIPALR_TAG_Msk & ((value) << L2CC_CIPALR_TAG_Pos)))
+/* -------- L2CC_CIIR : (L2CC Offset: 0x7F8) Clean Invalidate Index Register -------- */
+#define L2CC_CIIR_C (0x1u << 0) /**< \brief (L2CC_CIIR) Cache Synchronization Status */
+#define L2CC_CIIR_IDX_Pos 5
+#define L2CC_CIIR_IDX_Msk (0x1ffu << L2CC_CIIR_IDX_Pos) /**< \brief (L2CC_CIIR) Index Number */
+#define L2CC_CIIR_IDX(value) ((L2CC_CIIR_IDX_Msk & ((value) << L2CC_CIIR_IDX_Pos)))
+#define L2CC_CIIR_WAY_Pos 28
+#define L2CC_CIIR_WAY_Msk (0x7u << L2CC_CIIR_WAY_Pos) /**< \brief (L2CC_CIIR) Way Number */
+#define L2CC_CIIR_WAY(value) ((L2CC_CIIR_WAY_Msk & ((value) << L2CC_CIIR_WAY_Pos)))
+/* -------- L2CC_CIWR : (L2CC Offset: 0x7FC) Clean Invalidate Way Register -------- */
+#define L2CC_CIWR_WAY0 (0x1u << 0) /**< \brief (L2CC_CIWR) Clean Invalidate Way Number 0 */
+#define L2CC_CIWR_WAY1 (0x1u << 1) /**< \brief (L2CC_CIWR) Clean Invalidate Way Number 1 */
+#define L2CC_CIWR_WAY2 (0x1u << 2) /**< \brief (L2CC_CIWR) Clean Invalidate Way Number 2 */
+#define L2CC_CIWR_WAY3 (0x1u << 3) /**< \brief (L2CC_CIWR) Clean Invalidate Way Number 3 */
+#define L2CC_CIWR_WAY4 (0x1u << 4) /**< \brief (L2CC_CIWR) Clean Invalidate Way Number 4 */
+#define L2CC_CIWR_WAY5 (0x1u << 5) /**< \brief (L2CC_CIWR) Clean Invalidate Way Number 5 */
+#define L2CC_CIWR_WAY6 (0x1u << 6) /**< \brief (L2CC_CIWR) Clean Invalidate Way Number 6 */
+#define L2CC_CIWR_WAY7 (0x1u << 7) /**< \brief (L2CC_CIWR) Clean Invalidate Way Number 7 */
+/* -------- L2CC_DLKR : (L2CC Offset: 0x900) Data Lockdown Register -------- */
+#define L2CC_DLKR_DLK0 (0x1u << 0) /**< \brief (L2CC_DLKR) Data Lockdown in Way Number 0 */
+#define L2CC_DLKR_DLK1 (0x1u << 1) /**< \brief (L2CC_DLKR) Data Lockdown in Way Number 1 */
+#define L2CC_DLKR_DLK2 (0x1u << 2) /**< \brief (L2CC_DLKR) Data Lockdown in Way Number 2 */
+#define L2CC_DLKR_DLK3 (0x1u << 3) /**< \brief (L2CC_DLKR) Data Lockdown in Way Number 3 */
+#define L2CC_DLKR_DLK4 (0x1u << 4) /**< \brief (L2CC_DLKR) Data Lockdown in Way Number 4 */
+#define L2CC_DLKR_DLK5 (0x1u << 5) /**< \brief (L2CC_DLKR) Data Lockdown in Way Number 5 */
+#define L2CC_DLKR_DLK6 (0x1u << 6) /**< \brief (L2CC_DLKR) Data Lockdown in Way Number 6 */
+#define L2CC_DLKR_DLK7 (0x1u << 7) /**< \brief (L2CC_DLKR) Data Lockdown in Way Number 7 */
+/* -------- L2CC_ILKR : (L2CC Offset: 0x904) Instruction Lockdown Register -------- */
+#define L2CC_ILKR_ILK0 (0x1u << 0) /**< \brief (L2CC_ILKR) Instruction Lockdown in Way Number 0 */
+#define L2CC_ILKR_ILK1 (0x1u << 1) /**< \brief (L2CC_ILKR) Instruction Lockdown in Way Number 1 */
+#define L2CC_ILKR_ILK2 (0x1u << 2) /**< \brief (L2CC_ILKR) Instruction Lockdown in Way Number 2 */
+#define L2CC_ILKR_ILK3 (0x1u << 3) /**< \brief (L2CC_ILKR) Instruction Lockdown in Way Number 3 */
+#define L2CC_ILKR_ILK4 (0x1u << 4) /**< \brief (L2CC_ILKR) Instruction Lockdown in Way Number 4 */
+#define L2CC_ILKR_ILK5 (0x1u << 5) /**< \brief (L2CC_ILKR) Instruction Lockdown in Way Number 5 */
+#define L2CC_ILKR_ILK6 (0x1u << 6) /**< \brief (L2CC_ILKR) Instruction Lockdown in Way Number 6 */
+#define L2CC_ILKR_ILK7 (0x1u << 7) /**< \brief (L2CC_ILKR) Instruction Lockdown in Way Number 7 */
+/* -------- L2CC_DCR : (L2CC Offset: 0xF40) Debug Control Register -------- */
+#define L2CC_DCR_DCL (0x1u << 0) /**< \brief (L2CC_DCR) Disable Cache Linefill */
+#define L2CC_DCR_DWB (0x1u << 1) /**< \brief (L2CC_DCR) Disable Write-back, Force Write-through */
+#define L2CC_DCR_SPNIDEN (0x1u << 2) /**< \brief (L2CC_DCR) SPNIDEN Value */
+/* -------- L2CC_PCR : (L2CC Offset: 0xF60) Prefetch Control Register -------- */
+#define L2CC_PCR_OFFSET_Pos 0
+#define L2CC_PCR_OFFSET_Msk (0x1fu << L2CC_PCR_OFFSET_Pos) /**< \brief (L2CC_PCR) Prefetch Offset */
+#define L2CC_PCR_OFFSET(value) ((L2CC_PCR_OFFSET_Msk & ((value) << L2CC_PCR_OFFSET_Pos)))
+#define L2CC_PCR_NSIDEN (0x1u << 21) /**< \brief (L2CC_PCR) Not Same ID on Exclusive Sequence Enable */
+#define L2CC_PCR_IDLEN (0x1u << 23) /**< \brief (L2CC_PCR) INCR Double Linefill Enable */
+#define L2CC_PCR_PDEN (0x1u << 24) /**< \brief (L2CC_PCR) Prefetch Drop Enable */
+#define L2CC_PCR_DLFWRDIS (0x1u << 27) /**< \brief (L2CC_PCR) Double Linefill on WRAP Read Disable */
+#define L2CC_PCR_DATPEN (0x1u << 28) /**< \brief (L2CC_PCR) Data Prefetch Enable */
+#define L2CC_PCR_INSPEN (0x1u << 29) /**< \brief (L2CC_PCR) Instruction Prefetch Enable */
+#define L2CC_PCR_DLEN (0x1u << 30) /**< \brief (L2CC_PCR) Double Linefill Enable */
+/* -------- L2CC_POWCR : (L2CC Offset: 0xF80) Power Control Register -------- */
+#define L2CC_POWCR_STBYEN (0x1u << 0) /**< \brief (L2CC_POWCR) Standby Mode Enable */
+#define L2CC_POWCR_DCKGATEN (0x1u << 1) /**< \brief (L2CC_POWCR) Dynamic Clock Gating Enable */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_L2CC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_lcdc.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_lcdc.h
new file mode 100644
index 000000000..0bd702c3f
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_lcdc.h
@@ -0,0 +1,1499 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_LCDC_COMPONENT_
+#define _SAMA5D2_LCDC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR LCD Controller */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_LCDC LCD Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Lcdc hardware registers */
+typedef struct {
+  __IO uint32_t LCDC_LCDCFG0;       /**< \brief (Lcdc Offset: 0x00000000) LCD Controller Configuration Register 0 */
+  __IO uint32_t LCDC_LCDCFG1;       /**< \brief (Lcdc Offset: 0x00000004) LCD Controller Configuration Register 1 */
+  __IO uint32_t LCDC_LCDCFG2;       /**< \brief (Lcdc Offset: 0x00000008) LCD Controller Configuration Register 2 */
+  __IO uint32_t LCDC_LCDCFG3;       /**< \brief (Lcdc Offset: 0x0000000C) LCD Controller Configuration Register 3 */
+  __IO uint32_t LCDC_LCDCFG4;       /**< \brief (Lcdc Offset: 0x00000010) LCD Controller Configuration Register 4 */
+  __IO uint32_t LCDC_LCDCFG5;       /**< \brief (Lcdc Offset: 0x00000014) LCD Controller Configuration Register 5 */
+  __IO uint32_t LCDC_LCDCFG6;       /**< \brief (Lcdc Offset: 0x00000018) LCD Controller Configuration Register 6 */
+  __I  uint32_t Reserved1[1];
+  __O  uint32_t LCDC_LCDEN;         /**< \brief (Lcdc Offset: 0x00000020) LCD Controller Enable Register */
+  __O  uint32_t LCDC_LCDDIS;        /**< \brief (Lcdc Offset: 0x00000024) LCD Controller Disable Register */
+  __I  uint32_t LCDC_LCDSR;         /**< \brief (Lcdc Offset: 0x00000028) LCD Controller Status Register */
+  __O  uint32_t LCDC_LCDIER;        /**< \brief (Lcdc Offset: 0x0000002C) LCD Controller Interrupt Enable Register */
+  __O  uint32_t LCDC_LCDIDR;        /**< \brief (Lcdc Offset: 0x00000030) LCD Controller Interrupt Disable Register */
+  __I  uint32_t LCDC_LCDIMR;        /**< \brief (Lcdc Offset: 0x00000034) LCD Controller Interrupt Mask Register */
+  __I  uint32_t LCDC_LCDISR;        /**< \brief (Lcdc Offset: 0x00000038) LCD Controller Interrupt Status Register */
+  __O  uint32_t LCDC_ATTR;          /**< \brief (Lcdc Offset: 0x0000003C) LCD Controller Attribute Register */
+  __O  uint32_t LCDC_BASECHER;      /**< \brief (Lcdc Offset: 0x00000040) Base Layer Channel Enable Register */
+  __O  uint32_t LCDC_BASECHDR;      /**< \brief (Lcdc Offset: 0x00000044) Base Layer Channel Disable Register */
+  __I  uint32_t LCDC_BASECHSR;      /**< \brief (Lcdc Offset: 0x00000048) Base Layer Channel Status Register */
+  __O  uint32_t LCDC_BASEIER;       /**< \brief (Lcdc Offset: 0x0000004C) Base Layer Interrupt Enable Register */
+  __O  uint32_t LCDC_BASEIDR;       /**< \brief (Lcdc Offset: 0x00000050) Base Layer Interrupt Disabled Register */
+  __I  uint32_t LCDC_BASEIMR;       /**< \brief (Lcdc Offset: 0x00000054) Base Layer Interrupt Mask Register */
+  __I  uint32_t LCDC_BASEISR;       /**< \brief (Lcdc Offset: 0x00000058) Base Layer Interrupt Status Register */
+  __IO uint32_t LCDC_BASEHEAD;      /**< \brief (Lcdc Offset: 0x0000005C) Base DMA Head Register */
+  __IO uint32_t LCDC_BASEADDR;      /**< \brief (Lcdc Offset: 0x00000060) Base DMA Address Register */
+  __IO uint32_t LCDC_BASECTRL;      /**< \brief (Lcdc Offset: 0x00000064) Base DMA Control Register */
+  __IO uint32_t LCDC_BASENEXT;      /**< \brief (Lcdc Offset: 0x00000068) Base DMA Next Register */
+  __IO uint32_t LCDC_BASECFG0;      /**< \brief (Lcdc Offset: 0x0000006C) Base Layer Configuration Register 0 */
+  __IO uint32_t LCDC_BASECFG1;      /**< \brief (Lcdc Offset: 0x00000070) Base Layer Configuration Register 1 */
+  __IO uint32_t LCDC_BASECFG2;      /**< \brief (Lcdc Offset: 0x00000074) Base Layer Configuration Register 2 */
+  __IO uint32_t LCDC_BASECFG3;      /**< \brief (Lcdc Offset: 0x00000078) Base Layer Configuration Register 3 */
+  __IO uint32_t LCDC_BASECFG4;      /**< \brief (Lcdc Offset: 0x0000007C) Base Layer Configuration Register 4 */
+  __IO uint32_t LCDC_BASECFG5;      /**< \brief (Lcdc Offset: 0x00000080) Base Layer Configuration Register 5 */
+  __IO uint32_t LCDC_BASECFG6;      /**< \brief (Lcdc Offset: 0x00000084) Base Layer Configuration Register 6 */
+  __I  uint32_t Reserved2[46];
+  __O  uint32_t LCDC_OVR1CHER;      /**< \brief (Lcdc Offset: 0x00000140) Overlay 1 Channel Enable Register */
+  __O  uint32_t LCDC_OVR1CHDR;      /**< \brief (Lcdc Offset: 0x00000144) Overlay 1 Channel Disable Register */
+  __I  uint32_t LCDC_OVR1CHSR;      /**< \brief (Lcdc Offset: 0x00000148) Overlay 1 Channel Status Register */
+  __O  uint32_t LCDC_OVR1IER;       /**< \brief (Lcdc Offset: 0x0000014C) Overlay 1 Interrupt Enable Register */
+  __O  uint32_t LCDC_OVR1IDR;       /**< \brief (Lcdc Offset: 0x00000150) Overlay 1 Interrupt Disable Register */
+  __I  uint32_t LCDC_OVR1IMR;       /**< \brief (Lcdc Offset: 0x00000154) Overlay 1 Interrupt Mask Register */
+  __I  uint32_t LCDC_OVR1ISR;       /**< \brief (Lcdc Offset: 0x00000158) Overlay 1 Interrupt Status Register */
+  __IO uint32_t LCDC_OVR1HEAD;      /**< \brief (Lcdc Offset: 0x0000015C) Overlay 1 DMA Head Register */
+  __IO uint32_t LCDC_OVR1ADDR;      /**< \brief (Lcdc Offset: 0x00000160) Overlay 1 DMA Address Register */
+  __IO uint32_t LCDC_OVR1CTRL;      /**< \brief (Lcdc Offset: 0x00000164) Overlay 1 DMA Control Register */
+  __IO uint32_t LCDC_OVR1NEXT;      /**< \brief (Lcdc Offset: 0x00000168) Overlay 1 DMA Next Register */
+  __IO uint32_t LCDC_OVR1CFG0;      /**< \brief (Lcdc Offset: 0x0000016C) Overlay 1 Configuration Register 0 */
+  __IO uint32_t LCDC_OVR1CFG1;      /**< \brief (Lcdc Offset: 0x00000170) Overlay 1 Configuration Register 1 */
+  __IO uint32_t LCDC_OVR1CFG2;      /**< \brief (Lcdc Offset: 0x00000174) Overlay 1 Configuration Register 2 */
+  __IO uint32_t LCDC_OVR1CFG3;      /**< \brief (Lcdc Offset: 0x00000178) Overlay 1 Configuration Register 3 */
+  __IO uint32_t LCDC_OVR1CFG4;      /**< \brief (Lcdc Offset: 0x0000017C) Overlay 1 Configuration Register 4 */
+  __IO uint32_t LCDC_OVR1CFG5;      /**< \brief (Lcdc Offset: 0x00000180) Overlay 1 Configuration Register 5 */
+  __IO uint32_t LCDC_OVR1CFG6;      /**< \brief (Lcdc Offset: 0x00000184) Overlay 1 Configuration Register 6 */
+  __IO uint32_t LCDC_OVR1CFG7;      /**< \brief (Lcdc Offset: 0x00000188) Overlay 1 Configuration Register 7 */
+  __IO uint32_t LCDC_OVR1CFG8;      /**< \brief (Lcdc Offset: 0x0000018C) Overlay 1 Configuration Register 8 */
+  __IO uint32_t LCDC_OVR1CFG9;      /**< \brief (Lcdc Offset: 0x00000190) Overlay 1 Configuration Register 9 */
+  __I  uint32_t Reserved3[43];
+  __O  uint32_t LCDC_OVR2CHER;      /**< \brief (Lcdc Offset: 0x00000240) Overlay 2 Channel Enable Register */
+  __O  uint32_t LCDC_OVR2CHDR;      /**< \brief (Lcdc Offset: 0x00000244) Overlay 2 Channel Disable Register */
+  __I  uint32_t LCDC_OVR2CHSR;      /**< \brief (Lcdc Offset: 0x00000248) Overlay 2 Channel Status Register */
+  __O  uint32_t LCDC_OVR2IER;       /**< \brief (Lcdc Offset: 0x0000024C) Overlay 2 Interrupt Enable Register */
+  __O  uint32_t LCDC_OVR2IDR;       /**< \brief (Lcdc Offset: 0x00000250) Overlay 2 Interrupt Disable Register */
+  __I  uint32_t LCDC_OVR2IMR;       /**< \brief (Lcdc Offset: 0x00000254) Overlay 2 Interrupt Mask Register */
+  __I  uint32_t LCDC_OVR2ISR;       /**< \brief (Lcdc Offset: 0x00000258) Overlay 2 Interrupt Status Register */
+  __IO uint32_t LCDC_OVR2HEAD;      /**< \brief (Lcdc Offset: 0x0000025C) Overlay 2 DMA Head Register */
+  __IO uint32_t LCDC_OVR2ADDR;      /**< \brief (Lcdc Offset: 0x00000260) Overlay 2 DMA Address Register */
+  __IO uint32_t LCDC_OVR2CTRL;      /**< \brief (Lcdc Offset: 0x00000264) Overlay 2 DMA Control Register */
+  __IO uint32_t LCDC_OVR2NEXT;      /**< \brief (Lcdc Offset: 0x00000268) Overlay 2 DMA Next Register */
+  __IO uint32_t LCDC_OVR2CFG0;      /**< \brief (Lcdc Offset: 0x0000026C) Overlay 2 Configuration Register 0 */
+  __IO uint32_t LCDC_OVR2CFG1;      /**< \brief (Lcdc Offset: 0x00000270) Overlay 2 Configuration Register 1 */
+  __IO uint32_t LCDC_OVR2CFG2;      /**< \brief (Lcdc Offset: 0x00000274) Overlay 2 Configuration Register 2 */
+  __IO uint32_t LCDC_OVR2CFG3;      /**< \brief (Lcdc Offset: 0x00000278) Overlay 2 Configuration Register 3 */
+  __IO uint32_t LCDC_OVR2CFG4;      /**< \brief (Lcdc Offset: 0x0000027C) Overlay 2 Configuration Register 4 */
+  __IO uint32_t LCDC_OVR2CFG5;      /**< \brief (Lcdc Offset: 0x00000280) Overlay 2 Configuration Register 5 */
+  __IO uint32_t LCDC_OVR2CFG6;      /**< \brief (Lcdc Offset: 0x00000284) Overlay 2 Configuration Register 6 */
+  __IO uint32_t LCDC_OVR2CFG7;      /**< \brief (Lcdc Offset: 0x00000288) Overlay 2 Configuration Register 7 */
+  __IO uint32_t LCDC_OVR2CFG8;      /**< \brief (Lcdc Offset: 0x0000028C) Overlay 2 Configuration Register 8 */
+  __IO uint32_t LCDC_OVR2CFG9;      /**< \brief (Lcdc Offset: 0x00000290) Overlay 2 Configuration Register 8 */
+  __I  uint32_t Reserved4[43];
+  __O  uint32_t LCDC_HEOCHER;       /**< \brief (Lcdc Offset: 0x00000340) High End Overlay Channel Enable Register */
+  __O  uint32_t LCDC_HEOCHDR;       /**< \brief (Lcdc Offset: 0x00000344) High End Overlay Channel Disable Register */
+  __I  uint32_t LCDC_HEOCHSR;       /**< \brief (Lcdc Offset: 0x00000348) High End Overlay Channel Status Register */
+  __O  uint32_t LCDC_HEOIER;        /**< \brief (Lcdc Offset: 0x0000034C) High End Overlay Interrupt Enable Register */
+  __O  uint32_t LCDC_HEOIDR;        /**< \brief (Lcdc Offset: 0x00000350) High End Overlay Interrupt Disable Register */
+  __I  uint32_t LCDC_HEOIMR;        /**< \brief (Lcdc Offset: 0x00000354) High End Overlay Interrupt Mask Register */
+  __I  uint32_t LCDC_HEOISR;        /**< \brief (Lcdc Offset: 0x00000358) High End Overlay Interrupt Status Register */
+  __IO uint32_t LCDC_HEOHEAD;       /**< \brief (Lcdc Offset: 0x0000035C) High End Overlay DMA Head Register */
+  __IO uint32_t LCDC_HEOADDR;       /**< \brief (Lcdc Offset: 0x00000360) High End Overlay DMA Address Register */
+  __IO uint32_t LCDC_HEOCTRL;       /**< \brief (Lcdc Offset: 0x00000364) High End Overlay DMA Control Register */
+  __IO uint32_t LCDC_HEONEXT;       /**< \brief (Lcdc Offset: 0x00000368) High End Overlay DMA Next Register */
+  __IO uint32_t LCDC_HEOUHEAD;      /**< \brief (Lcdc Offset: 0x0000036C) High End Overlay U-UV DMA Head Register */
+  __IO uint32_t LCDC_HEOUADDR;      /**< \brief (Lcdc Offset: 0x00000370) High End Overlay U-UV DMA Address Register */
+  __IO uint32_t LCDC_HEOUCTRL;      /**< \brief (Lcdc Offset: 0x00000374) High End Overlay U-UV DMA Control Register */
+  __IO uint32_t LCDC_HEOUNEXT;      /**< \brief (Lcdc Offset: 0x00000378) High End Overlay U-UV DMA Next Register */
+  __IO uint32_t LCDC_HEOVHEAD;      /**< \brief (Lcdc Offset: 0x0000037C) High End Overlay V DMA Head Register */
+  __IO uint32_t LCDC_HEOVADDR;      /**< \brief (Lcdc Offset: 0x00000380) High End Overlay V DMA Address Register */
+  __IO uint32_t LCDC_HEOVCTRL;      /**< \brief (Lcdc Offset: 0x00000384) High End Overlay V DMA Control Register */
+  __IO uint32_t LCDC_HEOVNEXT;      /**< \brief (Lcdc Offset: 0x00000388) High End Overlay V DMA Next Register */
+  __IO uint32_t LCDC_HEOCFG0;       /**< \brief (Lcdc Offset: 0x0000038C) High End Overlay Configuration Register 0 */
+  __IO uint32_t LCDC_HEOCFG1;       /**< \brief (Lcdc Offset: 0x00000390) High End Overlay Configuration Register 1 */
+  __IO uint32_t LCDC_HEOCFG2;       /**< \brief (Lcdc Offset: 0x00000394) High End Overlay Configuration Register 2 */
+  __IO uint32_t LCDC_HEOCFG3;       /**< \brief (Lcdc Offset: 0x00000398) High End Overlay Configuration Register 3 */
+  __IO uint32_t LCDC_HEOCFG4;       /**< \brief (Lcdc Offset: 0x0000039C) High End Overlay Configuration Register 4 */
+  __IO uint32_t LCDC_HEOCFG5;       /**< \brief (Lcdc Offset: 0x000003A0) High End Overlay Configuration Register 5 */
+  __IO uint32_t LCDC_HEOCFG6;       /**< \brief (Lcdc Offset: 0x000003A4) High End Overlay Configuration Register 6 */
+  __IO uint32_t LCDC_HEOCFG7;       /**< \brief (Lcdc Offset: 0x000003A8) High End Overlay Configuration Register 7 */
+  __IO uint32_t LCDC_HEOCFG8;       /**< \brief (Lcdc Offset: 0x000003AC) High End Overlay Configuration Register 8 */
+  __IO uint32_t LCDC_HEOCFG9;       /**< \brief (Lcdc Offset: 0x000003B0) High End Overlay Configuration Register 9 */
+  __IO uint32_t LCDC_HEOCFG10;      /**< \brief (Lcdc Offset: 0x000003B4) High End Overlay Configuration Register 10 */
+  __IO uint32_t LCDC_HEOCFG11;      /**< \brief (Lcdc Offset: 0x000003B8) High End Overlay Configuration Register 11 */
+  __IO uint32_t LCDC_HEOCFG12;      /**< \brief (Lcdc Offset: 0x000003BC) High End Overlay Configuration Register 12 */
+  __IO uint32_t LCDC_HEOCFG13;      /**< \brief (Lcdc Offset: 0x000003C0) High End Overlay Configuration Register 13 */
+  __IO uint32_t LCDC_HEOCFG14;      /**< \brief (Lcdc Offset: 0x000003C4) High End Overlay Configuration Register 14 */
+  __IO uint32_t LCDC_HEOCFG15;      /**< \brief (Lcdc Offset: 0x000003C8) High End Overlay Configuration Register 15 */
+  __IO uint32_t LCDC_HEOCFG16;      /**< \brief (Lcdc Offset: 0x000003CC) High End Overlay Configuration Register 16 */
+  __IO uint32_t LCDC_HEOCFG17;      /**< \brief (Lcdc Offset: 0x000003D0) High End Overlay Configuration Register 17 */
+  __IO uint32_t LCDC_HEOCFG18;      /**< \brief (Lcdc Offset: 0x000003D4) High End Overlay Configuration Register 18 */
+  __IO uint32_t LCDC_HEOCFG19;      /**< \brief (Lcdc Offset: 0x000003D8) High End Overlay Configuration Register 19 */
+  __IO uint32_t LCDC_HEOCFG20;      /**< \brief (Lcdc Offset: 0x000003DC) High End Overlay Configuration Register 20 */
+  __IO uint32_t LCDC_HEOCFG21;      /**< \brief (Lcdc Offset: 0x000003E0) High End Overlay Configuration Register 21 */
+  __IO uint32_t LCDC_HEOCFG22;      /**< \brief (Lcdc Offset: 0x000003E4) High End Overlay Configuration Register 22 */
+  __IO uint32_t LCDC_HEOCFG23;      /**< \brief (Lcdc Offset: 0x000003E8) High End Overlay Configuration Register 23 */
+  __IO uint32_t LCDC_HEOCFG24;      /**< \brief (Lcdc Offset: 0x000003EC) High End Overlay Configuration Register 24 */
+  __IO uint32_t LCDC_HEOCFG25;      /**< \brief (Lcdc Offset: 0x000003F0) High End Overlay Configuration Register 25 */
+  __IO uint32_t LCDC_HEOCFG26;      /**< \brief (Lcdc Offset: 0x000003F4) High End Overlay Configuration Register 26 */
+  __IO uint32_t LCDC_HEOCFG27;      /**< \brief (Lcdc Offset: 0x000003F8) High End Overlay Configuration Register 27 */
+  __IO uint32_t LCDC_HEOCFG28;      /**< \brief (Lcdc Offset: 0x000003FC) High End Overlay Configuration Register 28 */
+  __IO uint32_t LCDC_HEOCFG29;      /**< \brief (Lcdc Offset: 0x00000400) High End Overlay Configuration Register 29 */
+  __IO uint32_t LCDC_HEOCFG30;      /**< \brief (Lcdc Offset: 0x00000404) High End Overlay Configuration Register 30 */
+  __IO uint32_t LCDC_HEOCFG31;      /**< \brief (Lcdc Offset: 0x00000408) High End Overlay Configuration Register 31 */
+  __IO uint32_t LCDC_HEOCFG32;      /**< \brief (Lcdc Offset: 0x0000040C) High End Overlay Configuration Register 32 */
+  __IO uint32_t LCDC_HEOCFG33;      /**< \brief (Lcdc Offset: 0x00000410) High End Overlay Configuration Register 33 */
+  __IO uint32_t LCDC_HEOCFG34;      /**< \brief (Lcdc Offset: 0x00000414) High End Overlay Configuration Register 34 */
+  __IO uint32_t LCDC_HEOCFG35;      /**< \brief (Lcdc Offset: 0x00000418) High End Overlay Configuration Register 35 */
+  __IO uint32_t LCDC_HEOCFG36;      /**< \brief (Lcdc Offset: 0x0000041C) High End Overlay Configuration Register 36 */
+  __IO uint32_t LCDC_HEOCFG37;      /**< \brief (Lcdc Offset: 0x00000420) High End Overlay Configuration Register 37 */
+  __IO uint32_t LCDC_HEOCFG38;      /**< \brief (Lcdc Offset: 0x00000424) High End Overlay Configuration Register 38 */
+  __IO uint32_t LCDC_HEOCFG39;      /**< \brief (Lcdc Offset: 0x00000428) High End Overlay Configuration Register 39 */
+  __IO uint32_t LCDC_HEOCFG40;      /**< \brief (Lcdc Offset: 0x0000042C) High End Overlay Configuration Register 40 */
+  __IO uint32_t LCDC_HEOCFG41;      /**< \brief (Lcdc Offset: 0x00000430) High End Overlay Configuration Register 41 */
+  __I  uint32_t Reserved5[67];
+  __O  uint32_t LCDC_PPCHER;        /**< \brief (Lcdc Offset: 0x00000540) Post Processing Channel Enable Register */
+  __O  uint32_t LCDC_PPCHDR;        /**< \brief (Lcdc Offset: 0x00000544) Post Processing Channel Disable Register */
+  __I  uint32_t LCDC_PPCHSR;        /**< \brief (Lcdc Offset: 0x00000548) Post Processing Channel Status Register */
+  __O  uint32_t LCDC_PPIER;         /**< \brief (Lcdc Offset: 0x0000054C) Post Processing Interrupt Enable Register */
+  __O  uint32_t LCDC_PPIDR;         /**< \brief (Lcdc Offset: 0x00000550) Post Processing Interrupt Disable Register */
+  __I  uint32_t LCDC_PPIMR;         /**< \brief (Lcdc Offset: 0x00000554) Post Processing Interrupt Mask Register */
+  __I  uint32_t LCDC_PPISR;         /**< \brief (Lcdc Offset: 0x00000558) Post Processing Interrupt Status Register */
+  __IO uint32_t LCDC_PPHEAD;        /**< \brief (Lcdc Offset: 0x0000055C) Post Processing Head Register */
+  __IO uint32_t LCDC_PPADDR;        /**< \brief (Lcdc Offset: 0x00000560) Post Processing Address Register */
+  __IO uint32_t LCDC_PPCTRL;        /**< \brief (Lcdc Offset: 0x00000564) Post Processing Control Register */
+  __IO uint32_t LCDC_PPNEXT;        /**< \brief (Lcdc Offset: 0x00000568) Post Processing Next Register */
+  __IO uint32_t LCDC_PPCFG0;        /**< \brief (Lcdc Offset: 0x0000056C) Post Processing Configuration Register 0 */
+  __IO uint32_t LCDC_PPCFG1;        /**< \brief (Lcdc Offset: 0x00000570) Post Processing Configuration Register 1 */
+  __IO uint32_t LCDC_PPCFG2;        /**< \brief (Lcdc Offset: 0x00000574) Post Processing Configuration Register 2 */
+  __IO uint32_t LCDC_PPCFG3;        /**< \brief (Lcdc Offset: 0x00000578) Post Processing Configuration Register 3 */
+  __IO uint32_t LCDC_PPCFG4;        /**< \brief (Lcdc Offset: 0x0000057C) Post Processing Configuration Register 4 */
+  __IO uint32_t LCDC_PPCFG5;        /**< \brief (Lcdc Offset: 0x00000580) Post Processing Configuration Register 5 */
+  __I  uint32_t Reserved6[31];
+  __IO uint32_t LCDC_BASECLUT[256]; /**< \brief (Lcdc Offset: 0x00000600) Base CLUT Register */
+  __IO uint32_t LCDC_OVR1CLUT[256]; /**< \brief (Lcdc Offset: 0x00000A00) Overlay 1 CLUT Register */
+  __IO uint32_t LCDC_OVR2CLUT[256]; /**< \brief (Lcdc Offset: 0x00000E00) Overlay 2 CLUT Register */
+  __IO uint32_t LCDC_HEOCLUT[256];  /**< \brief (Lcdc Offset: 0x00001200) High End Overlay CLUT Register */
+  __I  uint32_t Reserved7[639];
+  __I  uint32_t LCDC_VERSION;       /**< \brief (Lcdc Offset: 0x00001FFC) Version Register */
+} Lcdc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- LCDC_LCDCFG0 : (LCDC Offset: 0x00000000) LCD Controller Configuration Register 0 -------- */
+#define LCDC_LCDCFG0_CLKPOL (0x1u << 0) /**< \brief (LCDC_LCDCFG0) LCD Controller Clock Polarity */
+#define LCDC_LCDCFG0_CLKSEL (0x1u << 2) /**< \brief (LCDC_LCDCFG0) LCD Controller Clock Source Selection */
+#define LCDC_LCDCFG0_CLKPWMSEL (0x1u << 3) /**< \brief (LCDC_LCDCFG0) LCD Controller PWM Clock Source Selection */
+#define LCDC_LCDCFG0_CGDISBASE (0x1u << 8) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the Base Layer */
+#define LCDC_LCDCFG0_CGDISOVR1 (0x1u << 9) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the Overlay 1 Layer */
+#define LCDC_LCDCFG0_CGDISOVR2 (0x1u << 10) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the Overlay 2 Layer */
+#define LCDC_LCDCFG0_CGDISHEO (0x1u << 11) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the High End Overlay */
+#define LCDC_LCDCFG0_CGDISPP (0x1u << 13) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the Post Processing Layer */
+#define LCDC_LCDCFG0_CLKDIV_Pos 16
+#define LCDC_LCDCFG0_CLKDIV_Msk (0xffu << LCDC_LCDCFG0_CLKDIV_Pos) /**< \brief (LCDC_LCDCFG0) LCD Controller Clock Divider */
+#define LCDC_LCDCFG0_CLKDIV(value) ((LCDC_LCDCFG0_CLKDIV_Msk & ((value) << LCDC_LCDCFG0_CLKDIV_Pos)))
+/* -------- LCDC_LCDCFG1 : (LCDC Offset: 0x00000004) LCD Controller Configuration Register 1 -------- */
+#define LCDC_LCDCFG1_HSPW_Pos 0
+#define LCDC_LCDCFG1_HSPW_Msk (0xffu << LCDC_LCDCFG1_HSPW_Pos) /**< \brief (LCDC_LCDCFG1) Horizontal Synchronization Pulse Width */
+#define LCDC_LCDCFG1_HSPW(value) ((LCDC_LCDCFG1_HSPW_Msk & ((value) << LCDC_LCDCFG1_HSPW_Pos)))
+#define LCDC_LCDCFG1_VSPW_Pos 16
+#define LCDC_LCDCFG1_VSPW_Msk (0xffu << LCDC_LCDCFG1_VSPW_Pos) /**< \brief (LCDC_LCDCFG1) Vertical Synchronization Pulse Width */
+#define LCDC_LCDCFG1_VSPW(value) ((LCDC_LCDCFG1_VSPW_Msk & ((value) << LCDC_LCDCFG1_VSPW_Pos)))
+/* -------- LCDC_LCDCFG2 : (LCDC Offset: 0x00000008) LCD Controller Configuration Register 2 -------- */
+#define LCDC_LCDCFG2_VFPW_Pos 0
+#define LCDC_LCDCFG2_VFPW_Msk (0xffu << LCDC_LCDCFG2_VFPW_Pos) /**< \brief (LCDC_LCDCFG2) Vertical Front Porch Width */
+#define LCDC_LCDCFG2_VFPW(value) ((LCDC_LCDCFG2_VFPW_Msk & ((value) << LCDC_LCDCFG2_VFPW_Pos)))
+#define LCDC_LCDCFG2_VBPW_Pos 16
+#define LCDC_LCDCFG2_VBPW_Msk (0xffu << LCDC_LCDCFG2_VBPW_Pos) /**< \brief (LCDC_LCDCFG2) Vertical Back Porch Width */
+#define LCDC_LCDCFG2_VBPW(value) ((LCDC_LCDCFG2_VBPW_Msk & ((value) << LCDC_LCDCFG2_VBPW_Pos)))
+/* -------- LCDC_LCDCFG3 : (LCDC Offset: 0x0000000C) LCD Controller Configuration Register 3 -------- */
+#define LCDC_LCDCFG3_HFPW_Pos 0
+#define LCDC_LCDCFG3_HFPW_Msk (0x3ffu << LCDC_LCDCFG3_HFPW_Pos) /**< \brief (LCDC_LCDCFG3) Horizontal Front Porch Width */
+#define LCDC_LCDCFG3_HFPW(value) ((LCDC_LCDCFG3_HFPW_Msk & ((value) << LCDC_LCDCFG3_HFPW_Pos)))
+#define LCDC_LCDCFG3_HBPW_Pos 16
+#define LCDC_LCDCFG3_HBPW_Msk (0x3ffu << LCDC_LCDCFG3_HBPW_Pos) /**< \brief (LCDC_LCDCFG3) Horizontal Back Porch Width */
+#define LCDC_LCDCFG3_HBPW(value) ((LCDC_LCDCFG3_HBPW_Msk & ((value) << LCDC_LCDCFG3_HBPW_Pos)))
+/* -------- LCDC_LCDCFG4 : (LCDC Offset: 0x00000010) LCD Controller Configuration Register 4 -------- */
+#define LCDC_LCDCFG4_PPL_Pos 0
+#define LCDC_LCDCFG4_PPL_Msk (0x7ffu << LCDC_LCDCFG4_PPL_Pos) /**< \brief (LCDC_LCDCFG4) Number of Pixels Per Line */
+#define LCDC_LCDCFG4_PPL(value) ((LCDC_LCDCFG4_PPL_Msk & ((value) << LCDC_LCDCFG4_PPL_Pos)))
+#define LCDC_LCDCFG4_RPF_Pos 16
+#define LCDC_LCDCFG4_RPF_Msk (0x7ffu << LCDC_LCDCFG4_RPF_Pos) /**< \brief (LCDC_LCDCFG4) Number of Active Row Per Frame */
+#define LCDC_LCDCFG4_RPF(value) ((LCDC_LCDCFG4_RPF_Msk & ((value) << LCDC_LCDCFG4_RPF_Pos)))
+/* -------- LCDC_LCDCFG5 : (LCDC Offset: 0x00000014) LCD Controller Configuration Register 5 -------- */
+#define LCDC_LCDCFG5_HSPOL (0x1u << 0) /**< \brief (LCDC_LCDCFG5) Horizontal Synchronization Pulse Polarity */
+#define LCDC_LCDCFG5_VSPOL (0x1u << 1) /**< \brief (LCDC_LCDCFG5) Vertical Synchronization Pulse Polarity */
+#define LCDC_LCDCFG5_VSPDLYS (0x1u << 2) /**< \brief (LCDC_LCDCFG5) Vertical Synchronization Pulse Start */
+#define LCDC_LCDCFG5_VSPDLYE (0x1u << 3) /**< \brief (LCDC_LCDCFG5) Vertical Synchronization Pulse End */
+#define LCDC_LCDCFG5_DISPPOL (0x1u << 4) /**< \brief (LCDC_LCDCFG5) Display Signal Polarity */
+#define LCDC_LCDCFG5_DITHER (0x1u << 6) /**< \brief (LCDC_LCDCFG5) LCD Controller Dithering */
+#define LCDC_LCDCFG5_DISPDLY (0x1u << 7) /**< \brief (LCDC_LCDCFG5) LCD Controller Display Power Signal Synchronization */
+#define LCDC_LCDCFG5_MODE_Pos 8
+#define LCDC_LCDCFG5_MODE_Msk (0x3u << LCDC_LCDCFG5_MODE_Pos) /**< \brief (LCDC_LCDCFG5) LCD Controller Output Mode */
+#define LCDC_LCDCFG5_MODE(value) ((LCDC_LCDCFG5_MODE_Msk & ((value) << LCDC_LCDCFG5_MODE_Pos)))
+#define   LCDC_LCDCFG5_MODE_OUTPUT_12BPP (0x0u << 8) /**< \brief (LCDC_LCDCFG5) LCD Output mode is set to 12 bits per pixel */
+#define   LCDC_LCDCFG5_MODE_OUTPUT_16BPP (0x1u << 8) /**< \brief (LCDC_LCDCFG5) LCD Output mode is set to 16 bits per pixel */
+#define   LCDC_LCDCFG5_MODE_OUTPUT_18BPP (0x2u << 8) /**< \brief (LCDC_LCDCFG5) LCD Output mode is set to 18 bits per pixel */
+#define   LCDC_LCDCFG5_MODE_OUTPUT_24BPP (0x3u << 8) /**< \brief (LCDC_LCDCFG5) LCD Output mode is set to 24 bits per pixel */
+#define LCDC_LCDCFG5_PP (0x1u << 10) /**< \brief (LCDC_LCDCFG5) Post Processing Enable */
+#define LCDC_LCDCFG5_VSPSU (0x1u << 12) /**< \brief (LCDC_LCDCFG5) LCD Controller Vertical synchronization Pulse Setup Configuration */
+#define LCDC_LCDCFG5_VSPHO (0x1u << 13) /**< \brief (LCDC_LCDCFG5) LCD Controller Vertical synchronization Pulse Hold Configuration */
+#define LCDC_LCDCFG5_GUARDTIME_Pos 16
+#define LCDC_LCDCFG5_GUARDTIME_Msk (0xffu << LCDC_LCDCFG5_GUARDTIME_Pos) /**< \brief (LCDC_LCDCFG5) LCD DISPLAY Guard Time */
+#define LCDC_LCDCFG5_GUARDTIME(value) ((LCDC_LCDCFG5_GUARDTIME_Msk & ((value) << LCDC_LCDCFG5_GUARDTIME_Pos)))
+/* -------- LCDC_LCDCFG6 : (LCDC Offset: 0x00000018) LCD Controller Configuration Register 6 -------- */
+#define LCDC_LCDCFG6_PWMPS_Pos 0
+#define LCDC_LCDCFG6_PWMPS_Msk (0x7u << LCDC_LCDCFG6_PWMPS_Pos) /**< \brief (LCDC_LCDCFG6) PWM Clock Prescaler */
+#define LCDC_LCDCFG6_PWMPS(value) ((LCDC_LCDCFG6_PWMPS_Msk & ((value) << LCDC_LCDCFG6_PWMPS_Pos)))
+#define   LCDC_LCDCFG6_PWMPS_DIV_1 (0x0u << 0) /**< \brief (LCDC_LCDCFG6) The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK */
+#define   LCDC_LCDCFG6_PWMPS_DIV_2 (0x1u << 0) /**< \brief (LCDC_LCDCFG6) The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/2 */
+#define   LCDC_LCDCFG6_PWMPS_DIV_4 (0x2u << 0) /**< \brief (LCDC_LCDCFG6) The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/4 */
+#define   LCDC_LCDCFG6_PWMPS_DIV_8 (0x3u << 0) /**< \brief (LCDC_LCDCFG6) The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/8 */
+#define   LCDC_LCDCFG6_PWMPS_DIV_16 (0x4u << 0) /**< \brief (LCDC_LCDCFG6) The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/16 */
+#define   LCDC_LCDCFG6_PWMPS_DIV_32 (0x5u << 0) /**< \brief (LCDC_LCDCFG6) The counter advances at a of rate fCOUNTER = fPWM_SELECTED_CLOCK/32 */
+#define   LCDC_LCDCFG6_PWMPS_DIV_64 (0x6u << 0) /**< \brief (LCDC_LCDCFG6) The counter advances at a of rate fCOUNTER = fPWM_SELECTED_CLOCK/64 */
+#define LCDC_LCDCFG6_PWMPOL (0x1u << 4) /**< \brief (LCDC_LCDCFG6) LCD Controller PWM Signal Polarity */
+#define LCDC_LCDCFG6_PWMCVAL_Pos 8
+#define LCDC_LCDCFG6_PWMCVAL_Msk (0xffu << LCDC_LCDCFG6_PWMCVAL_Pos) /**< \brief (LCDC_LCDCFG6) LCD Controller PWM Compare Value */
+#define LCDC_LCDCFG6_PWMCVAL(value) ((LCDC_LCDCFG6_PWMCVAL_Msk & ((value) << LCDC_LCDCFG6_PWMCVAL_Pos)))
+/* -------- LCDC_LCDEN : (LCDC Offset: 0x00000020) LCD Controller Enable Register -------- */
+#define LCDC_LCDEN_CLKEN (0x1u << 0) /**< \brief (LCDC_LCDEN) LCD Controller Pixel Clock Enable */
+#define LCDC_LCDEN_SYNCEN (0x1u << 1) /**< \brief (LCDC_LCDEN) LCD Controller Horizontal and Vertical Synchronization Enable */
+#define LCDC_LCDEN_DISPEN (0x1u << 2) /**< \brief (LCDC_LCDEN) LCD Controller DISP Signal Enable */
+#define LCDC_LCDEN_PWMEN (0x1u << 3) /**< \brief (LCDC_LCDEN) LCD Controller Pulse Width Modulation Enable */
+/* -------- LCDC_LCDDIS : (LCDC Offset: 0x00000024) LCD Controller Disable Register -------- */
+#define LCDC_LCDDIS_CLKDIS (0x1u << 0) /**< \brief (LCDC_LCDDIS) LCD Controller Pixel Clock Disable */
+#define LCDC_LCDDIS_SYNCDIS (0x1u << 1) /**< \brief (LCDC_LCDDIS) LCD Controller Horizontal and Vertical Synchronization Disable */
+#define LCDC_LCDDIS_DISPDIS (0x1u << 2) /**< \brief (LCDC_LCDDIS) LCD Controller DISP Signal Disable */
+#define LCDC_LCDDIS_PWMDIS (0x1u << 3) /**< \brief (LCDC_LCDDIS) LCD Controller Pulse Width Modulation Disable */
+#define LCDC_LCDDIS_CLKRST (0x1u << 8) /**< \brief (LCDC_LCDDIS) LCD Controller Clock Reset */
+#define LCDC_LCDDIS_SYNCRST (0x1u << 9) /**< \brief (LCDC_LCDDIS) LCD Controller Horizontal and Vertical Synchronization Reset */
+#define LCDC_LCDDIS_DISPRST (0x1u << 10) /**< \brief (LCDC_LCDDIS) LCD Controller DISP Signal Reset */
+#define LCDC_LCDDIS_PWMRST (0x1u << 11) /**< \brief (LCDC_LCDDIS) LCD Controller PWM Reset */
+/* -------- LCDC_LCDSR : (LCDC Offset: 0x00000028) LCD Controller Status Register -------- */
+#define LCDC_LCDSR_CLKSTS (0x1u << 0) /**< \brief (LCDC_LCDSR) Clock Status */
+#define LCDC_LCDSR_LCDSTS (0x1u << 1) /**< \brief (LCDC_LCDSR) LCD Controller Synchronization status */
+#define LCDC_LCDSR_DISPSTS (0x1u << 2) /**< \brief (LCDC_LCDSR) LCD Controller DISP Signal Status */
+#define LCDC_LCDSR_PWMSTS (0x1u << 3) /**< \brief (LCDC_LCDSR) LCD Controller PWM Signal Status */
+#define LCDC_LCDSR_SIPSTS (0x1u << 4) /**< \brief (LCDC_LCDSR) Synchronization In Progress */
+/* -------- LCDC_LCDIER : (LCDC Offset: 0x0000002C) LCD Controller Interrupt Enable Register -------- */
+#define LCDC_LCDIER_SOFIE (0x1u << 0) /**< \brief (LCDC_LCDIER) Start of Frame Interrupt Enable Register */
+#define LCDC_LCDIER_DISIE (0x1u << 1) /**< \brief (LCDC_LCDIER) LCD Disable Interrupt Enable Register */
+#define LCDC_LCDIER_DISPIE (0x1u << 2) /**< \brief (LCDC_LCDIER) Power UP/Down Sequence Terminated Interrupt Enable Register */
+#define LCDC_LCDIER_FIFOERRIE (0x1u << 4) /**< \brief (LCDC_LCDIER) Output FIFO Error Interrupt Enable Register */
+#define LCDC_LCDIER_BASEIE (0x1u << 8) /**< \brief (LCDC_LCDIER) Base Layer Interrupt Enable Register */
+#define LCDC_LCDIER_OVR1IE (0x1u << 9) /**< \brief (LCDC_LCDIER) Overlay 1 Interrupt Enable Register */
+#define LCDC_LCDIER_OVR2IE (0x1u << 10) /**< \brief (LCDC_LCDIER) Overlay 2 Interrupt Enable Register */
+#define LCDC_LCDIER_HEOIE (0x1u << 11) /**< \brief (LCDC_LCDIER) High End Overlay Interrupt Enable Register */
+#define LCDC_LCDIER_PPIE (0x1u << 13) /**< \brief (LCDC_LCDIER) Post Processing Interrupt Enable Register */
+/* -------- LCDC_LCDIDR : (LCDC Offset: 0x00000030) LCD Controller Interrupt Disable Register -------- */
+#define LCDC_LCDIDR_SOFID (0x1u << 0) /**< \brief (LCDC_LCDIDR) Start of Frame Interrupt Disable Register */
+#define LCDC_LCDIDR_DISID (0x1u << 1) /**< \brief (LCDC_LCDIDR) LCD Disable Interrupt Disable Register */
+#define LCDC_LCDIDR_DISPID (0x1u << 2) /**< \brief (LCDC_LCDIDR) Power UP/Down Sequence Terminated Interrupt Disable Register */
+#define LCDC_LCDIDR_FIFOERRID (0x1u << 4) /**< \brief (LCDC_LCDIDR) Output FIFO Error Interrupt Disable Register */
+#define LCDC_LCDIDR_BASEID (0x1u << 8) /**< \brief (LCDC_LCDIDR) Base Layer Interrupt Disable Register */
+#define LCDC_LCDIDR_OVR1ID (0x1u << 9) /**< \brief (LCDC_LCDIDR) Overlay 1 Interrupt Disable Register */
+#define LCDC_LCDIDR_OVR2ID (0x1u << 10) /**< \brief (LCDC_LCDIDR) Overlay 2 Interrupt Disable Register */
+#define LCDC_LCDIDR_HEOID (0x1u << 11) /**< \brief (LCDC_LCDIDR) High End Overlay Interrupt Disable Register */
+#define LCDC_LCDIDR_PPID (0x1u << 13) /**< \brief (LCDC_LCDIDR) Post Processing Interrupt Disable Register */
+/* -------- LCDC_LCDIMR : (LCDC Offset: 0x00000034) LCD Controller Interrupt Mask Register -------- */
+#define LCDC_LCDIMR_SOFIM (0x1u << 0) /**< \brief (LCDC_LCDIMR) Start of Frame Interrupt Mask Register */
+#define LCDC_LCDIMR_DISIM (0x1u << 1) /**< \brief (LCDC_LCDIMR) LCD Disable Interrupt Mask Register */
+#define LCDC_LCDIMR_DISPIM (0x1u << 2) /**< \brief (LCDC_LCDIMR) Power UP/Down Sequence Terminated Interrupt Mask Register */
+#define LCDC_LCDIMR_FIFOERRIM (0x1u << 4) /**< \brief (LCDC_LCDIMR) Output FIFO Error Interrupt Mask Register */
+#define LCDC_LCDIMR_BASEIM (0x1u << 8) /**< \brief (LCDC_LCDIMR) Base Layer Interrupt Mask Register */
+#define LCDC_LCDIMR_OVR1IM (0x1u << 9) /**< \brief (LCDC_LCDIMR) Overlay 1 Interrupt Mask Register */
+#define LCDC_LCDIMR_OVR2IM (0x1u << 10) /**< \brief (LCDC_LCDIMR) Overlay 2 Interrupt Mask Register */
+#define LCDC_LCDIMR_HEOIM (0x1u << 11) /**< \brief (LCDC_LCDIMR) High End Overlay Interrupt Mask Register */
+#define LCDC_LCDIMR_PPIM (0x1u << 13) /**< \brief (LCDC_LCDIMR) Post Processing Interrupt Mask Register */
+/* -------- LCDC_LCDISR : (LCDC Offset: 0x00000038) LCD Controller Interrupt Status Register -------- */
+#define LCDC_LCDISR_SOF (0x1u << 0) /**< \brief (LCDC_LCDISR) Start of Frame Interrupt Status Register */
+#define LCDC_LCDISR_DIS (0x1u << 1) /**< \brief (LCDC_LCDISR) LCD Disable Interrupt Status Register */
+#define LCDC_LCDISR_DISP (0x1u << 2) /**< \brief (LCDC_LCDISR) Power-up/Power-down Sequence Terminated Interrupt Status Register */
+#define LCDC_LCDISR_FIFOERR (0x1u << 4) /**< \brief (LCDC_LCDISR) Output FIFO Error */
+#define LCDC_LCDISR_BASE (0x1u << 8) /**< \brief (LCDC_LCDISR) Base Layer Raw Interrupt Status Register */
+#define LCDC_LCDISR_OVR1 (0x1u << 9) /**< \brief (LCDC_LCDISR) Overlay 1 Raw Interrupt Status Register */
+#define LCDC_LCDISR_OVR2 (0x1u << 10) /**< \brief (LCDC_LCDISR) Overlay 2 Raw Interrupt Status Register */
+#define LCDC_LCDISR_HEO (0x1u << 11) /**< \brief (LCDC_LCDISR) High End Overlay Raw Interrupt Status Register */
+#define LCDC_LCDISR_PP (0x1u << 13) /**< \brief (LCDC_LCDISR) Post Processing Raw Interrupt Status Register */
+/* -------- LCDC_ATTR : (LCDC Offset: 0x0000003C) LCD Controller Attribute Register -------- */
+#define LCDC_ATTR_BASE (0x1u << 0) /**< \brief (LCDC_ATTR) Base Layer Update Attribute Register */
+#define LCDC_ATTR_OVR1 (0x1u << 1) /**< \brief (LCDC_ATTR) Overlay 1 Update Attribute Register */
+#define LCDC_ATTR_OVR2 (0x1u << 2) /**< \brief (LCDC_ATTR) Overlay 2 Update Attribute Register */
+#define LCDC_ATTR_HEO (0x1u << 3) /**< \brief (LCDC_ATTR) High End Overlay Update Attribute Register */
+#define LCDC_ATTR_PP (0x1u << 5) /**< \brief (LCDC_ATTR) Post-Processing Update Attribute Register */
+#define LCDC_ATTR_BASEA2Q (0x1u << 8) /**< \brief (LCDC_ATTR) Base Layer Update Add To Queue */
+#define LCDC_ATTR_OVR1A2Q (0x1u << 9) /**< \brief (LCDC_ATTR) Overlay 1 Update Add To Queue */
+#define LCDC_ATTR_OVR2A2Q (0x1u << 10) /**< \brief (LCDC_ATTR) Overlay 2 Update Add to Queue */
+#define LCDC_ATTR_HEOA2Q (0x1u << 11) /**< \brief (LCDC_ATTR) High End Overlay Update Add To Queue */
+#define LCDC_ATTR_PPA2Q (0x1u << 13) /**< \brief (LCDC_ATTR) Post-Processing Update Add To Queue */
+/* -------- LCDC_BASECHER : (LCDC Offset: 0x00000040) Base Layer Channel Enable Register -------- */
+#define LCDC_BASECHER_CHEN (0x1u << 0) /**< \brief (LCDC_BASECHER) Channel Enable Register */
+#define LCDC_BASECHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_BASECHER) Update Overlay Attributes Enable Register */
+#define LCDC_BASECHER_A2QEN (0x1u << 2) /**< \brief (LCDC_BASECHER) Add To Queue Enable Register */
+/* -------- LCDC_BASECHDR : (LCDC Offset: 0x00000044) Base Layer Channel Disable Register -------- */
+#define LCDC_BASECHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_BASECHDR) Channel Disable Register */
+#define LCDC_BASECHDR_CHRST (0x1u << 8) /**< \brief (LCDC_BASECHDR) Channel Reset Register */
+/* -------- LCDC_BASECHSR : (LCDC Offset: 0x00000048) Base Layer Channel Status Register -------- */
+#define LCDC_BASECHSR_CHSR (0x1u << 0) /**< \brief (LCDC_BASECHSR) Channel Status Register */
+#define LCDC_BASECHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_BASECHSR) Update Overlay Attributes In Progress Status Register */
+#define LCDC_BASECHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_BASECHSR) Add To Queue Status Register */
+/* -------- LCDC_BASEIER : (LCDC Offset: 0x0000004C) Base Layer Interrupt Enable Register -------- */
+#define LCDC_BASEIER_DMA (0x1u << 2) /**< \brief (LCDC_BASEIER) End of DMA Transfer Interrupt Enable Register */
+#define LCDC_BASEIER_DSCR (0x1u << 3) /**< \brief (LCDC_BASEIER) Descriptor Loaded Interrupt Enable Register */
+#define LCDC_BASEIER_ADD (0x1u << 4) /**< \brief (LCDC_BASEIER) Head Descriptor Loaded Interrupt Enable Register */
+#define LCDC_BASEIER_DONE (0x1u << 5) /**< \brief (LCDC_BASEIER) End of List Interrupt Enable Register */
+#define LCDC_BASEIER_OVR (0x1u << 6) /**< \brief (LCDC_BASEIER) Overflow Interrupt Enable Register */
+/* -------- LCDC_BASEIDR : (LCDC Offset: 0x00000050) Base Layer Interrupt Disabled Register -------- */
+#define LCDC_BASEIDR_DMA (0x1u << 2) /**< \brief (LCDC_BASEIDR) End of DMA Transfer Interrupt Disable Register */
+#define LCDC_BASEIDR_DSCR (0x1u << 3) /**< \brief (LCDC_BASEIDR) Descriptor Loaded Interrupt Disable Register */
+#define LCDC_BASEIDR_ADD (0x1u << 4) /**< \brief (LCDC_BASEIDR) Head Descriptor Loaded Interrupt Disable Register */
+#define LCDC_BASEIDR_DONE (0x1u << 5) /**< \brief (LCDC_BASEIDR) End of List Interrupt Disable Register */
+#define LCDC_BASEIDR_OVR (0x1u << 6) /**< \brief (LCDC_BASEIDR) Overflow Interrupt Disable Register */
+/* -------- LCDC_BASEIMR : (LCDC Offset: 0x00000054) Base Layer Interrupt Mask Register -------- */
+#define LCDC_BASEIMR_DMA (0x1u << 2) /**< \brief (LCDC_BASEIMR) End of DMA Transfer Interrupt Mask Register */
+#define LCDC_BASEIMR_DSCR (0x1u << 3) /**< \brief (LCDC_BASEIMR) Descriptor Loaded Interrupt Mask Register */
+#define LCDC_BASEIMR_ADD (0x1u << 4) /**< \brief (LCDC_BASEIMR) Head Descriptor Loaded Interrupt Mask Register */
+#define LCDC_BASEIMR_DONE (0x1u << 5) /**< \brief (LCDC_BASEIMR) End of List Interrupt Mask Register */
+#define LCDC_BASEIMR_OVR (0x1u << 6) /**< \brief (LCDC_BASEIMR) Overflow Interrupt Mask Register */
+/* -------- LCDC_BASEISR : (LCDC Offset: 0x00000058) Base Layer Interrupt Status Register -------- */
+#define LCDC_BASEISR_DMA (0x1u << 2) /**< \brief (LCDC_BASEISR) End of DMA Transfer */
+#define LCDC_BASEISR_DSCR (0x1u << 3) /**< \brief (LCDC_BASEISR) DMA Descriptor Loaded */
+#define LCDC_BASEISR_ADD (0x1u << 4) /**< \brief (LCDC_BASEISR) Head Descriptor Loaded */
+#define LCDC_BASEISR_DONE (0x1u << 5) /**< \brief (LCDC_BASEISR) End of List Detected */
+#define LCDC_BASEISR_OVR (0x1u << 6) /**< \brief (LCDC_BASEISR) Overflow Detected */
+/* -------- LCDC_BASEHEAD : (LCDC Offset: 0x0000005C) Base DMA Head Register -------- */
+#define LCDC_BASEHEAD_HEAD_Pos 2
+#define LCDC_BASEHEAD_HEAD_Msk (0x3fffffffu << LCDC_BASEHEAD_HEAD_Pos) /**< \brief (LCDC_BASEHEAD) DMA Head Pointer */
+#define LCDC_BASEHEAD_HEAD(value) ((LCDC_BASEHEAD_HEAD_Msk & ((value) << LCDC_BASEHEAD_HEAD_Pos)))
+/* -------- LCDC_BASEADDR : (LCDC Offset: 0x00000060) Base DMA Address Register -------- */
+#define LCDC_BASEADDR_ADDR_Pos 0
+#define LCDC_BASEADDR_ADDR_Msk (0xffffffffu << LCDC_BASEADDR_ADDR_Pos) /**< \brief (LCDC_BASEADDR) DMA Transfer Start Address */
+#define LCDC_BASEADDR_ADDR(value) ((LCDC_BASEADDR_ADDR_Msk & ((value) << LCDC_BASEADDR_ADDR_Pos)))
+/* -------- LCDC_BASECTRL : (LCDC Offset: 0x00000064) Base DMA Control Register -------- */
+#define LCDC_BASECTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_BASECTRL) Transfer Descriptor Fetch Enable */
+#define LCDC_BASECTRL_LFETCH (0x1u << 1) /**< \brief (LCDC_BASECTRL) Lookup Table Fetch Enable */
+#define LCDC_BASECTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_BASECTRL) End of DMA Transfer Interrupt Enable */
+#define LCDC_BASECTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_BASECTRL) Descriptor Loaded Interrupt Enable */
+#define LCDC_BASECTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_BASECTRL) Add Head Descriptor to Queue Interrupt Enable */
+#define LCDC_BASECTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_BASECTRL) End of List Interrupt Enable */
+/* -------- LCDC_BASENEXT : (LCDC Offset: 0x00000068) Base DMA Next Register -------- */
+#define LCDC_BASENEXT_NEXT_Pos 0
+#define LCDC_BASENEXT_NEXT_Msk (0xffffffffu << LCDC_BASENEXT_NEXT_Pos) /**< \brief (LCDC_BASENEXT) DMA Descriptor Next Address */
+#define LCDC_BASENEXT_NEXT(value) ((LCDC_BASENEXT_NEXT_Msk & ((value) << LCDC_BASENEXT_NEXT_Pos)))
+/* -------- LCDC_BASECFG0 : (LCDC Offset: 0x0000006C) Base Layer Configuration Register 0 -------- */
+#define LCDC_BASECFG0_SIF (0x1u << 0) /**< \brief (LCDC_BASECFG0) Source Interface */
+#define LCDC_BASECFG0_BLEN_Pos 4
+#define LCDC_BASECFG0_BLEN_Msk (0x3u << LCDC_BASECFG0_BLEN_Pos) /**< \brief (LCDC_BASECFG0) AHB Burst Length */
+#define LCDC_BASECFG0_BLEN(value) ((LCDC_BASECFG0_BLEN_Msk & ((value) << LCDC_BASECFG0_BLEN_Pos)))
+#define   LCDC_BASECFG0_BLEN_AHB_SINGLE (0x0u << 4) /**< \brief (LCDC_BASECFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define   LCDC_BASECFG0_BLEN_AHB_INCR4 (0x1u << 4) /**< \brief (LCDC_BASECFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define   LCDC_BASECFG0_BLEN_AHB_INCR8 (0x2u << 4) /**< \brief (LCDC_BASECFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define   LCDC_BASECFG0_BLEN_AHB_INCR16 (0x3u << 4) /**< \brief (LCDC_BASECFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define LCDC_BASECFG0_DLBO (0x1u << 8) /**< \brief (LCDC_BASECFG0) Defined Length Burst Only For Channel Bus Transaction */
+/* -------- LCDC_BASECFG1 : (LCDC Offset: 0x00000070) Base Layer Configuration Register 1 -------- */
+#define LCDC_BASECFG1_CLUTEN (0x1u << 0) /**< \brief (LCDC_BASECFG1) Color Lookup Table Mode Enable */
+#define LCDC_BASECFG1_RGBMODE_Pos 4
+#define LCDC_BASECFG1_RGBMODE_Msk (0xfu << LCDC_BASECFG1_RGBMODE_Pos) /**< \brief (LCDC_BASECFG1) RGB Mode Input Selection */
+#define LCDC_BASECFG1_RGBMODE(value) ((LCDC_BASECFG1_RGBMODE_Msk & ((value) << LCDC_BASECFG1_RGBMODE_Pos)))
+#define   LCDC_BASECFG1_RGBMODE_12BPP_RGB_444 (0x0u << 4) /**< \brief (LCDC_BASECFG1) 12 bpp RGB 444 */
+#define   LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444 (0x1u << 4) /**< \brief (LCDC_BASECFG1) 16 bpp ARGB 4444 */
+#define   LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444 (0x2u << 4) /**< \brief (LCDC_BASECFG1) 16 bpp RGBA 4444 */
+#define   LCDC_BASECFG1_RGBMODE_16BPP_RGB_565 (0x3u << 4) /**< \brief (LCDC_BASECFG1) 16 bpp RGB 565 */
+#define   LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555 (0x4u << 4) /**< \brief (LCDC_BASECFG1) 16 bpp TRGB 1555 */
+#define   LCDC_BASECFG1_RGBMODE_18BPP_RGB_666 (0x5u << 4) /**< \brief (LCDC_BASECFG1) 18 bpp RGB 666 */
+#define   LCDC_BASECFG1_RGBMODE_18BPP_RGB_666PACKED (0x6u << 4) /**< \brief (LCDC_BASECFG1) 18 bpp RGB 666 PACKED */
+#define   LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666 (0x7u << 4) /**< \brief (LCDC_BASECFG1) 19 bpp TRGB 1666 */
+#define   LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED (0x8u << 4) /**< \brief (LCDC_BASECFG1) 19 bpp TRGB 1666 PACKED */
+#define   LCDC_BASECFG1_RGBMODE_24BPP_RGB_888 (0x9u << 4) /**< \brief (LCDC_BASECFG1) 24 bpp RGB 888 */
+#define   LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED (0xAu << 4) /**< \brief (LCDC_BASECFG1) 24 bpp RGB 888 PACKED */
+#define   LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888 (0xBu << 4) /**< \brief (LCDC_BASECFG1) 25 bpp TRGB 1888 */
+#define   LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888 (0xCu << 4) /**< \brief (LCDC_BASECFG1) 32 bpp ARGB 8888 */
+#define   LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888 (0xDu << 4) /**< \brief (LCDC_BASECFG1) 32 bpp RGBA 8888 */
+#define LCDC_BASECFG1_CLUTMODE_Pos 8
+#define LCDC_BASECFG1_CLUTMODE_Msk (0x3u << LCDC_BASECFG1_CLUTMODE_Pos) /**< \brief (LCDC_BASECFG1) Color Lookup Table Mode Input Selection */
+#define LCDC_BASECFG1_CLUTMODE(value) ((LCDC_BASECFG1_CLUTMODE_Msk & ((value) << LCDC_BASECFG1_CLUTMODE_Pos)))
+#define   LCDC_BASECFG1_CLUTMODE_CLUT_1BPP (0x0u << 8) /**< \brief (LCDC_BASECFG1) Color Lookup Table mode set to 1 bit per pixel */
+#define   LCDC_BASECFG1_CLUTMODE_CLUT_2BPP (0x1u << 8) /**< \brief (LCDC_BASECFG1) Color Lookup Table mode set to 2 bits per pixel */
+#define   LCDC_BASECFG1_CLUTMODE_CLUT_4BPP (0x2u << 8) /**< \brief (LCDC_BASECFG1) Color Lookup Table mode set to 4 bits per pixel */
+#define   LCDC_BASECFG1_CLUTMODE_CLUT_8BPP (0x3u << 8) /**< \brief (LCDC_BASECFG1) Color Lookup Table mode set to 8 bits per pixel */
+/* -------- LCDC_BASECFG2 : (LCDC Offset: 0x00000074) Base Layer Configuration Register 2 -------- */
+#define LCDC_BASECFG2_XSTRIDE_Pos 0
+#define LCDC_BASECFG2_XSTRIDE_Msk (0xffffffffu << LCDC_BASECFG2_XSTRIDE_Pos) /**< \brief (LCDC_BASECFG2) Horizontal Stride */
+#define LCDC_BASECFG2_XSTRIDE(value) ((LCDC_BASECFG2_XSTRIDE_Msk & ((value) << LCDC_BASECFG2_XSTRIDE_Pos)))
+/* -------- LCDC_BASECFG3 : (LCDC Offset: 0x00000078) Base Layer Configuration Register 3 -------- */
+#define LCDC_BASECFG3_BDEF_Pos 0
+#define LCDC_BASECFG3_BDEF_Msk (0xffu << LCDC_BASECFG3_BDEF_Pos) /**< \brief (LCDC_BASECFG3) Blue Default */
+#define LCDC_BASECFG3_BDEF(value) ((LCDC_BASECFG3_BDEF_Msk & ((value) << LCDC_BASECFG3_BDEF_Pos)))
+#define LCDC_BASECFG3_GDEF_Pos 8
+#define LCDC_BASECFG3_GDEF_Msk (0xffu << LCDC_BASECFG3_GDEF_Pos) /**< \brief (LCDC_BASECFG3) Green Default */
+#define LCDC_BASECFG3_GDEF(value) ((LCDC_BASECFG3_GDEF_Msk & ((value) << LCDC_BASECFG3_GDEF_Pos)))
+#define LCDC_BASECFG3_RDEF_Pos 16
+#define LCDC_BASECFG3_RDEF_Msk (0xffu << LCDC_BASECFG3_RDEF_Pos) /**< \brief (LCDC_BASECFG3) Red Default */
+#define LCDC_BASECFG3_RDEF(value) ((LCDC_BASECFG3_RDEF_Msk & ((value) << LCDC_BASECFG3_RDEF_Pos)))
+/* -------- LCDC_BASECFG4 : (LCDC Offset: 0x0000007C) Base Layer Configuration Register 4 -------- */
+#define LCDC_BASECFG4_DMA (0x1u << 8) /**< \brief (LCDC_BASECFG4) Use DMA Data Path */
+#define LCDC_BASECFG4_REP (0x1u << 9) /**< \brief (LCDC_BASECFG4) Use Replication logic to expand RGB color to 24 bits */
+#define LCDC_BASECFG4_DISCEN (0x1u << 11) /**< \brief (LCDC_BASECFG4) Discard Area Enable */
+/* -------- LCDC_BASECFG5 : (LCDC Offset: 0x00000080) Base Layer Configuration Register 5 -------- */
+#define LCDC_BASECFG5_DISCXPOS_Pos 0
+#define LCDC_BASECFG5_DISCXPOS_Msk (0x7ffu << LCDC_BASECFG5_DISCXPOS_Pos) /**< \brief (LCDC_BASECFG5) Discard Area Horizontal Coordinate */
+#define LCDC_BASECFG5_DISCXPOS(value) ((LCDC_BASECFG5_DISCXPOS_Msk & ((value) << LCDC_BASECFG5_DISCXPOS_Pos)))
+#define LCDC_BASECFG5_DISCYPOS_Pos 16
+#define LCDC_BASECFG5_DISCYPOS_Msk (0x7ffu << LCDC_BASECFG5_DISCYPOS_Pos) /**< \brief (LCDC_BASECFG5) Discard Area Vertical Coordinate */
+#define LCDC_BASECFG5_DISCYPOS(value) ((LCDC_BASECFG5_DISCYPOS_Msk & ((value) << LCDC_BASECFG5_DISCYPOS_Pos)))
+/* -------- LCDC_BASECFG6 : (LCDC Offset: 0x00000084) Base Layer Configuration Register 6 -------- */
+#define LCDC_BASECFG6_DISCXSIZE_Pos 0
+#define LCDC_BASECFG6_DISCXSIZE_Msk (0x7ffu << LCDC_BASECFG6_DISCXSIZE_Pos) /**< \brief (LCDC_BASECFG6) Discard Area Horizontal Size */
+#define LCDC_BASECFG6_DISCXSIZE(value) ((LCDC_BASECFG6_DISCXSIZE_Msk & ((value) << LCDC_BASECFG6_DISCXSIZE_Pos)))
+#define LCDC_BASECFG6_DISCYSIZE_Pos 16
+#define LCDC_BASECFG6_DISCYSIZE_Msk (0x7ffu << LCDC_BASECFG6_DISCYSIZE_Pos) /**< \brief (LCDC_BASECFG6) Discard Area Vertical Size */
+#define LCDC_BASECFG6_DISCYSIZE(value) ((LCDC_BASECFG6_DISCYSIZE_Msk & ((value) << LCDC_BASECFG6_DISCYSIZE_Pos)))
+/* -------- LCDC_OVR1CHER : (LCDC Offset: 0x00000140) Overlay 1 Channel Enable Register -------- */
+#define LCDC_OVR1CHER_CHEN (0x1u << 0) /**< \brief (LCDC_OVR1CHER) Channel Enable Register */
+#define LCDC_OVR1CHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_OVR1CHER) Update Overlay Attributes Enable Register */
+#define LCDC_OVR1CHER_A2QEN (0x1u << 2) /**< \brief (LCDC_OVR1CHER) Add To Queue Enable Register */
+/* -------- LCDC_OVR1CHDR : (LCDC Offset: 0x00000144) Overlay 1 Channel Disable Register -------- */
+#define LCDC_OVR1CHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_OVR1CHDR) Channel Disable Register */
+#define LCDC_OVR1CHDR_CHRST (0x1u << 8) /**< \brief (LCDC_OVR1CHDR) Channel Reset Register */
+/* -------- LCDC_OVR1CHSR : (LCDC Offset: 0x00000148) Overlay 1 Channel Status Register -------- */
+#define LCDC_OVR1CHSR_CHSR (0x1u << 0) /**< \brief (LCDC_OVR1CHSR) Channel Status Register */
+#define LCDC_OVR1CHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_OVR1CHSR) Update Overlay Attributes In Progress Status Register */
+#define LCDC_OVR1CHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_OVR1CHSR) Add To Queue Status Register */
+/* -------- LCDC_OVR1IER : (LCDC Offset: 0x0000014C) Overlay 1 Interrupt Enable Register -------- */
+#define LCDC_OVR1IER_DMA (0x1u << 2) /**< \brief (LCDC_OVR1IER) End of DMA Transfer Interrupt Enable Register */
+#define LCDC_OVR1IER_DSCR (0x1u << 3) /**< \brief (LCDC_OVR1IER) Descriptor Loaded Interrupt Enable Register */
+#define LCDC_OVR1IER_ADD (0x1u << 4) /**< \brief (LCDC_OVR1IER) Head Descriptor Loaded Interrupt Enable Register */
+#define LCDC_OVR1IER_DONE (0x1u << 5) /**< \brief (LCDC_OVR1IER) End of List Interrupt Enable Register */
+#define LCDC_OVR1IER_OVR (0x1u << 6) /**< \brief (LCDC_OVR1IER) Overflow Interrupt Enable Register */
+/* -------- LCDC_OVR1IDR : (LCDC Offset: 0x00000150) Overlay 1 Interrupt Disable Register -------- */
+#define LCDC_OVR1IDR_DMA (0x1u << 2) /**< \brief (LCDC_OVR1IDR) End of DMA Transfer Interrupt Disable Register */
+#define LCDC_OVR1IDR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR1IDR) Descriptor Loaded Interrupt Disable Register */
+#define LCDC_OVR1IDR_ADD (0x1u << 4) /**< \brief (LCDC_OVR1IDR) Head Descriptor Loaded Interrupt Disable Register */
+#define LCDC_OVR1IDR_DONE (0x1u << 5) /**< \brief (LCDC_OVR1IDR) End of List Interrupt Disable Register */
+#define LCDC_OVR1IDR_OVR (0x1u << 6) /**< \brief (LCDC_OVR1IDR) Overflow Interrupt Disable Register */
+/* -------- LCDC_OVR1IMR : (LCDC Offset: 0x00000154) Overlay 1 Interrupt Mask Register -------- */
+#define LCDC_OVR1IMR_DMA (0x1u << 2) /**< \brief (LCDC_OVR1IMR) End of DMA Transfer Interrupt Mask Register */
+#define LCDC_OVR1IMR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR1IMR) Descriptor Loaded Interrupt Mask Register */
+#define LCDC_OVR1IMR_ADD (0x1u << 4) /**< \brief (LCDC_OVR1IMR) Head Descriptor Loaded Interrupt Mask Register */
+#define LCDC_OVR1IMR_DONE (0x1u << 5) /**< \brief (LCDC_OVR1IMR) End of List Interrupt Mask Register */
+#define LCDC_OVR1IMR_OVR (0x1u << 6) /**< \brief (LCDC_OVR1IMR) Overflow Interrupt Mask Register */
+/* -------- LCDC_OVR1ISR : (LCDC Offset: 0x00000158) Overlay 1 Interrupt Status Register -------- */
+#define LCDC_OVR1ISR_DMA (0x1u << 2) /**< \brief (LCDC_OVR1ISR) End of DMA Transfer */
+#define LCDC_OVR1ISR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR1ISR) DMA Descriptor Loaded */
+#define LCDC_OVR1ISR_ADD (0x1u << 4) /**< \brief (LCDC_OVR1ISR) Head Descriptor Loaded */
+#define LCDC_OVR1ISR_DONE (0x1u << 5) /**< \brief (LCDC_OVR1ISR) End of List Detected */
+#define LCDC_OVR1ISR_OVR (0x1u << 6) /**< \brief (LCDC_OVR1ISR) Overflow Detected */
+/* -------- LCDC_OVR1HEAD : (LCDC Offset: 0x0000015C) Overlay 1 DMA Head Register -------- */
+#define LCDC_OVR1HEAD_HEAD_Pos 2
+#define LCDC_OVR1HEAD_HEAD_Msk (0x3fffffffu << LCDC_OVR1HEAD_HEAD_Pos) /**< \brief (LCDC_OVR1HEAD) DMA Head Pointer */
+#define LCDC_OVR1HEAD_HEAD(value) ((LCDC_OVR1HEAD_HEAD_Msk & ((value) << LCDC_OVR1HEAD_HEAD_Pos)))
+/* -------- LCDC_OVR1ADDR : (LCDC Offset: 0x00000160) Overlay 1 DMA Address Register -------- */
+#define LCDC_OVR1ADDR_ADDR_Pos 0
+#define LCDC_OVR1ADDR_ADDR_Msk (0xffffffffu << LCDC_OVR1ADDR_ADDR_Pos) /**< \brief (LCDC_OVR1ADDR) DMA Transfer Overlay 1 Address */
+#define LCDC_OVR1ADDR_ADDR(value) ((LCDC_OVR1ADDR_ADDR_Msk & ((value) << LCDC_OVR1ADDR_ADDR_Pos)))
+/* -------- LCDC_OVR1CTRL : (LCDC Offset: 0x00000164) Overlay 1 DMA Control Register -------- */
+#define LCDC_OVR1CTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_OVR1CTRL) Transfer Descriptor Fetch Enable */
+#define LCDC_OVR1CTRL_LFETCH (0x1u << 1) /**< \brief (LCDC_OVR1CTRL) Lookup Table Fetch Enable */
+#define LCDC_OVR1CTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_OVR1CTRL) End of DMA Transfer Interrupt Enable */
+#define LCDC_OVR1CTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_OVR1CTRL) Descriptor Loaded Interrupt Enable */
+#define LCDC_OVR1CTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_OVR1CTRL) Add Head Descriptor to Queue Interrupt Enable */
+#define LCDC_OVR1CTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_OVR1CTRL) End of List Interrupt Enable */
+/* -------- LCDC_OVR1NEXT : (LCDC Offset: 0x00000168) Overlay 1 DMA Next Register -------- */
+#define LCDC_OVR1NEXT_NEXT_Pos 0
+#define LCDC_OVR1NEXT_NEXT_Msk (0xffffffffu << LCDC_OVR1NEXT_NEXT_Pos) /**< \brief (LCDC_OVR1NEXT) DMA Descriptor Next Address */
+#define LCDC_OVR1NEXT_NEXT(value) ((LCDC_OVR1NEXT_NEXT_Msk & ((value) << LCDC_OVR1NEXT_NEXT_Pos)))
+/* -------- LCDC_OVR1CFG0 : (LCDC Offset: 0x0000016C) Overlay 1 Configuration Register 0 -------- */
+#define LCDC_OVR1CFG0_SIF (0x1u << 0) /**< \brief (LCDC_OVR1CFG0) Source Interface */
+#define LCDC_OVR1CFG0_BLEN_Pos 4
+#define LCDC_OVR1CFG0_BLEN_Msk (0x3u << LCDC_OVR1CFG0_BLEN_Pos) /**< \brief (LCDC_OVR1CFG0) AHB Burst Length */
+#define LCDC_OVR1CFG0_BLEN(value) ((LCDC_OVR1CFG0_BLEN_Msk & ((value) << LCDC_OVR1CFG0_BLEN_Pos)))
+#define   LCDC_OVR1CFG0_BLEN_AHB_BLEN_SINGLE (0x0u << 4) /**< \brief (LCDC_OVR1CFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define   LCDC_OVR1CFG0_BLEN_AHB_BLEN_INCR4 (0x1u << 4) /**< \brief (LCDC_OVR1CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define   LCDC_OVR1CFG0_BLEN_AHB_BLEN_INCR8 (0x2u << 4) /**< \brief (LCDC_OVR1CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define   LCDC_OVR1CFG0_BLEN_AHB_BLEN_INCR16 (0x3u << 4) /**< \brief (LCDC_OVR1CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define LCDC_OVR1CFG0_DLBO (0x1u << 8) /**< \brief (LCDC_OVR1CFG0) Defined Length Burst Only for Channel Bus Transaction. */
+#define LCDC_OVR1CFG0_ROTDIS (0x1u << 12) /**< \brief (LCDC_OVR1CFG0) Hardware Rotation Optimization Disable */
+#define LCDC_OVR1CFG0_LOCKDIS (0x1u << 13) /**< \brief (LCDC_OVR1CFG0) Hardware Rotation Lock Disable */
+/* -------- LCDC_OVR1CFG1 : (LCDC Offset: 0x00000170) Overlay 1 Configuration Register 1 -------- */
+#define LCDC_OVR1CFG1_CLUTEN (0x1u << 0) /**< \brief (LCDC_OVR1CFG1) Color Lookup Table Mode Enable */
+#define LCDC_OVR1CFG1_RGBMODE_Pos 4
+#define LCDC_OVR1CFG1_RGBMODE_Msk (0xfu << LCDC_OVR1CFG1_RGBMODE_Pos) /**< \brief (LCDC_OVR1CFG1) RGB Mode Input Selection */
+#define LCDC_OVR1CFG1_RGBMODE(value) ((LCDC_OVR1CFG1_RGBMODE_Msk & ((value) << LCDC_OVR1CFG1_RGBMODE_Pos)))
+#define   LCDC_OVR1CFG1_RGBMODE_12BPP_RGB_444 (0x0u << 4) /**< \brief (LCDC_OVR1CFG1) 12 bpp RGB 444 */
+#define   LCDC_OVR1CFG1_RGBMODE_16BPP_ARGB_4444 (0x1u << 4) /**< \brief (LCDC_OVR1CFG1) 16 bpp ARGB 4444 */
+#define   LCDC_OVR1CFG1_RGBMODE_16BPP_RGBA_4444 (0x2u << 4) /**< \brief (LCDC_OVR1CFG1) 16 bpp RGBA 4444 */
+#define   LCDC_OVR1CFG1_RGBMODE_16BPP_RGB_565 (0x3u << 4) /**< \brief (LCDC_OVR1CFG1) 16 bpp RGB 565 */
+#define   LCDC_OVR1CFG1_RGBMODE_16BPP_TRGB_1555 (0x4u << 4) /**< \brief (LCDC_OVR1CFG1) 16 bpp TRGB 1555 */
+#define   LCDC_OVR1CFG1_RGBMODE_18BPP_RGB_666 (0x5u << 4) /**< \brief (LCDC_OVR1CFG1) 18 bpp RGB 666 */
+#define   LCDC_OVR1CFG1_RGBMODE_18BPP_RGB_666PACKED (0x6u << 4) /**< \brief (LCDC_OVR1CFG1) 18 bpp RGB 666 PACKED */
+#define   LCDC_OVR1CFG1_RGBMODE_19BPP_TRGB_1666 (0x7u << 4) /**< \brief (LCDC_OVR1CFG1) 19 bpp TRGB 1666 */
+#define   LCDC_OVR1CFG1_RGBMODE_19BPP_TRGB_PACKED (0x8u << 4) /**< \brief (LCDC_OVR1CFG1) 19 bpp TRGB 1666 PACKED */
+#define   LCDC_OVR1CFG1_RGBMODE_24BPP_RGB_888 (0x9u << 4) /**< \brief (LCDC_OVR1CFG1) 24 bpp RGB 888 */
+#define   LCDC_OVR1CFG1_RGBMODE_24BPP_RGB_888_PACKED (0xAu << 4) /**< \brief (LCDC_OVR1CFG1) 24 bpp RGB 888 PACKED */
+#define   LCDC_OVR1CFG1_RGBMODE_25BPP_TRGB_1888 (0xBu << 4) /**< \brief (LCDC_OVR1CFG1) 25 bpp TRGB 1888 */
+#define   LCDC_OVR1CFG1_RGBMODE_32BPP_ARGB_8888 (0xCu << 4) /**< \brief (LCDC_OVR1CFG1) 32 bpp ARGB 8888 */
+#define   LCDC_OVR1CFG1_RGBMODE_32BPP_RGBA_8888 (0xDu << 4) /**< \brief (LCDC_OVR1CFG1) 32 bpp RGBA 8888 */
+#define LCDC_OVR1CFG1_CLUTMODE_Pos 8
+#define LCDC_OVR1CFG1_CLUTMODE_Msk (0x3u << LCDC_OVR1CFG1_CLUTMODE_Pos) /**< \brief (LCDC_OVR1CFG1) Color Lookup Table Mode Input Selection */
+#define LCDC_OVR1CFG1_CLUTMODE(value) ((LCDC_OVR1CFG1_CLUTMODE_Msk & ((value) << LCDC_OVR1CFG1_CLUTMODE_Pos)))
+#define   LCDC_OVR1CFG1_CLUTMODE_CLUT_1BPP (0x0u << 8) /**< \brief (LCDC_OVR1CFG1) Color Lookup Table mode set to 1 bit per pixel */
+#define   LCDC_OVR1CFG1_CLUTMODE_CLUT_2BPP (0x1u << 8) /**< \brief (LCDC_OVR1CFG1) Color Lookup Table mode set to 2 bits per pixel */
+#define   LCDC_OVR1CFG1_CLUTMODE_CLUT_4BPP (0x2u << 8) /**< \brief (LCDC_OVR1CFG1) Color Lookup Table mode set to 4 bits per pixel */
+#define   LCDC_OVR1CFG1_CLUTMODE_CLUT_8BPP (0x3u << 8) /**< \brief (LCDC_OVR1CFG1) Color Lookup Table mode set to 8 bits per pixel */
+/* -------- LCDC_OVR1CFG2 : (LCDC Offset: 0x00000174) Overlay 1 Configuration Register 2 -------- */
+#define LCDC_OVR1CFG2_XPOS_Pos 0
+#define LCDC_OVR1CFG2_XPOS_Msk (0x7ffu << LCDC_OVR1CFG2_XPOS_Pos) /**< \brief (LCDC_OVR1CFG2) Horizontal Window Position */
+#define LCDC_OVR1CFG2_XPOS(value) ((LCDC_OVR1CFG2_XPOS_Msk & ((value) << LCDC_OVR1CFG2_XPOS_Pos)))
+#define LCDC_OVR1CFG2_YPOS_Pos 16
+#define LCDC_OVR1CFG2_YPOS_Msk (0x7ffu << LCDC_OVR1CFG2_YPOS_Pos) /**< \brief (LCDC_OVR1CFG2) Vertical Window Position */
+#define LCDC_OVR1CFG2_YPOS(value) ((LCDC_OVR1CFG2_YPOS_Msk & ((value) << LCDC_OVR1CFG2_YPOS_Pos)))
+/* -------- LCDC_OVR1CFG3 : (LCDC Offset: 0x00000178) Overlay 1 Configuration Register 3 -------- */
+#define LCDC_OVR1CFG3_XSIZE_Pos 0
+#define LCDC_OVR1CFG3_XSIZE_Msk (0x7ffu << LCDC_OVR1CFG3_XSIZE_Pos) /**< \brief (LCDC_OVR1CFG3) Horizontal Window Size */
+#define LCDC_OVR1CFG3_XSIZE(value) ((LCDC_OVR1CFG3_XSIZE_Msk & ((value) << LCDC_OVR1CFG3_XSIZE_Pos)))
+#define LCDC_OVR1CFG3_YSIZE_Pos 16
+#define LCDC_OVR1CFG3_YSIZE_Msk (0x7ffu << LCDC_OVR1CFG3_YSIZE_Pos) /**< \brief (LCDC_OVR1CFG3) Vertical Window Size */
+#define LCDC_OVR1CFG3_YSIZE(value) ((LCDC_OVR1CFG3_YSIZE_Msk & ((value) << LCDC_OVR1CFG3_YSIZE_Pos)))
+/* -------- LCDC_OVR1CFG4 : (LCDC Offset: 0x0000017C) Overlay 1 Configuration Register 4 -------- */
+#define LCDC_OVR1CFG4_XSTRIDE_Pos 0
+#define LCDC_OVR1CFG4_XSTRIDE_Msk (0xffffffffu << LCDC_OVR1CFG4_XSTRIDE_Pos) /**< \brief (LCDC_OVR1CFG4) Horizontal Stride */
+#define LCDC_OVR1CFG4_XSTRIDE(value) ((LCDC_OVR1CFG4_XSTRIDE_Msk & ((value) << LCDC_OVR1CFG4_XSTRIDE_Pos)))
+/* -------- LCDC_OVR1CFG5 : (LCDC Offset: 0x00000180) Overlay 1 Configuration Register 5 -------- */
+#define LCDC_OVR1CFG5_PSTRIDE_Pos 0
+#define LCDC_OVR1CFG5_PSTRIDE_Msk (0xffffffffu << LCDC_OVR1CFG5_PSTRIDE_Pos) /**< \brief (LCDC_OVR1CFG5) Pixel Stride */
+#define LCDC_OVR1CFG5_PSTRIDE(value) ((LCDC_OVR1CFG5_PSTRIDE_Msk & ((value) << LCDC_OVR1CFG5_PSTRIDE_Pos)))
+/* -------- LCDC_OVR1CFG6 : (LCDC Offset: 0x00000184) Overlay 1 Configuration Register 6 -------- */
+#define LCDC_OVR1CFG6_BDEF_Pos 0
+#define LCDC_OVR1CFG6_BDEF_Msk (0xffu << LCDC_OVR1CFG6_BDEF_Pos) /**< \brief (LCDC_OVR1CFG6) Blue Default */
+#define LCDC_OVR1CFG6_BDEF(value) ((LCDC_OVR1CFG6_BDEF_Msk & ((value) << LCDC_OVR1CFG6_BDEF_Pos)))
+#define LCDC_OVR1CFG6_GDEF_Pos 8
+#define LCDC_OVR1CFG6_GDEF_Msk (0xffu << LCDC_OVR1CFG6_GDEF_Pos) /**< \brief (LCDC_OVR1CFG6) Green Default */
+#define LCDC_OVR1CFG6_GDEF(value) ((LCDC_OVR1CFG6_GDEF_Msk & ((value) << LCDC_OVR1CFG6_GDEF_Pos)))
+#define LCDC_OVR1CFG6_RDEF_Pos 16
+#define LCDC_OVR1CFG6_RDEF_Msk (0xffu << LCDC_OVR1CFG6_RDEF_Pos) /**< \brief (LCDC_OVR1CFG6) Red Default */
+#define LCDC_OVR1CFG6_RDEF(value) ((LCDC_OVR1CFG6_RDEF_Msk & ((value) << LCDC_OVR1CFG6_RDEF_Pos)))
+/* -------- LCDC_OVR1CFG7 : (LCDC Offset: 0x00000188) Overlay 1 Configuration Register 7 -------- */
+#define LCDC_OVR1CFG7_BKEY_Pos 0
+#define LCDC_OVR1CFG7_BKEY_Msk (0xffu << LCDC_OVR1CFG7_BKEY_Pos) /**< \brief (LCDC_OVR1CFG7) Blue Color Component Chroma Key */
+#define LCDC_OVR1CFG7_BKEY(value) ((LCDC_OVR1CFG7_BKEY_Msk & ((value) << LCDC_OVR1CFG7_BKEY_Pos)))
+#define LCDC_OVR1CFG7_GKEY_Pos 8
+#define LCDC_OVR1CFG7_GKEY_Msk (0xffu << LCDC_OVR1CFG7_GKEY_Pos) /**< \brief (LCDC_OVR1CFG7) Green Color Component Chroma Key */
+#define LCDC_OVR1CFG7_GKEY(value) ((LCDC_OVR1CFG7_GKEY_Msk & ((value) << LCDC_OVR1CFG7_GKEY_Pos)))
+#define LCDC_OVR1CFG7_RKEY_Pos 16
+#define LCDC_OVR1CFG7_RKEY_Msk (0xffu << LCDC_OVR1CFG7_RKEY_Pos) /**< \brief (LCDC_OVR1CFG7) Red Color Component Chroma Key */
+#define LCDC_OVR1CFG7_RKEY(value) ((LCDC_OVR1CFG7_RKEY_Msk & ((value) << LCDC_OVR1CFG7_RKEY_Pos)))
+/* -------- LCDC_OVR1CFG8 : (LCDC Offset: 0x0000018C) Overlay 1 Configuration Register 8 -------- */
+#define LCDC_OVR1CFG8_BMASK_Pos 0
+#define LCDC_OVR1CFG8_BMASK_Msk (0xffu << LCDC_OVR1CFG8_BMASK_Pos) /**< \brief (LCDC_OVR1CFG8) Blue Color Component Chroma Key Mask */
+#define LCDC_OVR1CFG8_BMASK(value) ((LCDC_OVR1CFG8_BMASK_Msk & ((value) << LCDC_OVR1CFG8_BMASK_Pos)))
+#define LCDC_OVR1CFG8_GMASK_Pos 8
+#define LCDC_OVR1CFG8_GMASK_Msk (0xffu << LCDC_OVR1CFG8_GMASK_Pos) /**< \brief (LCDC_OVR1CFG8) Green Color Component Chroma Key Mask */
+#define LCDC_OVR1CFG8_GMASK(value) ((LCDC_OVR1CFG8_GMASK_Msk & ((value) << LCDC_OVR1CFG8_GMASK_Pos)))
+#define LCDC_OVR1CFG8_RMASK_Pos 16
+#define LCDC_OVR1CFG8_RMASK_Msk (0xffu << LCDC_OVR1CFG8_RMASK_Pos) /**< \brief (LCDC_OVR1CFG8) Red Color Component Chroma Key Mask */
+#define LCDC_OVR1CFG8_RMASK(value) ((LCDC_OVR1CFG8_RMASK_Msk & ((value) << LCDC_OVR1CFG8_RMASK_Pos)))
+/* -------- LCDC_OVR1CFG9 : (LCDC Offset: 0x00000190) Overlay 1 Configuration Register 9 -------- */
+#define LCDC_OVR1CFG9_CRKEY (0x1u << 0) /**< \brief (LCDC_OVR1CFG9) Blender Chroma Key Enable */
+#define LCDC_OVR1CFG9_INV (0x1u << 1) /**< \brief (LCDC_OVR1CFG9) Blender Inverted Blender Output Enable */
+#define LCDC_OVR1CFG9_ITER2BL (0x1u << 2) /**< \brief (LCDC_OVR1CFG9) Blender Iterated Color Enable */
+#define LCDC_OVR1CFG9_ITER (0x1u << 3) /**< \brief (LCDC_OVR1CFG9) Blender Use Iterated Color */
+#define LCDC_OVR1CFG9_REVALPHA (0x1u << 4) /**< \brief (LCDC_OVR1CFG9) Blender Reverse Alpha */
+#define LCDC_OVR1CFG9_GAEN (0x1u << 5) /**< \brief (LCDC_OVR1CFG9) Blender Global Alpha Enable */
+#define LCDC_OVR1CFG9_LAEN (0x1u << 6) /**< \brief (LCDC_OVR1CFG9) Blender Local Alpha Enable */
+#define LCDC_OVR1CFG9_OVR (0x1u << 7) /**< \brief (LCDC_OVR1CFG9) Blender Overlay Layer Enable */
+#define LCDC_OVR1CFG9_DMA (0x1u << 8) /**< \brief (LCDC_OVR1CFG9) Blender DMA Layer Enable */
+#define LCDC_OVR1CFG9_REP (0x1u << 9) /**< \brief (LCDC_OVR1CFG9) Use Replication logic to expand RGB color to 24 bits */
+#define LCDC_OVR1CFG9_DSTKEY (0x1u << 10) /**< \brief (LCDC_OVR1CFG9) Destination Chroma Keying */
+#define LCDC_OVR1CFG9_GA_Pos 16
+#define LCDC_OVR1CFG9_GA_Msk (0xffu << LCDC_OVR1CFG9_GA_Pos) /**< \brief (LCDC_OVR1CFG9) Blender Global Alpha */
+#define LCDC_OVR1CFG9_GA(value) ((LCDC_OVR1CFG9_GA_Msk & ((value) << LCDC_OVR1CFG9_GA_Pos)))
+/* -------- LCDC_OVR2CHER : (LCDC Offset: 0x00000240) Overlay 2 Channel Enable Register -------- */
+#define LCDC_OVR2CHER_CHEN (0x1u << 0) /**< \brief (LCDC_OVR2CHER) Channel Enable Register */
+#define LCDC_OVR2CHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_OVR2CHER) Update Overlay Attributes Enable Register */
+#define LCDC_OVR2CHER_A2QEN (0x1u << 2) /**< \brief (LCDC_OVR2CHER) Add To Queue Enable Register */
+/* -------- LCDC_OVR2CHDR : (LCDC Offset: 0x00000244) Overlay 2 Channel Disable Register -------- */
+#define LCDC_OVR2CHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_OVR2CHDR) Channel Disable Register */
+#define LCDC_OVR2CHDR_CHRST (0x1u << 8) /**< \brief (LCDC_OVR2CHDR) Channel Reset Register */
+/* -------- LCDC_OVR2CHSR : (LCDC Offset: 0x00000248) Overlay 2 Channel Status Register -------- */
+#define LCDC_OVR2CHSR_CHSR (0x1u << 0) /**< \brief (LCDC_OVR2CHSR) Channel Status Register */
+#define LCDC_OVR2CHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_OVR2CHSR) Update Overlay Attributes In Progress Status Register */
+#define LCDC_OVR2CHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_OVR2CHSR) Add To Queue Status Register */
+/* -------- LCDC_OVR2IER : (LCDC Offset: 0x0000024C) Overlay 2 Interrupt Enable Register -------- */
+#define LCDC_OVR2IER_DMA (0x1u << 2) /**< \brief (LCDC_OVR2IER) End of DMA Transfer Interrupt Enable Register */
+#define LCDC_OVR2IER_DSCR (0x1u << 3) /**< \brief (LCDC_OVR2IER) Descriptor Loaded Interrupt Enable Register */
+#define LCDC_OVR2IER_ADD (0x1u << 4) /**< \brief (LCDC_OVR2IER) Head Descriptor Loaded Interrupt Enable Register */
+#define LCDC_OVR2IER_DONE (0x1u << 5) /**< \brief (LCDC_OVR2IER) End of List Interrupt Enable Register */
+#define LCDC_OVR2IER_OVR (0x1u << 6) /**< \brief (LCDC_OVR2IER) Overflow Interrupt Enable Register */
+/* -------- LCDC_OVR2IDR : (LCDC Offset: 0x00000250) Overlay 2 Interrupt Disable Register -------- */
+#define LCDC_OVR2IDR_DMA (0x1u << 2) /**< \brief (LCDC_OVR2IDR) End of DMA Transfer Interrupt Disable Register */
+#define LCDC_OVR2IDR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR2IDR) Descriptor Loaded Interrupt Disable Register */
+#define LCDC_OVR2IDR_ADD (0x1u << 4) /**< \brief (LCDC_OVR2IDR) Head Descriptor Loaded Interrupt Disable Register */
+#define LCDC_OVR2IDR_DONE (0x1u << 5) /**< \brief (LCDC_OVR2IDR) End of List Interrupt Disable Register */
+#define LCDC_OVR2IDR_OVR (0x1u << 6) /**< \brief (LCDC_OVR2IDR) Overflow Interrupt Disable Register */
+/* -------- LCDC_OVR2IMR : (LCDC Offset: 0x00000254) Overlay 2 Interrupt Mask Register -------- */
+#define LCDC_OVR2IMR_DMA (0x1u << 2) /**< \brief (LCDC_OVR2IMR) End of DMA Transfer Interrupt Mask Register */
+#define LCDC_OVR2IMR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR2IMR) Descriptor Loaded Interrupt Mask Register */
+#define LCDC_OVR2IMR_ADD (0x1u << 4) /**< \brief (LCDC_OVR2IMR) Head Descriptor Loaded Interrupt Mask Register */
+#define LCDC_OVR2IMR_DONE (0x1u << 5) /**< \brief (LCDC_OVR2IMR) End of List Interrupt Mask Register */
+#define LCDC_OVR2IMR_OVR (0x1u << 6) /**< \brief (LCDC_OVR2IMR) Overflow Interrupt Mask Register */
+/* -------- LCDC_OVR2ISR : (LCDC Offset: 0x00000258) Overlay 2 Interrupt Status Register -------- */
+#define LCDC_OVR2ISR_DMA (0x1u << 2) /**< \brief (LCDC_OVR2ISR) End of DMA Transfer */
+#define LCDC_OVR2ISR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR2ISR) DMA Descriptor Loaded */
+#define LCDC_OVR2ISR_ADD (0x1u << 4) /**< \brief (LCDC_OVR2ISR) Head Descriptor Loaded */
+#define LCDC_OVR2ISR_DONE (0x1u << 5) /**< \brief (LCDC_OVR2ISR) End of List Detected */
+#define LCDC_OVR2ISR_OVR (0x1u << 6) /**< \brief (LCDC_OVR2ISR) Overflow Detected */
+/* -------- LCDC_OVR2HEAD : (LCDC Offset: 0x0000025C) Overlay 2 DMA Head Register -------- */
+#define LCDC_OVR2HEAD_HEAD_Pos 2
+#define LCDC_OVR2HEAD_HEAD_Msk (0x3fffffffu << LCDC_OVR2HEAD_HEAD_Pos) /**< \brief (LCDC_OVR2HEAD) DMA Head Pointer */
+#define LCDC_OVR2HEAD_HEAD(value) ((LCDC_OVR2HEAD_HEAD_Msk & ((value) << LCDC_OVR2HEAD_HEAD_Pos)))
+/* -------- LCDC_OVR2ADDR : (LCDC Offset: 0x00000260) Overlay 2 DMA Address Register -------- */
+#define LCDC_OVR2ADDR_ADDR_Pos 0
+#define LCDC_OVR2ADDR_ADDR_Msk (0xffffffffu << LCDC_OVR2ADDR_ADDR_Pos) /**< \brief (LCDC_OVR2ADDR) DMA Transfer Overlay 2 Address */
+#define LCDC_OVR2ADDR_ADDR(value) ((LCDC_OVR2ADDR_ADDR_Msk & ((value) << LCDC_OVR2ADDR_ADDR_Pos)))
+/* -------- LCDC_OVR2CTRL : (LCDC Offset: 0x00000264) Overlay 2 DMA Control Register -------- */
+#define LCDC_OVR2CTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_OVR2CTRL) Transfer Descriptor Fetch Enable */
+#define LCDC_OVR2CTRL_LFETCH (0x1u << 1) /**< \brief (LCDC_OVR2CTRL) Lookup Table Fetch Enable */
+#define LCDC_OVR2CTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_OVR2CTRL) End of DMA Transfer Interrupt Enable */
+#define LCDC_OVR2CTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_OVR2CTRL) Descriptor Loaded Interrupt Enable */
+#define LCDC_OVR2CTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_OVR2CTRL) Add Head Descriptor to Queue Interrupt Enable */
+#define LCDC_OVR2CTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_OVR2CTRL) End of List Interrupt Enable */
+/* -------- LCDC_OVR2NEXT : (LCDC Offset: 0x00000268) Overlay 2 DMA Next Register -------- */
+#define LCDC_OVR2NEXT_NEXT_Pos 0
+#define LCDC_OVR2NEXT_NEXT_Msk (0xffffffffu << LCDC_OVR2NEXT_NEXT_Pos) /**< \brief (LCDC_OVR2NEXT) DMA Descriptor Next Address */
+#define LCDC_OVR2NEXT_NEXT(value) ((LCDC_OVR2NEXT_NEXT_Msk & ((value) << LCDC_OVR2NEXT_NEXT_Pos)))
+/* -------- LCDC_OVR2CFG0 : (LCDC Offset: 0x0000026C) Overlay 2 Configuration Register 0 -------- */
+#define LCDC_OVR2CFG0_BLEN_Pos 4
+#define LCDC_OVR2CFG0_BLEN_Msk (0x3u << LCDC_OVR2CFG0_BLEN_Pos) /**< \brief (LCDC_OVR2CFG0) AHB Burst Length */
+#define LCDC_OVR2CFG0_BLEN(value) ((LCDC_OVR2CFG0_BLEN_Msk & ((value) << LCDC_OVR2CFG0_BLEN_Pos)))
+#define   LCDC_OVR2CFG0_BLEN_AHB_SINGLE (0x0u << 4) /**< \brief (LCDC_OVR2CFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define   LCDC_OVR2CFG0_BLEN_AHB_INCR4 (0x1u << 4) /**< \brief (LCDC_OVR2CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define   LCDC_OVR2CFG0_BLEN_AHB_INCR8 (0x2u << 4) /**< \brief (LCDC_OVR2CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define   LCDC_OVR2CFG0_BLEN_AHB_INCR16 (0x3u << 4) /**< \brief (LCDC_OVR2CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define LCDC_OVR2CFG0_DLBO (0x1u << 8) /**< \brief (LCDC_OVR2CFG0) Defined Length Burst Only For Channel Bus Transaction. */
+#define LCDC_OVR2CFG0_ROTDIS (0x1u << 12) /**< \brief (LCDC_OVR2CFG0) Hardware Rotation Optimization Disable */
+#define LCDC_OVR2CFG0_LOCKDIS (0x1u << 13) /**< \brief (LCDC_OVR2CFG0) Hardware Rotation Lock Disable */
+/* -------- LCDC_OVR2CFG1 : (LCDC Offset: 0x00000270) Overlay 2 Configuration Register 1 -------- */
+#define LCDC_OVR2CFG1_CLUTEN (0x1u << 0) /**< \brief (LCDC_OVR2CFG1) Color Lookup Table Mode Enable */
+#define LCDC_OVR2CFG1_RGBMODE_Pos 4
+#define LCDC_OVR2CFG1_RGBMODE_Msk (0xfu << LCDC_OVR2CFG1_RGBMODE_Pos) /**< \brief (LCDC_OVR2CFG1) RGB Mode Input Selection */
+#define LCDC_OVR2CFG1_RGBMODE(value) ((LCDC_OVR2CFG1_RGBMODE_Msk & ((value) << LCDC_OVR2CFG1_RGBMODE_Pos)))
+#define   LCDC_OVR2CFG1_RGBMODE_12BPP_RGB_444 (0x0u << 4) /**< \brief (LCDC_OVR2CFG1) 12 bpp RGB 444 */
+#define   LCDC_OVR2CFG1_RGBMODE_16BPP_ARGB_4444 (0x1u << 4) /**< \brief (LCDC_OVR2CFG1) 16 bpp ARGB 4444 */
+#define   LCDC_OVR2CFG1_RGBMODE_16BPP_RGBA_4444 (0x2u << 4) /**< \brief (LCDC_OVR2CFG1) 16 bpp RGBA 4444 */
+#define   LCDC_OVR2CFG1_RGBMODE_16BPP_RGB_565 (0x3u << 4) /**< \brief (LCDC_OVR2CFG1) 16 bpp RGB 565 */
+#define   LCDC_OVR2CFG1_RGBMODE_16BPP_TRGB_1555 (0x4u << 4) /**< \brief (LCDC_OVR2CFG1) 16 bpp TRGB 1555 */
+#define   LCDC_OVR2CFG1_RGBMODE_18BPP_RGB_666 (0x5u << 4) /**< \brief (LCDC_OVR2CFG1) 18 bpp RGB 666 */
+#define   LCDC_OVR2CFG1_RGBMODE_18BPP_RGB_666PACKED (0x6u << 4) /**< \brief (LCDC_OVR2CFG1) 18 bpp RGB 666 PACKED */
+#define   LCDC_OVR2CFG1_RGBMODE_19BPP_TRGB_1666 (0x7u << 4) /**< \brief (LCDC_OVR2CFG1) 19 bpp TRGB 1666 */
+#define   LCDC_OVR2CFG1_RGBMODE_19BPP_TRGB_PACKED (0x8u << 4) /**< \brief (LCDC_OVR2CFG1) 19 bpp TRGB 1666 PACKED */
+#define   LCDC_OVR2CFG1_RGBMODE_24BPP_RGB_888 (0x9u << 4) /**< \brief (LCDC_OVR2CFG1) 24 bpp RGB 888 */
+#define   LCDC_OVR2CFG1_RGBMODE_24BPP_RGB_888_PACKED (0xAu << 4) /**< \brief (LCDC_OVR2CFG1) 24 bpp RGB 888 PACKED */
+#define   LCDC_OVR2CFG1_RGBMODE_25BPP_TRGB_1888 (0xBu << 4) /**< \brief (LCDC_OVR2CFG1) 25 bpp TRGB 1888 */
+#define   LCDC_OVR2CFG1_RGBMODE_32BPP_ARGB_8888 (0xCu << 4) /**< \brief (LCDC_OVR2CFG1) 32 bpp ARGB 8888 */
+#define   LCDC_OVR2CFG1_RGBMODE_32BPP_RGBA_8888 (0xDu << 4) /**< \brief (LCDC_OVR2CFG1) 32 bpp RGBA 8888 */
+#define LCDC_OVR2CFG1_CLUTMODE_Pos 8
+#define LCDC_OVR2CFG1_CLUTMODE_Msk (0x3u << LCDC_OVR2CFG1_CLUTMODE_Pos) /**< \brief (LCDC_OVR2CFG1) Color Lookup Table Mode Input Selection */
+#define LCDC_OVR2CFG1_CLUTMODE(value) ((LCDC_OVR2CFG1_CLUTMODE_Msk & ((value) << LCDC_OVR2CFG1_CLUTMODE_Pos)))
+#define   LCDC_OVR2CFG1_CLUTMODE_CLUT_1BPP (0x0u << 8) /**< \brief (LCDC_OVR2CFG1) Color Lookup Table mode set to 1 bit per pixel */
+#define   LCDC_OVR2CFG1_CLUTMODE_CLUT_2BPP (0x1u << 8) /**< \brief (LCDC_OVR2CFG1) Color Lookup Table mode set to 2 bits per pixel */
+#define   LCDC_OVR2CFG1_CLUTMODE_CLUT_4BPP (0x2u << 8) /**< \brief (LCDC_OVR2CFG1) Color Lookup Table mode set to 4 bits per pixel */
+#define   LCDC_OVR2CFG1_CLUTMODE_CLUT_8BPP (0x3u << 8) /**< \brief (LCDC_OVR2CFG1) Color Lookup Table mode set to 8 bits per pixel */
+/* -------- LCDC_OVR2CFG2 : (LCDC Offset: 0x00000274) Overlay 2 Configuration Register 2 -------- */
+#define LCDC_OVR2CFG2_XPOS_Pos 0
+#define LCDC_OVR2CFG2_XPOS_Msk (0x7ffu << LCDC_OVR2CFG2_XPOS_Pos) /**< \brief (LCDC_OVR2CFG2) Horizontal Window Position */
+#define LCDC_OVR2CFG2_XPOS(value) ((LCDC_OVR2CFG2_XPOS_Msk & ((value) << LCDC_OVR2CFG2_XPOS_Pos)))
+#define LCDC_OVR2CFG2_YPOS_Pos 16
+#define LCDC_OVR2CFG2_YPOS_Msk (0x7ffu << LCDC_OVR2CFG2_YPOS_Pos) /**< \brief (LCDC_OVR2CFG2) Vertical Window Position */
+#define LCDC_OVR2CFG2_YPOS(value) ((LCDC_OVR2CFG2_YPOS_Msk & ((value) << LCDC_OVR2CFG2_YPOS_Pos)))
+/* -------- LCDC_OVR2CFG3 : (LCDC Offset: 0x00000278) Overlay 2 Configuration Register 3 -------- */
+#define LCDC_OVR2CFG3_XSIZE_Pos 0
+#define LCDC_OVR2CFG3_XSIZE_Msk (0x7ffu << LCDC_OVR2CFG3_XSIZE_Pos) /**< \brief (LCDC_OVR2CFG3) Horizontal Window Size */
+#define LCDC_OVR2CFG3_XSIZE(value) ((LCDC_OVR2CFG3_XSIZE_Msk & ((value) << LCDC_OVR2CFG3_XSIZE_Pos)))
+#define LCDC_OVR2CFG3_YSIZE_Pos 16
+#define LCDC_OVR2CFG3_YSIZE_Msk (0x7ffu << LCDC_OVR2CFG3_YSIZE_Pos) /**< \brief (LCDC_OVR2CFG3) Vertical Window Size */
+#define LCDC_OVR2CFG3_YSIZE(value) ((LCDC_OVR2CFG3_YSIZE_Msk & ((value) << LCDC_OVR2CFG3_YSIZE_Pos)))
+/* -------- LCDC_OVR2CFG4 : (LCDC Offset: 0x0000027C) Overlay 2 Configuration Register 4 -------- */
+#define LCDC_OVR2CFG4_XSTRIDE_Pos 0
+#define LCDC_OVR2CFG4_XSTRIDE_Msk (0xffffffffu << LCDC_OVR2CFG4_XSTRIDE_Pos) /**< \brief (LCDC_OVR2CFG4) Horizontal Stride */
+#define LCDC_OVR2CFG4_XSTRIDE(value) ((LCDC_OVR2CFG4_XSTRIDE_Msk & ((value) << LCDC_OVR2CFG4_XSTRIDE_Pos)))
+/* -------- LCDC_OVR2CFG5 : (LCDC Offset: 0x00000280) Overlay 2 Configuration Register 5 -------- */
+#define LCDC_OVR2CFG5_PSTRIDE_Pos 0
+#define LCDC_OVR2CFG5_PSTRIDE_Msk (0xffffffffu << LCDC_OVR2CFG5_PSTRIDE_Pos) /**< \brief (LCDC_OVR2CFG5) Pixel Stride */
+#define LCDC_OVR2CFG5_PSTRIDE(value) ((LCDC_OVR2CFG5_PSTRIDE_Msk & ((value) << LCDC_OVR2CFG5_PSTRIDE_Pos)))
+/* -------- LCDC_OVR2CFG6 : (LCDC Offset: 0x00000284) Overlay 2 Configuration Register 6 -------- */
+#define LCDC_OVR2CFG6_BDEF_Pos 0
+#define LCDC_OVR2CFG6_BDEF_Msk (0xffu << LCDC_OVR2CFG6_BDEF_Pos) /**< \brief (LCDC_OVR2CFG6) Blue Default */
+#define LCDC_OVR2CFG6_BDEF(value) ((LCDC_OVR2CFG6_BDEF_Msk & ((value) << LCDC_OVR2CFG6_BDEF_Pos)))
+#define LCDC_OVR2CFG6_GDEF_Pos 8
+#define LCDC_OVR2CFG6_GDEF_Msk (0xffu << LCDC_OVR2CFG6_GDEF_Pos) /**< \brief (LCDC_OVR2CFG6) Green Default */
+#define LCDC_OVR2CFG6_GDEF(value) ((LCDC_OVR2CFG6_GDEF_Msk & ((value) << LCDC_OVR2CFG6_GDEF_Pos)))
+#define LCDC_OVR2CFG6_RDEF_Pos 16
+#define LCDC_OVR2CFG6_RDEF_Msk (0xffu << LCDC_OVR2CFG6_RDEF_Pos) /**< \brief (LCDC_OVR2CFG6) Red Default */
+#define LCDC_OVR2CFG6_RDEF(value) ((LCDC_OVR2CFG6_RDEF_Msk & ((value) << LCDC_OVR2CFG6_RDEF_Pos)))
+/* -------- LCDC_OVR2CFG7 : (LCDC Offset: 0x00000288) Overlay 2 Configuration Register 7 -------- */
+#define LCDC_OVR2CFG7_BKEY_Pos 0
+#define LCDC_OVR2CFG7_BKEY_Msk (0xffu << LCDC_OVR2CFG7_BKEY_Pos) /**< \brief (LCDC_OVR2CFG7) Blue Color Component Chroma Key */
+#define LCDC_OVR2CFG7_BKEY(value) ((LCDC_OVR2CFG7_BKEY_Msk & ((value) << LCDC_OVR2CFG7_BKEY_Pos)))
+#define LCDC_OVR2CFG7_GKEY_Pos 8
+#define LCDC_OVR2CFG7_GKEY_Msk (0xffu << LCDC_OVR2CFG7_GKEY_Pos) /**< \brief (LCDC_OVR2CFG7) Green Color Component Chroma Key */
+#define LCDC_OVR2CFG7_GKEY(value) ((LCDC_OVR2CFG7_GKEY_Msk & ((value) << LCDC_OVR2CFG7_GKEY_Pos)))
+#define LCDC_OVR2CFG7_RKEY_Pos 16
+#define LCDC_OVR2CFG7_RKEY_Msk (0xffu << LCDC_OVR2CFG7_RKEY_Pos) /**< \brief (LCDC_OVR2CFG7) Red Color Component Chroma Key */
+#define LCDC_OVR2CFG7_RKEY(value) ((LCDC_OVR2CFG7_RKEY_Msk & ((value) << LCDC_OVR2CFG7_RKEY_Pos)))
+/* -------- LCDC_OVR2CFG8 : (LCDC Offset: 0x0000028C) Overlay 2 Configuration Register 8 -------- */
+#define LCDC_OVR2CFG8_BMASK_Pos 0
+#define LCDC_OVR2CFG8_BMASK_Msk (0xffu << LCDC_OVR2CFG8_BMASK_Pos) /**< \brief (LCDC_OVR2CFG8) Blue Color Component Chroma Key Mask */
+#define LCDC_OVR2CFG8_BMASK(value) ((LCDC_OVR2CFG8_BMASK_Msk & ((value) << LCDC_OVR2CFG8_BMASK_Pos)))
+#define LCDC_OVR2CFG8_GMASK_Pos 8
+#define LCDC_OVR2CFG8_GMASK_Msk (0xffu << LCDC_OVR2CFG8_GMASK_Pos) /**< \brief (LCDC_OVR2CFG8) Green Color Component Chroma Key Mask */
+#define LCDC_OVR2CFG8_GMASK(value) ((LCDC_OVR2CFG8_GMASK_Msk & ((value) << LCDC_OVR2CFG8_GMASK_Pos)))
+#define LCDC_OVR2CFG8_RMASK_Pos 16
+#define LCDC_OVR2CFG8_RMASK_Msk (0xffu << LCDC_OVR2CFG8_RMASK_Pos) /**< \brief (LCDC_OVR2CFG8) Red Color Component Chroma Key Mask */
+#define LCDC_OVR2CFG8_RMASK(value) ((LCDC_OVR2CFG8_RMASK_Msk & ((value) << LCDC_OVR2CFG8_RMASK_Pos)))
+/* -------- LCDC_OVR2CFG9 : (LCDC Offset: 0x00000290) Overlay 2 Configuration Register 8 -------- */
+#define LCDC_OVR2CFG9_CRKEY (0x1u << 0) /**< \brief (LCDC_OVR2CFG9) Blender Chroma Key Enable */
+#define LCDC_OVR2CFG9_INV (0x1u << 1) /**< \brief (LCDC_OVR2CFG9) Blender Inverted Blender Output Enable */
+#define LCDC_OVR2CFG9_ITER2BL (0x1u << 2) /**< \brief (LCDC_OVR2CFG9) Blender Iterated Color Enable */
+#define LCDC_OVR2CFG9_ITER (0x1u << 3) /**< \brief (LCDC_OVR2CFG9) Blender Use Iterated Color */
+#define LCDC_OVR2CFG9_REVALPHA (0x1u << 4) /**< \brief (LCDC_OVR2CFG9) Blender Reverse Alpha */
+#define LCDC_OVR2CFG9_GAEN (0x1u << 5) /**< \brief (LCDC_OVR2CFG9) Blender Global Alpha Enable */
+#define LCDC_OVR2CFG9_LAEN (0x1u << 6) /**< \brief (LCDC_OVR2CFG9) Blender Local Alpha Enable */
+#define LCDC_OVR2CFG9_OVR (0x1u << 7) /**< \brief (LCDC_OVR2CFG9) Blender Overlay Layer Enable */
+#define LCDC_OVR2CFG9_DMA (0x1u << 8) /**< \brief (LCDC_OVR2CFG9) Blender DMA Layer Enable */
+#define LCDC_OVR2CFG9_REP (0x1u << 9) /**< \brief (LCDC_OVR2CFG9) Use Replication logic to expand RGB color to 24 bits */
+#define LCDC_OVR2CFG9_DSTKEY (0x1u << 10) /**< \brief (LCDC_OVR2CFG9) Destination Chroma Keying */
+#define LCDC_OVR2CFG9_GA_Pos 16
+#define LCDC_OVR2CFG9_GA_Msk (0xffu << LCDC_OVR2CFG9_GA_Pos) /**< \brief (LCDC_OVR2CFG9) Blender Global Alpha */
+#define LCDC_OVR2CFG9_GA(value) ((LCDC_OVR2CFG9_GA_Msk & ((value) << LCDC_OVR2CFG9_GA_Pos)))
+/* -------- LCDC_HEOCHER : (LCDC Offset: 0x00000340) High End Overlay Channel Enable Register -------- */
+#define LCDC_HEOCHER_CHEN (0x1u << 0) /**< \brief (LCDC_HEOCHER) Channel Enable Register */
+#define LCDC_HEOCHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_HEOCHER) Update Overlay Attributes Enable Register */
+#define LCDC_HEOCHER_A2QEN (0x1u << 2) /**< \brief (LCDC_HEOCHER) Add To Queue Enable Register */
+/* -------- LCDC_HEOCHDR : (LCDC Offset: 0x00000344) High End Overlay Channel Disable Register -------- */
+#define LCDC_HEOCHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_HEOCHDR) Channel Disable Register */
+#define LCDC_HEOCHDR_CHRST (0x1u << 8) /**< \brief (LCDC_HEOCHDR) Channel Reset Register */
+/* -------- LCDC_HEOCHSR : (LCDC Offset: 0x00000348) High End Overlay Channel Status Register -------- */
+#define LCDC_HEOCHSR_CHSR (0x1u << 0) /**< \brief (LCDC_HEOCHSR) Channel Status Register */
+#define LCDC_HEOCHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_HEOCHSR) Update Overlay Attributes In Progress Status Register */
+#define LCDC_HEOCHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_HEOCHSR) Add To Queue Status Register */
+/* -------- LCDC_HEOIER : (LCDC Offset: 0x0000034C) High End Overlay Interrupt Enable Register -------- */
+#define LCDC_HEOIER_DMA (0x1u << 2) /**< \brief (LCDC_HEOIER) End of DMA Transfer Interrupt Enable Register */
+#define LCDC_HEOIER_DSCR (0x1u << 3) /**< \brief (LCDC_HEOIER) Descriptor Loaded Interrupt Enable Register */
+#define LCDC_HEOIER_ADD (0x1u << 4) /**< \brief (LCDC_HEOIER) Head Descriptor Loaded Interrupt Enable Register */
+#define LCDC_HEOIER_DONE (0x1u << 5) /**< \brief (LCDC_HEOIER) End of List Interrupt Enable Register */
+#define LCDC_HEOIER_OVR (0x1u << 6) /**< \brief (LCDC_HEOIER) Overflow Interrupt Enable Register */
+#define LCDC_HEOIER_UDMA (0x1u << 10) /**< \brief (LCDC_HEOIER) End of DMA Transfer for U or UV Chrominance Interrupt Enable Register */
+#define LCDC_HEOIER_UDSCR (0x1u << 11) /**< \brief (LCDC_HEOIER) Descriptor Loaded for U or UV Chrominance Interrupt Enable Register */
+#define LCDC_HEOIER_UADD (0x1u << 12) /**< \brief (LCDC_HEOIER) Head Descriptor Loaded for U or UV Chrominance Interrupt Enable Register */
+#define LCDC_HEOIER_UDONE (0x1u << 13) /**< \brief (LCDC_HEOIER) End of List for U or UV Chrominance Interrupt Enable Register */
+#define LCDC_HEOIER_UOVR (0x1u << 14) /**< \brief (LCDC_HEOIER) Overflow for U or UV Chrominance Interrupt Enable Register */
+#define LCDC_HEOIER_VDMA (0x1u << 18) /**< \brief (LCDC_HEOIER) End of DMA for V Chrominance Transfer Interrupt Enable Register */
+#define LCDC_HEOIER_VDSCR (0x1u << 19) /**< \brief (LCDC_HEOIER) Descriptor Loaded for V Chrominance Interrupt Enable Register */
+#define LCDC_HEOIER_VADD (0x1u << 20) /**< \brief (LCDC_HEOIER) Head Descriptor Loaded for V Chrominance Interrupt Enable Register */
+#define LCDC_HEOIER_VDONE (0x1u << 21) /**< \brief (LCDC_HEOIER) End of List for V Chrominance Interrupt Enable Register */
+#define LCDC_HEOIER_VOVR (0x1u << 22) /**< \brief (LCDC_HEOIER) Overflow for V Chrominance Interrupt Enable Register */
+/* -------- LCDC_HEOIDR : (LCDC Offset: 0x00000350) High End Overlay Interrupt Disable Register -------- */
+#define LCDC_HEOIDR_DMA (0x1u << 2) /**< \brief (LCDC_HEOIDR) End of DMA Transfer Interrupt Disable Register */
+#define LCDC_HEOIDR_DSCR (0x1u << 3) /**< \brief (LCDC_HEOIDR) Descriptor Loaded Interrupt Disable Register */
+#define LCDC_HEOIDR_ADD (0x1u << 4) /**< \brief (LCDC_HEOIDR) Head Descriptor Loaded Interrupt Disable Register */
+#define LCDC_HEOIDR_DONE (0x1u << 5) /**< \brief (LCDC_HEOIDR) End of List Interrupt Disable Register */
+#define LCDC_HEOIDR_OVR (0x1u << 6) /**< \brief (LCDC_HEOIDR) Overflow Interrupt Disable Register */
+#define LCDC_HEOIDR_UDMA (0x1u << 10) /**< \brief (LCDC_HEOIDR) End of DMA Transfer for U or UV Chrominance Component Interrupt Disable Register */
+#define LCDC_HEOIDR_UDSCR (0x1u << 11) /**< \brief (LCDC_HEOIDR) Descriptor Loaded for U or UV Chrominance Component Interrupt Disable Register */
+#define LCDC_HEOIDR_UADD (0x1u << 12) /**< \brief (LCDC_HEOIDR) Head Descriptor Loaded for U or UV Chrominance Component Interrupt Disable Register */
+#define LCDC_HEOIDR_UDONE (0x1u << 13) /**< \brief (LCDC_HEOIDR) End of List Interrupt for U or UV Chrominance Component Disable Register */
+#define LCDC_HEOIDR_UOVR (0x1u << 14) /**< \brief (LCDC_HEOIDR) Overflow Interrupt for U or UV Chrominance Component Disable Register */
+#define LCDC_HEOIDR_VDMA (0x1u << 18) /**< \brief (LCDC_HEOIDR) End of DMA Transfer for V Chrominance Component Interrupt Disable Register */
+#define LCDC_HEOIDR_VDSCR (0x1u << 19) /**< \brief (LCDC_HEOIDR) Descriptor Loaded for V Chrominance Component Interrupt Disable Register */
+#define LCDC_HEOIDR_VADD (0x1u << 20) /**< \brief (LCDC_HEOIDR) Head Descriptor Loaded for V Chrominance Component Interrupt Disable Register */
+#define LCDC_HEOIDR_VDONE (0x1u << 21) /**< \brief (LCDC_HEOIDR) End of List for V Chrominance Component Interrupt Disable Register */
+#define LCDC_HEOIDR_VOVR (0x1u << 22) /**< \brief (LCDC_HEOIDR) Overflow for V Chrominance Component Interrupt Disable Register */
+/* -------- LCDC_HEOIMR : (LCDC Offset: 0x00000354) High End Overlay Interrupt Mask Register -------- */
+#define LCDC_HEOIMR_DMA (0x1u << 2) /**< \brief (LCDC_HEOIMR) End of DMA Transfer Interrupt Mask Register */
+#define LCDC_HEOIMR_DSCR (0x1u << 3) /**< \brief (LCDC_HEOIMR) Descriptor Loaded Interrupt Mask Register */
+#define LCDC_HEOIMR_ADD (0x1u << 4) /**< \brief (LCDC_HEOIMR) Head Descriptor Loaded Interrupt Mask Register */
+#define LCDC_HEOIMR_DONE (0x1u << 5) /**< \brief (LCDC_HEOIMR) End of List Interrupt Mask Register */
+#define LCDC_HEOIMR_OVR (0x1u << 6) /**< \brief (LCDC_HEOIMR) Overflow Interrupt Mask Register */
+#define LCDC_HEOIMR_UDMA (0x1u << 10) /**< \brief (LCDC_HEOIMR) End of DMA Transfer for U or UV Chrominance Component Interrupt Mask Register */
+#define LCDC_HEOIMR_UDSCR (0x1u << 11) /**< \brief (LCDC_HEOIMR) Descriptor Loaded for U or UV Chrominance Component Interrupt Mask Register */
+#define LCDC_HEOIMR_UADD (0x1u << 12) /**< \brief (LCDC_HEOIMR) Head Descriptor Loaded for U or UV Chrominance Component Mask Register */
+#define LCDC_HEOIMR_UDONE (0x1u << 13) /**< \brief (LCDC_HEOIMR) End of List for U or UV Chrominance Component Mask Register */
+#define LCDC_HEOIMR_UOVR (0x1u << 14) /**< \brief (LCDC_HEOIMR) Overflow for U Chrominance Interrupt Mask Register */
+#define LCDC_HEOIMR_VDMA (0x1u << 18) /**< \brief (LCDC_HEOIMR) End of DMA Transfer for V Chrominance Component Interrupt Mask Register */
+#define LCDC_HEOIMR_VDSCR (0x1u << 19) /**< \brief (LCDC_HEOIMR) Descriptor Loaded for V Chrominance Component Interrupt Mask Register */
+#define LCDC_HEOIMR_VADD (0x1u << 20) /**< \brief (LCDC_HEOIMR) Head Descriptor Loaded for V Chrominance Component Mask Register */
+#define LCDC_HEOIMR_VDONE (0x1u << 21) /**< \brief (LCDC_HEOIMR) End of List for V Chrominance Component Mask Register */
+#define LCDC_HEOIMR_VOVR (0x1u << 22) /**< \brief (LCDC_HEOIMR) Overflow for V Chrominance Interrupt Mask Register */
+/* -------- LCDC_HEOISR : (LCDC Offset: 0x00000358) High End Overlay Interrupt Status Register -------- */
+#define LCDC_HEOISR_DMA (0x1u << 2) /**< \brief (LCDC_HEOISR) End of DMA Transfer */
+#define LCDC_HEOISR_DSCR (0x1u << 3) /**< \brief (LCDC_HEOISR) DMA Descriptor Loaded */
+#define LCDC_HEOISR_ADD (0x1u << 4) /**< \brief (LCDC_HEOISR) Head Descriptor Loaded */
+#define LCDC_HEOISR_DONE (0x1u << 5) /**< \brief (LCDC_HEOISR) End of List Detected */
+#define LCDC_HEOISR_OVR (0x1u << 6) /**< \brief (LCDC_HEOISR) Overflow Detected */
+#define LCDC_HEOISR_UDMA (0x1u << 10) /**< \brief (LCDC_HEOISR) End of DMA Transfer for U Component */
+#define LCDC_HEOISR_UDSCR (0x1u << 11) /**< \brief (LCDC_HEOISR) DMA Descriptor Loaded for U Component */
+#define LCDC_HEOISR_UADD (0x1u << 12) /**< \brief (LCDC_HEOISR) Head Descriptor Loaded for U Component */
+#define LCDC_HEOISR_UDONE (0x1u << 13) /**< \brief (LCDC_HEOISR) End of List Detected for U Component */
+#define LCDC_HEOISR_UOVR (0x1u << 14) /**< \brief (LCDC_HEOISR) Overflow Detected for U Component */
+#define LCDC_HEOISR_VDMA (0x1u << 18) /**< \brief (LCDC_HEOISR) End of DMA Transfer for V Component */
+#define LCDC_HEOISR_VDSCR (0x1u << 19) /**< \brief (LCDC_HEOISR) DMA Descriptor Loaded for V Component */
+#define LCDC_HEOISR_VADD (0x1u << 20) /**< \brief (LCDC_HEOISR) Head Descriptor Loaded for V Component */
+#define LCDC_HEOISR_VDONE (0x1u << 21) /**< \brief (LCDC_HEOISR) End of List Detected for V Component */
+#define LCDC_HEOISR_VOVR (0x1u << 22) /**< \brief (LCDC_HEOISR) Overflow Detected for V Component */
+/* -------- LCDC_HEOHEAD : (LCDC Offset: 0x0000035C) High End Overlay DMA Head Register -------- */
+#define LCDC_HEOHEAD_HEAD_Pos 2
+#define LCDC_HEOHEAD_HEAD_Msk (0x3fffffffu << LCDC_HEOHEAD_HEAD_Pos) /**< \brief (LCDC_HEOHEAD) DMA Head Pointer */
+#define LCDC_HEOHEAD_HEAD(value) ((LCDC_HEOHEAD_HEAD_Msk & ((value) << LCDC_HEOHEAD_HEAD_Pos)))
+/* -------- LCDC_HEOADDR : (LCDC Offset: 0x00000360) High End Overlay DMA Address Register -------- */
+#define LCDC_HEOADDR_ADDR_Pos 0
+#define LCDC_HEOADDR_ADDR_Msk (0xffffffffu << LCDC_HEOADDR_ADDR_Pos) /**< \brief (LCDC_HEOADDR) DMA Transfer start Address */
+#define LCDC_HEOADDR_ADDR(value) ((LCDC_HEOADDR_ADDR_Msk & ((value) << LCDC_HEOADDR_ADDR_Pos)))
+/* -------- LCDC_HEOCTRL : (LCDC Offset: 0x00000364) High End Overlay DMA Control Register -------- */
+#define LCDC_HEOCTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_HEOCTRL) Transfer Descriptor Fetch Enable */
+#define LCDC_HEOCTRL_LFETCH (0x1u << 1) /**< \brief (LCDC_HEOCTRL) Lookup Table Fetch Enable */
+#define LCDC_HEOCTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_HEOCTRL) End of DMA Transfer Interrupt Enable */
+#define LCDC_HEOCTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_HEOCTRL) Descriptor Loaded Interrupt Enable */
+#define LCDC_HEOCTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_HEOCTRL) Add Head Descriptor to Queue Interrupt Enable */
+#define LCDC_HEOCTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_HEOCTRL) End of List Interrupt Enable */
+/* -------- LCDC_HEONEXT : (LCDC Offset: 0x00000368) High End Overlay DMA Next Register -------- */
+#define LCDC_HEONEXT_NEXT_Pos 0
+#define LCDC_HEONEXT_NEXT_Msk (0xffffffffu << LCDC_HEONEXT_NEXT_Pos) /**< \brief (LCDC_HEONEXT) DMA Descriptor Next Address */
+#define LCDC_HEONEXT_NEXT(value) ((LCDC_HEONEXT_NEXT_Msk & ((value) << LCDC_HEONEXT_NEXT_Pos)))
+/* -------- LCDC_HEOUHEAD : (LCDC Offset: 0x0000036C) High End Overlay U-UV DMA Head Register -------- */
+#define LCDC_HEOUHEAD_UHEAD_Pos 0
+#define LCDC_HEOUHEAD_UHEAD_Msk (0xffffffffu << LCDC_HEOUHEAD_UHEAD_Pos) /**< \brief (LCDC_HEOUHEAD) DMA Head Pointer */
+#define LCDC_HEOUHEAD_UHEAD(value) ((LCDC_HEOUHEAD_UHEAD_Msk & ((value) << LCDC_HEOUHEAD_UHEAD_Pos)))
+/* -------- LCDC_HEOUADDR : (LCDC Offset: 0x00000370) High End Overlay U-UV DMA Address Register -------- */
+#define LCDC_HEOUADDR_UADDR_Pos 0
+#define LCDC_HEOUADDR_UADDR_Msk (0xffffffffu << LCDC_HEOUADDR_UADDR_Pos) /**< \brief (LCDC_HEOUADDR) DMA Transfer Start Address for U or UV Chrominance */
+#define LCDC_HEOUADDR_UADDR(value) ((LCDC_HEOUADDR_UADDR_Msk & ((value) << LCDC_HEOUADDR_UADDR_Pos)))
+/* -------- LCDC_HEOUCTRL : (LCDC Offset: 0x00000374) High End Overlay U-UV DMA Control Register -------- */
+#define LCDC_HEOUCTRL_UDFETCH (0x1u << 0) /**< \brief (LCDC_HEOUCTRL) Transfer Descriptor Fetch Enable */
+#define LCDC_HEOUCTRL_UDMAIEN (0x1u << 2) /**< \brief (LCDC_HEOUCTRL) End of DMA Transfer Interrupt Enable */
+#define LCDC_HEOUCTRL_UDSCRIEN (0x1u << 3) /**< \brief (LCDC_HEOUCTRL) Descriptor Loaded Interrupt Enable */
+#define LCDC_HEOUCTRL_UADDIEN (0x1u << 4) /**< \brief (LCDC_HEOUCTRL) Add Head Descriptor to Queue Interrupt Enable */
+#define LCDC_HEOUCTRL_UDONEIEN (0x1u << 5) /**< \brief (LCDC_HEOUCTRL) End of List Interrupt Enable */
+/* -------- LCDC_HEOUNEXT : (LCDC Offset: 0x00000378) High End Overlay U-UV DMA Next Register -------- */
+#define LCDC_HEOUNEXT_UNEXT_Pos 0
+#define LCDC_HEOUNEXT_UNEXT_Msk (0xffffffffu << LCDC_HEOUNEXT_UNEXT_Pos) /**< \brief (LCDC_HEOUNEXT) DMA Descriptor Next Address */
+#define LCDC_HEOUNEXT_UNEXT(value) ((LCDC_HEOUNEXT_UNEXT_Msk & ((value) << LCDC_HEOUNEXT_UNEXT_Pos)))
+/* -------- LCDC_HEOVHEAD : (LCDC Offset: 0x0000037C) High End Overlay V DMA Head Register -------- */
+#define LCDC_HEOVHEAD_VHEAD_Pos 0
+#define LCDC_HEOVHEAD_VHEAD_Msk (0xffffffffu << LCDC_HEOVHEAD_VHEAD_Pos) /**< \brief (LCDC_HEOVHEAD) DMA Head Pointer */
+#define LCDC_HEOVHEAD_VHEAD(value) ((LCDC_HEOVHEAD_VHEAD_Msk & ((value) << LCDC_HEOVHEAD_VHEAD_Pos)))
+/* -------- LCDC_HEOVADDR : (LCDC Offset: 0x00000380) High End Overlay V DMA Address Register -------- */
+#define LCDC_HEOVADDR_VADDR_Pos 0
+#define LCDC_HEOVADDR_VADDR_Msk (0xffffffffu << LCDC_HEOVADDR_VADDR_Pos) /**< \brief (LCDC_HEOVADDR) DMA Transfer Start Address for V Chrominance */
+#define LCDC_HEOVADDR_VADDR(value) ((LCDC_HEOVADDR_VADDR_Msk & ((value) << LCDC_HEOVADDR_VADDR_Pos)))
+/* -------- LCDC_HEOVCTRL : (LCDC Offset: 0x00000384) High End Overlay V DMA Control Register -------- */
+#define LCDC_HEOVCTRL_VDFETCH (0x1u << 0) /**< \brief (LCDC_HEOVCTRL) Transfer Descriptor Fetch Enable */
+#define LCDC_HEOVCTRL_VDMAIEN (0x1u << 2) /**< \brief (LCDC_HEOVCTRL) End of DMA Transfer Interrupt Enable */
+#define LCDC_HEOVCTRL_VDSCRIEN (0x1u << 3) /**< \brief (LCDC_HEOVCTRL) Descriptor Loaded Interrupt Enable */
+#define LCDC_HEOVCTRL_VADDIEN (0x1u << 4) /**< \brief (LCDC_HEOVCTRL) Add Head Descriptor to Queue Interrupt Enable */
+#define LCDC_HEOVCTRL_VDONEIEN (0x1u << 5) /**< \brief (LCDC_HEOVCTRL) End of List Interrupt Enable */
+/* -------- LCDC_HEOVNEXT : (LCDC Offset: 0x00000388) High End Overlay V DMA Next Register -------- */
+#define LCDC_HEOVNEXT_VNEXT_Pos 0
+#define LCDC_HEOVNEXT_VNEXT_Msk (0xffffffffu << LCDC_HEOVNEXT_VNEXT_Pos) /**< \brief (LCDC_HEOVNEXT) DMA Descriptor Next Address */
+#define LCDC_HEOVNEXT_VNEXT(value) ((LCDC_HEOVNEXT_VNEXT_Msk & ((value) << LCDC_HEOVNEXT_VNEXT_Pos)))
+/* -------- LCDC_HEOCFG0 : (LCDC Offset: 0x0000038C) High End Overlay Configuration Register 0 -------- */
+#define LCDC_HEOCFG0_SIF (0x1u << 0) /**< \brief (LCDC_HEOCFG0) Source Interface */
+#define LCDC_HEOCFG0_BLEN_Pos 4
+#define LCDC_HEOCFG0_BLEN_Msk (0x3u << LCDC_HEOCFG0_BLEN_Pos) /**< \brief (LCDC_HEOCFG0) AHB Burst Length */
+#define LCDC_HEOCFG0_BLEN(value) ((LCDC_HEOCFG0_BLEN_Msk & ((value) << LCDC_HEOCFG0_BLEN_Pos)))
+#define   LCDC_HEOCFG0_BLEN_AHB_BLEN_SINGLE (0x0u << 4) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define   LCDC_HEOCFG0_BLEN_AHB_BLEN_INCR4 (0x1u << 4) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define   LCDC_HEOCFG0_BLEN_AHB_BLEN_INCR8 (0x2u << 4) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define   LCDC_HEOCFG0_BLEN_AHB_BLEN_INCR16 (0x3u << 4) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define LCDC_HEOCFG0_BLENUV_Pos 6
+#define LCDC_HEOCFG0_BLENUV_Msk (0x3u << LCDC_HEOCFG0_BLENUV_Pos) /**< \brief (LCDC_HEOCFG0) AHB Burst Length for U-V channel */
+#define LCDC_HEOCFG0_BLENUV(value) ((LCDC_HEOCFG0_BLENUV_Msk & ((value) << LCDC_HEOCFG0_BLENUV_Pos)))
+#define   LCDC_HEOCFG0_BLENUV_AHB_SINGLE (0x0u << 6) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define   LCDC_HEOCFG0_BLENUV_AHB_INCR4 (0x1u << 6) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define   LCDC_HEOCFG0_BLENUV_AHB_INCR8 (0x2u << 6) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define   LCDC_HEOCFG0_BLENUV_AHB_INCR16 (0x3u << 6) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define LCDC_HEOCFG0_DLBO (0x1u << 8) /**< \brief (LCDC_HEOCFG0) Defined Length Burst Only For Channel Bus Transaction. */
+#define LCDC_HEOCFG0_ROTDIS (0x1u << 12) /**< \brief (LCDC_HEOCFG0) Hardware Rotation Optimization Disable */
+#define LCDC_HEOCFG0_LOCKDIS (0x1u << 13) /**< \brief (LCDC_HEOCFG0) Hardware Rotation Lock Disable */
+/* -------- LCDC_HEOCFG1 : (LCDC Offset: 0x00000390) High End Overlay Configuration Register 1 -------- */
+#define LCDC_HEOCFG1_CLUTEN (0x1u << 0) /**< \brief (LCDC_HEOCFG1) Color Lookup Table Mode Enable */
+#define LCDC_HEOCFG1_YUVEN (0x1u << 1) /**< \brief (LCDC_HEOCFG1) YUV Color Space Enable */
+#define LCDC_HEOCFG1_RGBMODE_Pos 4
+#define LCDC_HEOCFG1_RGBMODE_Msk (0xfu << LCDC_HEOCFG1_RGBMODE_Pos) /**< \brief (LCDC_HEOCFG1) RGB Mode Input selection */
+#define LCDC_HEOCFG1_RGBMODE(value) ((LCDC_HEOCFG1_RGBMODE_Msk & ((value) << LCDC_HEOCFG1_RGBMODE_Pos)))
+#define   LCDC_HEOCFG1_RGBMODE_12BPP_RGB_444 (0x0u << 4) /**< \brief (LCDC_HEOCFG1) 12 bpp RGB 444 */
+#define   LCDC_HEOCFG1_RGBMODE_16BPP_ARGB_4444 (0x1u << 4) /**< \brief (LCDC_HEOCFG1) 16 bpp ARGB 4444 */
+#define   LCDC_HEOCFG1_RGBMODE_16BPP_RGBA_4444 (0x2u << 4) /**< \brief (LCDC_HEOCFG1) 16 bpp RGBA 4444 */
+#define   LCDC_HEOCFG1_RGBMODE_16BPP_RGB_565 (0x3u << 4) /**< \brief (LCDC_HEOCFG1) 16 bpp RGB 565 */
+#define   LCDC_HEOCFG1_RGBMODE_16BPP_TRGB_1555 (0x4u << 4) /**< \brief (LCDC_HEOCFG1) 16 bpp TRGB 1555 */
+#define   LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666 (0x5u << 4) /**< \brief (LCDC_HEOCFG1) 18 bpp RGB 666 */
+#define   LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666PACKED (0x6u << 4) /**< \brief (LCDC_HEOCFG1) 18 bpp RGB 666 PACKED */
+#define   LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_1666 (0x7u << 4) /**< \brief (LCDC_HEOCFG1) 19 bpp TRGB 1666 */
+#define   LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_PACKED (0x8u << 4) /**< \brief (LCDC_HEOCFG1) 19 bpp TRGB 1666 PACKED */
+#define   LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888 (0x9u << 4) /**< \brief (LCDC_HEOCFG1) 24 bpp RGB 888 */
+#define   LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888_PACKED (0xAu << 4) /**< \brief (LCDC_HEOCFG1) 24 bpp RGB 888 PACKED */
+#define   LCDC_HEOCFG1_RGBMODE_25BPP_TRGB_1888 (0xBu << 4) /**< \brief (LCDC_HEOCFG1) 25 bpp TRGB 1888 */
+#define   LCDC_HEOCFG1_RGBMODE_32BPP_ARGB_8888 (0xCu << 4) /**< \brief (LCDC_HEOCFG1) 32 bpp ARGB 8888 */
+#define   LCDC_HEOCFG1_RGBMODE_32BPP_RGBA_8888 (0xDu << 4) /**< \brief (LCDC_HEOCFG1) 32 bpp RGBA 8888 */
+#define LCDC_HEOCFG1_CLUTMODE_Pos 8
+#define LCDC_HEOCFG1_CLUTMODE_Msk (0x3u << LCDC_HEOCFG1_CLUTMODE_Pos) /**< \brief (LCDC_HEOCFG1) Color Lookup Table Mode Input Selection */
+#define LCDC_HEOCFG1_CLUTMODE(value) ((LCDC_HEOCFG1_CLUTMODE_Msk & ((value) << LCDC_HEOCFG1_CLUTMODE_Pos)))
+#define   LCDC_HEOCFG1_CLUTMODE_CLUT_1BPP (0x0u << 8) /**< \brief (LCDC_HEOCFG1) Color Lookup Table mode set to 1 bit per pixel */
+#define   LCDC_HEOCFG1_CLUTMODE_CLUT_2BPP (0x1u << 8) /**< \brief (LCDC_HEOCFG1) Color Lookup Table mode set to 2 bits per pixel */
+#define   LCDC_HEOCFG1_CLUTMODE_CLUT_4BPP (0x2u << 8) /**< \brief (LCDC_HEOCFG1) Color Lookup Table mode set to 4 bits per pixel */
+#define   LCDC_HEOCFG1_CLUTMODE_CLUT_8BPP (0x3u << 8) /**< \brief (LCDC_HEOCFG1) Color Lookup Table mode set to 8 bits per pixel */
+#define LCDC_HEOCFG1_YUVMODE_Pos 12
+#define LCDC_HEOCFG1_YUVMODE_Msk (0xfu << LCDC_HEOCFG1_YUVMODE_Pos) /**< \brief (LCDC_HEOCFG1) YUV Mode Input Selection */
+#define LCDC_HEOCFG1_YUVMODE(value) ((LCDC_HEOCFG1_YUVMODE_Msk & ((value) << LCDC_HEOCFG1_YUVMODE_Pos)))
+#define   LCDC_HEOCFG1_YUVMODE_32BPP_AYCBCR (0x0u << 12) /**< \brief (LCDC_HEOCFG1) 32 bpp AYCbCr 444 */
+#define   LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE0 (0x1u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Cr(n)Y(n+1)Cb(n)Y(n) 422 */
+#define   LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE1 (0x2u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Y(n+1)Cr(n)Y(n)Cb(n) 422 */
+#define   LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE2 (0x3u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Cb(n)Y(+1)Cr(n)Y(n) 422 */
+#define   LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE3 (0x4u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Y(n+1)Cb(n)Y(n)Cr(n) 422 */
+#define   LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_SEMIPLANAR (0x5u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Semiplanar 422 YCbCr */
+#define   LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_PLANAR (0x6u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Planar 422 YCbCr */
+#define   LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_SEMIPLANAR (0x7u << 12) /**< \brief (LCDC_HEOCFG1) 12 bpp Semiplanar 420 YCbCr */
+#define   LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_PLANAR (0x8u << 12) /**< \brief (LCDC_HEOCFG1) 12 bpp Planar 420 YCbCr */
+#define LCDC_HEOCFG1_YUV422ROT (0x1u << 16) /**< \brief (LCDC_HEOCFG1) YUV 4:2:2 Rotation */
+#define LCDC_HEOCFG1_YUV422SWP (0x1u << 17) /**< \brief (LCDC_HEOCFG1) YUV 4:2:2 Swap */
+#define LCDC_HEOCFG1_DSCALEOPT (0x1u << 20) /**< \brief (LCDC_HEOCFG1) Down Scaling Bandwidth Optimization */
+/* -------- LCDC_HEOCFG2 : (LCDC Offset: 0x00000394) High End Overlay Configuration Register 2 -------- */
+#define LCDC_HEOCFG2_XPOS_Pos 0
+#define LCDC_HEOCFG2_XPOS_Msk (0x7ffu << LCDC_HEOCFG2_XPOS_Pos) /**< \brief (LCDC_HEOCFG2) Horizontal Window Position */
+#define LCDC_HEOCFG2_XPOS(value) ((LCDC_HEOCFG2_XPOS_Msk & ((value) << LCDC_HEOCFG2_XPOS_Pos)))
+#define LCDC_HEOCFG2_YPOS_Pos 16
+#define LCDC_HEOCFG2_YPOS_Msk (0x7ffu << LCDC_HEOCFG2_YPOS_Pos) /**< \brief (LCDC_HEOCFG2) Vertical Window Position */
+#define LCDC_HEOCFG2_YPOS(value) ((LCDC_HEOCFG2_YPOS_Msk & ((value) << LCDC_HEOCFG2_YPOS_Pos)))
+/* -------- LCDC_HEOCFG3 : (LCDC Offset: 0x00000398) High End Overlay Configuration Register 3 -------- */
+#define LCDC_HEOCFG3_XSIZE_Pos 0
+#define LCDC_HEOCFG3_XSIZE_Msk (0x7ffu << LCDC_HEOCFG3_XSIZE_Pos) /**< \brief (LCDC_HEOCFG3) Horizontal Window Size */
+#define LCDC_HEOCFG3_XSIZE(value) ((LCDC_HEOCFG3_XSIZE_Msk & ((value) << LCDC_HEOCFG3_XSIZE_Pos)))
+#define LCDC_HEOCFG3_YSIZE_Pos 16
+#define LCDC_HEOCFG3_YSIZE_Msk (0x7ffu << LCDC_HEOCFG3_YSIZE_Pos) /**< \brief (LCDC_HEOCFG3) Vertical Window Size */
+#define LCDC_HEOCFG3_YSIZE(value) ((LCDC_HEOCFG3_YSIZE_Msk & ((value) << LCDC_HEOCFG3_YSIZE_Pos)))
+/* -------- LCDC_HEOCFG4 : (LCDC Offset: 0x0000039C) High End Overlay Configuration Register 4 -------- */
+#define LCDC_HEOCFG4_XMEMSIZE_Pos 0
+#define LCDC_HEOCFG4_XMEMSIZE_Msk (0x7ffu << LCDC_HEOCFG4_XMEMSIZE_Pos) /**< \brief (LCDC_HEOCFG4) Horizontal image Size in Memory */
+#define LCDC_HEOCFG4_XMEMSIZE(value) ((LCDC_HEOCFG4_XMEMSIZE_Msk & ((value) << LCDC_HEOCFG4_XMEMSIZE_Pos)))
+#define LCDC_HEOCFG4_YMEMSIZE_Pos 16
+#define LCDC_HEOCFG4_YMEMSIZE_Msk (0x7ffu << LCDC_HEOCFG4_YMEMSIZE_Pos) /**< \brief (LCDC_HEOCFG4) Vertical image Size in Memory */
+#define LCDC_HEOCFG4_YMEMSIZE(value) ((LCDC_HEOCFG4_YMEMSIZE_Msk & ((value) << LCDC_HEOCFG4_YMEMSIZE_Pos)))
+/* -------- LCDC_HEOCFG5 : (LCDC Offset: 0x000003A0) High End Overlay Configuration Register 5 -------- */
+#define LCDC_HEOCFG5_XSTRIDE_Pos 0
+#define LCDC_HEOCFG5_XSTRIDE_Msk (0xffffffffu << LCDC_HEOCFG5_XSTRIDE_Pos) /**< \brief (LCDC_HEOCFG5) Horizontal Stride */
+#define LCDC_HEOCFG5_XSTRIDE(value) ((LCDC_HEOCFG5_XSTRIDE_Msk & ((value) << LCDC_HEOCFG5_XSTRIDE_Pos)))
+/* -------- LCDC_HEOCFG6 : (LCDC Offset: 0x000003A4) High End Overlay Configuration Register 6 -------- */
+#define LCDC_HEOCFG6_PSTRIDE_Pos 0
+#define LCDC_HEOCFG6_PSTRIDE_Msk (0xffffffffu << LCDC_HEOCFG6_PSTRIDE_Pos) /**< \brief (LCDC_HEOCFG6) Pixel Stride */
+#define LCDC_HEOCFG6_PSTRIDE(value) ((LCDC_HEOCFG6_PSTRIDE_Msk & ((value) << LCDC_HEOCFG6_PSTRIDE_Pos)))
+/* -------- LCDC_HEOCFG7 : (LCDC Offset: 0x000003A8) High End Overlay Configuration Register 7 -------- */
+#define LCDC_HEOCFG7_UVXSTRIDE_Pos 0
+#define LCDC_HEOCFG7_UVXSTRIDE_Msk (0xffffffffu << LCDC_HEOCFG7_UVXSTRIDE_Pos) /**< \brief (LCDC_HEOCFG7) UV Horizontal Stride */
+#define LCDC_HEOCFG7_UVXSTRIDE(value) ((LCDC_HEOCFG7_UVXSTRIDE_Msk & ((value) << LCDC_HEOCFG7_UVXSTRIDE_Pos)))
+/* -------- LCDC_HEOCFG8 : (LCDC Offset: 0x000003AC) High End Overlay Configuration Register 8 -------- */
+#define LCDC_HEOCFG8_UVPSTRIDE_Pos 0
+#define LCDC_HEOCFG8_UVPSTRIDE_Msk (0xffffffffu << LCDC_HEOCFG8_UVPSTRIDE_Pos) /**< \brief (LCDC_HEOCFG8) UV Pixel Stride */
+#define LCDC_HEOCFG8_UVPSTRIDE(value) ((LCDC_HEOCFG8_UVPSTRIDE_Msk & ((value) << LCDC_HEOCFG8_UVPSTRIDE_Pos)))
+/* -------- LCDC_HEOCFG9 : (LCDC Offset: 0x000003B0) High End Overlay Configuration Register 9 -------- */
+#define LCDC_HEOCFG9_BDEF_Pos 0
+#define LCDC_HEOCFG9_BDEF_Msk (0xffu << LCDC_HEOCFG9_BDEF_Pos) /**< \brief (LCDC_HEOCFG9) Blue Default */
+#define LCDC_HEOCFG9_BDEF(value) ((LCDC_HEOCFG9_BDEF_Msk & ((value) << LCDC_HEOCFG9_BDEF_Pos)))
+#define LCDC_HEOCFG9_GDEF_Pos 8
+#define LCDC_HEOCFG9_GDEF_Msk (0xffu << LCDC_HEOCFG9_GDEF_Pos) /**< \brief (LCDC_HEOCFG9) Green Default */
+#define LCDC_HEOCFG9_GDEF(value) ((LCDC_HEOCFG9_GDEF_Msk & ((value) << LCDC_HEOCFG9_GDEF_Pos)))
+#define LCDC_HEOCFG9_RDEF_Pos 16
+#define LCDC_HEOCFG9_RDEF_Msk (0xffu << LCDC_HEOCFG9_RDEF_Pos) /**< \brief (LCDC_HEOCFG9) Red Default */
+#define LCDC_HEOCFG9_RDEF(value) ((LCDC_HEOCFG9_RDEF_Msk & ((value) << LCDC_HEOCFG9_RDEF_Pos)))
+/* -------- LCDC_HEOCFG10 : (LCDC Offset: 0x000003B4) High End Overlay Configuration Register 10 -------- */
+#define LCDC_HEOCFG10_BKEY_Pos 0
+#define LCDC_HEOCFG10_BKEY_Msk (0xffu << LCDC_HEOCFG10_BKEY_Pos) /**< \brief (LCDC_HEOCFG10) Blue Color Component Chroma Key */
+#define LCDC_HEOCFG10_BKEY(value) ((LCDC_HEOCFG10_BKEY_Msk & ((value) << LCDC_HEOCFG10_BKEY_Pos)))
+#define LCDC_HEOCFG10_GKEY_Pos 8
+#define LCDC_HEOCFG10_GKEY_Msk (0xffu << LCDC_HEOCFG10_GKEY_Pos) /**< \brief (LCDC_HEOCFG10) Green Color Component Chroma Key */
+#define LCDC_HEOCFG10_GKEY(value) ((LCDC_HEOCFG10_GKEY_Msk & ((value) << LCDC_HEOCFG10_GKEY_Pos)))
+#define LCDC_HEOCFG10_RKEY_Pos 16
+#define LCDC_HEOCFG10_RKEY_Msk (0xffu << LCDC_HEOCFG10_RKEY_Pos) /**< \brief (LCDC_HEOCFG10) Red Color Component Chroma Key */
+#define LCDC_HEOCFG10_RKEY(value) ((LCDC_HEOCFG10_RKEY_Msk & ((value) << LCDC_HEOCFG10_RKEY_Pos)))
+/* -------- LCDC_HEOCFG11 : (LCDC Offset: 0x000003B8) High End Overlay Configuration Register 11 -------- */
+#define LCDC_HEOCFG11_BMASK_Pos 0
+#define LCDC_HEOCFG11_BMASK_Msk (0xffu << LCDC_HEOCFG11_BMASK_Pos) /**< \brief (LCDC_HEOCFG11) Blue Color Component Chroma Key Mask */
+#define LCDC_HEOCFG11_BMASK(value) ((LCDC_HEOCFG11_BMASK_Msk & ((value) << LCDC_HEOCFG11_BMASK_Pos)))
+#define LCDC_HEOCFG11_GMASK_Pos 8
+#define LCDC_HEOCFG11_GMASK_Msk (0xffu << LCDC_HEOCFG11_GMASK_Pos) /**< \brief (LCDC_HEOCFG11) Green Color Component Chroma Key Mask */
+#define LCDC_HEOCFG11_GMASK(value) ((LCDC_HEOCFG11_GMASK_Msk & ((value) << LCDC_HEOCFG11_GMASK_Pos)))
+#define LCDC_HEOCFG11_RMASK_Pos 16
+#define LCDC_HEOCFG11_RMASK_Msk (0xffu << LCDC_HEOCFG11_RMASK_Pos) /**< \brief (LCDC_HEOCFG11) Red Color Component Chroma Key Mask */
+#define LCDC_HEOCFG11_RMASK(value) ((LCDC_HEOCFG11_RMASK_Msk & ((value) << LCDC_HEOCFG11_RMASK_Pos)))
+/* -------- LCDC_HEOCFG12 : (LCDC Offset: 0x000003BC) High End Overlay Configuration Register 12 -------- */
+#define LCDC_HEOCFG12_CRKEY (0x1u << 0) /**< \brief (LCDC_HEOCFG12) Blender Chroma Key Enable */
+#define LCDC_HEOCFG12_INV (0x1u << 1) /**< \brief (LCDC_HEOCFG12) Blender Inverted Blender Output Enable */
+#define LCDC_HEOCFG12_ITER2BL (0x1u << 2) /**< \brief (LCDC_HEOCFG12) Blender Iterated Color Enable */
+#define LCDC_HEOCFG12_ITER (0x1u << 3) /**< \brief (LCDC_HEOCFG12) Blender Use Iterated Color */
+#define LCDC_HEOCFG12_REVALPHA (0x1u << 4) /**< \brief (LCDC_HEOCFG12) Blender Reverse Alpha */
+#define LCDC_HEOCFG12_GAEN (0x1u << 5) /**< \brief (LCDC_HEOCFG12) Blender Global Alpha Enable */
+#define LCDC_HEOCFG12_LAEN (0x1u << 6) /**< \brief (LCDC_HEOCFG12) Blender Local Alpha Enable */
+#define LCDC_HEOCFG12_OVR (0x1u << 7) /**< \brief (LCDC_HEOCFG12) Blender Overlay Layer Enable */
+#define LCDC_HEOCFG12_DMA (0x1u << 8) /**< \brief (LCDC_HEOCFG12) Blender DMA Layer Enable */
+#define LCDC_HEOCFG12_REP (0x1u << 9) /**< \brief (LCDC_HEOCFG12) Use Replication logic to expand RGB color to 24 bits */
+#define LCDC_HEOCFG12_DSTKEY (0x1u << 10) /**< \brief (LCDC_HEOCFG12) Destination Chroma Keying */
+#define LCDC_HEOCFG12_VIDPRI (0x1u << 12) /**< \brief (LCDC_HEOCFG12) Video Priority */
+#define LCDC_HEOCFG12_GA_Pos 16
+#define LCDC_HEOCFG12_GA_Msk (0xffu << LCDC_HEOCFG12_GA_Pos) /**< \brief (LCDC_HEOCFG12) Blender Global Alpha */
+#define LCDC_HEOCFG12_GA(value) ((LCDC_HEOCFG12_GA_Msk & ((value) << LCDC_HEOCFG12_GA_Pos)))
+/* -------- LCDC_HEOCFG13 : (LCDC Offset: 0x000003C0) High End Overlay Configuration Register 13 -------- */
+#define LCDC_HEOCFG13_XFACTOR_Pos 0
+#define LCDC_HEOCFG13_XFACTOR_Msk (0x3fffu << LCDC_HEOCFG13_XFACTOR_Pos) /**< \brief (LCDC_HEOCFG13) Horizontal Scaling Factor */
+#define LCDC_HEOCFG13_XFACTOR(value) ((LCDC_HEOCFG13_XFACTOR_Msk & ((value) << LCDC_HEOCFG13_XFACTOR_Pos)))
+#define LCDC_HEOCFG13_YFACTOR_Pos 16
+#define LCDC_HEOCFG13_YFACTOR_Msk (0x3fffu << LCDC_HEOCFG13_YFACTOR_Pos) /**< \brief (LCDC_HEOCFG13) Vertical Scaling Factor */
+#define LCDC_HEOCFG13_YFACTOR(value) ((LCDC_HEOCFG13_YFACTOR_Msk & ((value) << LCDC_HEOCFG13_YFACTOR_Pos)))
+#define LCDC_HEOCFG13_SCALEN (0x1u << 31) /**< \brief (LCDC_HEOCFG13) Hardware Scaler Enable */
+/* -------- LCDC_HEOCFG14 : (LCDC Offset: 0x000003C4) High End Overlay Configuration Register 14 -------- */
+#define LCDC_HEOCFG14_CSCRY_Pos 0
+#define LCDC_HEOCFG14_CSCRY_Msk (0x3ffu << LCDC_HEOCFG14_CSCRY_Pos) /**< \brief (LCDC_HEOCFG14) Color Space Conversion Y coefficient for Red Component 1:2:7 format */
+#define LCDC_HEOCFG14_CSCRY(value) ((LCDC_HEOCFG14_CSCRY_Msk & ((value) << LCDC_HEOCFG14_CSCRY_Pos)))
+#define LCDC_HEOCFG14_CSCRU_Pos 10
+#define LCDC_HEOCFG14_CSCRU_Msk (0x3ffu << LCDC_HEOCFG14_CSCRU_Pos) /**< \brief (LCDC_HEOCFG14) Color Space Conversion U coefficient for Red Component 1:2:7 format */
+#define LCDC_HEOCFG14_CSCRU(value) ((LCDC_HEOCFG14_CSCRU_Msk & ((value) << LCDC_HEOCFG14_CSCRU_Pos)))
+#define LCDC_HEOCFG14_CSCRV_Pos 20
+#define LCDC_HEOCFG14_CSCRV_Msk (0x3ffu << LCDC_HEOCFG14_CSCRV_Pos) /**< \brief (LCDC_HEOCFG14) Color Space Conversion V coefficient for Red Component 1:2:7 format */
+#define LCDC_HEOCFG14_CSCRV(value) ((LCDC_HEOCFG14_CSCRV_Msk & ((value) << LCDC_HEOCFG14_CSCRV_Pos)))
+#define LCDC_HEOCFG14_CSCYOFF (0x1u << 30) /**< \brief (LCDC_HEOCFG14) Color Space Conversion Offset */
+/* -------- LCDC_HEOCFG15 : (LCDC Offset: 0x000003C8) High End Overlay Configuration Register 15 -------- */
+#define LCDC_HEOCFG15_CSCGY_Pos 0
+#define LCDC_HEOCFG15_CSCGY_Msk (0x3ffu << LCDC_HEOCFG15_CSCGY_Pos) /**< \brief (LCDC_HEOCFG15) Color Space Conversion Y coefficient for Green Component 1:2:7 format */
+#define LCDC_HEOCFG15_CSCGY(value) ((LCDC_HEOCFG15_CSCGY_Msk & ((value) << LCDC_HEOCFG15_CSCGY_Pos)))
+#define LCDC_HEOCFG15_CSCGU_Pos 10
+#define LCDC_HEOCFG15_CSCGU_Msk (0x3ffu << LCDC_HEOCFG15_CSCGU_Pos) /**< \brief (LCDC_HEOCFG15) Color Space Conversion U coefficient for Green Component 1:2:7 format */
+#define LCDC_HEOCFG15_CSCGU(value) ((LCDC_HEOCFG15_CSCGU_Msk & ((value) << LCDC_HEOCFG15_CSCGU_Pos)))
+#define LCDC_HEOCFG15_CSCGV_Pos 20
+#define LCDC_HEOCFG15_CSCGV_Msk (0x3ffu << LCDC_HEOCFG15_CSCGV_Pos) /**< \brief (LCDC_HEOCFG15) Color Space Conversion V coefficient for Green Component 1:2:7 format */
+#define LCDC_HEOCFG15_CSCGV(value) ((LCDC_HEOCFG15_CSCGV_Msk & ((value) << LCDC_HEOCFG15_CSCGV_Pos)))
+#define LCDC_HEOCFG15_CSCUOFF (0x1u << 30) /**< \brief (LCDC_HEOCFG15) Color Space Conversion Offset */
+/* -------- LCDC_HEOCFG16 : (LCDC Offset: 0x000003CC) High End Overlay Configuration Register 16 -------- */
+#define LCDC_HEOCFG16_CSCBY_Pos 0
+#define LCDC_HEOCFG16_CSCBY_Msk (0x3ffu << LCDC_HEOCFG16_CSCBY_Pos) /**< \brief (LCDC_HEOCFG16) Color Space Conversion Y coefficient for Blue Component 1:2:7 format */
+#define LCDC_HEOCFG16_CSCBY(value) ((LCDC_HEOCFG16_CSCBY_Msk & ((value) << LCDC_HEOCFG16_CSCBY_Pos)))
+#define LCDC_HEOCFG16_CSCBU_Pos 10
+#define LCDC_HEOCFG16_CSCBU_Msk (0x3ffu << LCDC_HEOCFG16_CSCBU_Pos) /**< \brief (LCDC_HEOCFG16) Color Space Conversion U coefficient for Blue Component 1:2:7 format */
+#define LCDC_HEOCFG16_CSCBU(value) ((LCDC_HEOCFG16_CSCBU_Msk & ((value) << LCDC_HEOCFG16_CSCBU_Pos)))
+#define LCDC_HEOCFG16_CSCBV_Pos 20
+#define LCDC_HEOCFG16_CSCBV_Msk (0x3ffu << LCDC_HEOCFG16_CSCBV_Pos) /**< \brief (LCDC_HEOCFG16) Color Space Conversion V coefficient for Blue Component 1:2:7 format */
+#define LCDC_HEOCFG16_CSCBV(value) ((LCDC_HEOCFG16_CSCBV_Msk & ((value) << LCDC_HEOCFG16_CSCBV_Pos)))
+#define LCDC_HEOCFG16_CSCVOFF (0x1u << 30) /**< \brief (LCDC_HEOCFG16) Color Space Conversion Offset */
+/* -------- LCDC_HEOCFG17 : (LCDC Offset: 0x000003D0) High End Overlay Configuration Register 17 -------- */
+#define LCDC_HEOCFG17_XPHI0COEFF0_Pos 0
+#define LCDC_HEOCFG17_XPHI0COEFF0_Msk (0xffu << LCDC_HEOCFG17_XPHI0COEFF0_Pos) /**< \brief (LCDC_HEOCFG17) Horizontal Coefficient for phase 0 tap 0 */
+#define LCDC_HEOCFG17_XPHI0COEFF0(value) ((LCDC_HEOCFG17_XPHI0COEFF0_Msk & ((value) << LCDC_HEOCFG17_XPHI0COEFF0_Pos)))
+#define LCDC_HEOCFG17_XPHI0COEFF1_Pos 8
+#define LCDC_HEOCFG17_XPHI0COEFF1_Msk (0xffu << LCDC_HEOCFG17_XPHI0COEFF1_Pos) /**< \brief (LCDC_HEOCFG17) Horizontal Coefficient for phase 0 tap 1 */
+#define LCDC_HEOCFG17_XPHI0COEFF1(value) ((LCDC_HEOCFG17_XPHI0COEFF1_Msk & ((value) << LCDC_HEOCFG17_XPHI0COEFF1_Pos)))
+#define LCDC_HEOCFG17_XPHI0COEFF2_Pos 16
+#define LCDC_HEOCFG17_XPHI0COEFF2_Msk (0xffu << LCDC_HEOCFG17_XPHI0COEFF2_Pos) /**< \brief (LCDC_HEOCFG17) Horizontal Coefficient for phase 0 tap 2 */
+#define LCDC_HEOCFG17_XPHI0COEFF2(value) ((LCDC_HEOCFG17_XPHI0COEFF2_Msk & ((value) << LCDC_HEOCFG17_XPHI0COEFF2_Pos)))
+#define LCDC_HEOCFG17_XPHI0COEFF3_Pos 24
+#define LCDC_HEOCFG17_XPHI0COEFF3_Msk (0xffu << LCDC_HEOCFG17_XPHI0COEFF3_Pos) /**< \brief (LCDC_HEOCFG17) Horizontal Coefficient for phase 0 tap 3 */
+#define LCDC_HEOCFG17_XPHI0COEFF3(value) ((LCDC_HEOCFG17_XPHI0COEFF3_Msk & ((value) << LCDC_HEOCFG17_XPHI0COEFF3_Pos)))
+/* -------- LCDC_HEOCFG18 : (LCDC Offset: 0x000003D4) High End Overlay Configuration Register 18 -------- */
+#define LCDC_HEOCFG18_XPHI0COEFF4_Pos 0
+#define LCDC_HEOCFG18_XPHI0COEFF4_Msk (0xffu << LCDC_HEOCFG18_XPHI0COEFF4_Pos) /**< \brief (LCDC_HEOCFG18) Horizontal Coefficient for phase 0 tap 4 */
+#define LCDC_HEOCFG18_XPHI0COEFF4(value) ((LCDC_HEOCFG18_XPHI0COEFF4_Msk & ((value) << LCDC_HEOCFG18_XPHI0COEFF4_Pos)))
+/* -------- LCDC_HEOCFG19 : (LCDC Offset: 0x000003D8) High End Overlay Configuration Register 19 -------- */
+#define LCDC_HEOCFG19_XPHI1COEFF0_Pos 0
+#define LCDC_HEOCFG19_XPHI1COEFF0_Msk (0xffu << LCDC_HEOCFG19_XPHI1COEFF0_Pos) /**< \brief (LCDC_HEOCFG19) Horizontal Coefficient for phase 1 tap 0 */
+#define LCDC_HEOCFG19_XPHI1COEFF0(value) ((LCDC_HEOCFG19_XPHI1COEFF0_Msk & ((value) << LCDC_HEOCFG19_XPHI1COEFF0_Pos)))
+#define LCDC_HEOCFG19_XPHI1COEFF1_Pos 8
+#define LCDC_HEOCFG19_XPHI1COEFF1_Msk (0xffu << LCDC_HEOCFG19_XPHI1COEFF1_Pos) /**< \brief (LCDC_HEOCFG19) Horizontal Coefficient for phase 1 tap 1 */
+#define LCDC_HEOCFG19_XPHI1COEFF1(value) ((LCDC_HEOCFG19_XPHI1COEFF1_Msk & ((value) << LCDC_HEOCFG19_XPHI1COEFF1_Pos)))
+#define LCDC_HEOCFG19_XPHI1COEFF2_Pos 16
+#define LCDC_HEOCFG19_XPHI1COEFF2_Msk (0xffu << LCDC_HEOCFG19_XPHI1COEFF2_Pos) /**< \brief (LCDC_HEOCFG19) Horizontal Coefficient for phase 1 tap 2 */
+#define LCDC_HEOCFG19_XPHI1COEFF2(value) ((LCDC_HEOCFG19_XPHI1COEFF2_Msk & ((value) << LCDC_HEOCFG19_XPHI1COEFF2_Pos)))
+#define LCDC_HEOCFG19_XPHI1COEFF3_Pos 24
+#define LCDC_HEOCFG19_XPHI1COEFF3_Msk (0xffu << LCDC_HEOCFG19_XPHI1COEFF3_Pos) /**< \brief (LCDC_HEOCFG19) Horizontal Coefficient for phase 1 tap 3 */
+#define LCDC_HEOCFG19_XPHI1COEFF3(value) ((LCDC_HEOCFG19_XPHI1COEFF3_Msk & ((value) << LCDC_HEOCFG19_XPHI1COEFF3_Pos)))
+/* -------- LCDC_HEOCFG20 : (LCDC Offset: 0x000003DC) High End Overlay Configuration Register 20 -------- */
+#define LCDC_HEOCFG20_XPHI1COEFF4_Pos 0
+#define LCDC_HEOCFG20_XPHI1COEFF4_Msk (0xffu << LCDC_HEOCFG20_XPHI1COEFF4_Pos) /**< \brief (LCDC_HEOCFG20) Horizontal Coefficient for phase 1 tap 4 */
+#define LCDC_HEOCFG20_XPHI1COEFF4(value) ((LCDC_HEOCFG20_XPHI1COEFF4_Msk & ((value) << LCDC_HEOCFG20_XPHI1COEFF4_Pos)))
+/* -------- LCDC_HEOCFG21 : (LCDC Offset: 0x000003E0) High End Overlay Configuration Register 21 -------- */
+#define LCDC_HEOCFG21_XPHI2COEFF0_Pos 0
+#define LCDC_HEOCFG21_XPHI2COEFF0_Msk (0xffu << LCDC_HEOCFG21_XPHI2COEFF0_Pos) /**< \brief (LCDC_HEOCFG21) Horizontal Coefficient for phase 2 tap 0 */
+#define LCDC_HEOCFG21_XPHI2COEFF0(value) ((LCDC_HEOCFG21_XPHI2COEFF0_Msk & ((value) << LCDC_HEOCFG21_XPHI2COEFF0_Pos)))
+#define LCDC_HEOCFG21_XPHI2COEFF1_Pos 8
+#define LCDC_HEOCFG21_XPHI2COEFF1_Msk (0xffu << LCDC_HEOCFG21_XPHI2COEFF1_Pos) /**< \brief (LCDC_HEOCFG21) Horizontal Coefficient for phase 2 tap 1 */
+#define LCDC_HEOCFG21_XPHI2COEFF1(value) ((LCDC_HEOCFG21_XPHI2COEFF1_Msk & ((value) << LCDC_HEOCFG21_XPHI2COEFF1_Pos)))
+#define LCDC_HEOCFG21_XPHI2COEFF2_Pos 16
+#define LCDC_HEOCFG21_XPHI2COEFF2_Msk (0xffu << LCDC_HEOCFG21_XPHI2COEFF2_Pos) /**< \brief (LCDC_HEOCFG21) Horizontal Coefficient for phase 2 tap 2 */
+#define LCDC_HEOCFG21_XPHI2COEFF2(value) ((LCDC_HEOCFG21_XPHI2COEFF2_Msk & ((value) << LCDC_HEOCFG21_XPHI2COEFF2_Pos)))
+#define LCDC_HEOCFG21_XPHI2COEFF3_Pos 24
+#define LCDC_HEOCFG21_XPHI2COEFF3_Msk (0xffu << LCDC_HEOCFG21_XPHI2COEFF3_Pos) /**< \brief (LCDC_HEOCFG21) Horizontal Coefficient for phase 2 tap 3 */
+#define LCDC_HEOCFG21_XPHI2COEFF3(value) ((LCDC_HEOCFG21_XPHI2COEFF3_Msk & ((value) << LCDC_HEOCFG21_XPHI2COEFF3_Pos)))
+/* -------- LCDC_HEOCFG22 : (LCDC Offset: 0x000003E4) High End Overlay Configuration Register 22 -------- */
+#define LCDC_HEOCFG22_XPHI2COEFF4_Pos 0
+#define LCDC_HEOCFG22_XPHI2COEFF4_Msk (0xffu << LCDC_HEOCFG22_XPHI2COEFF4_Pos) /**< \brief (LCDC_HEOCFG22) Horizontal Coefficient for phase 2 tap 4 */
+#define LCDC_HEOCFG22_XPHI2COEFF4(value) ((LCDC_HEOCFG22_XPHI2COEFF4_Msk & ((value) << LCDC_HEOCFG22_XPHI2COEFF4_Pos)))
+/* -------- LCDC_HEOCFG23 : (LCDC Offset: 0x000003E8) High End Overlay Configuration Register 23 -------- */
+#define LCDC_HEOCFG23_XPHI3COEFF0_Pos 0
+#define LCDC_HEOCFG23_XPHI3COEFF0_Msk (0xffu << LCDC_HEOCFG23_XPHI3COEFF0_Pos) /**< \brief (LCDC_HEOCFG23) Horizontal Coefficient for phase 3 tap 0 */
+#define LCDC_HEOCFG23_XPHI3COEFF0(value) ((LCDC_HEOCFG23_XPHI3COEFF0_Msk & ((value) << LCDC_HEOCFG23_XPHI3COEFF0_Pos)))
+#define LCDC_HEOCFG23_XPHI3COEFF1_Pos 8
+#define LCDC_HEOCFG23_XPHI3COEFF1_Msk (0xffu << LCDC_HEOCFG23_XPHI3COEFF1_Pos) /**< \brief (LCDC_HEOCFG23) Horizontal Coefficient for phase 3 tap 1 */
+#define LCDC_HEOCFG23_XPHI3COEFF1(value) ((LCDC_HEOCFG23_XPHI3COEFF1_Msk & ((value) << LCDC_HEOCFG23_XPHI3COEFF1_Pos)))
+#define LCDC_HEOCFG23_XPHI3COEFF2_Pos 16
+#define LCDC_HEOCFG23_XPHI3COEFF2_Msk (0xffu << LCDC_HEOCFG23_XPHI3COEFF2_Pos) /**< \brief (LCDC_HEOCFG23) Horizontal Coefficient for phase 3 tap 2 */
+#define LCDC_HEOCFG23_XPHI3COEFF2(value) ((LCDC_HEOCFG23_XPHI3COEFF2_Msk & ((value) << LCDC_HEOCFG23_XPHI3COEFF2_Pos)))
+#define LCDC_HEOCFG23_XPHI3COEFF3_Pos 24
+#define LCDC_HEOCFG23_XPHI3COEFF3_Msk (0xffu << LCDC_HEOCFG23_XPHI3COEFF3_Pos) /**< \brief (LCDC_HEOCFG23) Horizontal Coefficient for phase 3 tap 3 */
+#define LCDC_HEOCFG23_XPHI3COEFF3(value) ((LCDC_HEOCFG23_XPHI3COEFF3_Msk & ((value) << LCDC_HEOCFG23_XPHI3COEFF3_Pos)))
+/* -------- LCDC_HEOCFG24 : (LCDC Offset: 0x000003EC) High End Overlay Configuration Register 24 -------- */
+#define LCDC_HEOCFG24_XPHI3COEFF4_Pos 0
+#define LCDC_HEOCFG24_XPHI3COEFF4_Msk (0xffu << LCDC_HEOCFG24_XPHI3COEFF4_Pos) /**< \brief (LCDC_HEOCFG24) Horizontal Coefficient for phase 3 tap 4 */
+#define LCDC_HEOCFG24_XPHI3COEFF4(value) ((LCDC_HEOCFG24_XPHI3COEFF4_Msk & ((value) << LCDC_HEOCFG24_XPHI3COEFF4_Pos)))
+/* -------- LCDC_HEOCFG25 : (LCDC Offset: 0x000003F0) High End Overlay Configuration Register 25 -------- */
+#define LCDC_HEOCFG25_XPHI4COEFF0_Pos 0
+#define LCDC_HEOCFG25_XPHI4COEFF0_Msk (0xffu << LCDC_HEOCFG25_XPHI4COEFF0_Pos) /**< \brief (LCDC_HEOCFG25) Horizontal Coefficient for phase 4 tap 0 */
+#define LCDC_HEOCFG25_XPHI4COEFF0(value) ((LCDC_HEOCFG25_XPHI4COEFF0_Msk & ((value) << LCDC_HEOCFG25_XPHI4COEFF0_Pos)))
+#define LCDC_HEOCFG25_XPHI4COEFF1_Pos 8
+#define LCDC_HEOCFG25_XPHI4COEFF1_Msk (0xffu << LCDC_HEOCFG25_XPHI4COEFF1_Pos) /**< \brief (LCDC_HEOCFG25) Horizontal Coefficient for phase 4 tap 1 */
+#define LCDC_HEOCFG25_XPHI4COEFF1(value) ((LCDC_HEOCFG25_XPHI4COEFF1_Msk & ((value) << LCDC_HEOCFG25_XPHI4COEFF1_Pos)))
+#define LCDC_HEOCFG25_XPHI4COEFF2_Pos 16
+#define LCDC_HEOCFG25_XPHI4COEFF2_Msk (0xffu << LCDC_HEOCFG25_XPHI4COEFF2_Pos) /**< \brief (LCDC_HEOCFG25) Horizontal Coefficient for phase 4 tap 2 */
+#define LCDC_HEOCFG25_XPHI4COEFF2(value) ((LCDC_HEOCFG25_XPHI4COEFF2_Msk & ((value) << LCDC_HEOCFG25_XPHI4COEFF2_Pos)))
+#define LCDC_HEOCFG25_XPHI4COEFF3_Pos 24
+#define LCDC_HEOCFG25_XPHI4COEFF3_Msk (0xffu << LCDC_HEOCFG25_XPHI4COEFF3_Pos) /**< \brief (LCDC_HEOCFG25) Horizontal Coefficient for phase 4 tap 3 */
+#define LCDC_HEOCFG25_XPHI4COEFF3(value) ((LCDC_HEOCFG25_XPHI4COEFF3_Msk & ((value) << LCDC_HEOCFG25_XPHI4COEFF3_Pos)))
+/* -------- LCDC_HEOCFG26 : (LCDC Offset: 0x000003F4) High End Overlay Configuration Register 26 -------- */
+#define LCDC_HEOCFG26_XPHI4COEFF4_Pos 0
+#define LCDC_HEOCFG26_XPHI4COEFF4_Msk (0xffu << LCDC_HEOCFG26_XPHI4COEFF4_Pos) /**< \brief (LCDC_HEOCFG26) Horizontal Coefficient for phase 4 tap 4 */
+#define LCDC_HEOCFG26_XPHI4COEFF4(value) ((LCDC_HEOCFG26_XPHI4COEFF4_Msk & ((value) << LCDC_HEOCFG26_XPHI4COEFF4_Pos)))
+/* -------- LCDC_HEOCFG27 : (LCDC Offset: 0x000003F8) High End Overlay Configuration Register 27 -------- */
+#define LCDC_HEOCFG27_XPHI5COEFF0_Pos 0
+#define LCDC_HEOCFG27_XPHI5COEFF0_Msk (0xffu << LCDC_HEOCFG27_XPHI5COEFF0_Pos) /**< \brief (LCDC_HEOCFG27) Horizontal Coefficient for phase 5 tap 0 */
+#define LCDC_HEOCFG27_XPHI5COEFF0(value) ((LCDC_HEOCFG27_XPHI5COEFF0_Msk & ((value) << LCDC_HEOCFG27_XPHI5COEFF0_Pos)))
+#define LCDC_HEOCFG27_XPHI5COEFF1_Pos 8
+#define LCDC_HEOCFG27_XPHI5COEFF1_Msk (0xffu << LCDC_HEOCFG27_XPHI5COEFF1_Pos) /**< \brief (LCDC_HEOCFG27) Horizontal Coefficient for phase 5 tap 1 */
+#define LCDC_HEOCFG27_XPHI5COEFF1(value) ((LCDC_HEOCFG27_XPHI5COEFF1_Msk & ((value) << LCDC_HEOCFG27_XPHI5COEFF1_Pos)))
+#define LCDC_HEOCFG27_XPHI5COEFF2_Pos 16
+#define LCDC_HEOCFG27_XPHI5COEFF2_Msk (0xffu << LCDC_HEOCFG27_XPHI5COEFF2_Pos) /**< \brief (LCDC_HEOCFG27) Horizontal Coefficient for phase 5 tap 2 */
+#define LCDC_HEOCFG27_XPHI5COEFF2(value) ((LCDC_HEOCFG27_XPHI5COEFF2_Msk & ((value) << LCDC_HEOCFG27_XPHI5COEFF2_Pos)))
+#define LCDC_HEOCFG27_XPHI5COEFF3_Pos 24
+#define LCDC_HEOCFG27_XPHI5COEFF3_Msk (0xffu << LCDC_HEOCFG27_XPHI5COEFF3_Pos) /**< \brief (LCDC_HEOCFG27) Horizontal Coefficient for phase 5 tap 3 */
+#define LCDC_HEOCFG27_XPHI5COEFF3(value) ((LCDC_HEOCFG27_XPHI5COEFF3_Msk & ((value) << LCDC_HEOCFG27_XPHI5COEFF3_Pos)))
+/* -------- LCDC_HEOCFG28 : (LCDC Offset: 0x000003FC) High End Overlay Configuration Register 28 -------- */
+#define LCDC_HEOCFG28_XPHI5COEFF4_Pos 0
+#define LCDC_HEOCFG28_XPHI5COEFF4_Msk (0xffu << LCDC_HEOCFG28_XPHI5COEFF4_Pos) /**< \brief (LCDC_HEOCFG28) Horizontal Coefficient for phase 5 tap 4 */
+#define LCDC_HEOCFG28_XPHI5COEFF4(value) ((LCDC_HEOCFG28_XPHI5COEFF4_Msk & ((value) << LCDC_HEOCFG28_XPHI5COEFF4_Pos)))
+/* -------- LCDC_HEOCFG29 : (LCDC Offset: 0x00000400) High End Overlay Configuration Register 29 -------- */
+#define LCDC_HEOCFG29_XPHI6COEFF0_Pos 0
+#define LCDC_HEOCFG29_XPHI6COEFF0_Msk (0xffu << LCDC_HEOCFG29_XPHI6COEFF0_Pos) /**< \brief (LCDC_HEOCFG29) Horizontal Coefficient for phase 6 tap 0 */
+#define LCDC_HEOCFG29_XPHI6COEFF0(value) ((LCDC_HEOCFG29_XPHI6COEFF0_Msk & ((value) << LCDC_HEOCFG29_XPHI6COEFF0_Pos)))
+#define LCDC_HEOCFG29_XPHI6COEFF1_Pos 8
+#define LCDC_HEOCFG29_XPHI6COEFF1_Msk (0xffu << LCDC_HEOCFG29_XPHI6COEFF1_Pos) /**< \brief (LCDC_HEOCFG29) Horizontal Coefficient for phase 6 tap 1 */
+#define LCDC_HEOCFG29_XPHI6COEFF1(value) ((LCDC_HEOCFG29_XPHI6COEFF1_Msk & ((value) << LCDC_HEOCFG29_XPHI6COEFF1_Pos)))
+#define LCDC_HEOCFG29_XPHI6COEFF2_Pos 16
+#define LCDC_HEOCFG29_XPHI6COEFF2_Msk (0xffu << LCDC_HEOCFG29_XPHI6COEFF2_Pos) /**< \brief (LCDC_HEOCFG29) Horizontal Coefficient for phase 6 tap 2 */
+#define LCDC_HEOCFG29_XPHI6COEFF2(value) ((LCDC_HEOCFG29_XPHI6COEFF2_Msk & ((value) << LCDC_HEOCFG29_XPHI6COEFF2_Pos)))
+#define LCDC_HEOCFG29_XPHI6COEFF3_Pos 24
+#define LCDC_HEOCFG29_XPHI6COEFF3_Msk (0xffu << LCDC_HEOCFG29_XPHI6COEFF3_Pos) /**< \brief (LCDC_HEOCFG29) Horizontal Coefficient for phase 6 tap 3 */
+#define LCDC_HEOCFG29_XPHI6COEFF3(value) ((LCDC_HEOCFG29_XPHI6COEFF3_Msk & ((value) << LCDC_HEOCFG29_XPHI6COEFF3_Pos)))
+/* -------- LCDC_HEOCFG30 : (LCDC Offset: 0x00000404) High End Overlay Configuration Register 30 -------- */
+#define LCDC_HEOCFG30_XPHI6COEFF4_Pos 0
+#define LCDC_HEOCFG30_XPHI6COEFF4_Msk (0xffu << LCDC_HEOCFG30_XPHI6COEFF4_Pos) /**< \brief (LCDC_HEOCFG30) Horizontal Coefficient for phase 6 tap 4 */
+#define LCDC_HEOCFG30_XPHI6COEFF4(value) ((LCDC_HEOCFG30_XPHI6COEFF4_Msk & ((value) << LCDC_HEOCFG30_XPHI6COEFF4_Pos)))
+/* -------- LCDC_HEOCFG31 : (LCDC Offset: 0x00000408) High End Overlay Configuration Register 31 -------- */
+#define LCDC_HEOCFG31_XPHI7COEFF0_Pos 0
+#define LCDC_HEOCFG31_XPHI7COEFF0_Msk (0xffu << LCDC_HEOCFG31_XPHI7COEFF0_Pos) /**< \brief (LCDC_HEOCFG31) Horizontal Coefficient for phase 7 tap 0 */
+#define LCDC_HEOCFG31_XPHI7COEFF0(value) ((LCDC_HEOCFG31_XPHI7COEFF0_Msk & ((value) << LCDC_HEOCFG31_XPHI7COEFF0_Pos)))
+#define LCDC_HEOCFG31_XPHI7COEFF1_Pos 8
+#define LCDC_HEOCFG31_XPHI7COEFF1_Msk (0xffu << LCDC_HEOCFG31_XPHI7COEFF1_Pos) /**< \brief (LCDC_HEOCFG31) Horizontal Coefficient for phase 7 tap 1 */
+#define LCDC_HEOCFG31_XPHI7COEFF1(value) ((LCDC_HEOCFG31_XPHI7COEFF1_Msk & ((value) << LCDC_HEOCFG31_XPHI7COEFF1_Pos)))
+#define LCDC_HEOCFG31_XPHI7COEFF2_Pos 16
+#define LCDC_HEOCFG31_XPHI7COEFF2_Msk (0xffu << LCDC_HEOCFG31_XPHI7COEFF2_Pos) /**< \brief (LCDC_HEOCFG31) Horizontal Coefficient for phase 7 tap 2 */
+#define LCDC_HEOCFG31_XPHI7COEFF2(value) ((LCDC_HEOCFG31_XPHI7COEFF2_Msk & ((value) << LCDC_HEOCFG31_XPHI7COEFF2_Pos)))
+#define LCDC_HEOCFG31_XPHI7COEFF3_Pos 24
+#define LCDC_HEOCFG31_XPHI7COEFF3_Msk (0xffu << LCDC_HEOCFG31_XPHI7COEFF3_Pos) /**< \brief (LCDC_HEOCFG31) Horizontal Coefficient for phase 7 tap 3 */
+#define LCDC_HEOCFG31_XPHI7COEFF3(value) ((LCDC_HEOCFG31_XPHI7COEFF3_Msk & ((value) << LCDC_HEOCFG31_XPHI7COEFF3_Pos)))
+/* -------- LCDC_HEOCFG32 : (LCDC Offset: 0x0000040C) High End Overlay Configuration Register 32 -------- */
+#define LCDC_HEOCFG32_XPHI7COEFF4_Pos 0
+#define LCDC_HEOCFG32_XPHI7COEFF4_Msk (0xffu << LCDC_HEOCFG32_XPHI7COEFF4_Pos) /**< \brief (LCDC_HEOCFG32) Horizontal Coefficient for phase 7 tap 4 */
+#define LCDC_HEOCFG32_XPHI7COEFF4(value) ((LCDC_HEOCFG32_XPHI7COEFF4_Msk & ((value) << LCDC_HEOCFG32_XPHI7COEFF4_Pos)))
+/* -------- LCDC_HEOCFG33 : (LCDC Offset: 0x00000410) High End Overlay Configuration Register 33 -------- */
+#define LCDC_HEOCFG33_YPHI0COEFF0_Pos 0
+#define LCDC_HEOCFG33_YPHI0COEFF0_Msk (0xffu << LCDC_HEOCFG33_YPHI0COEFF0_Pos) /**< \brief (LCDC_HEOCFG33) Vertical Coefficient for phase 0 tap 0 */
+#define LCDC_HEOCFG33_YPHI0COEFF0(value) ((LCDC_HEOCFG33_YPHI0COEFF0_Msk & ((value) << LCDC_HEOCFG33_YPHI0COEFF0_Pos)))
+#define LCDC_HEOCFG33_YPHI0COEFF1_Pos 8
+#define LCDC_HEOCFG33_YPHI0COEFF1_Msk (0xffu << LCDC_HEOCFG33_YPHI0COEFF1_Pos) /**< \brief (LCDC_HEOCFG33) Vertical Coefficient for phase 0 tap 1 */
+#define LCDC_HEOCFG33_YPHI0COEFF1(value) ((LCDC_HEOCFG33_YPHI0COEFF1_Msk & ((value) << LCDC_HEOCFG33_YPHI0COEFF1_Pos)))
+#define LCDC_HEOCFG33_YPHI0COEFF2_Pos 16
+#define LCDC_HEOCFG33_YPHI0COEFF2_Msk (0xffu << LCDC_HEOCFG33_YPHI0COEFF2_Pos) /**< \brief (LCDC_HEOCFG33) Vertical Coefficient for phase 0 tap 2 */
+#define LCDC_HEOCFG33_YPHI0COEFF2(value) ((LCDC_HEOCFG33_YPHI0COEFF2_Msk & ((value) << LCDC_HEOCFG33_YPHI0COEFF2_Pos)))
+/* -------- LCDC_HEOCFG34 : (LCDC Offset: 0x00000414) High End Overlay Configuration Register 34 -------- */
+#define LCDC_HEOCFG34_YPHI1COEFF0_Pos 0
+#define LCDC_HEOCFG34_YPHI1COEFF0_Msk (0xffu << LCDC_HEOCFG34_YPHI1COEFF0_Pos) /**< \brief (LCDC_HEOCFG34) Vertical Coefficient for phase 1 tap 0 */
+#define LCDC_HEOCFG34_YPHI1COEFF0(value) ((LCDC_HEOCFG34_YPHI1COEFF0_Msk & ((value) << LCDC_HEOCFG34_YPHI1COEFF0_Pos)))
+#define LCDC_HEOCFG34_YPHI1COEFF1_Pos 8
+#define LCDC_HEOCFG34_YPHI1COEFF1_Msk (0xffu << LCDC_HEOCFG34_YPHI1COEFF1_Pos) /**< \brief (LCDC_HEOCFG34) Vertical Coefficient for phase 1 tap 1 */
+#define LCDC_HEOCFG34_YPHI1COEFF1(value) ((LCDC_HEOCFG34_YPHI1COEFF1_Msk & ((value) << LCDC_HEOCFG34_YPHI1COEFF1_Pos)))
+#define LCDC_HEOCFG34_YPHI1COEFF2_Pos 16
+#define LCDC_HEOCFG34_YPHI1COEFF2_Msk (0xffu << LCDC_HEOCFG34_YPHI1COEFF2_Pos) /**< \brief (LCDC_HEOCFG34) Vertical Coefficient for phase 1 tap 2 */
+#define LCDC_HEOCFG34_YPHI1COEFF2(value) ((LCDC_HEOCFG34_YPHI1COEFF2_Msk & ((value) << LCDC_HEOCFG34_YPHI1COEFF2_Pos)))
+/* -------- LCDC_HEOCFG35 : (LCDC Offset: 0x00000418) High End Overlay Configuration Register 35 -------- */
+#define LCDC_HEOCFG35_YPHI2COEFF0_Pos 0
+#define LCDC_HEOCFG35_YPHI2COEFF0_Msk (0xffu << LCDC_HEOCFG35_YPHI2COEFF0_Pos) /**< \brief (LCDC_HEOCFG35) Vertical Coefficient for phase 2 tap 0 */
+#define LCDC_HEOCFG35_YPHI2COEFF0(value) ((LCDC_HEOCFG35_YPHI2COEFF0_Msk & ((value) << LCDC_HEOCFG35_YPHI2COEFF0_Pos)))
+#define LCDC_HEOCFG35_YPHI2COEFF1_Pos 8
+#define LCDC_HEOCFG35_YPHI2COEFF1_Msk (0xffu << LCDC_HEOCFG35_YPHI2COEFF1_Pos) /**< \brief (LCDC_HEOCFG35) Vertical Coefficient for phase 2 tap 1 */
+#define LCDC_HEOCFG35_YPHI2COEFF1(value) ((LCDC_HEOCFG35_YPHI2COEFF1_Msk & ((value) << LCDC_HEOCFG35_YPHI2COEFF1_Pos)))
+#define LCDC_HEOCFG35_YPHI2COEFF2_Pos 16
+#define LCDC_HEOCFG35_YPHI2COEFF2_Msk (0xffu << LCDC_HEOCFG35_YPHI2COEFF2_Pos) /**< \brief (LCDC_HEOCFG35) Vertical Coefficient for phase 2 tap 2 */
+#define LCDC_HEOCFG35_YPHI2COEFF2(value) ((LCDC_HEOCFG35_YPHI2COEFF2_Msk & ((value) << LCDC_HEOCFG35_YPHI2COEFF2_Pos)))
+/* -------- LCDC_HEOCFG36 : (LCDC Offset: 0x0000041C) High End Overlay Configuration Register 36 -------- */
+#define LCDC_HEOCFG36_YPHI3COEFF0_Pos 0
+#define LCDC_HEOCFG36_YPHI3COEFF0_Msk (0xffu << LCDC_HEOCFG36_YPHI3COEFF0_Pos) /**< \brief (LCDC_HEOCFG36) Vertical Coefficient for phase 3 tap 0 */
+#define LCDC_HEOCFG36_YPHI3COEFF0(value) ((LCDC_HEOCFG36_YPHI3COEFF0_Msk & ((value) << LCDC_HEOCFG36_YPHI3COEFF0_Pos)))
+#define LCDC_HEOCFG36_YPHI3COEFF1_Pos 8
+#define LCDC_HEOCFG36_YPHI3COEFF1_Msk (0xffu << LCDC_HEOCFG36_YPHI3COEFF1_Pos) /**< \brief (LCDC_HEOCFG36) Vertical Coefficient for phase 3 tap 1 */
+#define LCDC_HEOCFG36_YPHI3COEFF1(value) ((LCDC_HEOCFG36_YPHI3COEFF1_Msk & ((value) << LCDC_HEOCFG36_YPHI3COEFF1_Pos)))
+#define LCDC_HEOCFG36_YPHI3COEFF2_Pos 16
+#define LCDC_HEOCFG36_YPHI3COEFF2_Msk (0xffu << LCDC_HEOCFG36_YPHI3COEFF2_Pos) /**< \brief (LCDC_HEOCFG36) Vertical Coefficient for phase 3 tap 2 */
+#define LCDC_HEOCFG36_YPHI3COEFF2(value) ((LCDC_HEOCFG36_YPHI3COEFF2_Msk & ((value) << LCDC_HEOCFG36_YPHI3COEFF2_Pos)))
+/* -------- LCDC_HEOCFG37 : (LCDC Offset: 0x00000420) High End Overlay Configuration Register 37 -------- */
+#define LCDC_HEOCFG37_YPHI4COEFF0_Pos 0
+#define LCDC_HEOCFG37_YPHI4COEFF0_Msk (0xffu << LCDC_HEOCFG37_YPHI4COEFF0_Pos) /**< \brief (LCDC_HEOCFG37) Vertical Coefficient for phase 4 tap 0 */
+#define LCDC_HEOCFG37_YPHI4COEFF0(value) ((LCDC_HEOCFG37_YPHI4COEFF0_Msk & ((value) << LCDC_HEOCFG37_YPHI4COEFF0_Pos)))
+#define LCDC_HEOCFG37_YPHI4COEFF1_Pos 8
+#define LCDC_HEOCFG37_YPHI4COEFF1_Msk (0xffu << LCDC_HEOCFG37_YPHI4COEFF1_Pos) /**< \brief (LCDC_HEOCFG37) Vertical Coefficient for phase 4 tap 1 */
+#define LCDC_HEOCFG37_YPHI4COEFF1(value) ((LCDC_HEOCFG37_YPHI4COEFF1_Msk & ((value) << LCDC_HEOCFG37_YPHI4COEFF1_Pos)))
+#define LCDC_HEOCFG37_YPHI4COEFF2_Pos 16
+#define LCDC_HEOCFG37_YPHI4COEFF2_Msk (0xffu << LCDC_HEOCFG37_YPHI4COEFF2_Pos) /**< \brief (LCDC_HEOCFG37) Vertical Coefficient for phase 4 tap 2 */
+#define LCDC_HEOCFG37_YPHI4COEFF2(value) ((LCDC_HEOCFG37_YPHI4COEFF2_Msk & ((value) << LCDC_HEOCFG37_YPHI4COEFF2_Pos)))
+/* -------- LCDC_HEOCFG38 : (LCDC Offset: 0x00000424) High End Overlay Configuration Register 38 -------- */
+#define LCDC_HEOCFG38_YPHI5COEFF0_Pos 0
+#define LCDC_HEOCFG38_YPHI5COEFF0_Msk (0xffu << LCDC_HEOCFG38_YPHI5COEFF0_Pos) /**< \brief (LCDC_HEOCFG38) Vertical Coefficient for phase 5 tap 0 */
+#define LCDC_HEOCFG38_YPHI5COEFF0(value) ((LCDC_HEOCFG38_YPHI5COEFF0_Msk & ((value) << LCDC_HEOCFG38_YPHI5COEFF0_Pos)))
+#define LCDC_HEOCFG38_YPHI5COEFF1_Pos 8
+#define LCDC_HEOCFG38_YPHI5COEFF1_Msk (0xffu << LCDC_HEOCFG38_YPHI5COEFF1_Pos) /**< \brief (LCDC_HEOCFG38) Vertical Coefficient for phase 5 tap 1 */
+#define LCDC_HEOCFG38_YPHI5COEFF1(value) ((LCDC_HEOCFG38_YPHI5COEFF1_Msk & ((value) << LCDC_HEOCFG38_YPHI5COEFF1_Pos)))
+#define LCDC_HEOCFG38_YPHI5COEFF2_Pos 16
+#define LCDC_HEOCFG38_YPHI5COEFF2_Msk (0xffu << LCDC_HEOCFG38_YPHI5COEFF2_Pos) /**< \brief (LCDC_HEOCFG38) Vertical Coefficient for phase 5 tap 2 */
+#define LCDC_HEOCFG38_YPHI5COEFF2(value) ((LCDC_HEOCFG38_YPHI5COEFF2_Msk & ((value) << LCDC_HEOCFG38_YPHI5COEFF2_Pos)))
+/* -------- LCDC_HEOCFG39 : (LCDC Offset: 0x00000428) High End Overlay Configuration Register 39 -------- */
+#define LCDC_HEOCFG39_YPHI6COEFF0_Pos 0
+#define LCDC_HEOCFG39_YPHI6COEFF0_Msk (0xffu << LCDC_HEOCFG39_YPHI6COEFF0_Pos) /**< \brief (LCDC_HEOCFG39) Vertical Coefficient for phase 6 tap 0 */
+#define LCDC_HEOCFG39_YPHI6COEFF0(value) ((LCDC_HEOCFG39_YPHI6COEFF0_Msk & ((value) << LCDC_HEOCFG39_YPHI6COEFF0_Pos)))
+#define LCDC_HEOCFG39_YPHI6COEFF1_Pos 8
+#define LCDC_HEOCFG39_YPHI6COEFF1_Msk (0xffu << LCDC_HEOCFG39_YPHI6COEFF1_Pos) /**< \brief (LCDC_HEOCFG39) Vertical Coefficient for phase 6 tap 1 */
+#define LCDC_HEOCFG39_YPHI6COEFF1(value) ((LCDC_HEOCFG39_YPHI6COEFF1_Msk & ((value) << LCDC_HEOCFG39_YPHI6COEFF1_Pos)))
+#define LCDC_HEOCFG39_YPHI6COEFF2_Pos 16
+#define LCDC_HEOCFG39_YPHI6COEFF2_Msk (0xffu << LCDC_HEOCFG39_YPHI6COEFF2_Pos) /**< \brief (LCDC_HEOCFG39) Vertical Coefficient for phase 6 tap 2 */
+#define LCDC_HEOCFG39_YPHI6COEFF2(value) ((LCDC_HEOCFG39_YPHI6COEFF2_Msk & ((value) << LCDC_HEOCFG39_YPHI6COEFF2_Pos)))
+/* -------- LCDC_HEOCFG40 : (LCDC Offset: 0x0000042C) High End Overlay Configuration Register 40 -------- */
+#define LCDC_HEOCFG40_YPHI7COEFF0_Pos 0
+#define LCDC_HEOCFG40_YPHI7COEFF0_Msk (0xffu << LCDC_HEOCFG40_YPHI7COEFF0_Pos) /**< \brief (LCDC_HEOCFG40) Vertical Coefficient for phase 7 tap 0 */
+#define LCDC_HEOCFG40_YPHI7COEFF0(value) ((LCDC_HEOCFG40_YPHI7COEFF0_Msk & ((value) << LCDC_HEOCFG40_YPHI7COEFF0_Pos)))
+#define LCDC_HEOCFG40_YPHI7COEFF1_Pos 8
+#define LCDC_HEOCFG40_YPHI7COEFF1_Msk (0xffu << LCDC_HEOCFG40_YPHI7COEFF1_Pos) /**< \brief (LCDC_HEOCFG40) Vertical Coefficient for phase 7 tap 1 */
+#define LCDC_HEOCFG40_YPHI7COEFF1(value) ((LCDC_HEOCFG40_YPHI7COEFF1_Msk & ((value) << LCDC_HEOCFG40_YPHI7COEFF1_Pos)))
+#define LCDC_HEOCFG40_YPHI7COEFF2_Pos 16
+#define LCDC_HEOCFG40_YPHI7COEFF2_Msk (0xffu << LCDC_HEOCFG40_YPHI7COEFF2_Pos) /**< \brief (LCDC_HEOCFG40) Vertical Coefficient for phase 7 tap 2 */
+#define LCDC_HEOCFG40_YPHI7COEFF2(value) ((LCDC_HEOCFG40_YPHI7COEFF2_Msk & ((value) << LCDC_HEOCFG40_YPHI7COEFF2_Pos)))
+/* -------- LCDC_HEOCFG41 : (LCDC Offset: 0x00000430) High End Overlay Configuration Register 41 -------- */
+#define LCDC_HEOCFG41_XPHIDEF_Pos 0
+#define LCDC_HEOCFG41_XPHIDEF_Msk (0x7u << LCDC_HEOCFG41_XPHIDEF_Pos) /**< \brief (LCDC_HEOCFG41) Horizontal Filter Phase Offset */
+#define LCDC_HEOCFG41_XPHIDEF(value) ((LCDC_HEOCFG41_XPHIDEF_Msk & ((value) << LCDC_HEOCFG41_XPHIDEF_Pos)))
+#define LCDC_HEOCFG41_YPHIDEF_Pos 16
+#define LCDC_HEOCFG41_YPHIDEF_Msk (0x7u << LCDC_HEOCFG41_YPHIDEF_Pos) /**< \brief (LCDC_HEOCFG41) Vertical Filter Phase Offset */
+#define LCDC_HEOCFG41_YPHIDEF(value) ((LCDC_HEOCFG41_YPHIDEF_Msk & ((value) << LCDC_HEOCFG41_YPHIDEF_Pos)))
+/* -------- LCDC_PPCHER : (LCDC Offset: 0x00000540) Post Processing Channel Enable Register -------- */
+#define LCDC_PPCHER_CHEN (0x1u << 0) /**< \brief (LCDC_PPCHER) Channel Enable Register */
+#define LCDC_PPCHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_PPCHER) Update Overlay Attributes Enable Register */
+#define LCDC_PPCHER_A2QEN (0x1u << 2) /**< \brief (LCDC_PPCHER) Add To Queue Enable Register */
+/* -------- LCDC_PPCHDR : (LCDC Offset: 0x00000544) Post Processing Channel Disable Register -------- */
+#define LCDC_PPCHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_PPCHDR) Channel Disable Register */
+#define LCDC_PPCHDR_CHRST (0x1u << 8) /**< \brief (LCDC_PPCHDR) Channel Reset Register */
+/* -------- LCDC_PPCHSR : (LCDC Offset: 0x00000548) Post Processing Channel Status Register -------- */
+#define LCDC_PPCHSR_CHSR (0x1u << 0) /**< \brief (LCDC_PPCHSR) Channel Status Register */
+#define LCDC_PPCHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_PPCHSR) Update Overlay Attributes In Progress Status Register */
+#define LCDC_PPCHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_PPCHSR) Add To Queue Status Register */
+/* -------- LCDC_PPIER : (LCDC Offset: 0x0000054C) Post Processing Interrupt Enable Register -------- */
+#define LCDC_PPIER_DMA (0x1u << 2) /**< \brief (LCDC_PPIER) End of DMA Transfer Interrupt Enable Register */
+#define LCDC_PPIER_DSCR (0x1u << 3) /**< \brief (LCDC_PPIER) Descriptor Loaded Interrupt Enable Register */
+#define LCDC_PPIER_ADD (0x1u << 4) /**< \brief (LCDC_PPIER) Head Descriptor Loaded Interrupt Enable Register */
+#define LCDC_PPIER_DONE (0x1u << 5) /**< \brief (LCDC_PPIER) End of List Interrupt Enable Register */
+/* -------- LCDC_PPIDR : (LCDC Offset: 0x00000550) Post Processing Interrupt Disable Register -------- */
+#define LCDC_PPIDR_DMA (0x1u << 2) /**< \brief (LCDC_PPIDR) End of DMA Transfer Interrupt Disable Register */
+#define LCDC_PPIDR_DSCR (0x1u << 3) /**< \brief (LCDC_PPIDR) Descriptor Loaded Interrupt Disable Register */
+#define LCDC_PPIDR_ADD (0x1u << 4) /**< \brief (LCDC_PPIDR) Head Descriptor Loaded Interrupt Disable Register */
+#define LCDC_PPIDR_DONE (0x1u << 5) /**< \brief (LCDC_PPIDR) End of List Interrupt Disable Register */
+/* -------- LCDC_PPIMR : (LCDC Offset: 0x00000554) Post Processing Interrupt Mask Register -------- */
+#define LCDC_PPIMR_DMA (0x1u << 2) /**< \brief (LCDC_PPIMR) End of DMA Transfer Interrupt Mask Register */
+#define LCDC_PPIMR_DSCR (0x1u << 3) /**< \brief (LCDC_PPIMR) Descriptor Loaded Interrupt Mask Register */
+#define LCDC_PPIMR_ADD (0x1u << 4) /**< \brief (LCDC_PPIMR) Head Descriptor Loaded Interrupt Mask Register */
+#define LCDC_PPIMR_DONE (0x1u << 5) /**< \brief (LCDC_PPIMR) End of List Interrupt Mask Register */
+/* -------- LCDC_PPISR : (LCDC Offset: 0x00000558) Post Processing Interrupt Status Register -------- */
+#define LCDC_PPISR_DMA (0x1u << 2) /**< \brief (LCDC_PPISR) End of DMA Transfer */
+#define LCDC_PPISR_DSCR (0x1u << 3) /**< \brief (LCDC_PPISR) DMA Descriptor Loaded */
+#define LCDC_PPISR_ADD (0x1u << 4) /**< \brief (LCDC_PPISR) Head Descriptor Loaded */
+#define LCDC_PPISR_DONE (0x1u << 5) /**< \brief (LCDC_PPISR) End of List Detected */
+/* -------- LCDC_PPHEAD : (LCDC Offset: 0x0000055C) Post Processing Head Register -------- */
+#define LCDC_PPHEAD_HEAD_Pos 2
+#define LCDC_PPHEAD_HEAD_Msk (0x3fffffffu << LCDC_PPHEAD_HEAD_Pos) /**< \brief (LCDC_PPHEAD) DMA Head Pointer */
+#define LCDC_PPHEAD_HEAD(value) ((LCDC_PPHEAD_HEAD_Msk & ((value) << LCDC_PPHEAD_HEAD_Pos)))
+/* -------- LCDC_PPADDR : (LCDC Offset: 0x00000560) Post Processing Address Register -------- */
+#define LCDC_PPADDR_ADDR_Pos 0
+#define LCDC_PPADDR_ADDR_Msk (0xffffffffu << LCDC_PPADDR_ADDR_Pos) /**< \brief (LCDC_PPADDR) DMA Transfer start address */
+#define LCDC_PPADDR_ADDR(value) ((LCDC_PPADDR_ADDR_Msk & ((value) << LCDC_PPADDR_ADDR_Pos)))
+/* -------- LCDC_PPCTRL : (LCDC Offset: 0x00000564) Post Processing Control Register -------- */
+#define LCDC_PPCTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_PPCTRL) Transfer Descriptor Fetch Enable */
+#define LCDC_PPCTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_PPCTRL) End of DMA Transfer Interrupt Enable */
+#define LCDC_PPCTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_PPCTRL) Descriptor Loaded Interrupt Enable */
+#define LCDC_PPCTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_PPCTRL) Add Head Descriptor to Queue Interrupt Enable */
+#define LCDC_PPCTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_PPCTRL) End of List Interrupt Enable */
+/* -------- LCDC_PPNEXT : (LCDC Offset: 0x00000568) Post Processing Next Register -------- */
+#define LCDC_PPNEXT_NEXT_Pos 0
+#define LCDC_PPNEXT_NEXT_Msk (0xffffffffu << LCDC_PPNEXT_NEXT_Pos) /**< \brief (LCDC_PPNEXT) DMA Descriptor Next Address */
+#define LCDC_PPNEXT_NEXT(value) ((LCDC_PPNEXT_NEXT_Msk & ((value) << LCDC_PPNEXT_NEXT_Pos)))
+/* -------- LCDC_PPCFG0 : (LCDC Offset: 0x0000056C) Post Processing Configuration Register 0 -------- */
+#define LCDC_PPCFG0_SIF (0x1u << 0) /**< \brief (LCDC_PPCFG0) Source Interface */
+#define LCDC_PPCFG0_BLEN_Pos 4
+#define LCDC_PPCFG0_BLEN_Msk (0x3u << LCDC_PPCFG0_BLEN_Pos) /**< \brief (LCDC_PPCFG0) AHB Burst Length */
+#define LCDC_PPCFG0_BLEN(value) ((LCDC_PPCFG0_BLEN_Msk & ((value) << LCDC_PPCFG0_BLEN_Pos)))
+#define   LCDC_PPCFG0_BLEN_AHB_BLEN_SINGLE (0x0u << 4) /**< \brief (LCDC_PPCFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define   LCDC_PPCFG0_BLEN_AHB_BLEN_INCR4 (0x1u << 4) /**< \brief (LCDC_PPCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define   LCDC_PPCFG0_BLEN_AHB_BLEN_INCR8 (0x2u << 4) /**< \brief (LCDC_PPCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define   LCDC_PPCFG0_BLEN_AHB_BLEN_INCR16 (0x3u << 4) /**< \brief (LCDC_PPCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */
+#define LCDC_PPCFG0_DLBO (0x1u << 8) /**< \brief (LCDC_PPCFG0) Defined Length Burst Only For Channel Bus Transaction. */
+/* -------- LCDC_PPCFG1 : (LCDC Offset: 0x00000570) Post Processing Configuration Register 1 -------- */
+#define LCDC_PPCFG1_PPMODE_Pos 0
+#define LCDC_PPCFG1_PPMODE_Msk (0x7u << LCDC_PPCFG1_PPMODE_Pos) /**< \brief (LCDC_PPCFG1) Post Processing Output Format selection */
+#define LCDC_PPCFG1_PPMODE(value) ((LCDC_PPCFG1_PPMODE_Msk & ((value) << LCDC_PPCFG1_PPMODE_Pos)))
+#define   LCDC_PPCFG1_PPMODE_PPMODE_RGB_16BPP (0x0u << 0) /**< \brief (LCDC_PPCFG1) RGB 16 bpp */
+#define   LCDC_PPCFG1_PPMODE_PPMODE_RGB_24BPP_PACKED (0x1u << 0) /**< \brief (LCDC_PPCFG1) RGB 24 bpp PACKED */
+#define   LCDC_PPCFG1_PPMODE_PPMODE_RGB_24BPP_UNPACKED (0x2u << 0) /**< \brief (LCDC_PPCFG1) RGB 24 bpp UNPACKED */
+#define   LCDC_PPCFG1_PPMODE_PPMODE_YCBCR_422_MODE0 (0x3u << 0) /**< \brief (LCDC_PPCFG1) YCbCr 422 16 bpp (Mode 0) */
+#define   LCDC_PPCFG1_PPMODE_PPMODE_YCBCR_422_MODE1 (0x4u << 0) /**< \brief (LCDC_PPCFG1) YCbCr 422 16 bpp (Mode 1) */
+#define   LCDC_PPCFG1_PPMODE_PPMODE_YCBCR_422_MODE2 (0x5u << 0) /**< \brief (LCDC_PPCFG1) YCbCr 422 16 bpp (Mode 2) */
+#define   LCDC_PPCFG1_PPMODE_PPMODE_YCBCR_422_MODE3 (0x6u << 0) /**< \brief (LCDC_PPCFG1) YCbCr 422 16 bpp (Mode 3) */
+#define LCDC_PPCFG1_ITUBT601 (0x1u << 4) /**< \brief (LCDC_PPCFG1) Color Space Conversion Luminance */
+/* -------- LCDC_PPCFG2 : (LCDC Offset: 0x00000574) Post Processing Configuration Register 2 -------- */
+#define LCDC_PPCFG2_XSTRIDE_Pos 0
+#define LCDC_PPCFG2_XSTRIDE_Msk (0xffffffffu << LCDC_PPCFG2_XSTRIDE_Pos) /**< \brief (LCDC_PPCFG2) Horizontal Stride */
+#define LCDC_PPCFG2_XSTRIDE(value) ((LCDC_PPCFG2_XSTRIDE_Msk & ((value) << LCDC_PPCFG2_XSTRIDE_Pos)))
+/* -------- LCDC_PPCFG3 : (LCDC Offset: 0x00000578) Post Processing Configuration Register 3 -------- */
+#define LCDC_PPCFG3_CSCYR_Pos 0
+#define LCDC_PPCFG3_CSCYR_Msk (0x3ffu << LCDC_PPCFG3_CSCYR_Pos) /**< \brief (LCDC_PPCFG3) Color Space Conversion R coefficient for Luminance component, signed format, step set to 1/1024 */
+#define LCDC_PPCFG3_CSCYR(value) ((LCDC_PPCFG3_CSCYR_Msk & ((value) << LCDC_PPCFG3_CSCYR_Pos)))
+#define LCDC_PPCFG3_CSCYG_Pos 10
+#define LCDC_PPCFG3_CSCYG_Msk (0x3ffu << LCDC_PPCFG3_CSCYG_Pos) /**< \brief (LCDC_PPCFG3) Color Space Conversion G coefficient for Luminance component, signed format, step set to 1/512 */
+#define LCDC_PPCFG3_CSCYG(value) ((LCDC_PPCFG3_CSCYG_Msk & ((value) << LCDC_PPCFG3_CSCYG_Pos)))
+#define LCDC_PPCFG3_CSCYB_Pos 20
+#define LCDC_PPCFG3_CSCYB_Msk (0x3ffu << LCDC_PPCFG3_CSCYB_Pos) /**< \brief (LCDC_PPCFG3) Color Space Conversion B coefficient for Luminance component, signed format, step set to 1/1024 */
+#define LCDC_PPCFG3_CSCYB(value) ((LCDC_PPCFG3_CSCYB_Msk & ((value) << LCDC_PPCFG3_CSCYB_Pos)))
+#define LCDC_PPCFG3_CSCYOFF (0x1u << 30) /**< \brief (LCDC_PPCFG3) Color Space Conversion Luminance Offset */
+/* -------- LCDC_PPCFG4 : (LCDC Offset: 0x0000057C) Post Processing Configuration Register 4 -------- */
+#define LCDC_PPCFG4_CSCUR_Pos 0
+#define LCDC_PPCFG4_CSCUR_Msk (0x3ffu << LCDC_PPCFG4_CSCUR_Pos) /**< \brief (LCDC_PPCFG4) Color Space Conversion R coefficient for Chrominance B component, signed format. (step 1/1024) */
+#define LCDC_PPCFG4_CSCUR(value) ((LCDC_PPCFG4_CSCUR_Msk & ((value) << LCDC_PPCFG4_CSCUR_Pos)))
+#define LCDC_PPCFG4_CSCUG_Pos 10
+#define LCDC_PPCFG4_CSCUG_Msk (0x3ffu << LCDC_PPCFG4_CSCUG_Pos) /**< \brief (LCDC_PPCFG4) Color Space Conversion G coefficient for Chrominance B component, signed format. (step 1/512) */
+#define LCDC_PPCFG4_CSCUG(value) ((LCDC_PPCFG4_CSCUG_Msk & ((value) << LCDC_PPCFG4_CSCUG_Pos)))
+#define LCDC_PPCFG4_CSCUB_Pos 20
+#define LCDC_PPCFG4_CSCUB_Msk (0x3ffu << LCDC_PPCFG4_CSCUB_Pos) /**< \brief (LCDC_PPCFG4) Color Space Conversion B coefficient for Chrominance B component, signed format. (step 1/512) */
+#define LCDC_PPCFG4_CSCUB(value) ((LCDC_PPCFG4_CSCUB_Msk & ((value) << LCDC_PPCFG4_CSCUB_Pos)))
+#define LCDC_PPCFG4_CSCUOFF (0x1u << 30) /**< \brief (LCDC_PPCFG4) Color Space Conversion Chrominance B Offset */
+/* -------- LCDC_PPCFG5 : (LCDC Offset: 0x00000580) Post Processing Configuration Register 5 -------- */
+#define LCDC_PPCFG5_CSCVR_Pos 0
+#define LCDC_PPCFG5_CSCVR_Msk (0x3ffu << LCDC_PPCFG5_CSCVR_Pos) /**< \brief (LCDC_PPCFG5) Color Space Conversion R coefficient for Chrominance R component, signed format. (step 1/1024) */
+#define LCDC_PPCFG5_CSCVR(value) ((LCDC_PPCFG5_CSCVR_Msk & ((value) << LCDC_PPCFG5_CSCVR_Pos)))
+#define LCDC_PPCFG5_CSCVG_Pos 10
+#define LCDC_PPCFG5_CSCVG_Msk (0x3ffu << LCDC_PPCFG5_CSCVG_Pos) /**< \brief (LCDC_PPCFG5) Color Space Conversion G coefficient for Chrominance R component, signed format. (step 1/512) */
+#define LCDC_PPCFG5_CSCVG(value) ((LCDC_PPCFG5_CSCVG_Msk & ((value) << LCDC_PPCFG5_CSCVG_Pos)))
+#define LCDC_PPCFG5_CSCVB_Pos 20
+#define LCDC_PPCFG5_CSCVB_Msk (0x3ffu << LCDC_PPCFG5_CSCVB_Pos) /**< \brief (LCDC_PPCFG5) Color Space Conversion B coefficient for Chrominance R component, signed format. (step 1/1024) */
+#define LCDC_PPCFG5_CSCVB(value) ((LCDC_PPCFG5_CSCVB_Msk & ((value) << LCDC_PPCFG5_CSCVB_Pos)))
+#define LCDC_PPCFG5_CSCVOFF (0x1u << 30) /**< \brief (LCDC_PPCFG5) Color Space Conversion Chrominance R Offset */
+/* -------- LCDC_BASECLUT[256] : (LCDC Offset: 0x00000600) Base CLUT Register -------- */
+#define LCDC_BASECLUT_BCLUT_Pos 0
+#define LCDC_BASECLUT_BCLUT_Msk (0xffu << LCDC_BASECLUT_BCLUT_Pos) /**< \brief (LCDC_BASECLUT[256]) Blue Color entry */
+#define LCDC_BASECLUT_BCLUT(value) ((LCDC_BASECLUT_BCLUT_Msk & ((value) << LCDC_BASECLUT_BCLUT_Pos)))
+#define LCDC_BASECLUT_GCLUT_Pos 8
+#define LCDC_BASECLUT_GCLUT_Msk (0xffu << LCDC_BASECLUT_GCLUT_Pos) /**< \brief (LCDC_BASECLUT[256]) Green Color entry */
+#define LCDC_BASECLUT_GCLUT(value) ((LCDC_BASECLUT_GCLUT_Msk & ((value) << LCDC_BASECLUT_GCLUT_Pos)))
+#define LCDC_BASECLUT_RCLUT_Pos 16
+#define LCDC_BASECLUT_RCLUT_Msk (0xffu << LCDC_BASECLUT_RCLUT_Pos) /**< \brief (LCDC_BASECLUT[256]) Red Color entry */
+#define LCDC_BASECLUT_RCLUT(value) ((LCDC_BASECLUT_RCLUT_Msk & ((value) << LCDC_BASECLUT_RCLUT_Pos)))
+/* -------- LCDC_OVR1CLUT[256] : (LCDC Offset: 0x00000A00) Overlay 1 CLUT Register -------- */
+#define LCDC_OVR1CLUT_BCLUT_Pos 0
+#define LCDC_OVR1CLUT_BCLUT_Msk (0xffu << LCDC_OVR1CLUT_BCLUT_Pos) /**< \brief (LCDC_OVR1CLUT[256]) Blue Color entry */
+#define LCDC_OVR1CLUT_BCLUT(value) ((LCDC_OVR1CLUT_BCLUT_Msk & ((value) << LCDC_OVR1CLUT_BCLUT_Pos)))
+#define LCDC_OVR1CLUT_GCLUT_Pos 8
+#define LCDC_OVR1CLUT_GCLUT_Msk (0xffu << LCDC_OVR1CLUT_GCLUT_Pos) /**< \brief (LCDC_OVR1CLUT[256]) Green Color entry */
+#define LCDC_OVR1CLUT_GCLUT(value) ((LCDC_OVR1CLUT_GCLUT_Msk & ((value) << LCDC_OVR1CLUT_GCLUT_Pos)))
+#define LCDC_OVR1CLUT_RCLUT_Pos 16
+#define LCDC_OVR1CLUT_RCLUT_Msk (0xffu << LCDC_OVR1CLUT_RCLUT_Pos) /**< \brief (LCDC_OVR1CLUT[256]) Red Color entry */
+#define LCDC_OVR1CLUT_RCLUT(value) ((LCDC_OVR1CLUT_RCLUT_Msk & ((value) << LCDC_OVR1CLUT_RCLUT_Pos)))
+#define LCDC_OVR1CLUT_ACLUT_Pos 24
+#define LCDC_OVR1CLUT_ACLUT_Msk (0xffu << LCDC_OVR1CLUT_ACLUT_Pos) /**< \brief (LCDC_OVR1CLUT[256]) Alpha Color entry */
+#define LCDC_OVR1CLUT_ACLUT(value) ((LCDC_OVR1CLUT_ACLUT_Msk & ((value) << LCDC_OVR1CLUT_ACLUT_Pos)))
+/* -------- LCDC_OVR2CLUT[256] : (LCDC Offset: 0x00000E00) Overlay 2 CLUT Register -------- */
+#define LCDC_OVR2CLUT_BCLUT_Pos 0
+#define LCDC_OVR2CLUT_BCLUT_Msk (0xffu << LCDC_OVR2CLUT_BCLUT_Pos) /**< \brief (LCDC_OVR2CLUT[256]) Blue Color entry */
+#define LCDC_OVR2CLUT_BCLUT(value) ((LCDC_OVR2CLUT_BCLUT_Msk & ((value) << LCDC_OVR2CLUT_BCLUT_Pos)))
+#define LCDC_OVR2CLUT_GCLUT_Pos 8
+#define LCDC_OVR2CLUT_GCLUT_Msk (0xffu << LCDC_OVR2CLUT_GCLUT_Pos) /**< \brief (LCDC_OVR2CLUT[256]) Green Color entry */
+#define LCDC_OVR2CLUT_GCLUT(value) ((LCDC_OVR2CLUT_GCLUT_Msk & ((value) << LCDC_OVR2CLUT_GCLUT_Pos)))
+#define LCDC_OVR2CLUT_RCLUT_Pos 16
+#define LCDC_OVR2CLUT_RCLUT_Msk (0xffu << LCDC_OVR2CLUT_RCLUT_Pos) /**< \brief (LCDC_OVR2CLUT[256]) Red Color entry */
+#define LCDC_OVR2CLUT_RCLUT(value) ((LCDC_OVR2CLUT_RCLUT_Msk & ((value) << LCDC_OVR2CLUT_RCLUT_Pos)))
+#define LCDC_OVR2CLUT_ACLUT_Pos 24
+#define LCDC_OVR2CLUT_ACLUT_Msk (0xffu << LCDC_OVR2CLUT_ACLUT_Pos) /**< \brief (LCDC_OVR2CLUT[256]) Alpha Color entry */
+#define LCDC_OVR2CLUT_ACLUT(value) ((LCDC_OVR2CLUT_ACLUT_Msk & ((value) << LCDC_OVR2CLUT_ACLUT_Pos)))
+/* -------- LCDC_HEOCLUT[256] : (LCDC Offset: 0x00001200) High End Overlay CLUT Register -------- */
+#define LCDC_HEOCLUT_BCLUT_Pos 0
+#define LCDC_HEOCLUT_BCLUT_Msk (0xffu << LCDC_HEOCLUT_BCLUT_Pos) /**< \brief (LCDC_HEOCLUT[256]) Blue Color entry */
+#define LCDC_HEOCLUT_BCLUT(value) ((LCDC_HEOCLUT_BCLUT_Msk & ((value) << LCDC_HEOCLUT_BCLUT_Pos)))
+#define LCDC_HEOCLUT_GCLUT_Pos 8
+#define LCDC_HEOCLUT_GCLUT_Msk (0xffu << LCDC_HEOCLUT_GCLUT_Pos) /**< \brief (LCDC_HEOCLUT[256]) Green Color entry */
+#define LCDC_HEOCLUT_GCLUT(value) ((LCDC_HEOCLUT_GCLUT_Msk & ((value) << LCDC_HEOCLUT_GCLUT_Pos)))
+#define LCDC_HEOCLUT_RCLUT_Pos 16
+#define LCDC_HEOCLUT_RCLUT_Msk (0xffu << LCDC_HEOCLUT_RCLUT_Pos) /**< \brief (LCDC_HEOCLUT[256]) Red Color entry */
+#define LCDC_HEOCLUT_RCLUT(value) ((LCDC_HEOCLUT_RCLUT_Msk & ((value) << LCDC_HEOCLUT_RCLUT_Pos)))
+#define LCDC_HEOCLUT_ACLUT_Pos 24
+#define LCDC_HEOCLUT_ACLUT_Msk (0xffu << LCDC_HEOCLUT_ACLUT_Pos) /**< \brief (LCDC_HEOCLUT[256]) Alpha Color entry */
+#define LCDC_HEOCLUT_ACLUT(value) ((LCDC_HEOCLUT_ACLUT_Msk & ((value) << LCDC_HEOCLUT_ACLUT_Pos)))
+/* -------- LCDC_VERSION : (LCDC Offset: 0x00001FFC) Version Register -------- */
+#define LCDC_VERSION_VERSION_Pos 0
+#define LCDC_VERSION_VERSION_Msk (0xfffu << LCDC_VERSION_VERSION_Pos) /**< \brief (LCDC_VERSION) Version of the Hardware Module */
+#define LCDC_VERSION_MFN_Pos 16
+#define LCDC_VERSION_MFN_Msk (0x7u << LCDC_VERSION_MFN_Pos) /**< \brief (LCDC_VERSION) Metal Fix Number */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_LCDC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_matrix.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_matrix.h
new file mode 100644
index 000000000..eed3a43e0
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_matrix.h
@@ -0,0 +1,1520 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_MATRIX_COMPONENT_
+#define _SAMA5D2_MATRIX_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR AHB Bus Matrix */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_MATRIX AHB Bus Matrix */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief MatrixPr hardware registers */
+typedef struct {
+  __IO uint32_t MATRIX_PRAS; /**< \brief (MatrixPr Offset: 0x0) Priority Register A for Slave 0 */
+  __IO uint32_t MATRIX_PRBS; /**< \brief (MatrixPr Offset: 0x4) Priority Register B for Slave 0 */
+} MatrixPr;
+/** \brief Matrix hardware registers */
+#define MATRIXPR_NUMBER 15
+typedef struct {
+  __IO uint32_t MATRIX_MCFG0;               /**< \brief (Matrix Offset: 0x0000) Master Configuration Register 0 */
+  __IO uint32_t MATRIX_MCFG1;               /**< \brief (Matrix Offset: 0x0004) Master Configuration Register 1 */
+  __IO uint32_t MATRIX_MCFG2;               /**< \brief (Matrix Offset: 0x0008) Master Configuration Register 2 */
+  __IO uint32_t MATRIX_MCFG3;               /**< \brief (Matrix Offset: 0x000C) Master Configuration Register 3 */
+  __IO uint32_t MATRIX_MCFG4;               /**< \brief (Matrix Offset: 0x0010) Master Configuration Register 4 */
+  __IO uint32_t MATRIX_MCFG5;               /**< \brief (Matrix Offset: 0x0014) Master Configuration Register 5 */
+  __IO uint32_t MATRIX_MCFG6;               /**< \brief (Matrix Offset: 0x0018) Master Configuration Register 6 */
+  __IO uint32_t MATRIX_MCFG7;               /**< \brief (Matrix Offset: 0x001C) Master Configuration Register 7 */
+  __IO uint32_t MATRIX_MCFG8;               /**< \brief (Matrix Offset: 0x0020) Master Configuration Register 8 */
+  __IO uint32_t MATRIX_MCFG9;               /**< \brief (Matrix Offset: 0x0024) Master Configuration Register 9 */
+  __IO uint32_t MATRIX_MCFG10;              /**< \brief (Matrix Offset: 0x0028) Master Configuration Register 10 */
+  __IO uint32_t MATRIX_MCFG11;              /**< \brief (Matrix Offset: 0x002C) Master Configuration Register 11 */
+  __I  uint32_t Reserved1[4];
+  __IO uint32_t MATRIX_SCFG0;               /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register 0 */
+  __IO uint32_t MATRIX_SCFG1;               /**< \brief (Matrix Offset: 0x0044) Slave Configuration Register 1 */
+  __IO uint32_t MATRIX_SCFG2;               /**< \brief (Matrix Offset: 0x0048) Slave Configuration Register 2 */
+  __IO uint32_t MATRIX_SCFG3;               /**< \brief (Matrix Offset: 0x004C) Slave Configuration Register 3 */
+  __IO uint32_t MATRIX_SCFG4;               /**< \brief (Matrix Offset: 0x0050) Slave Configuration Register 4 */
+  __IO uint32_t MATRIX_SCFG5;               /**< \brief (Matrix Offset: 0x0054) Slave Configuration Register 5 */
+  __IO uint32_t MATRIX_SCFG6;               /**< \brief (Matrix Offset: 0x0058) Slave Configuration Register 6 */
+  __IO uint32_t MATRIX_SCFG7;               /**< \brief (Matrix Offset: 0x005C) Slave Configuration Register 7 */
+  __IO uint32_t MATRIX_SCFG8;               /**< \brief (Matrix Offset: 0x0060) Slave Configuration Register 8 */
+  __IO uint32_t MATRIX_SCFG9;               /**< \brief (Matrix Offset: 0x0064) Slave Configuration Register 9 */
+  __IO uint32_t MATRIX_SCFG10;              /**< \brief (Matrix Offset: 0x0068) Slave Configuration Register 10 */
+  __IO uint32_t MATRIX_SCFG11;              /**< \brief (Matrix Offset: 0x006C) Slave Configuration Register 11 */
+  __IO uint32_t MATRIX_SCFG12;              /**< \brief (Matrix Offset: 0x0070) Slave Configuration Register 12 */
+  __IO uint32_t MATRIX_SCFG13;              /**< \brief (Matrix Offset: 0x0074) Slave Configuration Register 13 */
+  __IO uint32_t MATRIX_SCFG14;              /**< \brief (Matrix Offset: 0x0078) Slave Configuration Register 14 */
+  __I  uint32_t Reserved2[1];
+       MatrixPr MATRIX_PR[MATRIXPR_NUMBER]; /**< \brief (Matrix Offset: 0x0080) 0 .. 14 */
+  __I  uint32_t Reserved3[22];
+  __O  uint32_t MATRIX_MEIER;               /**< \brief (Matrix Offset: 0x0150) Master Error Interrupt Enable Register */
+  __O  uint32_t MATRIX_MEIDR;               /**< \brief (Matrix Offset: 0x0154) Master Error Interrupt Disable Register */
+  __I  uint32_t MATRIX_MEIMR;               /**< \brief (Matrix Offset: 0x0158) Master Error Interrupt Mask Register */
+  __I  uint32_t MATRIX_MESR;                /**< \brief (Matrix Offset: 0x015C) Master Error Status Register */
+  __I  uint32_t MATRIX_MEAR0;               /**< \brief (Matrix Offset: 0x0160) Master 0 Error Address Register */
+  __I  uint32_t MATRIX_MEAR1;               /**< \brief (Matrix Offset: 0x0164) Master 1 Error Address Register */
+  __I  uint32_t MATRIX_MEAR2;               /**< \brief (Matrix Offset: 0x0168) Master 2 Error Address Register */
+  __I  uint32_t MATRIX_MEAR3;               /**< \brief (Matrix Offset: 0x016C) Master 3 Error Address Register */
+  __I  uint32_t MATRIX_MEAR4;               /**< \brief (Matrix Offset: 0x0170) Master 4 Error Address Register */
+  __I  uint32_t MATRIX_MEAR5;               /**< \brief (Matrix Offset: 0x0174) Master 5 Error Address Register */
+  __I  uint32_t MATRIX_MEAR6;               /**< \brief (Matrix Offset: 0x0178) Master 6 Error Address Register */
+  __I  uint32_t MATRIX_MEAR7;               /**< \brief (Matrix Offset: 0x017C) Master 7 Error Address Register */
+  __I  uint32_t MATRIX_MEAR8;               /**< \brief (Matrix Offset: 0x0180) Master 8 Error Address Register */
+  __I  uint32_t MATRIX_MEAR9;               /**< \brief (Matrix Offset: 0x0184) Master 9 Error Address Register */
+  __I  uint32_t MATRIX_MEAR10;              /**< \brief (Matrix Offset: 0x0188) Master 10 Error Address Register */
+  __I  uint32_t MATRIX_MEAR11;              /**< \brief (Matrix Offset: 0x018C) Master 11 Error Address Register */
+  __I  uint32_t Reserved4[21];
+  __IO uint32_t MATRIX_WPMR;                /**< \brief (Matrix Offset: 0x01E4) Write Protection Mode Register */
+  __I  uint32_t MATRIX_WPSR;                /**< \brief (Matrix Offset: 0x01E8) Write Protection Status Register */
+  __I  uint32_t Reserved5[4];
+  __I  uint32_t MATRIX_VERSION;             /**< \brief (Matrix Offset: 0x01FC) Version Register */
+  __IO uint32_t MATRIX_SSR[15];                /**< \brief (Matrix Offset: 0x0200) Security Slave x Register */
+  __I  uint32_t Reserved6[1];
+  __IO uint32_t MATRIX_SASSR[15];              /**< \brief (Matrix Offset: 0x0240) Security Areas Split Slave x Register */
+  __I  uint32_t Reserved7[1];
+  __IO uint32_t MATRIX_SRTSR[15];              /**< \brief (Matrix Offset: 0x0284) Security Region Top Slave x Register */
+  __I  uint32_t Reserved8[1];
+  __IO uint32_t MATRIX_SPSELR[3];           /**< \brief (Matrix Offset: 0x02C0) Security Peripheral Select x Register */
+} Matrix;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0000) Master Configuration Register 0 -------- */
+#define MATRIX_MCFG0_ULBT_Pos 0
+#define MATRIX_MCFG0_ULBT_Msk (0x7u << MATRIX_MCFG0_ULBT_Pos) /**< \brief (MATRIX_MCFG0) Undefined Length Burst Type */
+#define MATRIX_MCFG0_ULBT(value) ((MATRIX_MCFG0_ULBT_Msk & ((value) << MATRIX_MCFG0_ULBT_Pos)))
+#define   MATRIX_MCFG0_ULBT_UNLIMITED (0x0u << 0) /**< \brief (MATRIX_MCFG0) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
+#define   MATRIX_MCFG0_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG0) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
+#define   MATRIX_MCFG0_ULBT_4_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG0) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
+#define   MATRIX_MCFG0_ULBT_8_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG0) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
+#define   MATRIX_MCFG0_ULBT_16_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG0) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
+#define   MATRIX_MCFG0_ULBT_32_BEAT (0x5u << 0) /**< \brief (MATRIX_MCFG0) 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
+#define   MATRIX_MCFG0_ULBT_64_BEAT (0x6u << 0) /**< \brief (MATRIX_MCFG0) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
+#define   MATRIX_MCFG0_ULBT_128_BEAT (0x7u << 0) /**< \brief (MATRIX_MCFG0) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. */
+/* -------- MATRIX_MCFG1 : (MATRIX Offset: 0x0004) Master Configuration Register 1 -------- */
+#define MATRIX_MCFG1_ULBT_Pos 0
+#define MATRIX_MCFG1_ULBT_Msk (0x7u << MATRIX_MCFG1_ULBT_Pos) /**< \brief (MATRIX_MCFG1) Undefined Length Burst Type */
+#define MATRIX_MCFG1_ULBT(value) ((MATRIX_MCFG1_ULBT_Msk & ((value) << MATRIX_MCFG1_ULBT_Pos)))
+#define   MATRIX_MCFG1_ULBT_UNLIMITED (0x0u << 0) /**< \brief (MATRIX_MCFG1) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
+#define   MATRIX_MCFG1_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG1) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
+#define   MATRIX_MCFG1_ULBT_4_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG1) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
+#define   MATRIX_MCFG1_ULBT_8_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG1) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
+#define   MATRIX_MCFG1_ULBT_16_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG1) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
+#define   MATRIX_MCFG1_ULBT_32_BEAT (0x5u << 0) /**< \brief (MATRIX_MCFG1) 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
+#define   MATRIX_MCFG1_ULBT_64_BEAT (0x6u << 0) /**< \brief (MATRIX_MCFG1) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
+#define   MATRIX_MCFG1_ULBT_128_BEAT (0x7u << 0) /**< \brief (MATRIX_MCFG1) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. */
+/* -------- MATRIX_MCFG2 : (MATRIX Offset: 0x0008) Master Configuration Register 2 -------- */
+#define MATRIX_MCFG2_ULBT_Pos 0
+#define MATRIX_MCFG2_ULBT_Msk (0x7u << MATRIX_MCFG2_ULBT_Pos) /**< \brief (MATRIX_MCFG2) Undefined Length Burst Type */
+#define MATRIX_MCFG2_ULBT(value) ((MATRIX_MCFG2_ULBT_Msk & ((value) << MATRIX_MCFG2_ULBT_Pos)))
+#define   MATRIX_MCFG2_ULBT_UNLIMITED (0x0u << 0) /**< \brief (MATRIX_MCFG2) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
+#define   MATRIX_MCFG2_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG2) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
+#define   MATRIX_MCFG2_ULBT_4_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG2) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
+#define   MATRIX_MCFG2_ULBT_8_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG2) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
+#define   MATRIX_MCFG2_ULBT_16_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG2) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
+#define   MATRIX_MCFG2_ULBT_32_BEAT (0x5u << 0) /**< \brief (MATRIX_MCFG2) 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
+#define   MATRIX_MCFG2_ULBT_64_BEAT (0x6u << 0) /**< \brief (MATRIX_MCFG2) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
+#define   MATRIX_MCFG2_ULBT_128_BEAT (0x7u << 0) /**< \brief (MATRIX_MCFG2) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. */
+/* -------- MATRIX_MCFG3 : (MATRIX Offset: 0x000C) Master Configuration Register 3 -------- */
+#define MATRIX_MCFG3_ULBT_Pos 0
+#define MATRIX_MCFG3_ULBT_Msk (0x7u << MATRIX_MCFG3_ULBT_Pos) /**< \brief (MATRIX_MCFG3) Undefined Length Burst Type */
+#define MATRIX_MCFG3_ULBT(value) ((MATRIX_MCFG3_ULBT_Msk & ((value) << MATRIX_MCFG3_ULBT_Pos)))
+#define   MATRIX_MCFG3_ULBT_UNLIMITED (0x0u << 0) /**< \brief (MATRIX_MCFG3) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
+#define   MATRIX_MCFG3_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG3) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
+#define   MATRIX_MCFG3_ULBT_4_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG3) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
+#define   MATRIX_MCFG3_ULBT_8_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG3) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
+#define   MATRIX_MCFG3_ULBT_16_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG3) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
+#define   MATRIX_MCFG3_ULBT_32_BEAT (0x5u << 0) /**< \brief (MATRIX_MCFG3) 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
+#define   MATRIX_MCFG3_ULBT_64_BEAT (0x6u << 0) /**< \brief (MATRIX_MCFG3) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
+#define   MATRIX_MCFG3_ULBT_128_BEAT (0x7u << 0) /**< \brief (MATRIX_MCFG3) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. */
+/* -------- MATRIX_MCFG4 : (MATRIX Offset: 0x0010) Master Configuration Register 4 -------- */
+#define MATRIX_MCFG4_ULBT_Pos 0
+#define MATRIX_MCFG4_ULBT_Msk (0x7u << MATRIX_MCFG4_ULBT_Pos) /**< \brief (MATRIX_MCFG4) Undefined Length Burst Type */
+#define MATRIX_MCFG4_ULBT(value) ((MATRIX_MCFG4_ULBT_Msk & ((value) << MATRIX_MCFG4_ULBT_Pos)))
+#define   MATRIX_MCFG4_ULBT_UNLIMITED (0x0u << 0) /**< \brief (MATRIX_MCFG4) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
+#define   MATRIX_MCFG4_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG4) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
+#define   MATRIX_MCFG4_ULBT_4_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG4) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
+#define   MATRIX_MCFG4_ULBT_8_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG4) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
+#define   MATRIX_MCFG4_ULBT_16_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG4) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
+#define   MATRIX_MCFG4_ULBT_32_BEAT (0x5u << 0) /**< \brief (MATRIX_MCFG4) 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
+#define   MATRIX_MCFG4_ULBT_64_BEAT (0x6u << 0) /**< \brief (MATRIX_MCFG4) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
+#define   MATRIX_MCFG4_ULBT_128_BEAT (0x7u << 0) /**< \brief (MATRIX_MCFG4) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. */
+/* -------- MATRIX_MCFG5 : (MATRIX Offset: 0x0014) Master Configuration Register 5 -------- */
+#define MATRIX_MCFG5_ULBT_Pos 0
+#define MATRIX_MCFG5_ULBT_Msk (0x7u << MATRIX_MCFG5_ULBT_Pos) /**< \brief (MATRIX_MCFG5) Undefined Length Burst Type */
+#define MATRIX_MCFG5_ULBT(value) ((MATRIX_MCFG5_ULBT_Msk & ((value) << MATRIX_MCFG5_ULBT_Pos)))
+#define   MATRIX_MCFG5_ULBT_UNLIMITED (0x0u << 0) /**< \brief (MATRIX_MCFG5) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
+#define   MATRIX_MCFG5_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG5) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
+#define   MATRIX_MCFG5_ULBT_4_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG5) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
+#define   MATRIX_MCFG5_ULBT_8_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG5) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
+#define   MATRIX_MCFG5_ULBT_16_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG5) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
+#define   MATRIX_MCFG5_ULBT_32_BEAT (0x5u << 0) /**< \brief (MATRIX_MCFG5) 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
+#define   MATRIX_MCFG5_ULBT_64_BEAT (0x6u << 0) /**< \brief (MATRIX_MCFG5) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
+#define   MATRIX_MCFG5_ULBT_128_BEAT (0x7u << 0) /**< \brief (MATRIX_MCFG5) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. */
+/* -------- MATRIX_MCFG6 : (MATRIX Offset: 0x0018) Master Configuration Register 6 -------- */
+#define MATRIX_MCFG6_ULBT_Pos 0
+#define MATRIX_MCFG6_ULBT_Msk (0x7u << MATRIX_MCFG6_ULBT_Pos) /**< \brief (MATRIX_MCFG6) Undefined Length Burst Type */
+#define MATRIX_MCFG6_ULBT(value) ((MATRIX_MCFG6_ULBT_Msk & ((value) << MATRIX_MCFG6_ULBT_Pos)))
+#define   MATRIX_MCFG6_ULBT_UNLIMITED (0x0u << 0) /**< \brief (MATRIX_MCFG6) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
+#define   MATRIX_MCFG6_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG6) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
+#define   MATRIX_MCFG6_ULBT_4_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG6) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
+#define   MATRIX_MCFG6_ULBT_8_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG6) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
+#define   MATRIX_MCFG6_ULBT_16_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG6) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
+#define   MATRIX_MCFG6_ULBT_32_BEAT (0x5u << 0) /**< \brief (MATRIX_MCFG6) 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
+#define   MATRIX_MCFG6_ULBT_64_BEAT (0x6u << 0) /**< \brief (MATRIX_MCFG6) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
+#define   MATRIX_MCFG6_ULBT_128_BEAT (0x7u << 0) /**< \brief (MATRIX_MCFG6) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. */
+/* -------- MATRIX_MCFG7 : (MATRIX Offset: 0x001C) Master Configuration Register 7 -------- */
+#define MATRIX_MCFG7_ULBT_Pos 0
+#define MATRIX_MCFG7_ULBT_Msk (0x7u << MATRIX_MCFG7_ULBT_Pos) /**< \brief (MATRIX_MCFG7) Undefined Length Burst Type */
+#define MATRIX_MCFG7_ULBT(value) ((MATRIX_MCFG7_ULBT_Msk & ((value) << MATRIX_MCFG7_ULBT_Pos)))
+#define   MATRIX_MCFG7_ULBT_UNLIMITED (0x0u << 0) /**< \brief (MATRIX_MCFG7) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
+#define   MATRIX_MCFG7_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG7) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
+#define   MATRIX_MCFG7_ULBT_4_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG7) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
+#define   MATRIX_MCFG7_ULBT_8_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG7) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
+#define   MATRIX_MCFG7_ULBT_16_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG7) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
+#define   MATRIX_MCFG7_ULBT_32_BEAT (0x5u << 0) /**< \brief (MATRIX_MCFG7) 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
+#define   MATRIX_MCFG7_ULBT_64_BEAT (0x6u << 0) /**< \brief (MATRIX_MCFG7) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
+#define   MATRIX_MCFG7_ULBT_128_BEAT (0x7u << 0) /**< \brief (MATRIX_MCFG7) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. */
+/* -------- MATRIX_MCFG8 : (MATRIX Offset: 0x0020) Master Configuration Register 8 -------- */
+#define MATRIX_MCFG8_ULBT_Pos 0
+#define MATRIX_MCFG8_ULBT_Msk (0x7u << MATRIX_MCFG8_ULBT_Pos) /**< \brief (MATRIX_MCFG8) Undefined Length Burst Type */
+#define MATRIX_MCFG8_ULBT(value) ((MATRIX_MCFG8_ULBT_Msk & ((value) << MATRIX_MCFG8_ULBT_Pos)))
+#define   MATRIX_MCFG8_ULBT_UNLIMITED (0x0u << 0) /**< \brief (MATRIX_MCFG8) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
+#define   MATRIX_MCFG8_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG8) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
+#define   MATRIX_MCFG8_ULBT_4_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG8) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
+#define   MATRIX_MCFG8_ULBT_8_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG8) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
+#define   MATRIX_MCFG8_ULBT_16_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG8) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
+#define   MATRIX_MCFG8_ULBT_32_BEAT (0x5u << 0) /**< \brief (MATRIX_MCFG8) 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
+#define   MATRIX_MCFG8_ULBT_64_BEAT (0x6u << 0) /**< \brief (MATRIX_MCFG8) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
+#define   MATRIX_MCFG8_ULBT_128_BEAT (0x7u << 0) /**< \brief (MATRIX_MCFG8) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. */
+/* -------- MATRIX_MCFG9 : (MATRIX Offset: 0x0024) Master Configuration Register 9 -------- */
+#define MATRIX_MCFG9_ULBT_Pos 0
+#define MATRIX_MCFG9_ULBT_Msk (0x7u << MATRIX_MCFG9_ULBT_Pos) /**< \brief (MATRIX_MCFG9) Undefined Length Burst Type */
+#define MATRIX_MCFG9_ULBT(value) ((MATRIX_MCFG9_ULBT_Msk & ((value) << MATRIX_MCFG9_ULBT_Pos)))
+#define   MATRIX_MCFG9_ULBT_UNLIMITED (0x0u << 0) /**< \brief (MATRIX_MCFG9) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
+#define   MATRIX_MCFG9_ULBT_SINGLE (0x1u << 0) /**< \brief (MATRIX_MCFG9) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
+#define   MATRIX_MCFG9_ULBT_4_BEAT (0x2u << 0) /**< \brief (MATRIX_MCFG9) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
+#define   MATRIX_MCFG9_ULBT_8_BEAT (0x3u << 0) /**< \brief (MATRIX_MCFG9) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
+#define   MATRIX_MCFG9_ULBT_16_BEAT (0x4u << 0) /**< \brief (MATRIX_MCFG9) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
+#define   MATRIX_MCFG9_ULBT_32_BEAT (0x5u << 0) /**< \brief (MATRIX_MCFG9) 32-beat Burst-The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
+#define   MATRIX_MCFG9_ULBT_64_BEAT (0x6u << 0) /**< \brief (MATRIX_MCFG9) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
+#define   MATRIX_MCFG9_ULBT_128_BEAT (0x7u << 0) /**< \brief (MATRIX_MCFG9) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.Unless duly needed, the ULBT should be left at its default 0 value for power saving. */
+/* -------- MATRIX_SCFG0 : (MATRIX Offset: 0x0040) Slave Configuration Register 0 -------- */
+#define MATRIX_SCFG0_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG0_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG0_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG0) Maximum Bus Grant Duration for Masters */
+#define MATRIX_SCFG0_SLOT_CYCLE(value) ((MATRIX_SCFG0_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG0_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG0_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG0_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG0_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG0) Default Master Type */
+#define MATRIX_SCFG0_DEFMSTR_TYPE(value) ((MATRIX_SCFG0_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG0_DEFMSTR_TYPE_Pos)))
+#define   MATRIX_SCFG0_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG0) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */
+#define   MATRIX_SCFG0_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG0) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */
+#define   MATRIX_SCFG0_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG0) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */
+#define MATRIX_SCFG0_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG0_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG0_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG0) Fixed Default Master */
+#define MATRIX_SCFG0_FIXED_DEFMSTR(value) ((MATRIX_SCFG0_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG0_FIXED_DEFMSTR_Pos)))
+/* -------- MATRIX_SCFG1 : (MATRIX Offset: 0x0044) Slave Configuration Register 1 -------- */
+#define MATRIX_SCFG1_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG1_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG1_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG1) Maximum Bus Grant Duration for Masters */
+#define MATRIX_SCFG1_SLOT_CYCLE(value) ((MATRIX_SCFG1_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG1_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG1_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG1_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG1_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG1) Default Master Type */
+#define MATRIX_SCFG1_DEFMSTR_TYPE(value) ((MATRIX_SCFG1_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG1_DEFMSTR_TYPE_Pos)))
+#define   MATRIX_SCFG1_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG1) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */
+#define   MATRIX_SCFG1_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG1) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */
+#define   MATRIX_SCFG1_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG1) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */
+#define MATRIX_SCFG1_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG1_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG1_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG1) Fixed Default Master */
+#define MATRIX_SCFG1_FIXED_DEFMSTR(value) ((MATRIX_SCFG1_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG1_FIXED_DEFMSTR_Pos)))
+/* -------- MATRIX_SCFG2 : (MATRIX Offset: 0x0048) Slave Configuration Register 2 -------- */
+#define MATRIX_SCFG2_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG2_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG2_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG2) Maximum Bus Grant Duration for Masters */
+#define MATRIX_SCFG2_SLOT_CYCLE(value) ((MATRIX_SCFG2_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG2_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG2_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG2_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG2_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG2) Default Master Type */
+#define MATRIX_SCFG2_DEFMSTR_TYPE(value) ((MATRIX_SCFG2_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG2_DEFMSTR_TYPE_Pos)))
+#define   MATRIX_SCFG2_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG2) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */
+#define   MATRIX_SCFG2_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG2) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */
+#define   MATRIX_SCFG2_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG2) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */
+#define MATRIX_SCFG2_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG2_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG2_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG2) Fixed Default Master */
+#define MATRIX_SCFG2_FIXED_DEFMSTR(value) ((MATRIX_SCFG2_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG2_FIXED_DEFMSTR_Pos)))
+/* -------- MATRIX_SCFG3 : (MATRIX Offset: 0x004C) Slave Configuration Register 3 -------- */
+#define MATRIX_SCFG3_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG3_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG3_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG3) Maximum Bus Grant Duration for Masters */
+#define MATRIX_SCFG3_SLOT_CYCLE(value) ((MATRIX_SCFG3_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG3_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG3_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG3_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG3_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG3) Default Master Type */
+#define MATRIX_SCFG3_DEFMSTR_TYPE(value) ((MATRIX_SCFG3_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG3_DEFMSTR_TYPE_Pos)))
+#define   MATRIX_SCFG3_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG3) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */
+#define   MATRIX_SCFG3_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG3) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */
+#define   MATRIX_SCFG3_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG3) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */
+#define MATRIX_SCFG3_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG3_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG3_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG3) Fixed Default Master */
+#define MATRIX_SCFG3_FIXED_DEFMSTR(value) ((MATRIX_SCFG3_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG3_FIXED_DEFMSTR_Pos)))
+/* -------- MATRIX_SCFG4 : (MATRIX Offset: 0x0050) Slave Configuration Register 4 -------- */
+#define MATRIX_SCFG4_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG4_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG4_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG4) Maximum Bus Grant Duration for Masters */
+#define MATRIX_SCFG4_SLOT_CYCLE(value) ((MATRIX_SCFG4_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG4_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG4_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG4_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG4_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG4) Default Master Type */
+#define MATRIX_SCFG4_DEFMSTR_TYPE(value) ((MATRIX_SCFG4_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG4_DEFMSTR_TYPE_Pos)))
+#define   MATRIX_SCFG4_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG4) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */
+#define   MATRIX_SCFG4_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG4) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */
+#define   MATRIX_SCFG4_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG4) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */
+#define MATRIX_SCFG4_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG4_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG4_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG4) Fixed Default Master */
+#define MATRIX_SCFG4_FIXED_DEFMSTR(value) ((MATRIX_SCFG4_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG4_FIXED_DEFMSTR_Pos)))
+/* -------- MATRIX_SCFG5 : (MATRIX Offset: 0x0054) Slave Configuration Register 5 -------- */
+#define MATRIX_SCFG5_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG5_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG5_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG5) Maximum Bus Grant Duration for Masters */
+#define MATRIX_SCFG5_SLOT_CYCLE(value) ((MATRIX_SCFG5_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG5_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG5_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG5_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG5_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG5) Default Master Type */
+#define MATRIX_SCFG5_DEFMSTR_TYPE(value) ((MATRIX_SCFG5_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG5_DEFMSTR_TYPE_Pos)))
+#define   MATRIX_SCFG5_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG5) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */
+#define   MATRIX_SCFG5_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG5) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */
+#define   MATRIX_SCFG5_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG5) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */
+#define MATRIX_SCFG5_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG5_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG5_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG5) Fixed Default Master */
+#define MATRIX_SCFG5_FIXED_DEFMSTR(value) ((MATRIX_SCFG5_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG5_FIXED_DEFMSTR_Pos)))
+/* -------- MATRIX_SCFG6 : (MATRIX Offset: 0x0058) Slave Configuration Register 6 -------- */
+#define MATRIX_SCFG6_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG6_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG6_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG6) Maximum Bus Grant Duration for Masters */
+#define MATRIX_SCFG6_SLOT_CYCLE(value) ((MATRIX_SCFG6_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG6_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG6_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG6_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG6_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG6) Default Master Type */
+#define MATRIX_SCFG6_DEFMSTR_TYPE(value) ((MATRIX_SCFG6_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG6_DEFMSTR_TYPE_Pos)))
+#define   MATRIX_SCFG6_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG6) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */
+#define   MATRIX_SCFG6_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG6) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */
+#define   MATRIX_SCFG6_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG6) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */
+#define MATRIX_SCFG6_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG6_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG6_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG6) Fixed Default Master */
+#define MATRIX_SCFG6_FIXED_DEFMSTR(value) ((MATRIX_SCFG6_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG6_FIXED_DEFMSTR_Pos)))
+/* -------- MATRIX_SCFG7 : (MATRIX Offset: 0x005C) Slave Configuration Register 7 -------- */
+#define MATRIX_SCFG7_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG7_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG7_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG7) Maximum Bus Grant Duration for Masters */
+#define MATRIX_SCFG7_SLOT_CYCLE(value) ((MATRIX_SCFG7_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG7_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG7_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG7_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG7_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG7) Default Master Type */
+#define MATRIX_SCFG7_DEFMSTR_TYPE(value) ((MATRIX_SCFG7_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG7_DEFMSTR_TYPE_Pos)))
+#define   MATRIX_SCFG7_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG7) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */
+#define   MATRIX_SCFG7_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG7) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */
+#define   MATRIX_SCFG7_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG7) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */
+#define MATRIX_SCFG7_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG7_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG7_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG7) Fixed Default Master */
+#define MATRIX_SCFG7_FIXED_DEFMSTR(value) ((MATRIX_SCFG7_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG7_FIXED_DEFMSTR_Pos)))
+/* -------- MATRIX_SCFG8 : (MATRIX Offset: 0x0060) Slave Configuration Register 8 -------- */
+#define MATRIX_SCFG8_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG8_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG8_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG8) Maximum Bus Grant Duration for Masters */
+#define MATRIX_SCFG8_SLOT_CYCLE(value) ((MATRIX_SCFG8_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG8_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG8_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG8_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG8_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG8) Default Master Type */
+#define MATRIX_SCFG8_DEFMSTR_TYPE(value) ((MATRIX_SCFG8_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG8_DEFMSTR_TYPE_Pos)))
+#define   MATRIX_SCFG8_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG8) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */
+#define   MATRIX_SCFG8_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG8) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */
+#define   MATRIX_SCFG8_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG8) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */
+#define MATRIX_SCFG8_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG8_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG8_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG8) Fixed Default Master */
+#define MATRIX_SCFG8_FIXED_DEFMSTR(value) ((MATRIX_SCFG8_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG8_FIXED_DEFMSTR_Pos)))
+/* -------- MATRIX_SCFG9 : (MATRIX Offset: 0x0064) Slave Configuration Register 9 -------- */
+#define MATRIX_SCFG9_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG9_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG9_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG9) Maximum Bus Grant Duration for Masters */
+#define MATRIX_SCFG9_SLOT_CYCLE(value) ((MATRIX_SCFG9_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG9_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG9_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG9_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG9_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG9) Default Master Type */
+#define MATRIX_SCFG9_DEFMSTR_TYPE(value) ((MATRIX_SCFG9_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG9_DEFMSTR_TYPE_Pos)))
+#define   MATRIX_SCFG9_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG9) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */
+#define   MATRIX_SCFG9_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG9) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */
+#define   MATRIX_SCFG9_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG9) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */
+#define MATRIX_SCFG9_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG9_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG9_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG9) Fixed Default Master */
+#define MATRIX_SCFG9_FIXED_DEFMSTR(value) ((MATRIX_SCFG9_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG9_FIXED_DEFMSTR_Pos)))
+/* -------- MATRIX_SCFG10 : (MATRIX Offset: 0x0068) Slave Configuration Register 10 -------- */
+#define MATRIX_SCFG10_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG10_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG10_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG10) Maximum Bus Grant Duration for Masters */
+#define MATRIX_SCFG10_SLOT_CYCLE(value) ((MATRIX_SCFG10_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG10_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG10_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG10_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG10_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG10) Default Master Type */
+#define MATRIX_SCFG10_DEFMSTR_TYPE(value) ((MATRIX_SCFG10_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG10_DEFMSTR_TYPE_Pos)))
+#define   MATRIX_SCFG10_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG10) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */
+#define   MATRIX_SCFG10_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG10) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */
+#define   MATRIX_SCFG10_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG10) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */
+#define MATRIX_SCFG10_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG10_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG10_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG10) Fixed Default Master */
+#define MATRIX_SCFG10_FIXED_DEFMSTR(value) ((MATRIX_SCFG10_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG10_FIXED_DEFMSTR_Pos)))
+/* -------- MATRIX_SCFG11 : (MATRIX Offset: 0x006C) Slave Configuration Register 11 -------- */
+#define MATRIX_SCFG11_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG11_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG11_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG11) Maximum Bus Grant Duration for Masters */
+#define MATRIX_SCFG11_SLOT_CYCLE(value) ((MATRIX_SCFG11_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG11_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG11_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG11_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG11_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG11) Default Master Type */
+#define MATRIX_SCFG11_DEFMSTR_TYPE(value) ((MATRIX_SCFG11_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG11_DEFMSTR_TYPE_Pos)))
+#define   MATRIX_SCFG11_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG11) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */
+#define   MATRIX_SCFG11_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG11) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */
+#define   MATRIX_SCFG11_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG11) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */
+#define MATRIX_SCFG11_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG11_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG11_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG11) Fixed Default Master */
+#define MATRIX_SCFG11_FIXED_DEFMSTR(value) ((MATRIX_SCFG11_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG11_FIXED_DEFMSTR_Pos)))
+/* -------- MATRIX_SCFG12 : (MATRIX Offset: 0x0070) Slave Configuration Register 12 -------- */
+#define MATRIX_SCFG12_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG12_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG12_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG12) Maximum Bus Grant Duration for Masters */
+#define MATRIX_SCFG12_SLOT_CYCLE(value) ((MATRIX_SCFG12_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG12_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG12_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG12_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG12_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG12) Default Master Type */
+#define MATRIX_SCFG12_DEFMSTR_TYPE(value) ((MATRIX_SCFG12_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG12_DEFMSTR_TYPE_Pos)))
+#define   MATRIX_SCFG12_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG12) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */
+#define   MATRIX_SCFG12_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG12) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */
+#define   MATRIX_SCFG12_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG12) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */
+#define MATRIX_SCFG12_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG12_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG12_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG12) Fixed Default Master */
+#define MATRIX_SCFG12_FIXED_DEFMSTR(value) ((MATRIX_SCFG12_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG12_FIXED_DEFMSTR_Pos)))
+/* -------- MATRIX_PRAS : (MATRIX Offset: N/A) Priority Register A for Slave 0 -------- */
+#define MATRIX_PRAS_M0PR_Pos 0
+#define MATRIX_PRAS_M0PR_Msk (0x3u << MATRIX_PRAS_M0PR_Pos) /**< \brief (MATRIX_PRAS) Master 0 Priority */
+#define MATRIX_PRAS_M0PR(value) ((MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos)))
+#define MATRIX_PRAS_M1PR_Pos 4
+#define MATRIX_PRAS_M1PR_Msk (0x3u << MATRIX_PRAS_M1PR_Pos) /**< \brief (MATRIX_PRAS) Master 1 Priority */
+#define MATRIX_PRAS_M1PR(value) ((MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos)))
+#define MATRIX_PRAS_M2PR_Pos 8
+#define MATRIX_PRAS_M2PR_Msk (0x3u << MATRIX_PRAS_M2PR_Pos) /**< \brief (MATRIX_PRAS) Master 2 Priority */
+#define MATRIX_PRAS_M2PR(value) ((MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos)))
+#define MATRIX_PRAS_M3PR_Pos 12
+#define MATRIX_PRAS_M3PR_Msk (0x3u << MATRIX_PRAS_M3PR_Pos) /**< \brief (MATRIX_PRAS) Master 3 Priority */
+#define MATRIX_PRAS_M3PR(value) ((MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos)))
+#define MATRIX_PRAS_M4PR_Pos 16
+#define MATRIX_PRAS_M4PR_Msk (0x3u << MATRIX_PRAS_M4PR_Pos) /**< \brief (MATRIX_PRAS) Master 4 Priority */
+#define MATRIX_PRAS_M4PR(value) ((MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos)))
+#define MATRIX_PRAS_M5PR_Pos 20
+#define MATRIX_PRAS_M5PR_Msk (0x3u << MATRIX_PRAS_M5PR_Pos) /**< \brief (MATRIX_PRAS) Master 5 Priority */
+#define MATRIX_PRAS_M5PR(value) ((MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos)))
+#define MATRIX_PRAS_M6PR_Pos 24
+#define MATRIX_PRAS_M6PR_Msk (0x3u << MATRIX_PRAS_M6PR_Pos) /**< \brief (MATRIX_PRAS) Master 6 Priority */
+#define MATRIX_PRAS_M6PR(value) ((MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos)))
+#define MATRIX_PRAS_M7PR_Pos 28
+#define MATRIX_PRAS_M7PR_Msk (0x3u << MATRIX_PRAS_M7PR_Pos) /**< \brief (MATRIX_PRAS) Master 7 Priority */
+#define MATRIX_PRAS_M7PR(value) ((MATRIX_PRAS_M7PR_Msk & ((value) << MATRIX_PRAS_M7PR_Pos)))
+/* -------- MATRIX_PRBS : (MATRIX Offset: N/A) Priority Register B for Slave 0 -------- */
+#define MATRIX_PRBS_M8PR_Pos 0
+#define MATRIX_PRBS_M8PR_Msk (0x3u << MATRIX_PRBS_M8PR_Pos) /**< \brief (MATRIX_PRBS) Master 8 Priority */
+#define MATRIX_PRBS_M8PR(value) ((MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos)))
+#define MATRIX_PRBS_M9PR_Pos 4
+#define MATRIX_PRBS_M9PR_Msk (0x3u << MATRIX_PRBS_M9PR_Pos) /**< \brief (MATRIX_PRBS) Master 9 Priority */
+#define MATRIX_PRBS_M9PR(value) ((MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos)))
+#define MATRIX_PRBS_M10PR_Pos 8
+#define MATRIX_PRBS_M10PR_Msk (0x3u << MATRIX_PRBS_M10PR_Pos) /**< \brief (MATRIX_PRBS) Master 10 Priority */
+#define MATRIX_PRBS_M10PR(value) ((MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos)))
+#define MATRIX_PRBS_M11PR_Pos 12
+#define MATRIX_PRBS_M11PR_Msk (0x3u << MATRIX_PRBS_M11PR_Pos) /**< \brief (MATRIX_PRBS) Master 11 Priority */
+#define MATRIX_PRBS_M11PR(value) ((MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos)))
+/* -------- MATRIX_MEIER : (MATRIX Offset: 0x0150) Master Error Interrupt Enable Register -------- */
+#define MATRIX_MEIER_MERR0 (0x1u << 0) /**< \brief (MATRIX_MEIER) Master 0 Access Error */
+#define MATRIX_MEIER_MERR1 (0x1u << 1) /**< \brief (MATRIX_MEIER) Master 1 Access Error */
+#define MATRIX_MEIER_MERR2 (0x1u << 2) /**< \brief (MATRIX_MEIER) Master 2 Access Error */
+#define MATRIX_MEIER_MERR3 (0x1u << 3) /**< \brief (MATRIX_MEIER) Master 3 Access Error */
+#define MATRIX_MEIER_MERR4 (0x1u << 4) /**< \brief (MATRIX_MEIER) Master 4 Access Error */
+#define MATRIX_MEIER_MERR5 (0x1u << 5) /**< \brief (MATRIX_MEIER) Master 5 Access Error */
+#define MATRIX_MEIER_MERR6 (0x1u << 6) /**< \brief (MATRIX_MEIER) Master 6 Access Error */
+#define MATRIX_MEIER_MERR7 (0x1u << 7) /**< \brief (MATRIX_MEIER) Master 7 Access Error */
+#define MATRIX_MEIER_MERR8 (0x1u << 8) /**< \brief (MATRIX_MEIER) Master 8 Access Error */
+#define MATRIX_MEIER_MERR9 (0x1u << 9) /**< \brief (MATRIX_MEIER) Master 9 Access Error */
+#define MATRIX_MEIER_MERR10 (0x1u << 10) /**< \brief (MATRIX_MEIER) Master 10 Access Error */
+#define MATRIX_MEIER_MERR11 (0x1u << 11) /**< \brief (MATRIX_MEIER) Master 11 Access Error */
+/* -------- MATRIX_MEIDR : (MATRIX Offset: 0x0154) Master Error Interrupt Disable Register -------- */
+#define MATRIX_MEIDR_MERR0 (0x1u << 0) /**< \brief (MATRIX_MEIDR) Master 0 Access Error */
+#define MATRIX_MEIDR_MERR1 (0x1u << 1) /**< \brief (MATRIX_MEIDR) Master 1 Access Error */
+#define MATRIX_MEIDR_MERR2 (0x1u << 2) /**< \brief (MATRIX_MEIDR) Master 2 Access Error */
+#define MATRIX_MEIDR_MERR3 (0x1u << 3) /**< \brief (MATRIX_MEIDR) Master 3 Access Error */
+#define MATRIX_MEIDR_MERR4 (0x1u << 4) /**< \brief (MATRIX_MEIDR) Master 4 Access Error */
+#define MATRIX_MEIDR_MERR5 (0x1u << 5) /**< \brief (MATRIX_MEIDR) Master 5 Access Error */
+#define MATRIX_MEIDR_MERR6 (0x1u << 6) /**< \brief (MATRIX_MEIDR) Master 6 Access Error */
+#define MATRIX_MEIDR_MERR7 (0x1u << 7) /**< \brief (MATRIX_MEIDR) Master 7 Access Error */
+#define MATRIX_MEIDR_MERR8 (0x1u << 8) /**< \brief (MATRIX_MEIDR) Master 8 Access Error */
+#define MATRIX_MEIDR_MERR9 (0x1u << 9) /**< \brief (MATRIX_MEIDR) Master 9 Access Error */
+#define MATRIX_MEIDR_MERR10 (0x1u << 10) /**< \brief (MATRIX_MEIDR) Master 10 Access Error */
+#define MATRIX_MEIDR_MERR11 (0x1u << 11) /**< \brief (MATRIX_MEIDR) Master 11 Access Error */
+/* -------- MATRIX_MEIMR : (MATRIX Offset: 0x0158) Master Error Interrupt Mask Register -------- */
+#define MATRIX_MEIMR_MERR0 (0x1u << 0) /**< \brief (MATRIX_MEIMR) Master 0 Access Error */
+#define MATRIX_MEIMR_MERR1 (0x1u << 1) /**< \brief (MATRIX_MEIMR) Master 1 Access Error */
+#define MATRIX_MEIMR_MERR2 (0x1u << 2) /**< \brief (MATRIX_MEIMR) Master 2 Access Error */
+#define MATRIX_MEIMR_MERR3 (0x1u << 3) /**< \brief (MATRIX_MEIMR) Master 3 Access Error */
+#define MATRIX_MEIMR_MERR4 (0x1u << 4) /**< \brief (MATRIX_MEIMR) Master 4 Access Error */
+#define MATRIX_MEIMR_MERR5 (0x1u << 5) /**< \brief (MATRIX_MEIMR) Master 5 Access Error */
+#define MATRIX_MEIMR_MERR6 (0x1u << 6) /**< \brief (MATRIX_MEIMR) Master 6 Access Error */
+#define MATRIX_MEIMR_MERR7 (0x1u << 7) /**< \brief (MATRIX_MEIMR) Master 7 Access Error */
+#define MATRIX_MEIMR_MERR8 (0x1u << 8) /**< \brief (MATRIX_MEIMR) Master 8 Access Error */
+#define MATRIX_MEIMR_MERR9 (0x1u << 9) /**< \brief (MATRIX_MEIMR) Master 9 Access Error */
+#define MATRIX_MEIMR_MERR10 (0x1u << 10) /**< \brief (MATRIX_MEIMR) Master 10 Access Error */
+#define MATRIX_MEIMR_MERR11 (0x1u << 11) /**< \brief (MATRIX_MEIMR) Master 11 Access Error */
+/* -------- MATRIX_MESR : (MATRIX Offset: 0x015C) Master Error Status Register -------- */
+#define MATRIX_MESR_MERR0 (0x1u << 0) /**< \brief (MATRIX_MESR) Master 0 Access Error */
+#define MATRIX_MESR_MERR1 (0x1u << 1) /**< \brief (MATRIX_MESR) Master 1 Access Error */
+#define MATRIX_MESR_MERR2 (0x1u << 2) /**< \brief (MATRIX_MESR) Master 2 Access Error */
+#define MATRIX_MESR_MERR3 (0x1u << 3) /**< \brief (MATRIX_MESR) Master 3 Access Error */
+#define MATRIX_MESR_MERR4 (0x1u << 4) /**< \brief (MATRIX_MESR) Master 4 Access Error */
+#define MATRIX_MESR_MERR5 (0x1u << 5) /**< \brief (MATRIX_MESR) Master 5 Access Error */
+#define MATRIX_MESR_MERR6 (0x1u << 6) /**< \brief (MATRIX_MESR) Master 6 Access Error */
+#define MATRIX_MESR_MERR7 (0x1u << 7) /**< \brief (MATRIX_MESR) Master 7 Access Error */
+#define MATRIX_MESR_MERR8 (0x1u << 8) /**< \brief (MATRIX_MESR) Master 8 Access Error */
+#define MATRIX_MESR_MERR9 (0x1u << 9) /**< \brief (MATRIX_MESR) Master 9 Access Error */
+#define MATRIX_MESR_MERR10 (0x1u << 10) /**< \brief (MATRIX_MESR) Master 10 Access Error */
+#define MATRIX_MESR_MERR11 (0x1u << 11) /**< \brief (MATRIX_MESR) Master 11 Access Error */
+/* -------- MATRIX_MEAR0 : (MATRIX Offset: 0x0160) Master 0 Error Address Register -------- */
+#define MATRIX_MEAR0_ERRADD_Pos 0
+#define MATRIX_MEAR0_ERRADD_Msk (0xffffffffu << MATRIX_MEAR0_ERRADD_Pos) /**< \brief (MATRIX_MEAR0) Master Error Address */
+/* -------- MATRIX_MEAR1 : (MATRIX Offset: 0x0164) Master 1 Error Address Register -------- */
+#define MATRIX_MEAR1_ERRADD_Pos 0
+#define MATRIX_MEAR1_ERRADD_Msk (0xffffffffu << MATRIX_MEAR1_ERRADD_Pos) /**< \brief (MATRIX_MEAR1) Master Error Address */
+/* -------- MATRIX_MEAR2 : (MATRIX Offset: 0x0168) Master 2 Error Address Register -------- */
+#define MATRIX_MEAR2_ERRADD_Pos 0
+#define MATRIX_MEAR2_ERRADD_Msk (0xffffffffu << MATRIX_MEAR2_ERRADD_Pos) /**< \brief (MATRIX_MEAR2) Master Error Address */
+/* -------- MATRIX_MEAR3 : (MATRIX Offset: 0x016C) Master 3 Error Address Register -------- */
+#define MATRIX_MEAR3_ERRADD_Pos 0
+#define MATRIX_MEAR3_ERRADD_Msk (0xffffffffu << MATRIX_MEAR3_ERRADD_Pos) /**< \brief (MATRIX_MEAR3) Master Error Address */
+/* -------- MATRIX_MEAR4 : (MATRIX Offset: 0x0170) Master 4 Error Address Register -------- */
+#define MATRIX_MEAR4_ERRADD_Pos 0
+#define MATRIX_MEAR4_ERRADD_Msk (0xffffffffu << MATRIX_MEAR4_ERRADD_Pos) /**< \brief (MATRIX_MEAR4) Master Error Address */
+/* -------- MATRIX_MEAR5 : (MATRIX Offset: 0x0174) Master 5 Error Address Register -------- */
+#define MATRIX_MEAR5_ERRADD_Pos 0
+#define MATRIX_MEAR5_ERRADD_Msk (0xffffffffu << MATRIX_MEAR5_ERRADD_Pos) /**< \brief (MATRIX_MEAR5) Master Error Address */
+/* -------- MATRIX_MEAR6 : (MATRIX Offset: 0x0178) Master 6 Error Address Register -------- */
+#define MATRIX_MEAR6_ERRADD_Pos 0
+#define MATRIX_MEAR6_ERRADD_Msk (0xffffffffu << MATRIX_MEAR6_ERRADD_Pos) /**< \brief (MATRIX_MEAR6) Master Error Address */
+/* -------- MATRIX_MEAR7 : (MATRIX Offset: 0x017C) Master 7 Error Address Register -------- */
+#define MATRIX_MEAR7_ERRADD_Pos 0
+#define MATRIX_MEAR7_ERRADD_Msk (0xffffffffu << MATRIX_MEAR7_ERRADD_Pos) /**< \brief (MATRIX_MEAR7) Master Error Address */
+/* -------- MATRIX_MEAR8 : (MATRIX Offset: 0x0180) Master 8 Error Address Register -------- */
+#define MATRIX_MEAR8_ERRADD_Pos 0
+#define MATRIX_MEAR8_ERRADD_Msk (0xffffffffu << MATRIX_MEAR8_ERRADD_Pos) /**< \brief (MATRIX_MEAR8) Master Error Address */
+/* -------- MATRIX_MEAR9 : (MATRIX Offset: 0x0184) Master 9 Error Address Register -------- */
+#define MATRIX_MEAR9_ERRADD_Pos 0
+#define MATRIX_MEAR9_ERRADD_Msk (0xffffffffu << MATRIX_MEAR9_ERRADD_Pos) /**< \brief (MATRIX_MEAR9) Master Error Address */
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protection Mode Register -------- */
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protection Enable */
+#define MATRIX_WPMR_WPKEY_Pos 8
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protection Key (Write-only) */
+#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
+#define   MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8) /**< \brief (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protection Status Register -------- */
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protection Violation Status */
+#define MATRIX_WPSR_WPVSRC_Pos 8
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protection Violation Source */
+/* -------- MATRIX_VERSION : (MATRIX Offset: 0x01FC) Version Register -------- */
+#define MATRIX_VERSION_VERSION_Pos 0
+#define MATRIX_VERSION_VERSION_Msk (0xfffu << MATRIX_VERSION_VERSION_Pos) /**< \brief (MATRIX_VERSION) Version of the Hardware Module */
+#define MATRIX_VERSION_MFN_Pos 16
+#define MATRIX_VERSION_MFN_Msk (0x7u << MATRIX_VERSION_MFN_Pos) /**< \brief (MATRIX_VERSION) Metal Fix Number */
+/* -------- MATRIX_SSR0 : (MATRIX Offset: 0x0200) Security Slave 0 Register -------- */
+#define MATRIX_SSR0_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR0) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR0_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR0) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR0_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR0) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR0_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR0) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR0_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR0) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR0_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR0) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR0_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR0) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR0_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR0) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR0_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR0) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR0_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR0) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR0_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR0) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR0_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR0) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR0_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR0) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR0_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR0) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR0_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR0) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR0_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR0) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR0_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR0) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR0_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR0) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR0_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR0) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR0_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR0) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR0_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR0) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR0_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR0) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR0_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR0) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR0_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR0) Write Non-secured for HSELx Security Region */
+/* -------- MATRIX_SSR1 : (MATRIX Offset: 0x0204) Security Slave 1 Register -------- */
+#define MATRIX_SSR1_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR1) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR1_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR1) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR1_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR1) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR1_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR1) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR1_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR1) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR1_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR1) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR1_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR1) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR1_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR1) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR1_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR1) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR1_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR1) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR1_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR1) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR1_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR1) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR1_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR1) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR1_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR1) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR1_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR1) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR1_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR1) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR1_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR1) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR1_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR1) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR1_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR1) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR1_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR1) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR1_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR1) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR1_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR1) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR1_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR1) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR1_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR1) Write Non-secured for HSELx Security Region */
+/* -------- MATRIX_SSR2 : (MATRIX Offset: 0x0208) Security Slave 2 Register -------- */
+#define MATRIX_SSR2_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR2) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR2_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR2) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR2_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR2) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR2_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR2) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR2_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR2) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR2_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR2) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR2_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR2) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR2_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR2) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR2_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR2) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR2_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR2) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR2_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR2) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR2_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR2) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR2_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR2) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR2_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR2) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR2_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR2) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR2_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR2) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR2_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR2) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR2_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR2) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR2_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR2) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR2_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR2) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR2_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR2) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR2_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR2) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR2_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR2) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR2_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR2) Write Non-secured for HSELx Security Region */
+/* -------- MATRIX_SSR3 : (MATRIX Offset: 0x020C) Security Slave 3 Register -------- */
+#define MATRIX_SSR3_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR3) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR3_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR3) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR3_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR3) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR3_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR3) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR3_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR3) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR3_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR3) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR3_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR3) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR3_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR3) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR3_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR3) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR3_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR3) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR3_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR3) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR3_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR3) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR3_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR3) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR3_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR3) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR3_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR3) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR3_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR3) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR3_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR3) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR3_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR3) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR3_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR3) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR3_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR3) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR3_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR3) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR3_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR3) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR3_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR3) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR3_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR3) Write Non-secured for HSELx Security Region */
+/* -------- MATRIX_SSR4 : (MATRIX Offset: 0x0210) Security Slave 4 Register -------- */
+#define MATRIX_SSR4_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR4) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR4_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR4) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR4_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR4) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR4_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR4) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR4_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR4) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR4_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR4) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR4_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR4) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR4_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR4) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR4_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR4) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR4_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR4) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR4_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR4) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR4_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR4) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR4_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR4) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR4_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR4) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR4_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR4) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR4_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR4) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR4_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR4) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR4_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR4) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR4_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR4) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR4_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR4) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR4_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR4) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR4_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR4) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR4_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR4) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR4_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR4) Write Non-secured for HSELx Security Region */
+/* -------- MATRIX_SSR5 : (MATRIX Offset: 0x0214) Security Slave 5 Register -------- */
+#define MATRIX_SSR5_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR5) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR5_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR5) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR5_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR5) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR5_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR5) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR5_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR5) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR5_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR5) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR5_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR5) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR5_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR5) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR5_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR5) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR5_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR5) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR5_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR5) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR5_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR5) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR5_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR5) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR5_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR5) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR5_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR5) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR5_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR5) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR5_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR5) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR5_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR5) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR5_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR5) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR5_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR5) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR5_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR5) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR5_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR5) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR5_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR5) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR5_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR5) Write Non-secured for HSELx Security Region */
+/* -------- MATRIX_SSR6 : (MATRIX Offset: 0x0218) Security Slave 6 Register -------- */
+#define MATRIX_SSR6_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR6) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR6_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR6) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR6_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR6) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR6_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR6) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR6_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR6) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR6_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR6) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR6_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR6) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR6_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR6) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR6_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR6) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR6_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR6) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR6_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR6) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR6_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR6) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR6_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR6) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR6_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR6) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR6_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR6) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR6_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR6) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR6_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR6) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR6_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR6) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR6_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR6) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR6_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR6) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR6_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR6) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR6_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR6) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR6_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR6) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR6_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR6) Write Non-secured for HSELx Security Region */
+/* -------- MATRIX_SSR7 : (MATRIX Offset: 0x021C) Security Slave 7 Register -------- */
+#define MATRIX_SSR7_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR7) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR7_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR7) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR7_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR7) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR7_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR7) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR7_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR7) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR7_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR7) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR7_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR7) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR7_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR7) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR7_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR7) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR7_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR7) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR7_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR7) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR7_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR7) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR7_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR7) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR7_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR7) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR7_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR7) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR7_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR7) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR7_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR7) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR7_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR7) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR7_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR7) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR7_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR7) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR7_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR7) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR7_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR7) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR7_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR7) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR7_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR7) Write Non-secured for HSELx Security Region */
+/* -------- MATRIX_SSR8 : (MATRIX Offset: 0x0220) Security Slave 8 Register -------- */
+#define MATRIX_SSR8_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR8) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR8_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR8) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR8_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR8) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR8_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR8) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR8_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR8) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR8_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR8) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR8_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR8) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR8_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR8) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR8_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR8) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR8_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR8) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR8_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR8) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR8_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR8) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR8_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR8) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR8_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR8) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR8_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR8) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR8_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR8) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR8_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR8) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR8_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR8) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR8_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR8) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR8_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR8) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR8_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR8) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR8_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR8) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR8_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR8) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR8_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR8) Write Non-secured for HSELx Security Region */
+/* -------- MATRIX_SSR9 : (MATRIX Offset: 0x0224) Security Slave 9 Register -------- */
+#define MATRIX_SSR9_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR9) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR9_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR9) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR9_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR9) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR9_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR9) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR9_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR9) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR9_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR9) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR9_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR9) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR9_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR9) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR9_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR9) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR9_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR9) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR9_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR9) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR9_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR9) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR9_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR9) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR9_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR9) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR9_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR9) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR9_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR9) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR9_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR9) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR9_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR9) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR9_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR9) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR9_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR9) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR9_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR9) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR9_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR9) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR9_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR9) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR9_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR9) Write Non-secured for HSELx Security Region */
+/* -------- MATRIX_SSR10 : (MATRIX Offset: 0x0228) Security Slave 10 Register -------- */
+#define MATRIX_SSR10_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR10) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR10_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR10) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR10_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR10) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR10_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR10) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR10_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR10) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR10_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR10) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR10_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR10) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR10_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR10) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR10_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR10) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR10_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR10) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR10_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR10) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR10_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR10) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR10_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR10) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR10_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR10) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR10_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR10) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR10_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR10) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR10_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR10) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR10_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR10) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR10_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR10) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR10_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR10) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR10_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR10) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR10_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR10) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR10_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR10) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR10_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR10) Write Non-secured for HSELx Security Region */
+/* -------- MATRIX_SSR11 : (MATRIX Offset: 0x022C) Security Slave 11 Register -------- */
+#define MATRIX_SSR11_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR11) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR11_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR11) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR11_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR11) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR11_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR11) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR11_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR11) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR11_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR11) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR11_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR11) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR11_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR11) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR11_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR11) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR11_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR11) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR11_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR11) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR11_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR11) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR11_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR11) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR11_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR11) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR11_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR11) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR11_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR11) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR11_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR11) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR11_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR11) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR11_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR11) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR11_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR11) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR11_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR11) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR11_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR11) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR11_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR11) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR11_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR11) Write Non-secured for HSELx Security Region */
+/* -------- MATRIX_SSR12 : (MATRIX Offset: 0x0230) Security Slave 12 Register -------- */
+#define MATRIX_SSR12_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR12) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR12_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR12) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR12_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR12) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR12_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR12) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR12_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR12) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR12_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR12) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR12_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR12) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR12_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR12) Low Area Non-secured in HSELx Security Region */
+#define MATRIX_SSR12_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR12) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR12_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR12) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR12_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR12) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR12_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR12) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR12_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR12) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR12_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR12) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR12_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR12) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR12_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR12) Read Non-secured for HSELx Security Region */
+#define MATRIX_SSR12_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR12) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR12_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR12) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR12_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR12) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR12_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR12) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR12_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR12) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR12_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR12) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR12_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR12) Write Non-secured for HSELx Security Region */
+#define MATRIX_SSR12_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR12) Write Non-secured for HSELx Security Region */
+/* -------- MATRIX_SASSR0 : (MATRIX Offset: 0x0240) Security Areas Split Slave 0 Register -------- */
+#define MATRIX_SASSR0_SASPLIT0_Pos 0
+#define MATRIX_SASSR0_SASPLIT0_Msk (0xfu << MATRIX_SASSR0_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR0) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR0_SASPLIT0(value) ((MATRIX_SASSR0_SASPLIT0_Msk & ((value) << MATRIX_SASSR0_SASPLIT0_Pos)))
+#define MATRIX_SASSR0_SASPLIT1_Pos 4
+#define MATRIX_SASSR0_SASPLIT1_Msk (0xfu << MATRIX_SASSR0_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR0) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR0_SASPLIT1(value) ((MATRIX_SASSR0_SASPLIT1_Msk & ((value) << MATRIX_SASSR0_SASPLIT1_Pos)))
+#define MATRIX_SASSR0_SASPLIT2_Pos 8
+#define MATRIX_SASSR0_SASPLIT2_Msk (0xfu << MATRIX_SASSR0_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR0) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR0_SASPLIT2(value) ((MATRIX_SASSR0_SASPLIT2_Msk & ((value) << MATRIX_SASSR0_SASPLIT2_Pos)))
+#define MATRIX_SASSR0_SASPLIT3_Pos 12
+#define MATRIX_SASSR0_SASPLIT3_Msk (0xfu << MATRIX_SASSR0_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR0) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR0_SASPLIT3(value) ((MATRIX_SASSR0_SASPLIT3_Msk & ((value) << MATRIX_SASSR0_SASPLIT3_Pos)))
+#define MATRIX_SASSR0_SASPLIT4_Pos 16
+#define MATRIX_SASSR0_SASPLIT4_Msk (0xfu << MATRIX_SASSR0_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR0) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR0_SASPLIT4(value) ((MATRIX_SASSR0_SASPLIT4_Msk & ((value) << MATRIX_SASSR0_SASPLIT4_Pos)))
+#define MATRIX_SASSR0_SASPLIT5_Pos 20
+#define MATRIX_SASSR0_SASPLIT5_Msk (0xfu << MATRIX_SASSR0_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR0) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR0_SASPLIT5(value) ((MATRIX_SASSR0_SASPLIT5_Msk & ((value) << MATRIX_SASSR0_SASPLIT5_Pos)))
+#define MATRIX_SASSR0_SASPLIT6_Pos 24
+#define MATRIX_SASSR0_SASPLIT6_Msk (0xfu << MATRIX_SASSR0_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR0) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR0_SASPLIT6(value) ((MATRIX_SASSR0_SASPLIT6_Msk & ((value) << MATRIX_SASSR0_SASPLIT6_Pos)))
+#define MATRIX_SASSR0_SASPLIT7_Pos 28
+#define MATRIX_SASSR0_SASPLIT7_Msk (0xfu << MATRIX_SASSR0_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR0) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR0_SASPLIT7(value) ((MATRIX_SASSR0_SASPLIT7_Msk & ((value) << MATRIX_SASSR0_SASPLIT7_Pos)))
+/* -------- MATRIX_SASSR1 : (MATRIX Offset: 0x0244) Security Areas Split Slave 1 Register -------- */
+#define MATRIX_SASSR1_SASPLIT0_Pos 0
+#define MATRIX_SASSR1_SASPLIT0_Msk (0xfu << MATRIX_SASSR1_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR1) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR1_SASPLIT0(value) ((MATRIX_SASSR1_SASPLIT0_Msk & ((value) << MATRIX_SASSR1_SASPLIT0_Pos)))
+#define MATRIX_SASSR1_SASPLIT1_Pos 4
+#define MATRIX_SASSR1_SASPLIT1_Msk (0xfu << MATRIX_SASSR1_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR1) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR1_SASPLIT1(value) ((MATRIX_SASSR1_SASPLIT1_Msk & ((value) << MATRIX_SASSR1_SASPLIT1_Pos)))
+#define MATRIX_SASSR1_SASPLIT2_Pos 8
+#define MATRIX_SASSR1_SASPLIT2_Msk (0xfu << MATRIX_SASSR1_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR1) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR1_SASPLIT2(value) ((MATRIX_SASSR1_SASPLIT2_Msk & ((value) << MATRIX_SASSR1_SASPLIT2_Pos)))
+#define MATRIX_SASSR1_SASPLIT3_Pos 12
+#define MATRIX_SASSR1_SASPLIT3_Msk (0xfu << MATRIX_SASSR1_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR1) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR1_SASPLIT3(value) ((MATRIX_SASSR1_SASPLIT3_Msk & ((value) << MATRIX_SASSR1_SASPLIT3_Pos)))
+#define MATRIX_SASSR1_SASPLIT4_Pos 16
+#define MATRIX_SASSR1_SASPLIT4_Msk (0xfu << MATRIX_SASSR1_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR1) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR1_SASPLIT4(value) ((MATRIX_SASSR1_SASPLIT4_Msk & ((value) << MATRIX_SASSR1_SASPLIT4_Pos)))
+#define MATRIX_SASSR1_SASPLIT5_Pos 20
+#define MATRIX_SASSR1_SASPLIT5_Msk (0xfu << MATRIX_SASSR1_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR1) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR1_SASPLIT5(value) ((MATRIX_SASSR1_SASPLIT5_Msk & ((value) << MATRIX_SASSR1_SASPLIT5_Pos)))
+#define MATRIX_SASSR1_SASPLIT6_Pos 24
+#define MATRIX_SASSR1_SASPLIT6_Msk (0xfu << MATRIX_SASSR1_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR1) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR1_SASPLIT6(value) ((MATRIX_SASSR1_SASPLIT6_Msk & ((value) << MATRIX_SASSR1_SASPLIT6_Pos)))
+#define MATRIX_SASSR1_SASPLIT7_Pos 28
+#define MATRIX_SASSR1_SASPLIT7_Msk (0xfu << MATRIX_SASSR1_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR1) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR1_SASPLIT7(value) ((MATRIX_SASSR1_SASPLIT7_Msk & ((value) << MATRIX_SASSR1_SASPLIT7_Pos)))
+/* -------- MATRIX_SASSR2 : (MATRIX Offset: 0x0248) Security Areas Split Slave 2 Register -------- */
+#define MATRIX_SASSR2_SASPLIT0_Pos 0
+#define MATRIX_SASSR2_SASPLIT0_Msk (0xfu << MATRIX_SASSR2_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR2) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR2_SASPLIT0(value) ((MATRIX_SASSR2_SASPLIT0_Msk & ((value) << MATRIX_SASSR2_SASPLIT0_Pos)))
+#define MATRIX_SASSR2_SASPLIT1_Pos 4
+#define MATRIX_SASSR2_SASPLIT1_Msk (0xfu << MATRIX_SASSR2_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR2) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR2_SASPLIT1(value) ((MATRIX_SASSR2_SASPLIT1_Msk & ((value) << MATRIX_SASSR2_SASPLIT1_Pos)))
+#define MATRIX_SASSR2_SASPLIT2_Pos 8
+#define MATRIX_SASSR2_SASPLIT2_Msk (0xfu << MATRIX_SASSR2_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR2) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR2_SASPLIT2(value) ((MATRIX_SASSR2_SASPLIT2_Msk & ((value) << MATRIX_SASSR2_SASPLIT2_Pos)))
+#define MATRIX_SASSR2_SASPLIT3_Pos 12
+#define MATRIX_SASSR2_SASPLIT3_Msk (0xfu << MATRIX_SASSR2_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR2) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR2_SASPLIT3(value) ((MATRIX_SASSR2_SASPLIT3_Msk & ((value) << MATRIX_SASSR2_SASPLIT3_Pos)))
+#define MATRIX_SASSR2_SASPLIT4_Pos 16
+#define MATRIX_SASSR2_SASPLIT4_Msk (0xfu << MATRIX_SASSR2_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR2) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR2_SASPLIT4(value) ((MATRIX_SASSR2_SASPLIT4_Msk & ((value) << MATRIX_SASSR2_SASPLIT4_Pos)))
+#define MATRIX_SASSR2_SASPLIT5_Pos 20
+#define MATRIX_SASSR2_SASPLIT5_Msk (0xfu << MATRIX_SASSR2_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR2) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR2_SASPLIT5(value) ((MATRIX_SASSR2_SASPLIT5_Msk & ((value) << MATRIX_SASSR2_SASPLIT5_Pos)))
+#define MATRIX_SASSR2_SASPLIT6_Pos 24
+#define MATRIX_SASSR2_SASPLIT6_Msk (0xfu << MATRIX_SASSR2_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR2) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR2_SASPLIT6(value) ((MATRIX_SASSR2_SASPLIT6_Msk & ((value) << MATRIX_SASSR2_SASPLIT6_Pos)))
+#define MATRIX_SASSR2_SASPLIT7_Pos 28
+#define MATRIX_SASSR2_SASPLIT7_Msk (0xfu << MATRIX_SASSR2_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR2) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR2_SASPLIT7(value) ((MATRIX_SASSR2_SASPLIT7_Msk & ((value) << MATRIX_SASSR2_SASPLIT7_Pos)))
+/* -------- MATRIX_SASSR3 : (MATRIX Offset: 0x024C) Security Areas Split Slave 3 Register -------- */
+#define MATRIX_SASSR3_SASPLIT0_Pos 0
+#define MATRIX_SASSR3_SASPLIT0_Msk (0xfu << MATRIX_SASSR3_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR3) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR3_SASPLIT0(value) ((MATRIX_SASSR3_SASPLIT0_Msk & ((value) << MATRIX_SASSR3_SASPLIT0_Pos)))
+#define MATRIX_SASSR3_SASPLIT1_Pos 4
+#define MATRIX_SASSR3_SASPLIT1_Msk (0xfu << MATRIX_SASSR3_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR3) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR3_SASPLIT1(value) ((MATRIX_SASSR3_SASPLIT1_Msk & ((value) << MATRIX_SASSR3_SASPLIT1_Pos)))
+#define MATRIX_SASSR3_SASPLIT2_Pos 8
+#define MATRIX_SASSR3_SASPLIT2_Msk (0xfu << MATRIX_SASSR3_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR3) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR3_SASPLIT2(value) ((MATRIX_SASSR3_SASPLIT2_Msk & ((value) << MATRIX_SASSR3_SASPLIT2_Pos)))
+#define MATRIX_SASSR3_SASPLIT3_Pos 12
+#define MATRIX_SASSR3_SASPLIT3_Msk (0xfu << MATRIX_SASSR3_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR3) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR3_SASPLIT3(value) ((MATRIX_SASSR3_SASPLIT3_Msk & ((value) << MATRIX_SASSR3_SASPLIT3_Pos)))
+#define MATRIX_SASSR3_SASPLIT4_Pos 16
+#define MATRIX_SASSR3_SASPLIT4_Msk (0xfu << MATRIX_SASSR3_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR3) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR3_SASPLIT4(value) ((MATRIX_SASSR3_SASPLIT4_Msk & ((value) << MATRIX_SASSR3_SASPLIT4_Pos)))
+#define MATRIX_SASSR3_SASPLIT5_Pos 20
+#define MATRIX_SASSR3_SASPLIT5_Msk (0xfu << MATRIX_SASSR3_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR3) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR3_SASPLIT5(value) ((MATRIX_SASSR3_SASPLIT5_Msk & ((value) << MATRIX_SASSR3_SASPLIT5_Pos)))
+#define MATRIX_SASSR3_SASPLIT6_Pos 24
+#define MATRIX_SASSR3_SASPLIT6_Msk (0xfu << MATRIX_SASSR3_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR3) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR3_SASPLIT6(value) ((MATRIX_SASSR3_SASPLIT6_Msk & ((value) << MATRIX_SASSR3_SASPLIT6_Pos)))
+#define MATRIX_SASSR3_SASPLIT7_Pos 28
+#define MATRIX_SASSR3_SASPLIT7_Msk (0xfu << MATRIX_SASSR3_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR3) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR3_SASPLIT7(value) ((MATRIX_SASSR3_SASPLIT7_Msk & ((value) << MATRIX_SASSR3_SASPLIT7_Pos)))
+/* -------- MATRIX_SASSR4 : (MATRIX Offset: 0x0250) Security Areas Split Slave 4 Register -------- */
+#define MATRIX_SASSR4_SASPLIT0_Pos 0
+#define MATRIX_SASSR4_SASPLIT0_Msk (0xfu << MATRIX_SASSR4_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR4) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR4_SASPLIT0(value) ((MATRIX_SASSR4_SASPLIT0_Msk & ((value) << MATRIX_SASSR4_SASPLIT0_Pos)))
+#define MATRIX_SASSR4_SASPLIT1_Pos 4
+#define MATRIX_SASSR4_SASPLIT1_Msk (0xfu << MATRIX_SASSR4_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR4) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR4_SASPLIT1(value) ((MATRIX_SASSR4_SASPLIT1_Msk & ((value) << MATRIX_SASSR4_SASPLIT1_Pos)))
+#define MATRIX_SASSR4_SASPLIT2_Pos 8
+#define MATRIX_SASSR4_SASPLIT2_Msk (0xfu << MATRIX_SASSR4_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR4) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR4_SASPLIT2(value) ((MATRIX_SASSR4_SASPLIT2_Msk & ((value) << MATRIX_SASSR4_SASPLIT2_Pos)))
+#define MATRIX_SASSR4_SASPLIT3_Pos 12
+#define MATRIX_SASSR4_SASPLIT3_Msk (0xfu << MATRIX_SASSR4_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR4) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR4_SASPLIT3(value) ((MATRIX_SASSR4_SASPLIT3_Msk & ((value) << MATRIX_SASSR4_SASPLIT3_Pos)))
+#define MATRIX_SASSR4_SASPLIT4_Pos 16
+#define MATRIX_SASSR4_SASPLIT4_Msk (0xfu << MATRIX_SASSR4_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR4) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR4_SASPLIT4(value) ((MATRIX_SASSR4_SASPLIT4_Msk & ((value) << MATRIX_SASSR4_SASPLIT4_Pos)))
+#define MATRIX_SASSR4_SASPLIT5_Pos 20
+#define MATRIX_SASSR4_SASPLIT5_Msk (0xfu << MATRIX_SASSR4_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR4) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR4_SASPLIT5(value) ((MATRIX_SASSR4_SASPLIT5_Msk & ((value) << MATRIX_SASSR4_SASPLIT5_Pos)))
+#define MATRIX_SASSR4_SASPLIT6_Pos 24
+#define MATRIX_SASSR4_SASPLIT6_Msk (0xfu << MATRIX_SASSR4_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR4) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR4_SASPLIT6(value) ((MATRIX_SASSR4_SASPLIT6_Msk & ((value) << MATRIX_SASSR4_SASPLIT6_Pos)))
+#define MATRIX_SASSR4_SASPLIT7_Pos 28
+#define MATRIX_SASSR4_SASPLIT7_Msk (0xfu << MATRIX_SASSR4_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR4) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR4_SASPLIT7(value) ((MATRIX_SASSR4_SASPLIT7_Msk & ((value) << MATRIX_SASSR4_SASPLIT7_Pos)))
+/* -------- MATRIX_SASSR5 : (MATRIX Offset: 0x0254) Security Areas Split Slave 5 Register -------- */
+#define MATRIX_SASSR5_SASPLIT0_Pos 0
+#define MATRIX_SASSR5_SASPLIT0_Msk (0xfu << MATRIX_SASSR5_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR5) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR5_SASPLIT0(value) ((MATRIX_SASSR5_SASPLIT0_Msk & ((value) << MATRIX_SASSR5_SASPLIT0_Pos)))
+#define MATRIX_SASSR5_SASPLIT1_Pos 4
+#define MATRIX_SASSR5_SASPLIT1_Msk (0xfu << MATRIX_SASSR5_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR5) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR5_SASPLIT1(value) ((MATRIX_SASSR5_SASPLIT1_Msk & ((value) << MATRIX_SASSR5_SASPLIT1_Pos)))
+#define MATRIX_SASSR5_SASPLIT2_Pos 8
+#define MATRIX_SASSR5_SASPLIT2_Msk (0xfu << MATRIX_SASSR5_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR5) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR5_SASPLIT2(value) ((MATRIX_SASSR5_SASPLIT2_Msk & ((value) << MATRIX_SASSR5_SASPLIT2_Pos)))
+#define MATRIX_SASSR5_SASPLIT3_Pos 12
+#define MATRIX_SASSR5_SASPLIT3_Msk (0xfu << MATRIX_SASSR5_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR5) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR5_SASPLIT3(value) ((MATRIX_SASSR5_SASPLIT3_Msk & ((value) << MATRIX_SASSR5_SASPLIT3_Pos)))
+#define MATRIX_SASSR5_SASPLIT4_Pos 16
+#define MATRIX_SASSR5_SASPLIT4_Msk (0xfu << MATRIX_SASSR5_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR5) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR5_SASPLIT4(value) ((MATRIX_SASSR5_SASPLIT4_Msk & ((value) << MATRIX_SASSR5_SASPLIT4_Pos)))
+#define MATRIX_SASSR5_SASPLIT5_Pos 20
+#define MATRIX_SASSR5_SASPLIT5_Msk (0xfu << MATRIX_SASSR5_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR5) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR5_SASPLIT5(value) ((MATRIX_SASSR5_SASPLIT5_Msk & ((value) << MATRIX_SASSR5_SASPLIT5_Pos)))
+#define MATRIX_SASSR5_SASPLIT6_Pos 24
+#define MATRIX_SASSR5_SASPLIT6_Msk (0xfu << MATRIX_SASSR5_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR5) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR5_SASPLIT6(value) ((MATRIX_SASSR5_SASPLIT6_Msk & ((value) << MATRIX_SASSR5_SASPLIT6_Pos)))
+#define MATRIX_SASSR5_SASPLIT7_Pos 28
+#define MATRIX_SASSR5_SASPLIT7_Msk (0xfu << MATRIX_SASSR5_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR5) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR5_SASPLIT7(value) ((MATRIX_SASSR5_SASPLIT7_Msk & ((value) << MATRIX_SASSR5_SASPLIT7_Pos)))
+/* -------- MATRIX_SASSR6 : (MATRIX Offset: 0x0258) Security Areas Split Slave 6 Register -------- */
+#define MATRIX_SASSR6_SASPLIT0_Pos 0
+#define MATRIX_SASSR6_SASPLIT0_Msk (0xfu << MATRIX_SASSR6_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR6) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR6_SASPLIT0(value) ((MATRIX_SASSR6_SASPLIT0_Msk & ((value) << MATRIX_SASSR6_SASPLIT0_Pos)))
+#define MATRIX_SASSR6_SASPLIT1_Pos 4
+#define MATRIX_SASSR6_SASPLIT1_Msk (0xfu << MATRIX_SASSR6_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR6) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR6_SASPLIT1(value) ((MATRIX_SASSR6_SASPLIT1_Msk & ((value) << MATRIX_SASSR6_SASPLIT1_Pos)))
+#define MATRIX_SASSR6_SASPLIT2_Pos 8
+#define MATRIX_SASSR6_SASPLIT2_Msk (0xfu << MATRIX_SASSR6_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR6) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR6_SASPLIT2(value) ((MATRIX_SASSR6_SASPLIT2_Msk & ((value) << MATRIX_SASSR6_SASPLIT2_Pos)))
+#define MATRIX_SASSR6_SASPLIT3_Pos 12
+#define MATRIX_SASSR6_SASPLIT3_Msk (0xfu << MATRIX_SASSR6_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR6) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR6_SASPLIT3(value) ((MATRIX_SASSR6_SASPLIT3_Msk & ((value) << MATRIX_SASSR6_SASPLIT3_Pos)))
+#define MATRIX_SASSR6_SASPLIT4_Pos 16
+#define MATRIX_SASSR6_SASPLIT4_Msk (0xfu << MATRIX_SASSR6_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR6) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR6_SASPLIT4(value) ((MATRIX_SASSR6_SASPLIT4_Msk & ((value) << MATRIX_SASSR6_SASPLIT4_Pos)))
+#define MATRIX_SASSR6_SASPLIT5_Pos 20
+#define MATRIX_SASSR6_SASPLIT5_Msk (0xfu << MATRIX_SASSR6_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR6) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR6_SASPLIT5(value) ((MATRIX_SASSR6_SASPLIT5_Msk & ((value) << MATRIX_SASSR6_SASPLIT5_Pos)))
+#define MATRIX_SASSR6_SASPLIT6_Pos 24
+#define MATRIX_SASSR6_SASPLIT6_Msk (0xfu << MATRIX_SASSR6_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR6) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR6_SASPLIT6(value) ((MATRIX_SASSR6_SASPLIT6_Msk & ((value) << MATRIX_SASSR6_SASPLIT6_Pos)))
+#define MATRIX_SASSR6_SASPLIT7_Pos 28
+#define MATRIX_SASSR6_SASPLIT7_Msk (0xfu << MATRIX_SASSR6_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR6) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR6_SASPLIT7(value) ((MATRIX_SASSR6_SASPLIT7_Msk & ((value) << MATRIX_SASSR6_SASPLIT7_Pos)))
+/* -------- MATRIX_SASSR7 : (MATRIX Offset: 0x025C) Security Areas Split Slave 7 Register -------- */
+#define MATRIX_SASSR7_SASPLIT0_Pos 0
+#define MATRIX_SASSR7_SASPLIT0_Msk (0xfu << MATRIX_SASSR7_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR7) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR7_SASPLIT0(value) ((MATRIX_SASSR7_SASPLIT0_Msk & ((value) << MATRIX_SASSR7_SASPLIT0_Pos)))
+#define MATRIX_SASSR7_SASPLIT1_Pos 4
+#define MATRIX_SASSR7_SASPLIT1_Msk (0xfu << MATRIX_SASSR7_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR7) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR7_SASPLIT1(value) ((MATRIX_SASSR7_SASPLIT1_Msk & ((value) << MATRIX_SASSR7_SASPLIT1_Pos)))
+#define MATRIX_SASSR7_SASPLIT2_Pos 8
+#define MATRIX_SASSR7_SASPLIT2_Msk (0xfu << MATRIX_SASSR7_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR7) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR7_SASPLIT2(value) ((MATRIX_SASSR7_SASPLIT2_Msk & ((value) << MATRIX_SASSR7_SASPLIT2_Pos)))
+#define MATRIX_SASSR7_SASPLIT3_Pos 12
+#define MATRIX_SASSR7_SASPLIT3_Msk (0xfu << MATRIX_SASSR7_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR7) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR7_SASPLIT3(value) ((MATRIX_SASSR7_SASPLIT3_Msk & ((value) << MATRIX_SASSR7_SASPLIT3_Pos)))
+#define MATRIX_SASSR7_SASPLIT4_Pos 16
+#define MATRIX_SASSR7_SASPLIT4_Msk (0xfu << MATRIX_SASSR7_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR7) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR7_SASPLIT4(value) ((MATRIX_SASSR7_SASPLIT4_Msk & ((value) << MATRIX_SASSR7_SASPLIT4_Pos)))
+#define MATRIX_SASSR7_SASPLIT5_Pos 20
+#define MATRIX_SASSR7_SASPLIT5_Msk (0xfu << MATRIX_SASSR7_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR7) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR7_SASPLIT5(value) ((MATRIX_SASSR7_SASPLIT5_Msk & ((value) << MATRIX_SASSR7_SASPLIT5_Pos)))
+#define MATRIX_SASSR7_SASPLIT6_Pos 24
+#define MATRIX_SASSR7_SASPLIT6_Msk (0xfu << MATRIX_SASSR7_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR7) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR7_SASPLIT6(value) ((MATRIX_SASSR7_SASPLIT6_Msk & ((value) << MATRIX_SASSR7_SASPLIT6_Pos)))
+#define MATRIX_SASSR7_SASPLIT7_Pos 28
+#define MATRIX_SASSR7_SASPLIT7_Msk (0xfu << MATRIX_SASSR7_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR7) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR7_SASPLIT7(value) ((MATRIX_SASSR7_SASPLIT7_Msk & ((value) << MATRIX_SASSR7_SASPLIT7_Pos)))
+/* -------- MATRIX_SASSR8 : (MATRIX Offset: 0x0260) Security Areas Split Slave 8 Register -------- */
+#define MATRIX_SASSR8_SASPLIT0_Pos 0
+#define MATRIX_SASSR8_SASPLIT0_Msk (0xfu << MATRIX_SASSR8_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR8) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR8_SASPLIT0(value) ((MATRIX_SASSR8_SASPLIT0_Msk & ((value) << MATRIX_SASSR8_SASPLIT0_Pos)))
+#define MATRIX_SASSR8_SASPLIT1_Pos 4
+#define MATRIX_SASSR8_SASPLIT1_Msk (0xfu << MATRIX_SASSR8_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR8) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR8_SASPLIT1(value) ((MATRIX_SASSR8_SASPLIT1_Msk & ((value) << MATRIX_SASSR8_SASPLIT1_Pos)))
+#define MATRIX_SASSR8_SASPLIT2_Pos 8
+#define MATRIX_SASSR8_SASPLIT2_Msk (0xfu << MATRIX_SASSR8_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR8) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR8_SASPLIT2(value) ((MATRIX_SASSR8_SASPLIT2_Msk & ((value) << MATRIX_SASSR8_SASPLIT2_Pos)))
+#define MATRIX_SASSR8_SASPLIT3_Pos 12
+#define MATRIX_SASSR8_SASPLIT3_Msk (0xfu << MATRIX_SASSR8_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR8) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR8_SASPLIT3(value) ((MATRIX_SASSR8_SASPLIT3_Msk & ((value) << MATRIX_SASSR8_SASPLIT3_Pos)))
+#define MATRIX_SASSR8_SASPLIT4_Pos 16
+#define MATRIX_SASSR8_SASPLIT4_Msk (0xfu << MATRIX_SASSR8_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR8) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR8_SASPLIT4(value) ((MATRIX_SASSR8_SASPLIT4_Msk & ((value) << MATRIX_SASSR8_SASPLIT4_Pos)))
+#define MATRIX_SASSR8_SASPLIT5_Pos 20
+#define MATRIX_SASSR8_SASPLIT5_Msk (0xfu << MATRIX_SASSR8_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR8) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR8_SASPLIT5(value) ((MATRIX_SASSR8_SASPLIT5_Msk & ((value) << MATRIX_SASSR8_SASPLIT5_Pos)))
+#define MATRIX_SASSR8_SASPLIT6_Pos 24
+#define MATRIX_SASSR8_SASPLIT6_Msk (0xfu << MATRIX_SASSR8_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR8) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR8_SASPLIT6(value) ((MATRIX_SASSR8_SASPLIT6_Msk & ((value) << MATRIX_SASSR8_SASPLIT6_Pos)))
+#define MATRIX_SASSR8_SASPLIT7_Pos 28
+#define MATRIX_SASSR8_SASPLIT7_Msk (0xfu << MATRIX_SASSR8_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR8) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR8_SASPLIT7(value) ((MATRIX_SASSR8_SASPLIT7_Msk & ((value) << MATRIX_SASSR8_SASPLIT7_Pos)))
+/* -------- MATRIX_SASSR9 : (MATRIX Offset: 0x0264) Security Areas Split Slave 9 Register -------- */
+#define MATRIX_SASSR9_SASPLIT0_Pos 0
+#define MATRIX_SASSR9_SASPLIT0_Msk (0xfu << MATRIX_SASSR9_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR9) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR9_SASPLIT0(value) ((MATRIX_SASSR9_SASPLIT0_Msk & ((value) << MATRIX_SASSR9_SASPLIT0_Pos)))
+#define MATRIX_SASSR9_SASPLIT1_Pos 4
+#define MATRIX_SASSR9_SASPLIT1_Msk (0xfu << MATRIX_SASSR9_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR9) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR9_SASPLIT1(value) ((MATRIX_SASSR9_SASPLIT1_Msk & ((value) << MATRIX_SASSR9_SASPLIT1_Pos)))
+#define MATRIX_SASSR9_SASPLIT2_Pos 8
+#define MATRIX_SASSR9_SASPLIT2_Msk (0xfu << MATRIX_SASSR9_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR9) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR9_SASPLIT2(value) ((MATRIX_SASSR9_SASPLIT2_Msk & ((value) << MATRIX_SASSR9_SASPLIT2_Pos)))
+#define MATRIX_SASSR9_SASPLIT3_Pos 12
+#define MATRIX_SASSR9_SASPLIT3_Msk (0xfu << MATRIX_SASSR9_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR9) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR9_SASPLIT3(value) ((MATRIX_SASSR9_SASPLIT3_Msk & ((value) << MATRIX_SASSR9_SASPLIT3_Pos)))
+#define MATRIX_SASSR9_SASPLIT4_Pos 16
+#define MATRIX_SASSR9_SASPLIT4_Msk (0xfu << MATRIX_SASSR9_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR9) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR9_SASPLIT4(value) ((MATRIX_SASSR9_SASPLIT4_Msk & ((value) << MATRIX_SASSR9_SASPLIT4_Pos)))
+#define MATRIX_SASSR9_SASPLIT5_Pos 20
+#define MATRIX_SASSR9_SASPLIT5_Msk (0xfu << MATRIX_SASSR9_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR9) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR9_SASPLIT5(value) ((MATRIX_SASSR9_SASPLIT5_Msk & ((value) << MATRIX_SASSR9_SASPLIT5_Pos)))
+#define MATRIX_SASSR9_SASPLIT6_Pos 24
+#define MATRIX_SASSR9_SASPLIT6_Msk (0xfu << MATRIX_SASSR9_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR9) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR9_SASPLIT6(value) ((MATRIX_SASSR9_SASPLIT6_Msk & ((value) << MATRIX_SASSR9_SASPLIT6_Pos)))
+#define MATRIX_SASSR9_SASPLIT7_Pos 28
+#define MATRIX_SASSR9_SASPLIT7_Msk (0xfu << MATRIX_SASSR9_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR9) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR9_SASPLIT7(value) ((MATRIX_SASSR9_SASPLIT7_Msk & ((value) << MATRIX_SASSR9_SASPLIT7_Pos)))
+/* -------- MATRIX_SASSR10 : (MATRIX Offset: 0x0268) Security Areas Split Slave 10 Register -------- */
+#define MATRIX_SASSR10_SASPLIT0_Pos 0
+#define MATRIX_SASSR10_SASPLIT0_Msk (0xfu << MATRIX_SASSR10_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR10) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR10_SASPLIT0(value) ((MATRIX_SASSR10_SASPLIT0_Msk & ((value) << MATRIX_SASSR10_SASPLIT0_Pos)))
+#define MATRIX_SASSR10_SASPLIT1_Pos 4
+#define MATRIX_SASSR10_SASPLIT1_Msk (0xfu << MATRIX_SASSR10_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR10) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR10_SASPLIT1(value) ((MATRIX_SASSR10_SASPLIT1_Msk & ((value) << MATRIX_SASSR10_SASPLIT1_Pos)))
+#define MATRIX_SASSR10_SASPLIT2_Pos 8
+#define MATRIX_SASSR10_SASPLIT2_Msk (0xfu << MATRIX_SASSR10_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR10) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR10_SASPLIT2(value) ((MATRIX_SASSR10_SASPLIT2_Msk & ((value) << MATRIX_SASSR10_SASPLIT2_Pos)))
+#define MATRIX_SASSR10_SASPLIT3_Pos 12
+#define MATRIX_SASSR10_SASPLIT3_Msk (0xfu << MATRIX_SASSR10_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR10) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR10_SASPLIT3(value) ((MATRIX_SASSR10_SASPLIT3_Msk & ((value) << MATRIX_SASSR10_SASPLIT3_Pos)))
+#define MATRIX_SASSR10_SASPLIT4_Pos 16
+#define MATRIX_SASSR10_SASPLIT4_Msk (0xfu << MATRIX_SASSR10_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR10) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR10_SASPLIT4(value) ((MATRIX_SASSR10_SASPLIT4_Msk & ((value) << MATRIX_SASSR10_SASPLIT4_Pos)))
+#define MATRIX_SASSR10_SASPLIT5_Pos 20
+#define MATRIX_SASSR10_SASPLIT5_Msk (0xfu << MATRIX_SASSR10_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR10) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR10_SASPLIT5(value) ((MATRIX_SASSR10_SASPLIT5_Msk & ((value) << MATRIX_SASSR10_SASPLIT5_Pos)))
+#define MATRIX_SASSR10_SASPLIT6_Pos 24
+#define MATRIX_SASSR10_SASPLIT6_Msk (0xfu << MATRIX_SASSR10_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR10) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR10_SASPLIT6(value) ((MATRIX_SASSR10_SASPLIT6_Msk & ((value) << MATRIX_SASSR10_SASPLIT6_Pos)))
+#define MATRIX_SASSR10_SASPLIT7_Pos 28
+#define MATRIX_SASSR10_SASPLIT7_Msk (0xfu << MATRIX_SASSR10_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR10) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR10_SASPLIT7(value) ((MATRIX_SASSR10_SASPLIT7_Msk & ((value) << MATRIX_SASSR10_SASPLIT7_Pos)))
+/* -------- MATRIX_SASSR11 : (MATRIX Offset: 0x026C) Security Areas Split Slave 11 Register -------- */
+#define MATRIX_SASSR11_SASPLIT0_Pos 0
+#define MATRIX_SASSR11_SASPLIT0_Msk (0xfu << MATRIX_SASSR11_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR11) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR11_SASPLIT0(value) ((MATRIX_SASSR11_SASPLIT0_Msk & ((value) << MATRIX_SASSR11_SASPLIT0_Pos)))
+#define MATRIX_SASSR11_SASPLIT1_Pos 4
+#define MATRIX_SASSR11_SASPLIT1_Msk (0xfu << MATRIX_SASSR11_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR11) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR11_SASPLIT1(value) ((MATRIX_SASSR11_SASPLIT1_Msk & ((value) << MATRIX_SASSR11_SASPLIT1_Pos)))
+#define MATRIX_SASSR11_SASPLIT2_Pos 8
+#define MATRIX_SASSR11_SASPLIT2_Msk (0xfu << MATRIX_SASSR11_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR11) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR11_SASPLIT2(value) ((MATRIX_SASSR11_SASPLIT2_Msk & ((value) << MATRIX_SASSR11_SASPLIT2_Pos)))
+#define MATRIX_SASSR11_SASPLIT3_Pos 12
+#define MATRIX_SASSR11_SASPLIT3_Msk (0xfu << MATRIX_SASSR11_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR11) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR11_SASPLIT3(value) ((MATRIX_SASSR11_SASPLIT3_Msk & ((value) << MATRIX_SASSR11_SASPLIT3_Pos)))
+#define MATRIX_SASSR11_SASPLIT4_Pos 16
+#define MATRIX_SASSR11_SASPLIT4_Msk (0xfu << MATRIX_SASSR11_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR11) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR11_SASPLIT4(value) ((MATRIX_SASSR11_SASPLIT4_Msk & ((value) << MATRIX_SASSR11_SASPLIT4_Pos)))
+#define MATRIX_SASSR11_SASPLIT5_Pos 20
+#define MATRIX_SASSR11_SASPLIT5_Msk (0xfu << MATRIX_SASSR11_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR11) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR11_SASPLIT5(value) ((MATRIX_SASSR11_SASPLIT5_Msk & ((value) << MATRIX_SASSR11_SASPLIT5_Pos)))
+#define MATRIX_SASSR11_SASPLIT6_Pos 24
+#define MATRIX_SASSR11_SASPLIT6_Msk (0xfu << MATRIX_SASSR11_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR11) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR11_SASPLIT6(value) ((MATRIX_SASSR11_SASPLIT6_Msk & ((value) << MATRIX_SASSR11_SASPLIT6_Pos)))
+#define MATRIX_SASSR11_SASPLIT7_Pos 28
+#define MATRIX_SASSR11_SASPLIT7_Msk (0xfu << MATRIX_SASSR11_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR11) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR11_SASPLIT7(value) ((MATRIX_SASSR11_SASPLIT7_Msk & ((value) << MATRIX_SASSR11_SASPLIT7_Pos)))
+/* -------- MATRIX_SASSR12 : (MATRIX Offset: 0x0270) Security Areas Split Slave 12 Register -------- */
+#define MATRIX_SASSR12_SASPLIT0_Pos 0
+#define MATRIX_SASSR12_SASPLIT0_Msk (0xfu << MATRIX_SASSR12_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR12) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR12_SASPLIT0(value) ((MATRIX_SASSR12_SASPLIT0_Msk & ((value) << MATRIX_SASSR12_SASPLIT0_Pos)))
+#define MATRIX_SASSR12_SASPLIT1_Pos 4
+#define MATRIX_SASSR12_SASPLIT1_Msk (0xfu << MATRIX_SASSR12_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR12) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR12_SASPLIT1(value) ((MATRIX_SASSR12_SASPLIT1_Msk & ((value) << MATRIX_SASSR12_SASPLIT1_Pos)))
+#define MATRIX_SASSR12_SASPLIT2_Pos 8
+#define MATRIX_SASSR12_SASPLIT2_Msk (0xfu << MATRIX_SASSR12_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR12) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR12_SASPLIT2(value) ((MATRIX_SASSR12_SASPLIT2_Msk & ((value) << MATRIX_SASSR12_SASPLIT2_Pos)))
+#define MATRIX_SASSR12_SASPLIT3_Pos 12
+#define MATRIX_SASSR12_SASPLIT3_Msk (0xfu << MATRIX_SASSR12_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR12) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR12_SASPLIT3(value) ((MATRIX_SASSR12_SASPLIT3_Msk & ((value) << MATRIX_SASSR12_SASPLIT3_Pos)))
+#define MATRIX_SASSR12_SASPLIT4_Pos 16
+#define MATRIX_SASSR12_SASPLIT4_Msk (0xfu << MATRIX_SASSR12_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR12) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR12_SASPLIT4(value) ((MATRIX_SASSR12_SASPLIT4_Msk & ((value) << MATRIX_SASSR12_SASPLIT4_Pos)))
+#define MATRIX_SASSR12_SASPLIT5_Pos 20
+#define MATRIX_SASSR12_SASPLIT5_Msk (0xfu << MATRIX_SASSR12_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR12) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR12_SASPLIT5(value) ((MATRIX_SASSR12_SASPLIT5_Msk & ((value) << MATRIX_SASSR12_SASPLIT5_Pos)))
+#define MATRIX_SASSR12_SASPLIT6_Pos 24
+#define MATRIX_SASSR12_SASPLIT6_Msk (0xfu << MATRIX_SASSR12_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR12) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR12_SASPLIT6(value) ((MATRIX_SASSR12_SASPLIT6_Msk & ((value) << MATRIX_SASSR12_SASPLIT6_Pos)))
+#define MATRIX_SASSR12_SASPLIT7_Pos 28
+#define MATRIX_SASSR12_SASPLIT7_Msk (0xfu << MATRIX_SASSR12_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR12) Security Areas Split for HSELx Security Region */
+#define MATRIX_SASSR12_SASPLIT7(value) ((MATRIX_SASSR12_SASPLIT7_Msk & ((value) << MATRIX_SASSR12_SASPLIT7_Pos)))
+/* -------- MATRIX_SRTSR1 : (MATRIX Offset: 0x0284) Security Region Top Slave 1 Register -------- */
+#define MATRIX_SRTSR1_SRTOP0_Pos 0
+#define MATRIX_SRTSR1_SRTOP0_Msk (0xfu << MATRIX_SRTSR1_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR1) HSELx Security Region Top */
+#define MATRIX_SRTSR1_SRTOP0(value) ((MATRIX_SRTSR1_SRTOP0_Msk & ((value) << MATRIX_SRTSR1_SRTOP0_Pos)))
+#define MATRIX_SRTSR1_SRTOP1_Pos 4
+#define MATRIX_SRTSR1_SRTOP1_Msk (0xfu << MATRIX_SRTSR1_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR1) HSELx Security Region Top */
+#define MATRIX_SRTSR1_SRTOP1(value) ((MATRIX_SRTSR1_SRTOP1_Msk & ((value) << MATRIX_SRTSR1_SRTOP1_Pos)))
+#define MATRIX_SRTSR1_SRTOP2_Pos 8
+#define MATRIX_SRTSR1_SRTOP2_Msk (0xfu << MATRIX_SRTSR1_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR1) HSELx Security Region Top */
+#define MATRIX_SRTSR1_SRTOP2(value) ((MATRIX_SRTSR1_SRTOP2_Msk & ((value) << MATRIX_SRTSR1_SRTOP2_Pos)))
+#define MATRIX_SRTSR1_SRTOP3_Pos 12
+#define MATRIX_SRTSR1_SRTOP3_Msk (0xfu << MATRIX_SRTSR1_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR1) HSELx Security Region Top */
+#define MATRIX_SRTSR1_SRTOP3(value) ((MATRIX_SRTSR1_SRTOP3_Msk & ((value) << MATRIX_SRTSR1_SRTOP3_Pos)))
+#define MATRIX_SRTSR1_SRTOP4_Pos 16
+#define MATRIX_SRTSR1_SRTOP4_Msk (0xfu << MATRIX_SRTSR1_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR1) HSELx Security Region Top */
+#define MATRIX_SRTSR1_SRTOP4(value) ((MATRIX_SRTSR1_SRTOP4_Msk & ((value) << MATRIX_SRTSR1_SRTOP4_Pos)))
+#define MATRIX_SRTSR1_SRTOP5_Pos 20
+#define MATRIX_SRTSR1_SRTOP5_Msk (0xfu << MATRIX_SRTSR1_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR1) HSELx Security Region Top */
+#define MATRIX_SRTSR1_SRTOP5(value) ((MATRIX_SRTSR1_SRTOP5_Msk & ((value) << MATRIX_SRTSR1_SRTOP5_Pos)))
+#define MATRIX_SRTSR1_SRTOP6_Pos 24
+#define MATRIX_SRTSR1_SRTOP6_Msk (0xfu << MATRIX_SRTSR1_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR1) HSELx Security Region Top */
+#define MATRIX_SRTSR1_SRTOP6(value) ((MATRIX_SRTSR1_SRTOP6_Msk & ((value) << MATRIX_SRTSR1_SRTOP6_Pos)))
+#define MATRIX_SRTSR1_SRTOP7_Pos 28
+#define MATRIX_SRTSR1_SRTOP7_Msk (0xfu << MATRIX_SRTSR1_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR1) HSELx Security Region Top */
+#define MATRIX_SRTSR1_SRTOP7(value) ((MATRIX_SRTSR1_SRTOP7_Msk & ((value) << MATRIX_SRTSR1_SRTOP7_Pos)))
+/* -------- MATRIX_SRTSR2 : (MATRIX Offset: 0x0288) Security Region Top Slave 2 Register -------- */
+#define MATRIX_SRTSR2_SRTOP0_Pos 0
+#define MATRIX_SRTSR2_SRTOP0_Msk (0xfu << MATRIX_SRTSR2_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR2) HSELx Security Region Top */
+#define MATRIX_SRTSR2_SRTOP0(value) ((MATRIX_SRTSR2_SRTOP0_Msk & ((value) << MATRIX_SRTSR2_SRTOP0_Pos)))
+#define MATRIX_SRTSR2_SRTOP1_Pos 4
+#define MATRIX_SRTSR2_SRTOP1_Msk (0xfu << MATRIX_SRTSR2_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR2) HSELx Security Region Top */
+#define MATRIX_SRTSR2_SRTOP1(value) ((MATRIX_SRTSR2_SRTOP1_Msk & ((value) << MATRIX_SRTSR2_SRTOP1_Pos)))
+#define MATRIX_SRTSR2_SRTOP2_Pos 8
+#define MATRIX_SRTSR2_SRTOP2_Msk (0xfu << MATRIX_SRTSR2_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR2) HSELx Security Region Top */
+#define MATRIX_SRTSR2_SRTOP2(value) ((MATRIX_SRTSR2_SRTOP2_Msk & ((value) << MATRIX_SRTSR2_SRTOP2_Pos)))
+#define MATRIX_SRTSR2_SRTOP3_Pos 12
+#define MATRIX_SRTSR2_SRTOP3_Msk (0xfu << MATRIX_SRTSR2_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR2) HSELx Security Region Top */
+#define MATRIX_SRTSR2_SRTOP3(value) ((MATRIX_SRTSR2_SRTOP3_Msk & ((value) << MATRIX_SRTSR2_SRTOP3_Pos)))
+#define MATRIX_SRTSR2_SRTOP4_Pos 16
+#define MATRIX_SRTSR2_SRTOP4_Msk (0xfu << MATRIX_SRTSR2_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR2) HSELx Security Region Top */
+#define MATRIX_SRTSR2_SRTOP4(value) ((MATRIX_SRTSR2_SRTOP4_Msk & ((value) << MATRIX_SRTSR2_SRTOP4_Pos)))
+#define MATRIX_SRTSR2_SRTOP5_Pos 20
+#define MATRIX_SRTSR2_SRTOP5_Msk (0xfu << MATRIX_SRTSR2_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR2) HSELx Security Region Top */
+#define MATRIX_SRTSR2_SRTOP5(value) ((MATRIX_SRTSR2_SRTOP5_Msk & ((value) << MATRIX_SRTSR2_SRTOP5_Pos)))
+#define MATRIX_SRTSR2_SRTOP6_Pos 24
+#define MATRIX_SRTSR2_SRTOP6_Msk (0xfu << MATRIX_SRTSR2_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR2) HSELx Security Region Top */
+#define MATRIX_SRTSR2_SRTOP6(value) ((MATRIX_SRTSR2_SRTOP6_Msk & ((value) << MATRIX_SRTSR2_SRTOP6_Pos)))
+#define MATRIX_SRTSR2_SRTOP7_Pos 28
+#define MATRIX_SRTSR2_SRTOP7_Msk (0xfu << MATRIX_SRTSR2_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR2) HSELx Security Region Top */
+#define MATRIX_SRTSR2_SRTOP7(value) ((MATRIX_SRTSR2_SRTOP7_Msk & ((value) << MATRIX_SRTSR2_SRTOP7_Pos)))
+/* -------- MATRIX_SRTSR3 : (MATRIX Offset: 0x028C) Security Region Top Slave 3 Register -------- */
+#define MATRIX_SRTSR3_SRTOP0_Pos 0
+#define MATRIX_SRTSR3_SRTOP0_Msk (0xfu << MATRIX_SRTSR3_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR3) HSELx Security Region Top */
+#define MATRIX_SRTSR3_SRTOP0(value) ((MATRIX_SRTSR3_SRTOP0_Msk & ((value) << MATRIX_SRTSR3_SRTOP0_Pos)))
+#define MATRIX_SRTSR3_SRTOP1_Pos 4
+#define MATRIX_SRTSR3_SRTOP1_Msk (0xfu << MATRIX_SRTSR3_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR3) HSELx Security Region Top */
+#define MATRIX_SRTSR3_SRTOP1(value) ((MATRIX_SRTSR3_SRTOP1_Msk & ((value) << MATRIX_SRTSR3_SRTOP1_Pos)))
+#define MATRIX_SRTSR3_SRTOP2_Pos 8
+#define MATRIX_SRTSR3_SRTOP2_Msk (0xfu << MATRIX_SRTSR3_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR3) HSELx Security Region Top */
+#define MATRIX_SRTSR3_SRTOP2(value) ((MATRIX_SRTSR3_SRTOP2_Msk & ((value) << MATRIX_SRTSR3_SRTOP2_Pos)))
+#define MATRIX_SRTSR3_SRTOP3_Pos 12
+#define MATRIX_SRTSR3_SRTOP3_Msk (0xfu << MATRIX_SRTSR3_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR3) HSELx Security Region Top */
+#define MATRIX_SRTSR3_SRTOP3(value) ((MATRIX_SRTSR3_SRTOP3_Msk & ((value) << MATRIX_SRTSR3_SRTOP3_Pos)))
+#define MATRIX_SRTSR3_SRTOP4_Pos 16
+#define MATRIX_SRTSR3_SRTOP4_Msk (0xfu << MATRIX_SRTSR3_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR3) HSELx Security Region Top */
+#define MATRIX_SRTSR3_SRTOP4(value) ((MATRIX_SRTSR3_SRTOP4_Msk & ((value) << MATRIX_SRTSR3_SRTOP4_Pos)))
+#define MATRIX_SRTSR3_SRTOP5_Pos 20
+#define MATRIX_SRTSR3_SRTOP5_Msk (0xfu << MATRIX_SRTSR3_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR3) HSELx Security Region Top */
+#define MATRIX_SRTSR3_SRTOP5(value) ((MATRIX_SRTSR3_SRTOP5_Msk & ((value) << MATRIX_SRTSR3_SRTOP5_Pos)))
+#define MATRIX_SRTSR3_SRTOP6_Pos 24
+#define MATRIX_SRTSR3_SRTOP6_Msk (0xfu << MATRIX_SRTSR3_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR3) HSELx Security Region Top */
+#define MATRIX_SRTSR3_SRTOP6(value) ((MATRIX_SRTSR3_SRTOP6_Msk & ((value) << MATRIX_SRTSR3_SRTOP6_Pos)))
+#define MATRIX_SRTSR3_SRTOP7_Pos 28
+#define MATRIX_SRTSR3_SRTOP7_Msk (0xfu << MATRIX_SRTSR3_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR3) HSELx Security Region Top */
+#define MATRIX_SRTSR3_SRTOP7(value) ((MATRIX_SRTSR3_SRTOP7_Msk & ((value) << MATRIX_SRTSR3_SRTOP7_Pos)))
+/* -------- MATRIX_SRTSR4 : (MATRIX Offset: 0x0290) Security Region Top Slave 4 Register -------- */
+#define MATRIX_SRTSR4_SRTOP0_Pos 0
+#define MATRIX_SRTSR4_SRTOP0_Msk (0xfu << MATRIX_SRTSR4_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR4) HSELx Security Region Top */
+#define MATRIX_SRTSR4_SRTOP0(value) ((MATRIX_SRTSR4_SRTOP0_Msk & ((value) << MATRIX_SRTSR4_SRTOP0_Pos)))
+#define MATRIX_SRTSR4_SRTOP1_Pos 4
+#define MATRIX_SRTSR4_SRTOP1_Msk (0xfu << MATRIX_SRTSR4_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR4) HSELx Security Region Top */
+#define MATRIX_SRTSR4_SRTOP1(value) ((MATRIX_SRTSR4_SRTOP1_Msk & ((value) << MATRIX_SRTSR4_SRTOP1_Pos)))
+#define MATRIX_SRTSR4_SRTOP2_Pos 8
+#define MATRIX_SRTSR4_SRTOP2_Msk (0xfu << MATRIX_SRTSR4_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR4) HSELx Security Region Top */
+#define MATRIX_SRTSR4_SRTOP2(value) ((MATRIX_SRTSR4_SRTOP2_Msk & ((value) << MATRIX_SRTSR4_SRTOP2_Pos)))
+#define MATRIX_SRTSR4_SRTOP3_Pos 12
+#define MATRIX_SRTSR4_SRTOP3_Msk (0xfu << MATRIX_SRTSR4_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR4) HSELx Security Region Top */
+#define MATRIX_SRTSR4_SRTOP3(value) ((MATRIX_SRTSR4_SRTOP3_Msk & ((value) << MATRIX_SRTSR4_SRTOP3_Pos)))
+#define MATRIX_SRTSR4_SRTOP4_Pos 16
+#define MATRIX_SRTSR4_SRTOP4_Msk (0xfu << MATRIX_SRTSR4_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR4) HSELx Security Region Top */
+#define MATRIX_SRTSR4_SRTOP4(value) ((MATRIX_SRTSR4_SRTOP4_Msk & ((value) << MATRIX_SRTSR4_SRTOP4_Pos)))
+#define MATRIX_SRTSR4_SRTOP5_Pos 20
+#define MATRIX_SRTSR4_SRTOP5_Msk (0xfu << MATRIX_SRTSR4_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR4) HSELx Security Region Top */
+#define MATRIX_SRTSR4_SRTOP5(value) ((MATRIX_SRTSR4_SRTOP5_Msk & ((value) << MATRIX_SRTSR4_SRTOP5_Pos)))
+#define MATRIX_SRTSR4_SRTOP6_Pos 24
+#define MATRIX_SRTSR4_SRTOP6_Msk (0xfu << MATRIX_SRTSR4_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR4) HSELx Security Region Top */
+#define MATRIX_SRTSR4_SRTOP6(value) ((MATRIX_SRTSR4_SRTOP6_Msk & ((value) << MATRIX_SRTSR4_SRTOP6_Pos)))
+#define MATRIX_SRTSR4_SRTOP7_Pos 28
+#define MATRIX_SRTSR4_SRTOP7_Msk (0xfu << MATRIX_SRTSR4_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR4) HSELx Security Region Top */
+#define MATRIX_SRTSR4_SRTOP7(value) ((MATRIX_SRTSR4_SRTOP7_Msk & ((value) << MATRIX_SRTSR4_SRTOP7_Pos)))
+/* -------- MATRIX_SRTSR5 : (MATRIX Offset: 0x0294) Security Region Top Slave 5 Register -------- */
+#define MATRIX_SRTSR5_SRTOP0_Pos 0
+#define MATRIX_SRTSR5_SRTOP0_Msk (0xfu << MATRIX_SRTSR5_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR5) HSELx Security Region Top */
+#define MATRIX_SRTSR5_SRTOP0(value) ((MATRIX_SRTSR5_SRTOP0_Msk & ((value) << MATRIX_SRTSR5_SRTOP0_Pos)))
+#define MATRIX_SRTSR5_SRTOP1_Pos 4
+#define MATRIX_SRTSR5_SRTOP1_Msk (0xfu << MATRIX_SRTSR5_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR5) HSELx Security Region Top */
+#define MATRIX_SRTSR5_SRTOP1(value) ((MATRIX_SRTSR5_SRTOP1_Msk & ((value) << MATRIX_SRTSR5_SRTOP1_Pos)))
+#define MATRIX_SRTSR5_SRTOP2_Pos 8
+#define MATRIX_SRTSR5_SRTOP2_Msk (0xfu << MATRIX_SRTSR5_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR5) HSELx Security Region Top */
+#define MATRIX_SRTSR5_SRTOP2(value) ((MATRIX_SRTSR5_SRTOP2_Msk & ((value) << MATRIX_SRTSR5_SRTOP2_Pos)))
+#define MATRIX_SRTSR5_SRTOP3_Pos 12
+#define MATRIX_SRTSR5_SRTOP3_Msk (0xfu << MATRIX_SRTSR5_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR5) HSELx Security Region Top */
+#define MATRIX_SRTSR5_SRTOP3(value) ((MATRIX_SRTSR5_SRTOP3_Msk & ((value) << MATRIX_SRTSR5_SRTOP3_Pos)))
+#define MATRIX_SRTSR5_SRTOP4_Pos 16
+#define MATRIX_SRTSR5_SRTOP4_Msk (0xfu << MATRIX_SRTSR5_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR5) HSELx Security Region Top */
+#define MATRIX_SRTSR5_SRTOP4(value) ((MATRIX_SRTSR5_SRTOP4_Msk & ((value) << MATRIX_SRTSR5_SRTOP4_Pos)))
+#define MATRIX_SRTSR5_SRTOP5_Pos 20
+#define MATRIX_SRTSR5_SRTOP5_Msk (0xfu << MATRIX_SRTSR5_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR5) HSELx Security Region Top */
+#define MATRIX_SRTSR5_SRTOP5(value) ((MATRIX_SRTSR5_SRTOP5_Msk & ((value) << MATRIX_SRTSR5_SRTOP5_Pos)))
+#define MATRIX_SRTSR5_SRTOP6_Pos 24
+#define MATRIX_SRTSR5_SRTOP6_Msk (0xfu << MATRIX_SRTSR5_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR5) HSELx Security Region Top */
+#define MATRIX_SRTSR5_SRTOP6(value) ((MATRIX_SRTSR5_SRTOP6_Msk & ((value) << MATRIX_SRTSR5_SRTOP6_Pos)))
+#define MATRIX_SRTSR5_SRTOP7_Pos 28
+#define MATRIX_SRTSR5_SRTOP7_Msk (0xfu << MATRIX_SRTSR5_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR5) HSELx Security Region Top */
+#define MATRIX_SRTSR5_SRTOP7(value) ((MATRIX_SRTSR5_SRTOP7_Msk & ((value) << MATRIX_SRTSR5_SRTOP7_Pos)))
+/* -------- MATRIX_SRTSR6 : (MATRIX Offset: 0x0298) Security Region Top Slave 6 Register -------- */
+#define MATRIX_SRTSR6_SRTOP0_Pos 0
+#define MATRIX_SRTSR6_SRTOP0_Msk (0xfu << MATRIX_SRTSR6_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR6) HSELx Security Region Top */
+#define MATRIX_SRTSR6_SRTOP0(value) ((MATRIX_SRTSR6_SRTOP0_Msk & ((value) << MATRIX_SRTSR6_SRTOP0_Pos)))
+#define MATRIX_SRTSR6_SRTOP1_Pos 4
+#define MATRIX_SRTSR6_SRTOP1_Msk (0xfu << MATRIX_SRTSR6_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR6) HSELx Security Region Top */
+#define MATRIX_SRTSR6_SRTOP1(value) ((MATRIX_SRTSR6_SRTOP1_Msk & ((value) << MATRIX_SRTSR6_SRTOP1_Pos)))
+#define MATRIX_SRTSR6_SRTOP2_Pos 8
+#define MATRIX_SRTSR6_SRTOP2_Msk (0xfu << MATRIX_SRTSR6_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR6) HSELx Security Region Top */
+#define MATRIX_SRTSR6_SRTOP2(value) ((MATRIX_SRTSR6_SRTOP2_Msk & ((value) << MATRIX_SRTSR6_SRTOP2_Pos)))
+#define MATRIX_SRTSR6_SRTOP3_Pos 12
+#define MATRIX_SRTSR6_SRTOP3_Msk (0xfu << MATRIX_SRTSR6_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR6) HSELx Security Region Top */
+#define MATRIX_SRTSR6_SRTOP3(value) ((MATRIX_SRTSR6_SRTOP3_Msk & ((value) << MATRIX_SRTSR6_SRTOP3_Pos)))
+#define MATRIX_SRTSR6_SRTOP4_Pos 16
+#define MATRIX_SRTSR6_SRTOP4_Msk (0xfu << MATRIX_SRTSR6_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR6) HSELx Security Region Top */
+#define MATRIX_SRTSR6_SRTOP4(value) ((MATRIX_SRTSR6_SRTOP4_Msk & ((value) << MATRIX_SRTSR6_SRTOP4_Pos)))
+#define MATRIX_SRTSR6_SRTOP5_Pos 20
+#define MATRIX_SRTSR6_SRTOP5_Msk (0xfu << MATRIX_SRTSR6_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR6) HSELx Security Region Top */
+#define MATRIX_SRTSR6_SRTOP5(value) ((MATRIX_SRTSR6_SRTOP5_Msk & ((value) << MATRIX_SRTSR6_SRTOP5_Pos)))
+#define MATRIX_SRTSR6_SRTOP6_Pos 24
+#define MATRIX_SRTSR6_SRTOP6_Msk (0xfu << MATRIX_SRTSR6_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR6) HSELx Security Region Top */
+#define MATRIX_SRTSR6_SRTOP6(value) ((MATRIX_SRTSR6_SRTOP6_Msk & ((value) << MATRIX_SRTSR6_SRTOP6_Pos)))
+#define MATRIX_SRTSR6_SRTOP7_Pos 28
+#define MATRIX_SRTSR6_SRTOP7_Msk (0xfu << MATRIX_SRTSR6_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR6) HSELx Security Region Top */
+#define MATRIX_SRTSR6_SRTOP7(value) ((MATRIX_SRTSR6_SRTOP7_Msk & ((value) << MATRIX_SRTSR6_SRTOP7_Pos)))
+/* -------- MATRIX_SRTSR7 : (MATRIX Offset: 0x029C) Security Region Top Slave 7 Register -------- */
+#define MATRIX_SRTSR7_SRTOP0_Pos 0
+#define MATRIX_SRTSR7_SRTOP0_Msk (0xfu << MATRIX_SRTSR7_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR7) HSELx Security Region Top */
+#define MATRIX_SRTSR7_SRTOP0(value) ((MATRIX_SRTSR7_SRTOP0_Msk & ((value) << MATRIX_SRTSR7_SRTOP0_Pos)))
+#define MATRIX_SRTSR7_SRTOP1_Pos 4
+#define MATRIX_SRTSR7_SRTOP1_Msk (0xfu << MATRIX_SRTSR7_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR7) HSELx Security Region Top */
+#define MATRIX_SRTSR7_SRTOP1(value) ((MATRIX_SRTSR7_SRTOP1_Msk & ((value) << MATRIX_SRTSR7_SRTOP1_Pos)))
+#define MATRIX_SRTSR7_SRTOP2_Pos 8
+#define MATRIX_SRTSR7_SRTOP2_Msk (0xfu << MATRIX_SRTSR7_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR7) HSELx Security Region Top */
+#define MATRIX_SRTSR7_SRTOP2(value) ((MATRIX_SRTSR7_SRTOP2_Msk & ((value) << MATRIX_SRTSR7_SRTOP2_Pos)))
+#define MATRIX_SRTSR7_SRTOP3_Pos 12
+#define MATRIX_SRTSR7_SRTOP3_Msk (0xfu << MATRIX_SRTSR7_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR7) HSELx Security Region Top */
+#define MATRIX_SRTSR7_SRTOP3(value) ((MATRIX_SRTSR7_SRTOP3_Msk & ((value) << MATRIX_SRTSR7_SRTOP3_Pos)))
+#define MATRIX_SRTSR7_SRTOP4_Pos 16
+#define MATRIX_SRTSR7_SRTOP4_Msk (0xfu << MATRIX_SRTSR7_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR7) HSELx Security Region Top */
+#define MATRIX_SRTSR7_SRTOP4(value) ((MATRIX_SRTSR7_SRTOP4_Msk & ((value) << MATRIX_SRTSR7_SRTOP4_Pos)))
+#define MATRIX_SRTSR7_SRTOP5_Pos 20
+#define MATRIX_SRTSR7_SRTOP5_Msk (0xfu << MATRIX_SRTSR7_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR7) HSELx Security Region Top */
+#define MATRIX_SRTSR7_SRTOP5(value) ((MATRIX_SRTSR7_SRTOP5_Msk & ((value) << MATRIX_SRTSR7_SRTOP5_Pos)))
+#define MATRIX_SRTSR7_SRTOP6_Pos 24
+#define MATRIX_SRTSR7_SRTOP6_Msk (0xfu << MATRIX_SRTSR7_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR7) HSELx Security Region Top */
+#define MATRIX_SRTSR7_SRTOP6(value) ((MATRIX_SRTSR7_SRTOP6_Msk & ((value) << MATRIX_SRTSR7_SRTOP6_Pos)))
+#define MATRIX_SRTSR7_SRTOP7_Pos 28
+#define MATRIX_SRTSR7_SRTOP7_Msk (0xfu << MATRIX_SRTSR7_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR7) HSELx Security Region Top */
+#define MATRIX_SRTSR7_SRTOP7(value) ((MATRIX_SRTSR7_SRTOP7_Msk & ((value) << MATRIX_SRTSR7_SRTOP7_Pos)))
+/* -------- MATRIX_SRTSR8 : (MATRIX Offset: 0x02A0) Security Region Top Slave 8 Register -------- */
+#define MATRIX_SRTSR8_SRTOP0_Pos 0
+#define MATRIX_SRTSR8_SRTOP0_Msk (0xfu << MATRIX_SRTSR8_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR8) HSELx Security Region Top */
+#define MATRIX_SRTSR8_SRTOP0(value) ((MATRIX_SRTSR8_SRTOP0_Msk & ((value) << MATRIX_SRTSR8_SRTOP0_Pos)))
+#define MATRIX_SRTSR8_SRTOP1_Pos 4
+#define MATRIX_SRTSR8_SRTOP1_Msk (0xfu << MATRIX_SRTSR8_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR8) HSELx Security Region Top */
+#define MATRIX_SRTSR8_SRTOP1(value) ((MATRIX_SRTSR8_SRTOP1_Msk & ((value) << MATRIX_SRTSR8_SRTOP1_Pos)))
+#define MATRIX_SRTSR8_SRTOP2_Pos 8
+#define MATRIX_SRTSR8_SRTOP2_Msk (0xfu << MATRIX_SRTSR8_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR8) HSELx Security Region Top */
+#define MATRIX_SRTSR8_SRTOP2(value) ((MATRIX_SRTSR8_SRTOP2_Msk & ((value) << MATRIX_SRTSR8_SRTOP2_Pos)))
+#define MATRIX_SRTSR8_SRTOP3_Pos 12
+#define MATRIX_SRTSR8_SRTOP3_Msk (0xfu << MATRIX_SRTSR8_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR8) HSELx Security Region Top */
+#define MATRIX_SRTSR8_SRTOP3(value) ((MATRIX_SRTSR8_SRTOP3_Msk & ((value) << MATRIX_SRTSR8_SRTOP3_Pos)))
+#define MATRIX_SRTSR8_SRTOP4_Pos 16
+#define MATRIX_SRTSR8_SRTOP4_Msk (0xfu << MATRIX_SRTSR8_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR8) HSELx Security Region Top */
+#define MATRIX_SRTSR8_SRTOP4(value) ((MATRIX_SRTSR8_SRTOP4_Msk & ((value) << MATRIX_SRTSR8_SRTOP4_Pos)))
+#define MATRIX_SRTSR8_SRTOP5_Pos 20
+#define MATRIX_SRTSR8_SRTOP5_Msk (0xfu << MATRIX_SRTSR8_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR8) HSELx Security Region Top */
+#define MATRIX_SRTSR8_SRTOP5(value) ((MATRIX_SRTSR8_SRTOP5_Msk & ((value) << MATRIX_SRTSR8_SRTOP5_Pos)))
+#define MATRIX_SRTSR8_SRTOP6_Pos 24
+#define MATRIX_SRTSR8_SRTOP6_Msk (0xfu << MATRIX_SRTSR8_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR8) HSELx Security Region Top */
+#define MATRIX_SRTSR8_SRTOP6(value) ((MATRIX_SRTSR8_SRTOP6_Msk & ((value) << MATRIX_SRTSR8_SRTOP6_Pos)))
+#define MATRIX_SRTSR8_SRTOP7_Pos 28
+#define MATRIX_SRTSR8_SRTOP7_Msk (0xfu << MATRIX_SRTSR8_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR8) HSELx Security Region Top */
+#define MATRIX_SRTSR8_SRTOP7(value) ((MATRIX_SRTSR8_SRTOP7_Msk & ((value) << MATRIX_SRTSR8_SRTOP7_Pos)))
+/* -------- MATRIX_SRTSR9 : (MATRIX Offset: 0x02A4) Security Region Top Slave 9 Register -------- */
+#define MATRIX_SRTSR9_SRTOP0_Pos 0
+#define MATRIX_SRTSR9_SRTOP0_Msk (0xfu << MATRIX_SRTSR9_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR9) HSELx Security Region Top */
+#define MATRIX_SRTSR9_SRTOP0(value) ((MATRIX_SRTSR9_SRTOP0_Msk & ((value) << MATRIX_SRTSR9_SRTOP0_Pos)))
+#define MATRIX_SRTSR9_SRTOP1_Pos 4
+#define MATRIX_SRTSR9_SRTOP1_Msk (0xfu << MATRIX_SRTSR9_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR9) HSELx Security Region Top */
+#define MATRIX_SRTSR9_SRTOP1(value) ((MATRIX_SRTSR9_SRTOP1_Msk & ((value) << MATRIX_SRTSR9_SRTOP1_Pos)))
+#define MATRIX_SRTSR9_SRTOP2_Pos 8
+#define MATRIX_SRTSR9_SRTOP2_Msk (0xfu << MATRIX_SRTSR9_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR9) HSELx Security Region Top */
+#define MATRIX_SRTSR9_SRTOP2(value) ((MATRIX_SRTSR9_SRTOP2_Msk & ((value) << MATRIX_SRTSR9_SRTOP2_Pos)))
+#define MATRIX_SRTSR9_SRTOP3_Pos 12
+#define MATRIX_SRTSR9_SRTOP3_Msk (0xfu << MATRIX_SRTSR9_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR9) HSELx Security Region Top */
+#define MATRIX_SRTSR9_SRTOP3(value) ((MATRIX_SRTSR9_SRTOP3_Msk & ((value) << MATRIX_SRTSR9_SRTOP3_Pos)))
+#define MATRIX_SRTSR9_SRTOP4_Pos 16
+#define MATRIX_SRTSR9_SRTOP4_Msk (0xfu << MATRIX_SRTSR9_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR9) HSELx Security Region Top */
+#define MATRIX_SRTSR9_SRTOP4(value) ((MATRIX_SRTSR9_SRTOP4_Msk & ((value) << MATRIX_SRTSR9_SRTOP4_Pos)))
+#define MATRIX_SRTSR9_SRTOP5_Pos 20
+#define MATRIX_SRTSR9_SRTOP5_Msk (0xfu << MATRIX_SRTSR9_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR9) HSELx Security Region Top */
+#define MATRIX_SRTSR9_SRTOP5(value) ((MATRIX_SRTSR9_SRTOP5_Msk & ((value) << MATRIX_SRTSR9_SRTOP5_Pos)))
+#define MATRIX_SRTSR9_SRTOP6_Pos 24
+#define MATRIX_SRTSR9_SRTOP6_Msk (0xfu << MATRIX_SRTSR9_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR9) HSELx Security Region Top */
+#define MATRIX_SRTSR9_SRTOP6(value) ((MATRIX_SRTSR9_SRTOP6_Msk & ((value) << MATRIX_SRTSR9_SRTOP6_Pos)))
+#define MATRIX_SRTSR9_SRTOP7_Pos 28
+#define MATRIX_SRTSR9_SRTOP7_Msk (0xfu << MATRIX_SRTSR9_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR9) HSELx Security Region Top */
+#define MATRIX_SRTSR9_SRTOP7(value) ((MATRIX_SRTSR9_SRTOP7_Msk & ((value) << MATRIX_SRTSR9_SRTOP7_Pos)))
+/* -------- MATRIX_SRTSR10 : (MATRIX Offset: 0x02A8) Security Region Top Slave 10 Register -------- */
+#define MATRIX_SRTSR10_SRTOP0_Pos 0
+#define MATRIX_SRTSR10_SRTOP0_Msk (0xfu << MATRIX_SRTSR10_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR10) HSELx Security Region Top */
+#define MATRIX_SRTSR10_SRTOP0(value) ((MATRIX_SRTSR10_SRTOP0_Msk & ((value) << MATRIX_SRTSR10_SRTOP0_Pos)))
+#define MATRIX_SRTSR10_SRTOP1_Pos 4
+#define MATRIX_SRTSR10_SRTOP1_Msk (0xfu << MATRIX_SRTSR10_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR10) HSELx Security Region Top */
+#define MATRIX_SRTSR10_SRTOP1(value) ((MATRIX_SRTSR10_SRTOP1_Msk & ((value) << MATRIX_SRTSR10_SRTOP1_Pos)))
+#define MATRIX_SRTSR10_SRTOP2_Pos 8
+#define MATRIX_SRTSR10_SRTOP2_Msk (0xfu << MATRIX_SRTSR10_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR10) HSELx Security Region Top */
+#define MATRIX_SRTSR10_SRTOP2(value) ((MATRIX_SRTSR10_SRTOP2_Msk & ((value) << MATRIX_SRTSR10_SRTOP2_Pos)))
+#define MATRIX_SRTSR10_SRTOP3_Pos 12
+#define MATRIX_SRTSR10_SRTOP3_Msk (0xfu << MATRIX_SRTSR10_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR10) HSELx Security Region Top */
+#define MATRIX_SRTSR10_SRTOP3(value) ((MATRIX_SRTSR10_SRTOP3_Msk & ((value) << MATRIX_SRTSR10_SRTOP3_Pos)))
+#define MATRIX_SRTSR10_SRTOP4_Pos 16
+#define MATRIX_SRTSR10_SRTOP4_Msk (0xfu << MATRIX_SRTSR10_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR10) HSELx Security Region Top */
+#define MATRIX_SRTSR10_SRTOP4(value) ((MATRIX_SRTSR10_SRTOP4_Msk & ((value) << MATRIX_SRTSR10_SRTOP4_Pos)))
+#define MATRIX_SRTSR10_SRTOP5_Pos 20
+#define MATRIX_SRTSR10_SRTOP5_Msk (0xfu << MATRIX_SRTSR10_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR10) HSELx Security Region Top */
+#define MATRIX_SRTSR10_SRTOP5(value) ((MATRIX_SRTSR10_SRTOP5_Msk & ((value) << MATRIX_SRTSR10_SRTOP5_Pos)))
+#define MATRIX_SRTSR10_SRTOP6_Pos 24
+#define MATRIX_SRTSR10_SRTOP6_Msk (0xfu << MATRIX_SRTSR10_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR10) HSELx Security Region Top */
+#define MATRIX_SRTSR10_SRTOP6(value) ((MATRIX_SRTSR10_SRTOP6_Msk & ((value) << MATRIX_SRTSR10_SRTOP6_Pos)))
+#define MATRIX_SRTSR10_SRTOP7_Pos 28
+#define MATRIX_SRTSR10_SRTOP7_Msk (0xfu << MATRIX_SRTSR10_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR10) HSELx Security Region Top */
+#define MATRIX_SRTSR10_SRTOP7(value) ((MATRIX_SRTSR10_SRTOP7_Msk & ((value) << MATRIX_SRTSR10_SRTOP7_Pos)))
+/* -------- MATRIX_SRTSR11 : (MATRIX Offset: 0x02AC) Security Region Top Slave 11 Register -------- */
+#define MATRIX_SRTSR11_SRTOP0_Pos 0
+#define MATRIX_SRTSR11_SRTOP0_Msk (0xfu << MATRIX_SRTSR11_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR11) HSELx Security Region Top */
+#define MATRIX_SRTSR11_SRTOP0(value) ((MATRIX_SRTSR11_SRTOP0_Msk & ((value) << MATRIX_SRTSR11_SRTOP0_Pos)))
+#define MATRIX_SRTSR11_SRTOP1_Pos 4
+#define MATRIX_SRTSR11_SRTOP1_Msk (0xfu << MATRIX_SRTSR11_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR11) HSELx Security Region Top */
+#define MATRIX_SRTSR11_SRTOP1(value) ((MATRIX_SRTSR11_SRTOP1_Msk & ((value) << MATRIX_SRTSR11_SRTOP1_Pos)))
+#define MATRIX_SRTSR11_SRTOP2_Pos 8
+#define MATRIX_SRTSR11_SRTOP2_Msk (0xfu << MATRIX_SRTSR11_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR11) HSELx Security Region Top */
+#define MATRIX_SRTSR11_SRTOP2(value) ((MATRIX_SRTSR11_SRTOP2_Msk & ((value) << MATRIX_SRTSR11_SRTOP2_Pos)))
+#define MATRIX_SRTSR11_SRTOP3_Pos 12
+#define MATRIX_SRTSR11_SRTOP3_Msk (0xfu << MATRIX_SRTSR11_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR11) HSELx Security Region Top */
+#define MATRIX_SRTSR11_SRTOP3(value) ((MATRIX_SRTSR11_SRTOP3_Msk & ((value) << MATRIX_SRTSR11_SRTOP3_Pos)))
+#define MATRIX_SRTSR11_SRTOP4_Pos 16
+#define MATRIX_SRTSR11_SRTOP4_Msk (0xfu << MATRIX_SRTSR11_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR11) HSELx Security Region Top */
+#define MATRIX_SRTSR11_SRTOP4(value) ((MATRIX_SRTSR11_SRTOP4_Msk & ((value) << MATRIX_SRTSR11_SRTOP4_Pos)))
+#define MATRIX_SRTSR11_SRTOP5_Pos 20
+#define MATRIX_SRTSR11_SRTOP5_Msk (0xfu << MATRIX_SRTSR11_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR11) HSELx Security Region Top */
+#define MATRIX_SRTSR11_SRTOP5(value) ((MATRIX_SRTSR11_SRTOP5_Msk & ((value) << MATRIX_SRTSR11_SRTOP5_Pos)))
+#define MATRIX_SRTSR11_SRTOP6_Pos 24
+#define MATRIX_SRTSR11_SRTOP6_Msk (0xfu << MATRIX_SRTSR11_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR11) HSELx Security Region Top */
+#define MATRIX_SRTSR11_SRTOP6(value) ((MATRIX_SRTSR11_SRTOP6_Msk & ((value) << MATRIX_SRTSR11_SRTOP6_Pos)))
+#define MATRIX_SRTSR11_SRTOP7_Pos 28
+#define MATRIX_SRTSR11_SRTOP7_Msk (0xfu << MATRIX_SRTSR11_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR11) HSELx Security Region Top */
+#define MATRIX_SRTSR11_SRTOP7(value) ((MATRIX_SRTSR11_SRTOP7_Msk & ((value) << MATRIX_SRTSR11_SRTOP7_Pos)))
+/* -------- MATRIX_SRTSR12 : (MATRIX Offset: 0x02B0) Security Region Top Slave 12 Register -------- */
+#define MATRIX_SRTSR12_SRTOP0_Pos 0
+#define MATRIX_SRTSR12_SRTOP0_Msk (0xfu << MATRIX_SRTSR12_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR12) HSELx Security Region Top */
+#define MATRIX_SRTSR12_SRTOP0(value) ((MATRIX_SRTSR12_SRTOP0_Msk & ((value) << MATRIX_SRTSR12_SRTOP0_Pos)))
+#define MATRIX_SRTSR12_SRTOP1_Pos 4
+#define MATRIX_SRTSR12_SRTOP1_Msk (0xfu << MATRIX_SRTSR12_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR12) HSELx Security Region Top */
+#define MATRIX_SRTSR12_SRTOP1(value) ((MATRIX_SRTSR12_SRTOP1_Msk & ((value) << MATRIX_SRTSR12_SRTOP1_Pos)))
+#define MATRIX_SRTSR12_SRTOP2_Pos 8
+#define MATRIX_SRTSR12_SRTOP2_Msk (0xfu << MATRIX_SRTSR12_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR12) HSELx Security Region Top */
+#define MATRIX_SRTSR12_SRTOP2(value) ((MATRIX_SRTSR12_SRTOP2_Msk & ((value) << MATRIX_SRTSR12_SRTOP2_Pos)))
+#define MATRIX_SRTSR12_SRTOP3_Pos 12
+#define MATRIX_SRTSR12_SRTOP3_Msk (0xfu << MATRIX_SRTSR12_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR12) HSELx Security Region Top */
+#define MATRIX_SRTSR12_SRTOP3(value) ((MATRIX_SRTSR12_SRTOP3_Msk & ((value) << MATRIX_SRTSR12_SRTOP3_Pos)))
+#define MATRIX_SRTSR12_SRTOP4_Pos 16
+#define MATRIX_SRTSR12_SRTOP4_Msk (0xfu << MATRIX_SRTSR12_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR12) HSELx Security Region Top */
+#define MATRIX_SRTSR12_SRTOP4(value) ((MATRIX_SRTSR12_SRTOP4_Msk & ((value) << MATRIX_SRTSR12_SRTOP4_Pos)))
+#define MATRIX_SRTSR12_SRTOP5_Pos 20
+#define MATRIX_SRTSR12_SRTOP5_Msk (0xfu << MATRIX_SRTSR12_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR12) HSELx Security Region Top */
+#define MATRIX_SRTSR12_SRTOP5(value) ((MATRIX_SRTSR12_SRTOP5_Msk & ((value) << MATRIX_SRTSR12_SRTOP5_Pos)))
+#define MATRIX_SRTSR12_SRTOP6_Pos 24
+#define MATRIX_SRTSR12_SRTOP6_Msk (0xfu << MATRIX_SRTSR12_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR12) HSELx Security Region Top */
+#define MATRIX_SRTSR12_SRTOP6(value) ((MATRIX_SRTSR12_SRTOP6_Msk & ((value) << MATRIX_SRTSR12_SRTOP6_Pos)))
+#define MATRIX_SRTSR12_SRTOP7_Pos 28
+#define MATRIX_SRTSR12_SRTOP7_Msk (0xfu << MATRIX_SRTSR12_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR12) HSELx Security Region Top */
+#define MATRIX_SRTSR12_SRTOP7(value) ((MATRIX_SRTSR12_SRTOP7_Msk & ((value) << MATRIX_SRTSR12_SRTOP7_Pos)))
+/* -------- MATRIX_SPSELR[3] : (MATRIX Offset: 0x02C0) Security Peripheral Select 1 Register -------- */
+#define MATRIX_SPSELR_NSECP0 (0x1u << 0) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP1 (0x1u << 1) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP2 (0x1u << 2) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP3 (0x1u << 3) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP4 (0x1u << 4) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP5 (0x1u << 5) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP6 (0x1u << 6) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP7 (0x1u << 7) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP8 (0x1u << 8) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP9 (0x1u << 9) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP10 (0x1u << 10) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP11 (0x1u << 11) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP12 (0x1u << 12) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP13 (0x1u << 13) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP14 (0x1u << 14) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP15 (0x1u << 15) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP16 (0x1u << 16) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP17 (0x1u << 17) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP18 (0x1u << 18) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP19 (0x1u << 19) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP20 (0x1u << 20) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP21 (0x1u << 21) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP22 (0x1u << 22) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP23 (0x1u << 23) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP24 (0x1u << 24) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP25 (0x1u << 25) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP26 (0x1u << 26) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP27 (0x1u << 27) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP28 (0x1u << 28) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP29 (0x1u << 29) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP30 (0x1u << 30) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+#define MATRIX_SPSELR_NSECP31 (0x1u << 31) /**< \brief (MATRIX_SPSELR[3]) Non-secured Peripheral */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_MATRIX_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_mcan.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_mcan.h
new file mode 100644
index 000000000..05ab5c078
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_mcan.h
@@ -0,0 +1,961 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_MCAN_COMPONENT_
+#define _SAMA5D2_MCAN_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Controller Area Network */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_MCAN Controller Area Network */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Mcan hardware registers */
+typedef struct {
+  __I  uint32_t MCAN_CREL;    /**< \brief (Mcan Offset: 0x00) Core Release Register */
+  __I  uint32_t MCAN_ENDN;    /**< \brief (Mcan Offset: 0x04) Endian Register */
+  __IO uint32_t MCAN_CUST;    /**< \brief (Mcan Offset: 0x08) Customer Register */
+  __IO uint32_t MCAN_DBTP;    /**< \brief (Mcan Offset: 0x0C) Fast Bit Timing and Prescaler Register */
+  __IO uint32_t MCAN_TEST;    /**< \brief (Mcan Offset: 0x10) Test Register */
+  __IO uint32_t MCAN_RWD;     /**< \brief (Mcan Offset: 0x14) RAM Watchdog Register */
+  __IO uint32_t MCAN_CCCR;    /**< \brief (Mcan Offset: 0x18) CC Control Register */
+  __IO uint32_t MCAN_NBTP;    /**< \brief (Mcan Offset: 0x1C) Bit Timing and Prescaler Register */
+  __IO uint32_t MCAN_TSCC;    /**< \brief (Mcan Offset: 0x20) Timestamp Counter Configuration Register */
+  __IO uint32_t MCAN_TSCV;    /**< \brief (Mcan Offset: 0x24) Timestamp Counter Value Register */
+  __IO uint32_t MCAN_TOCC;    /**< \brief (Mcan Offset: 0x28) Timeout Counter Configuration Register */
+  __IO uint32_t MCAN_TOCV;    /**< \brief (Mcan Offset: 0x2C) Timeout Counter Value Register */
+  __I  uint32_t Reserved1[4];
+  __I  uint32_t MCAN_ECR;     /**< \brief (Mcan Offset: 0x40) Error Counter Register */
+  __I  uint32_t MCAN_PSR;     /**< \brief (Mcan Offset: 0x44) Protocol Status Register */
+  __IO uint32_t MCAN_TDCR;    /**< \brief (Mcan Offset: 0x48) Transmit Delay Compensation Register */
+  __I  uint32_t Reserved2[1];
+  __IO uint32_t MCAN_IR;      /**< \brief (Mcan Offset: 0x50) Interrupt Register */
+  __IO uint32_t MCAN_IE;      /**< \brief (Mcan Offset: 0x54) Interrupt Enable Register */
+  __IO uint32_t MCAN_ILS;     /**< \brief (Mcan Offset: 0x58) Interrupt Line Select Register */
+  __IO uint32_t MCAN_ILE;     /**< \brief (Mcan Offset: 0x5C) Interrupt Line Enable Register */
+  __I  uint32_t Reserved3[8];
+  __IO uint32_t MCAN_GFC;     /**< \brief (Mcan Offset: 0x80) Global Filter Configuration Register */
+  __IO uint32_t MCAN_SIDFC;   /**< \brief (Mcan Offset: 0x84) Standard ID Filter Configuration Register */
+  __IO uint32_t MCAN_XIDFC;   /**< \brief (Mcan Offset: 0x88) Extended ID Filter Configuration Register */
+  __I  uint32_t Reserved4[1];
+  __IO uint32_t MCAN_XIDAM;   /**< \brief (Mcan Offset: 0x90) Extended ID AND Mask Register */
+  __I  uint32_t MCAN_HPMS;    /**< \brief (Mcan Offset: 0x94) High Priority Message Status Register */
+  __IO uint32_t MCAN_NDAT1;   /**< \brief (Mcan Offset: 0x98) New Data 1 Register */
+  __IO uint32_t MCAN_NDAT2;   /**< \brief (Mcan Offset: 0x9C) New Data 2 Register */
+  __IO uint32_t MCAN_RXF0C;   /**< \brief (Mcan Offset: 0xA0) Receive FIFO 0 Configuration Register */
+  __I  uint32_t MCAN_RXF0S;   /**< \brief (Mcan Offset: 0xA4) Receive FIFO 0 Status Register */
+  __IO uint32_t MCAN_RXF0A;   /**< \brief (Mcan Offset: 0xA8) Receive FIFO 0 Acknowledge Register */
+  __IO uint32_t MCAN_RXBC;    /**< \brief (Mcan Offset: 0xAC) Receive Rx Buffer Configuration Register */
+  __IO uint32_t MCAN_RXF1C;   /**< \brief (Mcan Offset: 0xB0) Receive FIFO 1 Configuration Register */
+  __I  uint32_t MCAN_RXF1S;   /**< \brief (Mcan Offset: 0xB4) Receive FIFO 1 Status Register */
+  __IO uint32_t MCAN_RXF1A;   /**< \brief (Mcan Offset: 0xB8) Receive FIFO 1 Acknowledge Register */
+  __IO uint32_t MCAN_RXESC;   /**< \brief (Mcan Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register */
+  __IO uint32_t MCAN_TXBC;    /**< \brief (Mcan Offset: 0xC0) Transmit Buffer Configuration Register */
+  __I  uint32_t MCAN_TXFQS;   /**< \brief (Mcan Offset: 0xC4) Transmit FIFO/Queue Status Register */
+  __IO uint32_t MCAN_TXESC;   /**< \brief (Mcan Offset: 0xC8) Transmit Buffer Element Size Configuration Register */
+  __I  uint32_t MCAN_TXBRP;   /**< \brief (Mcan Offset: 0xCC) Transmit Buffer Request Pending Register */
+  __IO uint32_t MCAN_TXBAR;   /**< \brief (Mcan Offset: 0xD0) Transmit Buffer Add Request Register */
+  __IO uint32_t MCAN_TXBCR;   /**< \brief (Mcan Offset: 0xD4) Transmit Buffer Cancellation Request Register */
+  __I  uint32_t MCAN_TXBTO;   /**< \brief (Mcan Offset: 0xD8) Transmit Buffer Transmission Occurred Register */
+  __I  uint32_t MCAN_TXBCF;   /**< \brief (Mcan Offset: 0xDC) Transmit Buffer Cancellation Finished Register */
+  __IO uint32_t MCAN_TXBTIE;  /**< \brief (Mcan Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register */
+  __IO uint32_t MCAN_TXBCIE;  /**< \brief (Mcan Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register */
+  __I  uint32_t Reserved5[2];
+  __IO uint32_t MCAN_TXEFC;   /**< \brief (Mcan Offset: 0xF0) Transmit Event FIFO Configuration Register */
+  __I  uint32_t MCAN_TXEFS;   /**< \brief (Mcan Offset: 0xF4) Transmit Event FIFO Status Register */
+  __IO uint32_t MCAN_TXEFA;   /**< \brief (Mcan Offset: 0xF8) Transmit Event FIFO Acknowledge Register */
+} Mcan;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- MCAN_CREL : (MCAN Offset: 0x00) Core Release Register -------- */
+#define MCAN_CREL_DAY_Pos 0
+#define MCAN_CREL_DAY_Msk (0xffu << MCAN_CREL_DAY_Pos) /**< \brief (MCAN_CREL) Timestamp Day */
+#define MCAN_CREL_MON_Pos 8
+#define MCAN_CREL_MON_Msk (0xffu << MCAN_CREL_MON_Pos) /**< \brief (MCAN_CREL) Timestamp Month */
+#define MCAN_CREL_YEAR_Pos 16
+#define MCAN_CREL_YEAR_Msk (0xfu << MCAN_CREL_YEAR_Pos) /**< \brief (MCAN_CREL) Timestamp Year */
+#define MCAN_CREL_SUBSTEP_Pos 20
+#define MCAN_CREL_SUBSTEP_Msk (0xfu << MCAN_CREL_SUBSTEP_Pos) /**< \brief (MCAN_CREL) Sub-step of Core Release */
+#define MCAN_CREL_STEP_Pos 24
+#define MCAN_CREL_STEP_Msk (0xfu << MCAN_CREL_STEP_Pos) /**< \brief (MCAN_CREL) Step of Core Release */
+#define MCAN_CREL_REL_Pos 28
+#define MCAN_CREL_REL_Msk (0xfu << MCAN_CREL_REL_Pos) /**< \brief (MCAN_CREL) Core Release */
+/* -------- MCAN_ENDN : (MCAN Offset: 0x04) Endian Register -------- */
+#define MCAN_ENDN_ETV_Pos 0
+#define MCAN_ENDN_ETV_Msk (0xffffffffu << MCAN_ENDN_ETV_Pos) /**< \brief (MCAN_ENDN) Endianness Test Value */
+/* -------- MCAN_CUST : (MCAN Offset: 0x08) Customer Register -------- */
+#define MCAN_CUST_CSV_Pos 0
+#define MCAN_CUST_CSV_Msk (0xffffffffu << MCAN_CUST_CSV_Pos) /**< \brief (MCAN_CUST) Customer-specific Value */
+#define MCAN_CUST_CSV(value) ((MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos)))
+/* -------- MCAN_DBTP : (MCAN Offset: 0x0C) Fast Bit Timing and Prescaler Register -------- */
+#define MCAN_DBTP_DSJW_Pos 0
+#define MCAN_DBTP_DSJW_Msk (0x7u << MCAN_DBTP_DSJW_Pos) /**< \brief (MCAN_DBTP) Fast (Re) Synchronization Jump Width */
+#define MCAN_DBTP_DSJW(value) ((MCAN_DBTP_DSJW_Msk & ((value) << MCAN_DBTP_DSJW_Pos)))
+#define MCAN_DBTP_DTSEG2_Pos 4
+#define MCAN_DBTP_DTSEG2_Msk (0xfu << MCAN_DBTP_DTSEG2_Pos) /**< \brief (MCAN_DBTP) Fast Time Segment After Sample Point */
+#define MCAN_DBTP_DTSEG2(value) ((MCAN_DBTP_DTSEG2_Msk & ((value) << MCAN_DBTP_DTSEG2_Pos)))
+#define MCAN_DBTP_DTSEG1_Pos 8
+#define MCAN_DBTP_DTSEG1_Msk (0x1fu << MCAN_DBTP_DTSEG1_Pos) /**< \brief (MCAN_DBTP) Fast Time Segment Before Sample Point */
+#define MCAN_DBTP_DTSEG1(value) ((MCAN_DBTP_DTSEG1_Msk & ((value) << MCAN_DBTP_DTSEG1_Pos)))
+#define MCAN_DBTP_FBRP_Pos 16
+#define MCAN_DBTP_FBRP_Msk (0x1fu << MCAN_DBTP_FBRP_Pos) /**< \brief (MCAN_DBTP) Fast Baud Rate Prescaler */
+#define MCAN_DBTP_FBRP(value) ((MCAN_DBTP_FBRP_Msk & ((value) << MCAN_DBTP_FBRP_Pos)))
+#define MCAN_DBTP_TDC (0x1u << 23) /**< \brief (MCAN_DBTP) Transceiver Delay Compensation */
+#define   MCAN_DBTP_TDC_DISABLED (0x0u << 23) /**< \brief (MCAN_DBTP) Transceiver Delay Compensation disabled. */
+#define   MCAN_DBTP_TDC_ENABLED (0x1u << 23) /**< \brief (MCAN_DBTP) Transceiver Delay Compensation enabled. */
+/* -------- MCAN_TEST : (MCAN Offset: 0x10) Test Register -------- */
+#define MCAN_TEST_LBCK (0x1u << 4) /**< \brief (MCAN_TEST) Loop Back Mode (read/write) */
+#define   MCAN_TEST_LBCK_DISABLED (0x0u << 4) /**< \brief (MCAN_TEST) Reset value. Loop Back mode is disabled. */
+#define   MCAN_TEST_LBCK_ENABLED (0x1u << 4) /**< \brief (MCAN_TEST) Loop Back mode is enabled (see Section 1.5.1.9). */
+#define MCAN_TEST_TX_Pos 5
+#define MCAN_TEST_TX_Msk (0x3u << MCAN_TEST_TX_Pos) /**< \brief (MCAN_TEST) Control of Transmit Pin (read/write) */
+#define MCAN_TEST_TX(value) ((MCAN_TEST_TX_Msk & ((value) << MCAN_TEST_TX_Pos)))
+#define   MCAN_TEST_TX_RESET (0x0u << 5) /**< \brief (MCAN_TEST) Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. */
+#define   MCAN_TEST_TX_SAMPLE_POINT_MONITORING (0x1u << 5) /**< \brief (MCAN_TEST) Sample Point can be monitored at pin CANTX. */
+#define   MCAN_TEST_TX_DOMINANT (0x2u << 5) /**< \brief (MCAN_TEST) Dominant ('0') level at pin CANTX. */
+#define   MCAN_TEST_TX_RECESSIVE (0x3u << 5) /**< \brief (MCAN_TEST) Recessive ('1') at pin CANTX. */
+#define MCAN_TEST_RX (0x1u << 7) /**< \brief (MCAN_TEST) Receive Pin (read-only) */
+/* -------- MCAN_RWD : (MCAN Offset: 0x14) RAM Watchdog Register -------- */
+#define MCAN_RWD_WDC_Pos 0
+#define MCAN_RWD_WDC_Msk (0xffu << MCAN_RWD_WDC_Pos) /**< \brief (MCAN_RWD) Watchdog Configuration (read/write) */
+#define MCAN_RWD_WDC(value) ((MCAN_RWD_WDC_Msk & ((value) << MCAN_RWD_WDC_Pos)))
+#define MCAN_RWD_WDV_Pos 8
+#define MCAN_RWD_WDV_Msk (0xffu << MCAN_RWD_WDV_Pos) /**< \brief (MCAN_RWD) Watchdog Value (read-only) */
+#define MCAN_RWD_WDV(value) ((MCAN_RWD_WDV_Msk & ((value) << MCAN_RWD_WDV_Pos)))
+/* -------- MCAN_CCCR : (MCAN Offset: 0x18) CC Control Register -------- */
+#define MCAN_CCCR_INIT (0x1u << 0) /**< \brief (MCAN_CCCR) Initialization (read/write) */
+#define   MCAN_CCCR_INIT_DISABLED (0x0u << 0) /**< \brief (MCAN_CCCR) Normal operation. */
+#define   MCAN_CCCR_INIT_ENABLED (0x1u << 0) /**< \brief (MCAN_CCCR) Initialization is started. */
+#define MCAN_CCCR_CCE (0x1u << 1) /**< \brief (MCAN_CCCR) Configuration Change Enable (read/write, write protection) */
+#define   MCAN_CCCR_CCE_PROTECTED (0x0u << 1) /**< \brief (MCAN_CCCR) The processor has no write access to the protected configuration registers. */
+#define   MCAN_CCCR_CCE_CONFIGURABLE (0x1u << 1) /**< \brief (MCAN_CCCR) The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). */
+#define MCAN_CCCR_ASM (0x1u << 2) /**< \brief (MCAN_CCCR) Restricted Operation Mode (read/write, write protection against '1') */
+#define   MCAN_CCCR_ASM_NORMAL (0x0u << 2) /**< \brief (MCAN_CCCR) Normal CAN operation. */
+#define   MCAN_CCCR_ASM_RESTRICTED (0x1u << 2) /**< \brief (MCAN_CCCR) Restricted operation mode active. */
+#define MCAN_CCCR_CSA (0x1u << 3) /**< \brief (MCAN_CCCR) Clock Stop Acknowledge (read-only) */
+#define MCAN_CCCR_CSR (0x1u << 4) /**< \brief (MCAN_CCCR) Clock Stop Request (read/write) */
+#define   MCAN_CCCR_CSR_NO_CLOCK_STOP (0x0u << 4) /**< \brief (MCAN_CCCR) No clock stop is requested. */
+#define   MCAN_CCCR_CSR_CLOCK_STOP (0x1u << 4) /**< \brief (MCAN_CCCR) Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. */
+#define MCAN_CCCR_MON (0x1u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring Mode (read/write, write protection against '1') */
+#define   MCAN_CCCR_MON_DISABLED (0x0u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring mode is disabled. */
+#define   MCAN_CCCR_MON_ENABLED (0x1u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring mode is enabled. */
+#define MCAN_CCCR_DAR (0x1u << 6) /**< \brief (MCAN_CCCR) Disable Automatic Retransmission (read/write, write protection) */
+#define   MCAN_CCCR_DAR_AUTO_RETX (0x0u << 6) /**< \brief (MCAN_CCCR) Automatic retransmission of messages not transmitted successfully enabled. */
+#define   MCAN_CCCR_DAR_NO_AUTO_RETX (0x1u << 6) /**< \brief (MCAN_CCCR) Automatic retransmission disabled. */
+#define MCAN_CCCR_TEST (0x1u << 7) /**< \brief (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') */
+#define   MCAN_CCCR_TEST_DISABLED (0x0u << 7) /**< \brief (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. */
+#define   MCAN_CCCR_TEST_ENABLED (0x1u << 7) /**< \brief (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. */
+#define MCAN_CCCR_FDOE (0x1u << 8) /**< \brief (MCAN_CCCR) CAN FD Operation Enable (read/write, write protection) */
+#define   MCAN_CCCR_FDOE_DISABLED (0x0u << 8) /**< \brief (MCAN_CCCR) Classic CAN frame */
+#define   MCAN_CCCR_FDOE_ENABLED (0x1u << 8) /**< \brief (MCAN_CCCR) CAN FD frame */
+#define MCAN_CCCR_BRSE (0x1u << 9) /**< \brief (MCAN_CCCR) Bit Rate Switching Enable (read/write, write protection) */
+#define   MCAN_CCCR_BRSE_DISABLED (0x0u << 9) /**< \brief (MCAN_CCCR) Frames without bit rate switching */
+#define   MCAN_CCCR_BRSE_ENABLED (0x1u << 9) /**< \brief (MCAN_CCCR) Frames with bit rate switching */
+#define MCAN_CCCR_PXHD (0x1u << 12) /**< \brief (MCAN_CCCR) Protocol Exception Event Handling (read/write, write protection) */
+#define MCAN_CCCR_EFBI (0x1u << 13) /**< \brief (MCAN_CCCR) Edge Filtering during Bus Integration (read/write, write protection) */
+#define MCAN_CCCR_TXP (0x1u << 14) /**< \brief (MCAN_CCCR) Transmit Pause (read/write, write protection) */
+/* -------- MCAN_NBTP : (MCAN Offset: 0x1C) Bit Timing and Prescaler Register -------- */
+#define MCAN_NBTP_NTSEG2_Pos 0
+#define MCAN_NBTP_NTSEG2_Msk (0x7fu << MCAN_NBTP_NTSEG2_Pos) /**< \brief (MCAN_NBTP) Nominal Time Segment After Sample Point */
+#define MCAN_NBTP_NTSEG2(value) ((MCAN_NBTP_NTSEG2_Msk & ((value) << MCAN_NBTP_NTSEG2_Pos)))
+#define MCAN_NBTP_NTSEG1_Pos 8
+#define MCAN_NBTP_NTSEG1_Msk (0xffu << MCAN_NBTP_NTSEG1_Pos) /**< \brief (MCAN_NBTP) Nominal Time Segment Before Sample Point */
+#define MCAN_NBTP_NTSEG1(value) ((MCAN_NBTP_NTSEG1_Msk & ((value) << MCAN_NBTP_NTSEG1_Pos)))
+#define MCAN_NBTP_NBRP_Pos 16
+#define MCAN_NBTP_NBRP_Msk (0x1ffu << MCAN_NBTP_NBRP_Pos) /**< \brief (MCAN_NBTP) Nominal Baud Rate Prescaler */
+#define MCAN_NBTP_NBRP(value) ((MCAN_NBTP_NBRP_Msk & ((value) << MCAN_NBTP_NBRP_Pos)))
+#define MCAN_NBTP_NSJW_Pos 25
+#define MCAN_NBTP_NSJW_Msk (0x7fu << MCAN_NBTP_NSJW_Pos) /**< \brief (MCAN_NBTP) Nominal (Re) Synchronization Jump Width */
+#define MCAN_NBTP_NSJW(value) ((MCAN_NBTP_NSJW_Msk & ((value) << MCAN_NBTP_NSJW_Pos)))
+/* -------- MCAN_TSCC : (MCAN Offset: 0x20) Timestamp Counter Configuration Register -------- */
+#define MCAN_TSCC_TSS_Pos 0
+#define MCAN_TSCC_TSS_Msk (0x3u << MCAN_TSCC_TSS_Pos) /**< \brief (MCAN_TSCC) Timestamp Select */
+#define MCAN_TSCC_TSS(value) ((MCAN_TSCC_TSS_Msk & ((value) << MCAN_TSCC_TSS_Pos)))
+#define   MCAN_TSCC_TSS_ALWAYS_0 (0x0u << 0) /**< \brief (MCAN_TSCC) Timestamp counter value always 0x0000 */
+#define   MCAN_TSCC_TSS_TCP_INC (0x1u << 0) /**< \brief (MCAN_TSCC) Timestamp counter value incremented according to TCP */
+#define   MCAN_TSCC_TSS_EXT_TIMESTAMP (0x2u << 0) /**< \brief (MCAN_TSCC) External timestamp counter value used */
+#define MCAN_TSCC_TCP_Pos 16
+#define MCAN_TSCC_TCP_Msk (0xfu << MCAN_TSCC_TCP_Pos) /**< \brief (MCAN_TSCC) Timestamp Counter Prescaler */
+#define MCAN_TSCC_TCP(value) ((MCAN_TSCC_TCP_Msk & ((value) << MCAN_TSCC_TCP_Pos)))
+/* -------- MCAN_TSCV : (MCAN Offset: 0x24) Timestamp Counter Value Register -------- */
+#define MCAN_TSCV_TSC_Pos 0
+#define MCAN_TSCV_TSC_Msk (0xffffu << MCAN_TSCV_TSC_Pos) /**< \brief (MCAN_TSCV) Timestamp Counter (cleared on write) */
+#define MCAN_TSCV_TSC(value) ((MCAN_TSCV_TSC_Msk & ((value) << MCAN_TSCV_TSC_Pos)))
+/* -------- MCAN_TOCC : (MCAN Offset: 0x28) Timeout Counter Configuration Register -------- */
+#define MCAN_TOCC_ETOC (0x1u << 0) /**< \brief (MCAN_TOCC) Enable Timeout Counter */
+#define   MCAN_TOCC_ETOC_NO_TIMEOUT (0x0u << 0) /**< \brief (MCAN_TOCC) Timeout Counter disabled. */
+#define   MCAN_TOCC_ETOC_TOS_CONTROLLED (0x1u << 0) /**< \brief (MCAN_TOCC) Timeout Counter enabled. */
+#define MCAN_TOCC_TOS_Pos 1
+#define MCAN_TOCC_TOS_Msk (0x3u << MCAN_TOCC_TOS_Pos) /**< \brief (MCAN_TOCC) Timeout Select */
+#define MCAN_TOCC_TOS(value) ((MCAN_TOCC_TOS_Msk & ((value) << MCAN_TOCC_TOS_Pos)))
+#define   MCAN_TOCC_TOS_CONTINUOUS (0x0u << 1) /**< \brief (MCAN_TOCC) Continuous operation */
+#define   MCAN_TOCC_TOS_TX_EV_TIMEOUT (0x1u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Tx Event FIFO */
+#define   MCAN_TOCC_TOS_RX0_EV_TIMEOUT (0x2u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 0 */
+#define   MCAN_TOCC_TOS_RX1_EV_TIMEOUT (0x3u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 1 */
+#define MCAN_TOCC_TOP_Pos 16
+#define MCAN_TOCC_TOP_Msk (0xffffu << MCAN_TOCC_TOP_Pos) /**< \brief (MCAN_TOCC) Timeout Period */
+#define MCAN_TOCC_TOP(value) ((MCAN_TOCC_TOP_Msk & ((value) << MCAN_TOCC_TOP_Pos)))
+/* -------- MCAN_TOCV : (MCAN Offset: 0x2C) Timeout Counter Value Register -------- */
+#define MCAN_TOCV_TOC_Pos 0
+#define MCAN_TOCV_TOC_Msk (0xffffu << MCAN_TOCV_TOC_Pos) /**< \brief (MCAN_TOCV) Timeout Counter (cleared on write) */
+#define MCAN_TOCV_TOC(value) ((MCAN_TOCV_TOC_Msk & ((value) << MCAN_TOCV_TOC_Pos)))
+/* -------- MCAN_ECR : (MCAN Offset: 0x40) Error Counter Register -------- */
+#define MCAN_ECR_TEC_Pos 0
+#define MCAN_ECR_TEC_Msk (0xffu << MCAN_ECR_TEC_Pos) /**< \brief (MCAN_ECR) Transmit Error Counter */
+#define MCAN_ECR_REC_Pos 8
+#define MCAN_ECR_REC_Msk (0x7fu << MCAN_ECR_REC_Pos) /**< \brief (MCAN_ECR) Receive Error Counter */
+#define MCAN_ECR_RP (0x1u << 15) /**< \brief (MCAN_ECR) Receive Error Passive */
+#define MCAN_ECR_CEL_Pos 16
+#define MCAN_ECR_CEL_Msk (0xffu << MCAN_ECR_CEL_Pos) /**< \brief (MCAN_ECR) CAN Error Logging (cleared on read) */
+/* -------- MCAN_PSR : (MCAN Offset: 0x44) Protocol Status Register -------- */
+#define MCAN_PSR_LEC_Pos 0
+#define MCAN_PSR_LEC_Msk (0x7u << MCAN_PSR_LEC_Pos) /**< \brief (MCAN_PSR) Last Error Code (set to 111 on read) */
+#define   MCAN_PSR_LEC_NO_ERROR (0x0u << 0) /**< \brief (MCAN_PSR) No error occurred since LEC has been reset by successful reception or transmission. */
+#define   MCAN_PSR_LEC_STUFF_ERROR (0x1u << 0) /**< \brief (MCAN_PSR) More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. */
+#define   MCAN_PSR_LEC_FORM_ERROR (0x2u << 0) /**< \brief (MCAN_PSR) A fixed format part of a received frame has the wrong format. */
+#define   MCAN_PSR_LEC_ACK_ERROR (0x3u << 0) /**< \brief (MCAN_PSR) The message transmitted by the MCAN was not acknowledged by another node. */
+#define   MCAN_PSR_LEC_BIT1_ERROR (0x4u << 0) /**< \brief (MCAN_PSR) During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. */
+#define   MCAN_PSR_LEC_BIT0_ERROR (0x5u << 0) /**< \brief (MCAN_PSR) During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). */
+#define   MCAN_PSR_LEC_CRC_ERROR (0x6u << 0) /**< \brief (MCAN_PSR) The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. */
+#define   MCAN_PSR_LEC_NO_CHANGE (0x7u << 0) /**< \brief (MCAN_PSR) Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. */
+#define MCAN_PSR_ACT_Pos 3
+#define MCAN_PSR_ACT_Msk (0x3u << MCAN_PSR_ACT_Pos) /**< \brief (MCAN_PSR) Activity */
+#define   MCAN_PSR_ACT_SYNCHRONIZING (0x0u << 3) /**< \brief (MCAN_PSR) Node is synchronizing on CAN communication */
+#define   MCAN_PSR_ACT_IDLE (0x1u << 3) /**< \brief (MCAN_PSR) Node is neither receiver nor transmitter */
+#define   MCAN_PSR_ACT_RECEIVER (0x2u << 3) /**< \brief (MCAN_PSR) Node is operating as receiver */
+#define   MCAN_PSR_ACT_TRANSMITTER (0x3u << 3) /**< \brief (MCAN_PSR) Node is operating as transmitter */
+#define MCAN_PSR_EP (0x1u << 5) /**< \brief (MCAN_PSR) Error Passive */
+#define MCAN_PSR_EW (0x1u << 6) /**< \brief (MCAN_PSR) Warning Status */
+#define MCAN_PSR_BO (0x1u << 7) /**< \brief (MCAN_PSR) Bus_Off Status */
+#define MCAN_PSR_DLEC_Pos 8
+#define MCAN_PSR_DLEC_Msk (0x7u << MCAN_PSR_DLEC_Pos) /**< \brief (MCAN_PSR) Data Phase Last Error Code (set to 111 on read) */
+#define MCAN_PSR_RESI (0x1u << 11) /**< \brief (MCAN_PSR) ESI Flag of Last Received CAN FD Message (cleared on read) */
+#define MCAN_PSR_RBRS (0x1u << 12) /**< \brief (MCAN_PSR) BRS Flag of Last Received CAN FD Message (cleared on read) */
+#define MCAN_PSR_RFDF (0x1u << 13) /**< \brief (MCAN_PSR) Received a CAN FD Message (cleared on read) */
+#define MCAN_PSR_PXE (0x1u << 14) /**< \brief (MCAN_PSR) Protocol Exception Event (cleared on read) */
+#define MCAN_PSR_TDCV_Pos 16
+#define MCAN_PSR_TDCV_Msk (0x7fu << MCAN_PSR_TDCV_Pos) /**< \brief (MCAN_PSR) Transceiver Delay Compensation Value */
+/* -------- MCAN_TDCR : (MCAN Offset: 0x48) Transmit Delay Compensation Register -------- */
+#define MCAN_TDCR_TDCF_Pos 0
+#define MCAN_TDCR_TDCF_Msk (0x7fu << MCAN_TDCR_TDCF_Pos) /**< \brief (MCAN_TDCR) Transmitter Delay Compensation Filter */
+#define MCAN_TDCR_TDCF(value) ((MCAN_TDCR_TDCF_Msk & ((value) << MCAN_TDCR_TDCF_Pos)))
+#define MCAN_TDCR_TDCO_Pos 8
+#define MCAN_TDCR_TDCO_Msk (0x7fu << MCAN_TDCR_TDCO_Pos) /**< \brief (MCAN_TDCR) Transmitter Delay Compensation Offset */
+#define MCAN_TDCR_TDCO(value) ((MCAN_TDCR_TDCO_Msk & ((value) << MCAN_TDCR_TDCO_Pos)))
+/* -------- MCAN_IR : (MCAN Offset: 0x50) Interrupt Register -------- */
+#define MCAN_IR_RF0N (0x1u << 0) /**< \brief (MCAN_IR) Receive FIFO 0 New Message */
+#define MCAN_IR_RF0W (0x1u << 1) /**< \brief (MCAN_IR) Receive FIFO 0 Watermark Reached */
+#define MCAN_IR_RF0F (0x1u << 2) /**< \brief (MCAN_IR) Receive FIFO 0 Full */
+#define MCAN_IR_RF0L (0x1u << 3) /**< \brief (MCAN_IR) Receive FIFO 0 Message Lost */
+#define MCAN_IR_RF1N (0x1u << 4) /**< \brief (MCAN_IR) Receive FIFO 1 New Message */
+#define MCAN_IR_RF1W (0x1u << 5) /**< \brief (MCAN_IR) Receive FIFO 1 Watermark Reached */
+#define MCAN_IR_RF1F (0x1u << 6) /**< \brief (MCAN_IR) Receive FIFO 1 Full */
+#define MCAN_IR_RF1L (0x1u << 7) /**< \brief (MCAN_IR) Receive FIFO 1 Message Lost */
+#define MCAN_IR_HPM (0x1u << 8) /**< \brief (MCAN_IR) High Priority Message */
+#define MCAN_IR_TC (0x1u << 9) /**< \brief (MCAN_IR) Transmission Completed */
+#define MCAN_IR_TCF (0x1u << 10) /**< \brief (MCAN_IR) Transmission Cancellation Finished */
+#define MCAN_IR_TFE (0x1u << 11) /**< \brief (MCAN_IR) Tx FIFO Empty */
+#define MCAN_IR_TEFN (0x1u << 12) /**< \brief (MCAN_IR) Tx Event FIFO New Entry */
+#define MCAN_IR_TEFW (0x1u << 13) /**< \brief (MCAN_IR) Tx Event FIFO Watermark Reached */
+#define MCAN_IR_TEFF (0x1u << 14) /**< \brief (MCAN_IR) Tx Event FIFO Full */
+#define MCAN_IR_TEFL (0x1u << 15) /**< \brief (MCAN_IR) Tx Event FIFO Element Lost */
+#define MCAN_IR_TSW (0x1u << 16) /**< \brief (MCAN_IR) Timestamp Wraparound */
+#define MCAN_IR_MRAF (0x1u << 17) /**< \brief (MCAN_IR) Message RAM Access Failure */
+#define MCAN_IR_TOO (0x1u << 18) /**< \brief (MCAN_IR) Timeout Occurred */
+#define MCAN_IR_DRX (0x1u << 19) /**< \brief (MCAN_IR) Message stored to Dedicated Receive Buffer */
+#define MCAN_IR_BEC (0x1u << 20) /**< \brief (MCAN_IR) Bit Error Corrected */
+#define MCAN_IR_BEU (0x1u << 21) /**< \brief (MCAN_IR) Bit Error Uncorrected */
+#define MCAN_IR_ELO (0x1u << 22) /**< \brief (MCAN_IR) Error Logging Overflow */
+#define MCAN_IR_EP (0x1u << 23) /**< \brief (MCAN_IR) Error Passive */
+#define MCAN_IR_EW (0x1u << 24) /**< \brief (MCAN_IR) Warning Status */
+#define MCAN_IR_BO (0x1u << 25) /**< \brief (MCAN_IR) Bus_Off Status */
+#define MCAN_IR_WDI (0x1u << 26) /**< \brief (MCAN_IR) Watchdog Interrupt */
+#define MCAN_IR_PEA (0x1u << 27) /**< \brief (MCAN_IR) Protocol Error in Arbitration Phase */
+#define MCAN_IR_PED (0x1u << 28) /**< \brief (MCAN_IR) Protocol Error in Data Phase */
+#define MCAN_IR_ARA (0x1u << 29) /**< \brief (MCAN_IR) Access to Reserved Address */
+/* -------- MCAN_IE : (MCAN Offset: 0x54) Interrupt Enable Register -------- */
+#define MCAN_IE_RF0NE (0x1u << 0) /**< \brief (MCAN_IE) Receive FIFO 0 New Message Interrupt Enable */
+#define MCAN_IE_RF0WE (0x1u << 1) /**< \brief (MCAN_IE) Receive FIFO 0 Watermark Reached Interrupt Enable */
+#define MCAN_IE_RF0FE (0x1u << 2) /**< \brief (MCAN_IE) Receive FIFO 0 Full Interrupt Enable */
+#define MCAN_IE_RF0LE (0x1u << 3) /**< \brief (MCAN_IE) Receive FIFO 0 Message Lost Interrupt Enable */
+#define MCAN_IE_RF1NE (0x1u << 4) /**< \brief (MCAN_IE) Receive FIFO 1 New Message Interrupt Enable */
+#define MCAN_IE_RF1WE (0x1u << 5) /**< \brief (MCAN_IE) Receive FIFO 1 Watermark Reached Interrupt Enable */
+#define MCAN_IE_RF1FE (0x1u << 6) /**< \brief (MCAN_IE) Receive FIFO 1 Full Interrupt Enable */
+#define MCAN_IE_RF1LE (0x1u << 7) /**< \brief (MCAN_IE) Receive FIFO 1 Message Lost Interrupt Enable */
+#define MCAN_IE_HPME (0x1u << 8) /**< \brief (MCAN_IE) High Priority Message Interrupt Enable */
+#define MCAN_IE_TCE (0x1u << 9) /**< \brief (MCAN_IE) Transmission Completed Interrupt Enable */
+#define MCAN_IE_TCFE (0x1u << 10) /**< \brief (MCAN_IE) Transmission Cancellation Finished Interrupt Enable */
+#define MCAN_IE_TFEE (0x1u << 11) /**< \brief (MCAN_IE) Tx FIFO Empty Interrupt Enable */
+#define MCAN_IE_TEFNE (0x1u << 12) /**< \brief (MCAN_IE) Tx Event FIFO New Entry Interrupt Enable */
+#define MCAN_IE_TEFWE (0x1u << 13) /**< \brief (MCAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */
+#define MCAN_IE_TEFFE (0x1u << 14) /**< \brief (MCAN_IE) Tx Event FIFO Full Interrupt Enable */
+#define MCAN_IE_TEFLE (0x1u << 15) /**< \brief (MCAN_IE) Tx Event FIFO Event Lost Interrupt Enable */
+#define MCAN_IE_TSWE (0x1u << 16) /**< \brief (MCAN_IE) Timestamp Wraparound Interrupt Enable */
+#define MCAN_IE_MRAFE (0x1u << 17) /**< \brief (MCAN_IE) Message RAM Access Failure Interrupt Enable */
+#define MCAN_IE_TOOE (0x1u << 18) /**< \brief (MCAN_IE) Timeout Occurred Interrupt Enable */
+#define MCAN_IE_DRXE (0x1u << 19) /**< \brief (MCAN_IE) Message stored to Dedicated Receive Buffer Interrupt Enable */
+#define MCAN_IE_BECE (0x1u << 20) /**< \brief (MCAN_IE) Bit Error Corrected Interrupt Enable */
+#define MCAN_IE_BEUE (0x1u << 21) /**< \brief (MCAN_IE) Bit Error Uncorrected Interrupt Enable */
+#define MCAN_IE_ELOE (0x1u << 22) /**< \brief (MCAN_IE) Error Logging Overflow Interrupt Enable */
+#define MCAN_IE_EPE (0x1u << 23) /**< \brief (MCAN_IE) Error Passive Interrupt Enable */
+#define MCAN_IE_EWE (0x1u << 24) /**< \brief (MCAN_IE) Warning Status Interrupt Enable */
+#define MCAN_IE_BOE (0x1u << 25) /**< \brief (MCAN_IE) Bus_Off Status Interrupt Enable */
+#define MCAN_IE_WDIE (0x1u << 26) /**< \brief (MCAN_IE) Watchdog Interrupt Enable */
+#define MCAN_IE_PEAE (0x1u << 27) /**< \brief (MCAN_IE) Protocol Error in Arbitration Phase Enable */
+#define MCAN_IE_PEDE (0x1u << 28) /**< \brief (MCAN_IE) Protocol Error in Data Phase Enable */
+#define MCAN_IE_ARAE (0x1u << 29) /**< \brief (MCAN_IE) Access to Reserved Address Enable */
+/* -------- MCAN_ILS : (MCAN Offset: 0x58) Interrupt Line Select Register -------- */
+#define MCAN_ILS_RF0NL (0x1u << 0) /**< \brief (MCAN_ILS) Receive FIFO 0 New Message Interrupt Line */
+#define MCAN_ILS_RF0WL (0x1u << 1) /**< \brief (MCAN_ILS) Receive FIFO 0 Watermark Reached Interrupt Line */
+#define MCAN_ILS_RF0FL (0x1u << 2) /**< \brief (MCAN_ILS) Receive FIFO 0 Full Interrupt Line */
+#define MCAN_ILS_RF0LL (0x1u << 3) /**< \brief (MCAN_ILS) Receive FIFO 0 Message Lost Interrupt Line */
+#define MCAN_ILS_RF1NL (0x1u << 4) /**< \brief (MCAN_ILS) Receive FIFO 1 New Message Interrupt Line */
+#define MCAN_ILS_RF1WL (0x1u << 5) /**< \brief (MCAN_ILS) Receive FIFO 1 Watermark Reached Interrupt Line */
+#define MCAN_ILS_RF1FL (0x1u << 6) /**< \brief (MCAN_ILS) Receive FIFO 1 Full Interrupt Line */
+#define MCAN_ILS_RF1LL (0x1u << 7) /**< \brief (MCAN_ILS) Receive FIFO 1 Message Lost Interrupt Line */
+#define MCAN_ILS_HPML (0x1u << 8) /**< \brief (MCAN_ILS) High Priority Message Interrupt Line */
+#define MCAN_ILS_TCL (0x1u << 9) /**< \brief (MCAN_ILS) Transmission Completed Interrupt Line */
+#define MCAN_ILS_TCFL (0x1u << 10) /**< \brief (MCAN_ILS) Transmission Cancellation Finished Interrupt Line */
+#define MCAN_ILS_TFEL (0x1u << 11) /**< \brief (MCAN_ILS) Tx FIFO Empty Interrupt Line */
+#define MCAN_ILS_TEFNL (0x1u << 12) /**< \brief (MCAN_ILS) Tx Event FIFO New Entry Interrupt Line */
+#define MCAN_ILS_TEFWL (0x1u << 13) /**< \brief (MCAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */
+#define MCAN_ILS_TEFFL (0x1u << 14) /**< \brief (MCAN_ILS) Tx Event FIFO Full Interrupt Line */
+#define MCAN_ILS_TEFLL (0x1u << 15) /**< \brief (MCAN_ILS) Tx Event FIFO Event Lost Interrupt Line */
+#define MCAN_ILS_TSWL (0x1u << 16) /**< \brief (MCAN_ILS) Timestamp Wraparound Interrupt Line */
+#define MCAN_ILS_MRAFL (0x1u << 17) /**< \brief (MCAN_ILS) Message RAM Access Failure Interrupt Line */
+#define MCAN_ILS_TOOL (0x1u << 18) /**< \brief (MCAN_ILS) Timeout Occurred Interrupt Line */
+#define MCAN_ILS_DRXL (0x1u << 19) /**< \brief (MCAN_ILS) Message stored to Dedicated Receive Buffer Interrupt Line */
+#define MCAN_ILS_BECL (0x1u << 20) /**< \brief (MCAN_ILS) Bit Error Corrected Interrupt Line */
+#define MCAN_ILS_BEUL (0x1u << 21) /**< \brief (MCAN_ILS) Bit Error Uncorrected Interrupt Line */
+#define MCAN_ILS_ELOL (0x1u << 22) /**< \brief (MCAN_ILS) Error Logging Overflow Interrupt Line */
+#define MCAN_ILS_EPL (0x1u << 23) /**< \brief (MCAN_ILS) Error Passive Interrupt Line */
+#define MCAN_ILS_EWL (0x1u << 24) /**< \brief (MCAN_ILS) Warning Status Interrupt Line */
+#define MCAN_ILS_BOL (0x1u << 25) /**< \brief (MCAN_ILS) Bus_Off Status Interrupt Line */
+#define MCAN_ILS_WDIL (0x1u << 26) /**< \brief (MCAN_ILS) Watchdog Interrupt Line */
+#define MCAN_ILS_PEAL (0x1u << 27) /**< \brief (MCAN_ILS) Protocol Error in Arbitration Phase Line */
+#define MCAN_ILS_PEDL (0x1u << 28) /**< \brief (MCAN_ILS) Protocol Error in Data Phase Line */
+#define MCAN_ILS_ARAL (0x1u << 29) /**< \brief (MCAN_ILS) Access to Reserved Address Line */
+/* -------- MCAN_ILE : (MCAN Offset: 0x5C) Interrupt Line Enable Register -------- */
+#define MCAN_ILE_EINT0 (0x1u << 0) /**< \brief (MCAN_ILE) Enable Interrupt Line 0 */
+#define MCAN_ILE_EINT1 (0x1u << 1) /**< \brief (MCAN_ILE) Enable Interrupt Line 1 */
+/* -------- MCAN_GFC : (MCAN Offset: 0x80) Global Filter Configuration Register -------- */
+#define MCAN_GFC_RRFE (0x1u << 0) /**< \brief (MCAN_GFC) Reject Remote Frames Extended */
+#define   MCAN_GFC_RRFE_FILTER (0x0u << 0) /**< \brief (MCAN_GFC) Filter remote frames with 29-bit extended IDs. */
+#define   MCAN_GFC_RRFE_REJECT (0x1u << 0) /**< \brief (MCAN_GFC) Reject all remote frames with 29-bit extended IDs. */
+#define MCAN_GFC_RRFS (0x1u << 1) /**< \brief (MCAN_GFC) Reject Remote Frames Standard */
+#define   MCAN_GFC_RRFS_FILTER (0x0u << 1) /**< \brief (MCAN_GFC) Filter remote frames with 11-bit standard IDs. */
+#define   MCAN_GFC_RRFS_REJECT (0x1u << 1) /**< \brief (MCAN_GFC) Reject all remote frames with 11-bit standard IDs. */
+#define MCAN_GFC_ANFE_Pos 2
+#define MCAN_GFC_ANFE_Msk (0x3u << MCAN_GFC_ANFE_Pos) /**< \brief (MCAN_GFC) Accept Non-matching Frames Extended */
+#define MCAN_GFC_ANFE(value) ((MCAN_GFC_ANFE_Msk & ((value) << MCAN_GFC_ANFE_Pos)))
+#define   MCAN_GFC_ANFE_RX_FIFO_0 (0x0u << 2) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 0 */
+#define   MCAN_GFC_ANFE_RX_FIFO_1 (0x1u << 2) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 1 */
+#define MCAN_GFC_ANFS_Pos 4
+#define MCAN_GFC_ANFS_Msk (0x3u << MCAN_GFC_ANFS_Pos) /**< \brief (MCAN_GFC) Accept Non-matching Frames Standard */
+#define MCAN_GFC_ANFS(value) ((MCAN_GFC_ANFS_Msk & ((value) << MCAN_GFC_ANFS_Pos)))
+#define   MCAN_GFC_ANFS_RX_FIFO_0 (0x0u << 4) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 0 */
+#define   MCAN_GFC_ANFS_RX_FIFO_1 (0x1u << 4) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 1 */
+/* -------- MCAN_SIDFC : (MCAN Offset: 0x84) Standard ID Filter Configuration Register -------- */
+#define MCAN_SIDFC_FLSSA_Pos 2
+#define MCAN_SIDFC_FLSSA_Msk (0x3fffu << MCAN_SIDFC_FLSSA_Pos) /**< \brief (MCAN_SIDFC) Filter List Standard Start Address */
+#define MCAN_SIDFC_FLSSA(value) ((MCAN_SIDFC_FLSSA_Msk & ((value) << MCAN_SIDFC_FLSSA_Pos)))
+#define MCAN_SIDFC_LSS_Pos 16
+#define MCAN_SIDFC_LSS_Msk (0xffu << MCAN_SIDFC_LSS_Pos) /**< \brief (MCAN_SIDFC) List Size Standard */
+#define MCAN_SIDFC_LSS(value) ((MCAN_SIDFC_LSS_Msk & ((value) << MCAN_SIDFC_LSS_Pos)))
+/* -------- MCAN_XIDFC : (MCAN Offset: 0x88) Extended ID Filter Configuration Register -------- */
+#define MCAN_XIDFC_FLESA_Pos 2
+#define MCAN_XIDFC_FLESA_Msk (0x3fffu << MCAN_XIDFC_FLESA_Pos) /**< \brief (MCAN_XIDFC) Filter List Extended Start Address */
+#define MCAN_XIDFC_FLESA(value) ((MCAN_XIDFC_FLESA_Msk & ((value) << MCAN_XIDFC_FLESA_Pos)))
+#define MCAN_XIDFC_LSE_Pos 16
+#define MCAN_XIDFC_LSE_Msk (0x7fu << MCAN_XIDFC_LSE_Pos) /**< \brief (MCAN_XIDFC) List Size Extended */
+#define MCAN_XIDFC_LSE(value) ((MCAN_XIDFC_LSE_Msk & ((value) << MCAN_XIDFC_LSE_Pos)))
+/* -------- MCAN_XIDAM : (MCAN Offset: 0x90) Extended ID AND Mask Register -------- */
+#define MCAN_XIDAM_EIDM_Pos 0
+#define MCAN_XIDAM_EIDM_Msk (0x1fffffffu << MCAN_XIDAM_EIDM_Pos) /**< \brief (MCAN_XIDAM) Extended ID Mask */
+#define MCAN_XIDAM_EIDM(value) ((MCAN_XIDAM_EIDM_Msk & ((value) << MCAN_XIDAM_EIDM_Pos)))
+/* -------- MCAN_HPMS : (MCAN Offset: 0x94) High Priority Message Status Register -------- */
+#define MCAN_HPMS_BIDX_Pos 0
+#define MCAN_HPMS_BIDX_Msk (0x3fu << MCAN_HPMS_BIDX_Pos) /**< \brief (MCAN_HPMS) Buffer Index */
+#define MCAN_HPMS_MSI_Pos 6
+#define MCAN_HPMS_MSI_Msk (0x3u << MCAN_HPMS_MSI_Pos) /**< \brief (MCAN_HPMS) Message Storage Indicator */
+#define   MCAN_HPMS_MSI_NO_FIFO_SEL (0x0u << 6) /**< \brief (MCAN_HPMS) No FIFO selected. */
+#define   MCAN_HPMS_MSI_LOST (0x1u << 6) /**< \brief (MCAN_HPMS) FIFO message. */
+#define   MCAN_HPMS_MSI_FIFO_0 (0x2u << 6) /**< \brief (MCAN_HPMS) Message stored in FIFO 0. */
+#define   MCAN_HPMS_MSI_FIFO_1 (0x3u << 6) /**< \brief (MCAN_HPMS) Message stored in FIFO 1. */
+#define MCAN_HPMS_FIDX_Pos 8
+#define MCAN_HPMS_FIDX_Msk (0x7fu << MCAN_HPMS_FIDX_Pos) /**< \brief (MCAN_HPMS) Filter Index */
+#define MCAN_HPMS_FLST (0x1u << 15) /**< \brief (MCAN_HPMS) Filter List */
+/* -------- MCAN_NDAT1 : (MCAN Offset: 0x98) New Data 1 Register -------- */
+#define MCAN_NDAT1_ND0 (0x1u << 0) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND1 (0x1u << 1) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND2 (0x1u << 2) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND3 (0x1u << 3) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND4 (0x1u << 4) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND5 (0x1u << 5) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND6 (0x1u << 6) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND7 (0x1u << 7) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND8 (0x1u << 8) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND9 (0x1u << 9) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND10 (0x1u << 10) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND11 (0x1u << 11) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND12 (0x1u << 12) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND13 (0x1u << 13) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND14 (0x1u << 14) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND15 (0x1u << 15) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND16 (0x1u << 16) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND17 (0x1u << 17) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND18 (0x1u << 18) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND19 (0x1u << 19) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND20 (0x1u << 20) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND21 (0x1u << 21) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND22 (0x1u << 22) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND23 (0x1u << 23) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND24 (0x1u << 24) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND25 (0x1u << 25) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND26 (0x1u << 26) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND27 (0x1u << 27) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND28 (0x1u << 28) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND29 (0x1u << 29) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND30 (0x1u << 30) /**< \brief (MCAN_NDAT1) New Data */
+#define MCAN_NDAT1_ND31 (0x1u << 31) /**< \brief (MCAN_NDAT1) New Data */
+/* -------- MCAN_NDAT2 : (MCAN Offset: 0x9C) New Data 2 Register -------- */
+#define MCAN_NDAT2_ND32 (0x1u << 0) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND33 (0x1u << 1) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND34 (0x1u << 2) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND35 (0x1u << 3) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND36 (0x1u << 4) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND37 (0x1u << 5) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND38 (0x1u << 6) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND39 (0x1u << 7) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND40 (0x1u << 8) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND41 (0x1u << 9) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND42 (0x1u << 10) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND43 (0x1u << 11) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND44 (0x1u << 12) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND45 (0x1u << 13) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND46 (0x1u << 14) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND47 (0x1u << 15) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND48 (0x1u << 16) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND49 (0x1u << 17) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND50 (0x1u << 18) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND51 (0x1u << 19) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND52 (0x1u << 20) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND53 (0x1u << 21) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND54 (0x1u << 22) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND55 (0x1u << 23) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND56 (0x1u << 24) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND57 (0x1u << 25) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND58 (0x1u << 26) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND59 (0x1u << 27) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND60 (0x1u << 28) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND61 (0x1u << 29) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND62 (0x1u << 30) /**< \brief (MCAN_NDAT2) New Data */
+#define MCAN_NDAT2_ND63 (0x1u << 31) /**< \brief (MCAN_NDAT2) New Data */
+/* -------- MCAN_RXF0C : (MCAN Offset: 0xA0) Receive FIFO 0 Configuration Register -------- */
+#define MCAN_RXF0C_F0SA_Pos 2
+#define MCAN_RXF0C_F0SA_Msk (0x3fffu << MCAN_RXF0C_F0SA_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address */
+#define MCAN_RXF0C_F0SA(value) ((MCAN_RXF0C_F0SA_Msk & ((value) << MCAN_RXF0C_F0SA_Pos)))
+#define MCAN_RXF0C_F0S_Pos 16
+#define MCAN_RXF0C_F0S_Msk (0x7fu << MCAN_RXF0C_F0S_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address */
+#define MCAN_RXF0C_F0S(value) ((MCAN_RXF0C_F0S_Msk & ((value) << MCAN_RXF0C_F0S_Pos)))
+#define MCAN_RXF0C_F0WM_Pos 24
+#define MCAN_RXF0C_F0WM_Msk (0x7fu << MCAN_RXF0C_F0WM_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Watermark */
+#define MCAN_RXF0C_F0WM(value) ((MCAN_RXF0C_F0WM_Msk & ((value) << MCAN_RXF0C_F0WM_Pos)))
+#define MCAN_RXF0C_F0OM (0x1u << 31) /**< \brief (MCAN_RXF0C) FIFO 0 Operation Mode */
+/* -------- MCAN_RXF0S : (MCAN Offset: 0xA4) Receive FIFO 0 Status Register -------- */
+#define MCAN_RXF0S_F0FL_Pos 0
+#define MCAN_RXF0S_F0FL_Msk (0x7fu << MCAN_RXF0S_F0FL_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level */
+#define MCAN_RXF0S_F0GI_Pos 8
+#define MCAN_RXF0S_F0GI_Msk (0x3fu << MCAN_RXF0S_F0GI_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Get Index */
+#define MCAN_RXF0S_F0PI_Pos 16
+#define MCAN_RXF0S_F0PI_Msk (0x3fu << MCAN_RXF0S_F0PI_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Put Index */
+#define MCAN_RXF0S_F0F (0x1u << 24) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level */
+#define MCAN_RXF0S_RF0L (0x1u << 25) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Message Lost */
+/* -------- MCAN_RXF0A : (MCAN Offset: 0xA8) Receive FIFO 0 Acknowledge Register -------- */
+#define MCAN_RXF0A_F0AI_Pos 0
+#define MCAN_RXF0A_F0AI_Msk (0x3fu << MCAN_RXF0A_F0AI_Pos) /**< \brief (MCAN_RXF0A) Receive FIFO 0 Acknowledge Index */
+#define MCAN_RXF0A_F0AI(value) ((MCAN_RXF0A_F0AI_Msk & ((value) << MCAN_RXF0A_F0AI_Pos)))
+/* -------- MCAN_RXBC : (MCAN Offset: 0xAC) Receive Rx Buffer Configuration Register -------- */
+#define MCAN_RXBC_RBSA_Pos 2
+#define MCAN_RXBC_RBSA_Msk (0x3fffu << MCAN_RXBC_RBSA_Pos) /**< \brief (MCAN_RXBC) Receive Buffer Start Address */
+#define MCAN_RXBC_RBSA(value) ((MCAN_RXBC_RBSA_Msk & ((value) << MCAN_RXBC_RBSA_Pos)))
+/* -------- MCAN_RXF1C : (MCAN Offset: 0xB0) Receive FIFO 1 Configuration Register -------- */
+#define MCAN_RXF1C_F1SA_Pos 2
+#define MCAN_RXF1C_F1SA_Msk (0x3fffu << MCAN_RXF1C_F1SA_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address */
+#define MCAN_RXF1C_F1SA(value) ((MCAN_RXF1C_F1SA_Msk & ((value) << MCAN_RXF1C_F1SA_Pos)))
+#define MCAN_RXF1C_F1S_Pos 16
+#define MCAN_RXF1C_F1S_Msk (0x7fu << MCAN_RXF1C_F1S_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address */
+#define MCAN_RXF1C_F1S(value) ((MCAN_RXF1C_F1S_Msk & ((value) << MCAN_RXF1C_F1S_Pos)))
+#define MCAN_RXF1C_F1WM_Pos 24
+#define MCAN_RXF1C_F1WM_Msk (0x7fu << MCAN_RXF1C_F1WM_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Watermark */
+#define MCAN_RXF1C_F1WM(value) ((MCAN_RXF1C_F1WM_Msk & ((value) << MCAN_RXF1C_F1WM_Pos)))
+#define MCAN_RXF1C_F1OM (0x1u << 31) /**< \brief (MCAN_RXF1C) FIFO 1 Operation Mode */
+/* -------- MCAN_RXF1S : (MCAN Offset: 0xB4) Receive FIFO 1 Status Register -------- */
+#define MCAN_RXF1S_F1FL_Pos 0
+#define MCAN_RXF1S_F1FL_Msk (0x7fu << MCAN_RXF1S_F1FL_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level */
+#define MCAN_RXF1S_F1GI_Pos 8
+#define MCAN_RXF1S_F1GI_Msk (0x3fu << MCAN_RXF1S_F1GI_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Get Index */
+#define MCAN_RXF1S_F1PI_Pos 16
+#define MCAN_RXF1S_F1PI_Msk (0x3fu << MCAN_RXF1S_F1PI_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Put Index */
+#define MCAN_RXF1S_F1F (0x1u << 24) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level */
+#define MCAN_RXF1S_RF1L (0x1u << 25) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Message Lost */
+#define MCAN_RXF1S_DMS_Pos 30
+#define MCAN_RXF1S_DMS_Msk (0x3u << MCAN_RXF1S_DMS_Pos) /**< \brief (MCAN_RXF1S) Debug Message Status */
+#define   MCAN_RXF1S_DMS_IDLE (0x0u << 30) /**< \brief (MCAN_RXF1S) Idle state, wait for reception of debug messages, DMA request is cleared. */
+#define   MCAN_RXF1S_DMS_MSG_A (0x1u << 30) /**< \brief (MCAN_RXF1S) Debug message A received. */
+#define   MCAN_RXF1S_DMS_MSG_AB (0x2u << 30) /**< \brief (MCAN_RXF1S) Debug messages A, B received. */
+#define   MCAN_RXF1S_DMS_MSG_ABC (0x3u << 30) /**< \brief (MCAN_RXF1S) Debug messages A, B, C received, DMA request is set. */
+/* -------- MCAN_RXF1A : (MCAN Offset: 0xB8) Receive FIFO 1 Acknowledge Register -------- */
+#define MCAN_RXF1A_F1AI_Pos 0
+#define MCAN_RXF1A_F1AI_Msk (0x3fu << MCAN_RXF1A_F1AI_Pos) /**< \brief (MCAN_RXF1A) Receive FIFO 1 Acknowledge Index */
+#define MCAN_RXF1A_F1AI(value) ((MCAN_RXF1A_F1AI_Msk & ((value) << MCAN_RXF1A_F1AI_Pos)))
+/* -------- MCAN_RXESC : (MCAN Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register -------- */
+#define MCAN_RXESC_F0DS_Pos 0
+#define MCAN_RXESC_F0DS_Msk (0x7u << MCAN_RXESC_F0DS_Pos) /**< \brief (MCAN_RXESC) Receive FIFO 0 Data Field Size */
+#define MCAN_RXESC_F0DS(value) ((MCAN_RXESC_F0DS_Msk & ((value) << MCAN_RXESC_F0DS_Pos)))
+#define   MCAN_RXESC_F0DS_8_BYTE (0x0u << 0) /**< \brief (MCAN_RXESC) 8-byte data field */
+#define   MCAN_RXESC_F0DS_12_BYTE (0x1u << 0) /**< \brief (MCAN_RXESC) 12-byte data field */
+#define   MCAN_RXESC_F0DS_16_BYTE (0x2u << 0) /**< \brief (MCAN_RXESC) 16-byte data field */
+#define   MCAN_RXESC_F0DS_20_BYTE (0x3u << 0) /**< \brief (MCAN_RXESC) 20-byte data field */
+#define   MCAN_RXESC_F0DS_24_BYTE (0x4u << 0) /**< \brief (MCAN_RXESC) 24-byte data field */
+#define   MCAN_RXESC_F0DS_32_BYTE (0x5u << 0) /**< \brief (MCAN_RXESC) 32-byte data field */
+#define   MCAN_RXESC_F0DS_48_BYTE (0x6u << 0) /**< \brief (MCAN_RXESC) 48-byte data field */
+#define   MCAN_RXESC_F0DS_64_BYTE (0x7u << 0) /**< \brief (MCAN_RXESC) 64-byte data field */
+#define MCAN_RXESC_F1DS_Pos 4
+#define MCAN_RXESC_F1DS_Msk (0x7u << MCAN_RXESC_F1DS_Pos) /**< \brief (MCAN_RXESC) Receive FIFO 1 Data Field Size */
+#define MCAN_RXESC_F1DS(value) ((MCAN_RXESC_F1DS_Msk & ((value) << MCAN_RXESC_F1DS_Pos)))
+#define   MCAN_RXESC_F1DS_8_BYTE (0x0u << 4) /**< \brief (MCAN_RXESC) 8-byte data field */
+#define   MCAN_RXESC_F1DS_12_BYTE (0x1u << 4) /**< \brief (MCAN_RXESC) 12-byte data field */
+#define   MCAN_RXESC_F1DS_16_BYTE (0x2u << 4) /**< \brief (MCAN_RXESC) 16-byte data field */
+#define   MCAN_RXESC_F1DS_20_BYTE (0x3u << 4) /**< \brief (MCAN_RXESC) 20-byte data field */
+#define   MCAN_RXESC_F1DS_24_BYTE (0x4u << 4) /**< \brief (MCAN_RXESC) 24-byte data field */
+#define   MCAN_RXESC_F1DS_32_BYTE (0x5u << 4) /**< \brief (MCAN_RXESC) 32-byte data field */
+#define   MCAN_RXESC_F1DS_48_BYTE (0x6u << 4) /**< \brief (MCAN_RXESC) 48-byte data field */
+#define   MCAN_RXESC_F1DS_64_BYTE (0x7u << 4) /**< \brief (MCAN_RXESC) 64-byte data field */
+#define MCAN_RXESC_RBDS_Pos 8
+#define MCAN_RXESC_RBDS_Msk (0x7u << MCAN_RXESC_RBDS_Pos) /**< \brief (MCAN_RXESC) Receive Buffer Data Field Size */
+#define MCAN_RXESC_RBDS(value) ((MCAN_RXESC_RBDS_Msk & ((value) << MCAN_RXESC_RBDS_Pos)))
+#define   MCAN_RXESC_RBDS_8_BYTE (0x0u << 8) /**< \brief (MCAN_RXESC) 8-byte data field */
+#define   MCAN_RXESC_RBDS_12_BYTE (0x1u << 8) /**< \brief (MCAN_RXESC) 12-byte data field */
+#define   MCAN_RXESC_RBDS_16_BYTE (0x2u << 8) /**< \brief (MCAN_RXESC) 16-byte data field */
+#define   MCAN_RXESC_RBDS_20_BYTE (0x3u << 8) /**< \brief (MCAN_RXESC) 20-byte data field */
+#define   MCAN_RXESC_RBDS_24_BYTE (0x4u << 8) /**< \brief (MCAN_RXESC) 24-byte data field */
+#define   MCAN_RXESC_RBDS_32_BYTE (0x5u << 8) /**< \brief (MCAN_RXESC) 32-byte data field */
+#define   MCAN_RXESC_RBDS_48_BYTE (0x6u << 8) /**< \brief (MCAN_RXESC) 48-byte data field */
+#define   MCAN_RXESC_RBDS_64_BYTE (0x7u << 8) /**< \brief (MCAN_RXESC) 64-byte data field */
+/* -------- MCAN_TXBC : (MCAN Offset: 0xC0) Transmit Buffer Configuration Register -------- */
+#define MCAN_TXBC_TBSA_Pos 2
+#define MCAN_TXBC_TBSA_Msk (0x3fffu << MCAN_TXBC_TBSA_Pos) /**< \brief (MCAN_TXBC) Tx Buffers Start Address */
+#define MCAN_TXBC_TBSA(value) ((MCAN_TXBC_TBSA_Msk & ((value) << MCAN_TXBC_TBSA_Pos)))
+#define MCAN_TXBC_NDTB_Pos 16
+#define MCAN_TXBC_NDTB_Msk (0x3fu << MCAN_TXBC_NDTB_Pos) /**< \brief (MCAN_TXBC) Number of Dedicated Transmit Buffers */
+#define MCAN_TXBC_NDTB(value) ((MCAN_TXBC_NDTB_Msk & ((value) << MCAN_TXBC_NDTB_Pos)))
+#define MCAN_TXBC_TFQS_Pos 24
+#define MCAN_TXBC_TFQS_Msk (0x3fu << MCAN_TXBC_TFQS_Pos) /**< \brief (MCAN_TXBC) Transmit FIFO/Queue Size */
+#define MCAN_TXBC_TFQS(value) ((MCAN_TXBC_TFQS_Msk & ((value) << MCAN_TXBC_TFQS_Pos)))
+#define MCAN_TXBC_TFQM (0x1u << 30) /**< \brief (MCAN_TXBC) Tx FIFO/Queue Mode */
+/* -------- MCAN_TXFQS : (MCAN Offset: 0xC4) Transmit FIFO/Queue Status Register -------- */
+#define MCAN_TXFQS_TFFL_Pos 0
+#define MCAN_TXFQS_TFFL_Msk (0x3fu << MCAN_TXFQS_TFFL_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO Free Level */
+#define MCAN_TXFQS_TFGI_Pos 8
+#define MCAN_TXFQS_TFGI_Msk (0x1fu << MCAN_TXFQS_TFGI_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO Get Index */
+#define MCAN_TXFQS_TFQPI_Pos 16
+#define MCAN_TXFQS_TFQPI_Msk (0x1fu << MCAN_TXFQS_TFQPI_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO/Queue Put Index */
+#define MCAN_TXFQS_TFQF (0x1u << 21) /**< \brief (MCAN_TXFQS) Tx FIFO/Queue Full */
+/* -------- MCAN_TXESC : (MCAN Offset: 0xC8) Transmit Buffer Element Size Configuration Register -------- */
+#define MCAN_TXESC_TBDS_Pos 0
+#define MCAN_TXESC_TBDS_Msk (0x7u << MCAN_TXESC_TBDS_Pos) /**< \brief (MCAN_TXESC) Tx Buffer Data Field Size */
+#define MCAN_TXESC_TBDS(value) ((MCAN_TXESC_TBDS_Msk & ((value) << MCAN_TXESC_TBDS_Pos)))
+#define   MCAN_TXESC_TBDS_8_BYTE (0x0u << 0) /**< \brief (MCAN_TXESC) 8-byte data field */
+#define   MCAN_TXESC_TBDS_12_BYTE (0x1u << 0) /**< \brief (MCAN_TXESC) 12-byte data field */
+#define   MCAN_TXESC_TBDS_16_BYTE (0x2u << 0) /**< \brief (MCAN_TXESC) 16-byte data field */
+#define   MCAN_TXESC_TBDS_20_BYTE (0x3u << 0) /**< \brief (MCAN_TXESC) 20-byte data field */
+#define   MCAN_TXESC_TBDS_24_BYTE (0x4u << 0) /**< \brief (MCAN_TXESC) 24-byte data field */
+#define   MCAN_TXESC_TBDS_32_BYTE (0x5u << 0) /**< \brief (MCAN_TXESC) 32-byte data field */
+#define   MCAN_TXESC_TBDS_48_BYTE (0x6u << 0) /**< \brief (MCAN_TXESC) 48-byte data field */
+#define   MCAN_TXESC_TBDS_64_BYTE (0x7u << 0) /**< \brief (MCAN_TXESC) 64-byte data field */
+/* -------- MCAN_TXBRP : (MCAN Offset: 0xCC) Transmit Buffer Request Pending Register -------- */
+#define MCAN_TXBRP_TRP0 (0x1u << 0) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 0 */
+#define MCAN_TXBRP_TRP1 (0x1u << 1) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 1 */
+#define MCAN_TXBRP_TRP2 (0x1u << 2) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 2 */
+#define MCAN_TXBRP_TRP3 (0x1u << 3) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 3 */
+#define MCAN_TXBRP_TRP4 (0x1u << 4) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 4 */
+#define MCAN_TXBRP_TRP5 (0x1u << 5) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 5 */
+#define MCAN_TXBRP_TRP6 (0x1u << 6) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 6 */
+#define MCAN_TXBRP_TRP7 (0x1u << 7) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 7 */
+#define MCAN_TXBRP_TRP8 (0x1u << 8) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 8 */
+#define MCAN_TXBRP_TRP9 (0x1u << 9) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 9 */
+#define MCAN_TXBRP_TRP10 (0x1u << 10) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 10 */
+#define MCAN_TXBRP_TRP11 (0x1u << 11) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 11 */
+#define MCAN_TXBRP_TRP12 (0x1u << 12) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 12 */
+#define MCAN_TXBRP_TRP13 (0x1u << 13) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 13 */
+#define MCAN_TXBRP_TRP14 (0x1u << 14) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 14 */
+#define MCAN_TXBRP_TRP15 (0x1u << 15) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 15 */
+#define MCAN_TXBRP_TRP16 (0x1u << 16) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 16 */
+#define MCAN_TXBRP_TRP17 (0x1u << 17) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 17 */
+#define MCAN_TXBRP_TRP18 (0x1u << 18) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 18 */
+#define MCAN_TXBRP_TRP19 (0x1u << 19) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 19 */
+#define MCAN_TXBRP_TRP20 (0x1u << 20) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 20 */
+#define MCAN_TXBRP_TRP21 (0x1u << 21) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 21 */
+#define MCAN_TXBRP_TRP22 (0x1u << 22) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 22 */
+#define MCAN_TXBRP_TRP23 (0x1u << 23) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 23 */
+#define MCAN_TXBRP_TRP24 (0x1u << 24) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 24 */
+#define MCAN_TXBRP_TRP25 (0x1u << 25) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 25 */
+#define MCAN_TXBRP_TRP26 (0x1u << 26) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 26 */
+#define MCAN_TXBRP_TRP27 (0x1u << 27) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 27 */
+#define MCAN_TXBRP_TRP28 (0x1u << 28) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 28 */
+#define MCAN_TXBRP_TRP29 (0x1u << 29) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 29 */
+#define MCAN_TXBRP_TRP30 (0x1u << 30) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 30 */
+#define MCAN_TXBRP_TRP31 (0x1u << 31) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 31 */
+/* -------- MCAN_TXBAR : (MCAN Offset: 0xD0) Transmit Buffer Add Request Register -------- */
+#define MCAN_TXBAR_AR0 (0x1u << 0) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 0 */
+#define MCAN_TXBAR_AR1 (0x1u << 1) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 1 */
+#define MCAN_TXBAR_AR2 (0x1u << 2) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 2 */
+#define MCAN_TXBAR_AR3 (0x1u << 3) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 3 */
+#define MCAN_TXBAR_AR4 (0x1u << 4) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 4 */
+#define MCAN_TXBAR_AR5 (0x1u << 5) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 5 */
+#define MCAN_TXBAR_AR6 (0x1u << 6) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 6 */
+#define MCAN_TXBAR_AR7 (0x1u << 7) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 7 */
+#define MCAN_TXBAR_AR8 (0x1u << 8) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 8 */
+#define MCAN_TXBAR_AR9 (0x1u << 9) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 9 */
+#define MCAN_TXBAR_AR10 (0x1u << 10) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 10 */
+#define MCAN_TXBAR_AR11 (0x1u << 11) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 11 */
+#define MCAN_TXBAR_AR12 (0x1u << 12) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 12 */
+#define MCAN_TXBAR_AR13 (0x1u << 13) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 13 */
+#define MCAN_TXBAR_AR14 (0x1u << 14) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 14 */
+#define MCAN_TXBAR_AR15 (0x1u << 15) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 15 */
+#define MCAN_TXBAR_AR16 (0x1u << 16) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 16 */
+#define MCAN_TXBAR_AR17 (0x1u << 17) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 17 */
+#define MCAN_TXBAR_AR18 (0x1u << 18) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 18 */
+#define MCAN_TXBAR_AR19 (0x1u << 19) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 19 */
+#define MCAN_TXBAR_AR20 (0x1u << 20) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 20 */
+#define MCAN_TXBAR_AR21 (0x1u << 21) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 21 */
+#define MCAN_TXBAR_AR22 (0x1u << 22) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 22 */
+#define MCAN_TXBAR_AR23 (0x1u << 23) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 23 */
+#define MCAN_TXBAR_AR24 (0x1u << 24) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 24 */
+#define MCAN_TXBAR_AR25 (0x1u << 25) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 25 */
+#define MCAN_TXBAR_AR26 (0x1u << 26) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 26 */
+#define MCAN_TXBAR_AR27 (0x1u << 27) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 27 */
+#define MCAN_TXBAR_AR28 (0x1u << 28) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 28 */
+#define MCAN_TXBAR_AR29 (0x1u << 29) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 29 */
+#define MCAN_TXBAR_AR30 (0x1u << 30) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 30 */
+#define MCAN_TXBAR_AR31 (0x1u << 31) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 31 */
+/* -------- MCAN_TXBCR : (MCAN Offset: 0xD4) Transmit Buffer Cancellation Request Register -------- */
+#define MCAN_TXBCR_CR0 (0x1u << 0) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 0 */
+#define MCAN_TXBCR_CR1 (0x1u << 1) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 1 */
+#define MCAN_TXBCR_CR2 (0x1u << 2) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 2 */
+#define MCAN_TXBCR_CR3 (0x1u << 3) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 3 */
+#define MCAN_TXBCR_CR4 (0x1u << 4) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 4 */
+#define MCAN_TXBCR_CR5 (0x1u << 5) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 5 */
+#define MCAN_TXBCR_CR6 (0x1u << 6) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 6 */
+#define MCAN_TXBCR_CR7 (0x1u << 7) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 7 */
+#define MCAN_TXBCR_CR8 (0x1u << 8) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 8 */
+#define MCAN_TXBCR_CR9 (0x1u << 9) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 9 */
+#define MCAN_TXBCR_CR10 (0x1u << 10) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 10 */
+#define MCAN_TXBCR_CR11 (0x1u << 11) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 11 */
+#define MCAN_TXBCR_CR12 (0x1u << 12) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 12 */
+#define MCAN_TXBCR_CR13 (0x1u << 13) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 13 */
+#define MCAN_TXBCR_CR14 (0x1u << 14) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 14 */
+#define MCAN_TXBCR_CR15 (0x1u << 15) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 15 */
+#define MCAN_TXBCR_CR16 (0x1u << 16) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 16 */
+#define MCAN_TXBCR_CR17 (0x1u << 17) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 17 */
+#define MCAN_TXBCR_CR18 (0x1u << 18) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 18 */
+#define MCAN_TXBCR_CR19 (0x1u << 19) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 19 */
+#define MCAN_TXBCR_CR20 (0x1u << 20) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 20 */
+#define MCAN_TXBCR_CR21 (0x1u << 21) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 21 */
+#define MCAN_TXBCR_CR22 (0x1u << 22) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 22 */
+#define MCAN_TXBCR_CR23 (0x1u << 23) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 23 */
+#define MCAN_TXBCR_CR24 (0x1u << 24) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 24 */
+#define MCAN_TXBCR_CR25 (0x1u << 25) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 25 */
+#define MCAN_TXBCR_CR26 (0x1u << 26) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 26 */
+#define MCAN_TXBCR_CR27 (0x1u << 27) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 27 */
+#define MCAN_TXBCR_CR28 (0x1u << 28) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 28 */
+#define MCAN_TXBCR_CR29 (0x1u << 29) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 29 */
+#define MCAN_TXBCR_CR30 (0x1u << 30) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 30 */
+#define MCAN_TXBCR_CR31 (0x1u << 31) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 31 */
+/* -------- MCAN_TXBTO : (MCAN Offset: 0xD8) Transmit Buffer Transmission Occurred Register -------- */
+#define MCAN_TXBTO_TO0 (0x1u << 0) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 0 */
+#define MCAN_TXBTO_TO1 (0x1u << 1) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 1 */
+#define MCAN_TXBTO_TO2 (0x1u << 2) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 2 */
+#define MCAN_TXBTO_TO3 (0x1u << 3) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 3 */
+#define MCAN_TXBTO_TO4 (0x1u << 4) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 4 */
+#define MCAN_TXBTO_TO5 (0x1u << 5) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 5 */
+#define MCAN_TXBTO_TO6 (0x1u << 6) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 6 */
+#define MCAN_TXBTO_TO7 (0x1u << 7) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 7 */
+#define MCAN_TXBTO_TO8 (0x1u << 8) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 8 */
+#define MCAN_TXBTO_TO9 (0x1u << 9) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 9 */
+#define MCAN_TXBTO_TO10 (0x1u << 10) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 10 */
+#define MCAN_TXBTO_TO11 (0x1u << 11) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 11 */
+#define MCAN_TXBTO_TO12 (0x1u << 12) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 12 */
+#define MCAN_TXBTO_TO13 (0x1u << 13) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 13 */
+#define MCAN_TXBTO_TO14 (0x1u << 14) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 14 */
+#define MCAN_TXBTO_TO15 (0x1u << 15) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 15 */
+#define MCAN_TXBTO_TO16 (0x1u << 16) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 16 */
+#define MCAN_TXBTO_TO17 (0x1u << 17) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 17 */
+#define MCAN_TXBTO_TO18 (0x1u << 18) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 18 */
+#define MCAN_TXBTO_TO19 (0x1u << 19) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 19 */
+#define MCAN_TXBTO_TO20 (0x1u << 20) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 20 */
+#define MCAN_TXBTO_TO21 (0x1u << 21) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 21 */
+#define MCAN_TXBTO_TO22 (0x1u << 22) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 22 */
+#define MCAN_TXBTO_TO23 (0x1u << 23) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 23 */
+#define MCAN_TXBTO_TO24 (0x1u << 24) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 24 */
+#define MCAN_TXBTO_TO25 (0x1u << 25) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 25 */
+#define MCAN_TXBTO_TO26 (0x1u << 26) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 26 */
+#define MCAN_TXBTO_TO27 (0x1u << 27) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 27 */
+#define MCAN_TXBTO_TO28 (0x1u << 28) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 28 */
+#define MCAN_TXBTO_TO29 (0x1u << 29) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 29 */
+#define MCAN_TXBTO_TO30 (0x1u << 30) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 30 */
+#define MCAN_TXBTO_TO31 (0x1u << 31) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 31 */
+/* -------- MCAN_TXBCF : (MCAN Offset: 0xDC) Transmit Buffer Cancellation Finished Register -------- */
+#define MCAN_TXBCF_CF0 (0x1u << 0) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 0 */
+#define MCAN_TXBCF_CF1 (0x1u << 1) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 1 */
+#define MCAN_TXBCF_CF2 (0x1u << 2) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 2 */
+#define MCAN_TXBCF_CF3 (0x1u << 3) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 3 */
+#define MCAN_TXBCF_CF4 (0x1u << 4) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 4 */
+#define MCAN_TXBCF_CF5 (0x1u << 5) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 5 */
+#define MCAN_TXBCF_CF6 (0x1u << 6) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 6 */
+#define MCAN_TXBCF_CF7 (0x1u << 7) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 7 */
+#define MCAN_TXBCF_CF8 (0x1u << 8) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 8 */
+#define MCAN_TXBCF_CF9 (0x1u << 9) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 9 */
+#define MCAN_TXBCF_CF10 (0x1u << 10) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 10 */
+#define MCAN_TXBCF_CF11 (0x1u << 11) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 11 */
+#define MCAN_TXBCF_CF12 (0x1u << 12) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 12 */
+#define MCAN_TXBCF_CF13 (0x1u << 13) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 13 */
+#define MCAN_TXBCF_CF14 (0x1u << 14) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 14 */
+#define MCAN_TXBCF_CF15 (0x1u << 15) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 15 */
+#define MCAN_TXBCF_CF16 (0x1u << 16) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 16 */
+#define MCAN_TXBCF_CF17 (0x1u << 17) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 17 */
+#define MCAN_TXBCF_CF18 (0x1u << 18) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 18 */
+#define MCAN_TXBCF_CF19 (0x1u << 19) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 19 */
+#define MCAN_TXBCF_CF20 (0x1u << 20) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 20 */
+#define MCAN_TXBCF_CF21 (0x1u << 21) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 21 */
+#define MCAN_TXBCF_CF22 (0x1u << 22) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 22 */
+#define MCAN_TXBCF_CF23 (0x1u << 23) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 23 */
+#define MCAN_TXBCF_CF24 (0x1u << 24) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 24 */
+#define MCAN_TXBCF_CF25 (0x1u << 25) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 25 */
+#define MCAN_TXBCF_CF26 (0x1u << 26) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 26 */
+#define MCAN_TXBCF_CF27 (0x1u << 27) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 27 */
+#define MCAN_TXBCF_CF28 (0x1u << 28) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 28 */
+#define MCAN_TXBCF_CF29 (0x1u << 29) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 29 */
+#define MCAN_TXBCF_CF30 (0x1u << 30) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 30 */
+#define MCAN_TXBCF_CF31 (0x1u << 31) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 31 */
+/* -------- MCAN_TXBTIE : (MCAN Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register -------- */
+#define MCAN_TXBTIE_TIE0 (0x1u << 0) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 0 */
+#define MCAN_TXBTIE_TIE1 (0x1u << 1) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 1 */
+#define MCAN_TXBTIE_TIE2 (0x1u << 2) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 2 */
+#define MCAN_TXBTIE_TIE3 (0x1u << 3) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 3 */
+#define MCAN_TXBTIE_TIE4 (0x1u << 4) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 4 */
+#define MCAN_TXBTIE_TIE5 (0x1u << 5) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 5 */
+#define MCAN_TXBTIE_TIE6 (0x1u << 6) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 6 */
+#define MCAN_TXBTIE_TIE7 (0x1u << 7) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 7 */
+#define MCAN_TXBTIE_TIE8 (0x1u << 8) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 8 */
+#define MCAN_TXBTIE_TIE9 (0x1u << 9) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 9 */
+#define MCAN_TXBTIE_TIE10 (0x1u << 10) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 10 */
+#define MCAN_TXBTIE_TIE11 (0x1u << 11) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 11 */
+#define MCAN_TXBTIE_TIE12 (0x1u << 12) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 12 */
+#define MCAN_TXBTIE_TIE13 (0x1u << 13) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 13 */
+#define MCAN_TXBTIE_TIE14 (0x1u << 14) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 14 */
+#define MCAN_TXBTIE_TIE15 (0x1u << 15) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 15 */
+#define MCAN_TXBTIE_TIE16 (0x1u << 16) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 16 */
+#define MCAN_TXBTIE_TIE17 (0x1u << 17) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 17 */
+#define MCAN_TXBTIE_TIE18 (0x1u << 18) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 18 */
+#define MCAN_TXBTIE_TIE19 (0x1u << 19) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 19 */
+#define MCAN_TXBTIE_TIE20 (0x1u << 20) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 20 */
+#define MCAN_TXBTIE_TIE21 (0x1u << 21) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 21 */
+#define MCAN_TXBTIE_TIE22 (0x1u << 22) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 22 */
+#define MCAN_TXBTIE_TIE23 (0x1u << 23) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 23 */
+#define MCAN_TXBTIE_TIE24 (0x1u << 24) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 24 */
+#define MCAN_TXBTIE_TIE25 (0x1u << 25) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 25 */
+#define MCAN_TXBTIE_TIE26 (0x1u << 26) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 26 */
+#define MCAN_TXBTIE_TIE27 (0x1u << 27) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 27 */
+#define MCAN_TXBTIE_TIE28 (0x1u << 28) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 28 */
+#define MCAN_TXBTIE_TIE29 (0x1u << 29) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 29 */
+#define MCAN_TXBTIE_TIE30 (0x1u << 30) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 30 */
+#define MCAN_TXBTIE_TIE31 (0x1u << 31) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 31 */
+/* -------- MCAN_TXBCIE : (MCAN Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register -------- */
+#define MCAN_TXBCIE_CFIE0 (0x1u << 0) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 0 */
+#define MCAN_TXBCIE_CFIE1 (0x1u << 1) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 1 */
+#define MCAN_TXBCIE_CFIE2 (0x1u << 2) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 2 */
+#define MCAN_TXBCIE_CFIE3 (0x1u << 3) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 3 */
+#define MCAN_TXBCIE_CFIE4 (0x1u << 4) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 4 */
+#define MCAN_TXBCIE_CFIE5 (0x1u << 5) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 5 */
+#define MCAN_TXBCIE_CFIE6 (0x1u << 6) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 6 */
+#define MCAN_TXBCIE_CFIE7 (0x1u << 7) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 7 */
+#define MCAN_TXBCIE_CFIE8 (0x1u << 8) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 8 */
+#define MCAN_TXBCIE_CFIE9 (0x1u << 9) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 9 */
+#define MCAN_TXBCIE_CFIE10 (0x1u << 10) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 10 */
+#define MCAN_TXBCIE_CFIE11 (0x1u << 11) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 11 */
+#define MCAN_TXBCIE_CFIE12 (0x1u << 12) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 12 */
+#define MCAN_TXBCIE_CFIE13 (0x1u << 13) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 13 */
+#define MCAN_TXBCIE_CFIE14 (0x1u << 14) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 14 */
+#define MCAN_TXBCIE_CFIE15 (0x1u << 15) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 15 */
+#define MCAN_TXBCIE_CFIE16 (0x1u << 16) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 16 */
+#define MCAN_TXBCIE_CFIE17 (0x1u << 17) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 17 */
+#define MCAN_TXBCIE_CFIE18 (0x1u << 18) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 18 */
+#define MCAN_TXBCIE_CFIE19 (0x1u << 19) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 19 */
+#define MCAN_TXBCIE_CFIE20 (0x1u << 20) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 20 */
+#define MCAN_TXBCIE_CFIE21 (0x1u << 21) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 21 */
+#define MCAN_TXBCIE_CFIE22 (0x1u << 22) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 22 */
+#define MCAN_TXBCIE_CFIE23 (0x1u << 23) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 23 */
+#define MCAN_TXBCIE_CFIE24 (0x1u << 24) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 24 */
+#define MCAN_TXBCIE_CFIE25 (0x1u << 25) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 25 */
+#define MCAN_TXBCIE_CFIE26 (0x1u << 26) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 26 */
+#define MCAN_TXBCIE_CFIE27 (0x1u << 27) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 27 */
+#define MCAN_TXBCIE_CFIE28 (0x1u << 28) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 28 */
+#define MCAN_TXBCIE_CFIE29 (0x1u << 29) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 29 */
+#define MCAN_TXBCIE_CFIE30 (0x1u << 30) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 30 */
+#define MCAN_TXBCIE_CFIE31 (0x1u << 31) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 31 */
+/* -------- MCAN_TXEFC : (MCAN Offset: 0xF0) Transmit Event FIFO Configuration Register -------- */
+#define MCAN_TXEFC_EFSA_Pos 2
+#define MCAN_TXEFC_EFSA_Msk (0x3fffu << MCAN_TXEFC_EFSA_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Start Address */
+#define MCAN_TXEFC_EFSA(value) ((MCAN_TXEFC_EFSA_Msk & ((value) << MCAN_TXEFC_EFSA_Pos)))
+#define MCAN_TXEFC_EFS_Pos 16
+#define MCAN_TXEFC_EFS_Msk (0x3fu << MCAN_TXEFC_EFS_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Size */
+#define MCAN_TXEFC_EFS(value) ((MCAN_TXEFC_EFS_Msk & ((value) << MCAN_TXEFC_EFS_Pos)))
+#define MCAN_TXEFC_EFWM_Pos 24
+#define MCAN_TXEFC_EFWM_Msk (0x3fu << MCAN_TXEFC_EFWM_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Watermark */
+#define MCAN_TXEFC_EFWM(value) ((MCAN_TXEFC_EFWM_Msk & ((value) << MCAN_TXEFC_EFWM_Pos)))
+/* -------- MCAN_TXEFS : (MCAN Offset: 0xF4) Transmit Event FIFO Status Register -------- */
+#define MCAN_TXEFS_EFFL_Pos 0
+#define MCAN_TXEFS_EFFL_Msk (0x3fu << MCAN_TXEFS_EFFL_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Fill Level */
+#define MCAN_TXEFS_EFGI_Pos 8
+#define MCAN_TXEFS_EFGI_Msk (0x1fu << MCAN_TXEFS_EFGI_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Get Index */
+#define MCAN_TXEFS_EFPI_Pos 16
+#define MCAN_TXEFS_EFPI_Msk (0x1fu << MCAN_TXEFS_EFPI_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Put Index */
+#define MCAN_TXEFS_EFF (0x1u << 24) /**< \brief (MCAN_TXEFS) Event FIFO Full */
+#define MCAN_TXEFS_TEFL (0x1u << 25) /**< \brief (MCAN_TXEFS) Tx Event FIFO Element Lost */
+/* -------- MCAN_TXEFA : (MCAN Offset: 0xF8) Transmit Event FIFO Acknowledge Register -------- */
+#define MCAN_TXEFA_EFAI_Pos 0
+#define MCAN_TXEFA_EFAI_Msk (0x1fu << MCAN_TXEFA_EFAI_Pos) /**< \brief (MCAN_TXEFA) Event FIFO Acknowledge Index */
+#define MCAN_TXEFA_EFAI(value) ((MCAN_TXEFA_EFAI_Msk & ((value) << MCAN_TXEFA_EFAI_Pos)))
+/* -------- MCAN Message RAM : Standard Message ID Rx Filter Element -------- */
+#define MCAN_RAM_FILT_STD_SIZE (1u) /**< \brief Size of the 11-bit Message ID Rx Filter Element, in words */
+#define MCAN_RAM_FILT_SFID2_Pos 0
+#define MCAN_RAM_FILT_SFID2_Msk (0x7ffu << MCAN_RAM_FILT_SFID2_Pos) /**< \brief (S0) Standard Filter ID 2 */
+#define MCAN_RAM_FILT_SFID2(value) ((MCAN_RAM_FILT_SFID2_Msk & ((value) << MCAN_RAM_FILT_SFID2_Pos)))
+#define   MCAN_RAM_FILT_SFID2_BUF_IDX_Pos 0
+#define   MCAN_RAM_FILT_SFID2_BUF_IDX_Msk (0x3fu << MCAN_RAM_FILT_SFID2_BUF_IDX_Pos) /**< \brief (S0) Index of Rx Buffer for storage of a matching message. */
+#define   MCAN_RAM_FILT_SFID2_BUF_IDX(value) ((MCAN_RAM_FILT_SFID2_BUF_IDX_Msk & ((value) << MCAN_RAM_FILT_SFID2_BUF_IDX_Pos)))
+#define   MCAN_RAM_FILT_SFID2_FE0 (0x1u << 6) /**< \brief (S0) Generate a pulse at m_can_fe0 filter event pin in case the filter matches. */
+#define   MCAN_RAM_FILT_SFID2_FE1 (0x1u << 7) /**< \brief (S0) Generate a pulse at m_can_fe1 filter event pin in case the filter matches. */
+#define   MCAN_RAM_FILT_SFID2_FE2 (0x1u << 8) /**< \brief (S0) Generate a pulse at m_can_fe2 filter event pin in case the filter matches. */
+#define   MCAN_RAM_FILT_SFID2_BUF (0x0u << 9) /**< \brief (S0) Store message in a Rx buffer. */
+#define   MCAN_RAM_FILT_SFID2_DBG_A (0x1u << 9) /**< \brief (S0) Debug Message A. */
+#define   MCAN_RAM_FILT_SFID2_DBG_B (0x2u << 9) /**< \brief (S0) Debug Message B. */
+#define   MCAN_RAM_FILT_SFID2_DBG_C (0x3u << 9) /**< \brief (S0) Debug Message C. */
+#define MCAN_RAM_FILT_SFID1_Pos 16
+#define MCAN_RAM_FILT_SFID1_Msk (0x7ffu << MCAN_RAM_FILT_SFID1_Pos) /**< \brief (S0) Standard Filter ID 1 */
+#define MCAN_RAM_FILT_SFID1(value) ((MCAN_RAM_FILT_SFID1_Msk & ((value) << MCAN_RAM_FILT_SFID1_Pos)))
+#define MCAN_RAM_FILT_SFEC_Pos 27
+#define MCAN_RAM_FILT_SFEC_Msk (0x7u << MCAN_RAM_FILT_SFEC_Pos) /**< \brief (S0) Standard Filter Element Configuration */
+#define MCAN_RAM_FILT_SFEC(value) ((MCAN_RAM_FILT_SFEC_Msk & ((value) << MCAN_RAM_FILT_SFEC_Pos)))
+#define   MCAN_RAM_FILT_SFEC_DIS (0x0u << 27) /**< \brief (S0) Disable filter element. */
+#define   MCAN_RAM_FILT_SFEC_FIFO0 (0x1u << 27) /**< \brief (S0) Store in Rx FIFO 0 if filter matches. */
+#define   MCAN_RAM_FILT_SFEC_FIFO1 (0x2u << 27) /**< \brief (S0) Store in Rx FIFO 1 if filter matches. */
+#define   MCAN_RAM_FILT_SFEC_INV (0x3u << 27) /**< \brief (S0) Reject ID if filter matches. */
+#define   MCAN_RAM_FILT_SFEC_PTY (0x4u << 27) /**< \brief (S0) Set priority if filter matches. */
+#define   MCAN_RAM_FILT_SFEC_PTY_FIFO0 (0x5u << 27) /**< \brief (S0) Set priority and store in FIFO 0 if filter matches. */
+#define   MCAN_RAM_FILT_SFEC_PTY_FIFO1 (0x6u << 27) /**< \brief (S0) Set priority and store in FIFO 1 if filter matches. */
+#define   MCAN_RAM_FILT_SFEC_BUF (0x7u << 27) /**< \brief (S0) Store into Rx Buffer or as debug message. */
+#define MCAN_RAM_FILT_SFT_Pos 30
+#define MCAN_RAM_FILT_SFT_Msk (0x3u << MCAN_RAM_FILT_SFT_Pos) /**< \brief (S0) Standard Filter Type */
+#define MCAN_RAM_FILT_SFT(value) ((MCAN_RAM_FILT_SFT_Msk & ((value) << MCAN_RAM_FILT_SFT_Pos)))
+#define   MCAN_RAM_FILT_SFT_RANGE (0x0u << 30) /**< \brief (S0) Range filter from SF1ID to SF2ID. */
+#define   MCAN_RAM_FILT_SFT_DUAL_ID (0x1u << 30) /**< \brief (S0) Dual ID filter for SF1ID or SF2ID. */
+#define   MCAN_RAM_FILT_SFT_CLASSIC (0x2u << 30) /**< \brief (S0) Classic filter: SF1ID = filter, SF2ID = mask. */
+/* -------- MCAN Message RAM : Extended Message ID Rx Filter Element : F0 Word -------- */
+#define MCAN_RAM_FILT_EXT_SIZE (2u) /**< \brief Size of the 29-bit Message ID Rx Filter Element, in words */
+#define MCAN_RAM_FILT_EFID1_Pos 0
+#define MCAN_RAM_FILT_EFID1_Msk (0x1fffffffu << MCAN_RAM_FILT_EFID1_Pos) /**< \brief (F0) Standard Filter ID 1 */
+#define MCAN_RAM_FILT_EFID1(value) ((MCAN_RAM_FILT_EFID1_Msk & ((value) << MCAN_RAM_FILT_EFID1_Pos)))
+#define MCAN_RAM_FILT_EFEC_Pos 29
+#define MCAN_RAM_FILT_EFEC_Msk (0x7u << MCAN_RAM_FILT_EFEC_Pos) /**< \brief (F0) Extended Filter Element Configuration */
+#define MCAN_RAM_FILT_EFEC(value) ((MCAN_RAM_FILT_EFEC_Msk & ((value) << MCAN_RAM_FILT_EFEC_Pos)))
+#define   MCAN_RAM_FILT_EFEC_DIS (0x0u << 29) /**< \brief (F0) Disable filter element. */
+#define   MCAN_RAM_FILT_EFEC_FIFO0 (0x1u << 29) /**< \brief (F0) Store in Rx FIFO 0 if filter matches. */
+#define   MCAN_RAM_FILT_EFEC_FIFO1 (0x2u << 29) /**< \brief (F0) Store in Rx FIFO 1 if filter matches. */
+#define   MCAN_RAM_FILT_EFEC_INV (0x3u << 29) /**< \brief (F0) Reject ID if filter matches. */
+#define   MCAN_RAM_FILT_EFEC_PTY (0x4u << 29) /**< \brief (F0) Set priority if filter matches. */
+#define   MCAN_RAM_FILT_EFEC_PTY_FIFO0 (0x5u << 29) /**< \brief (F0) Set priority and store in FIFO 0 if filter matches. */
+#define   MCAN_RAM_FILT_EFEC_PTY_FIFO1 (0x6u << 29) /**< \brief (F0) Set priority and store in FIFO 1 if filter matches. */
+#define   MCAN_RAM_FILT_EFEC_BUF (0x7u << 29) /**< \brief (F0) Store into Rx Buffer or as debug message. */
+/* -------- MCAN Message RAM : Extended Message ID Rx Filter Element : F1 Word -------- */
+#define MCAN_RAM_FILT_EFID2_Pos 0
+#define MCAN_RAM_FILT_EFID2_Msk (0x1fffffffu << MCAN_RAM_FILT_EFID2_Pos) /**< \brief (F1) Standard Filter ID 2 */
+#define MCAN_RAM_FILT_EFID2(value) ((MCAN_RAM_FILT_EFID2_Msk & ((value) << MCAN_RAM_FILT_EFID2_Pos)))
+#define   MCAN_RAM_FILT_EFID2_BUF_IDX_Pos 0
+#define   MCAN_RAM_FILT_EFID2_BUF_IDX_Msk (0x3fu << MCAN_RAM_FILT_EFID2_BUF_IDX_Pos) /**< \brief (F1) Index of Rx Buffer for storage of a matching message. */
+#define   MCAN_RAM_FILT_EFID2_BUF_IDX(value) ((MCAN_RAM_FILT_EFID2_BUF_IDX_Msk & ((value) << MCAN_RAM_FILT_EFID2_BUF_IDX_Pos)))
+#define   MCAN_RAM_FILT_EFID2_FE0 (0x1u << 6) /**< \brief (F1) Generate a pulse at m_can_fe0 filter event pin in case the filter matches. */
+#define   MCAN_RAM_FILT_EFID2_FE1 (0x1u << 7) /**< \brief (F1) Generate a pulse at m_can_fe1 filter event pin in case the filter matches. */
+#define   MCAN_RAM_FILT_EFID2_FE2 (0x1u << 8) /**< \brief (F1) Generate a pulse at m_can_fe2 filter event pin in case the filter matches. */
+#define   MCAN_RAM_FILT_EFID2_BUF (0x0u << 9) /**< \brief (F1) Store message in a Rx buffer. */
+#define   MCAN_RAM_FILT_EFID2_DBG_A (0x1u << 9) /**< \brief (F1) Debug Message A. */
+#define   MCAN_RAM_FILT_EFID2_DBG_B (0x2u << 9) /**< \brief (F1) Debug Message B. */
+#define   MCAN_RAM_FILT_EFID2_DBG_C (0x3u << 9) /**< \brief (F1) Debug Message C. */
+#define MCAN_RAM_FILT_EFT_Pos 30
+#define MCAN_RAM_FILT_EFT_Msk (0x3u << MCAN_RAM_FILT_EFT_Pos) /**< \brief (F1) Extended Filter Type */
+#define MCAN_RAM_FILT_EFT(value) ((MCAN_RAM_FILT_EFT_Msk & ((value) << MCAN_RAM_FILT_EFT_Pos)))
+#define   MCAN_RAM_FILT_EFT_RANGE_EIDM (0x0u << 30) /**< \brief (F1) Range filter from EF1ID to EF2ID (Extended ID Mask applied). */
+#define   MCAN_RAM_FILT_EFT_DUAL_ID (0x1u << 30) /**< \brief (F1) Dual ID filter for EF1ID or EF2ID. */
+#define   MCAN_RAM_FILT_EFT_CLASSIC (0x2u << 30) /**< \brief (F1) Classic filter: EF1ID = filter, EF2ID = mask. */
+#define   MCAN_RAM_FILT_EFT_RANGE (0x3u << 30) /**< \brief (F1) Range filter from EF1ID to EF2ID, Extended ID Mask not applied. */
+/* -------- MCAN Message RAM : Tx/Rx Buffer Element : T0/R0 Heading Word -------- */
+#define MCAN_RAM_BUF_HDR_SIZE (2u) /**< \brief Size of the header in Rx and Tx Buffer Elements, in words */
+#define MCAN_RAM_BUF_ID_XTD_Pos 0
+#define MCAN_RAM_BUF_ID_XTD_Msk (0x1fffffffu << MCAN_RAM_BUF_ID_XTD_Pos) /**< \brief (T0, R0) Extended (29-bit) Message identifier */
+#define MCAN_RAM_BUF_ID_XTD(value) ((MCAN_RAM_BUF_ID_XTD_Msk & ((value) << MCAN_RAM_BUF_ID_XTD_Pos)))
+#define MCAN_RAM_BUF_ID_STD_Pos 18
+#define MCAN_RAM_BUF_ID_STD_Msk (0x7ffu << MCAN_RAM_BUF_ID_STD_Pos) /**< \brief (T0, R0) Standard (11-bit) Message identifier */
+#define MCAN_RAM_BUF_ID_STD(value) ((MCAN_RAM_BUF_ID_STD_Msk & ((value) << MCAN_RAM_BUF_ID_STD_Pos)))
+#define MCAN_RAM_BUF_RTR (0x1u << 29) /**< \brief (T0, R0) Remote Transmission Request */
+#define MCAN_RAM_BUF_XTD (0x1u << 30) /**< \brief (T0, R0) Flag that signals an extended Message identifier */
+#define MCAN_RAM_BUF_ESI (0x1u << 31) /**< \brief (T0, R0) Error State Indicator */
+/* -------- MCAN Message RAM : Tx/Rx Buffer Element : T1/R1 Heading Word -------- */
+#define MCAN_RAM_BUF_RXTS_Pos 0
+#define MCAN_RAM_BUF_RXTS_Msk (0xffffu << MCAN_RAM_BUF_RXTS_Pos) /**< \brief (R1) Rx Timestamp */
+#define MCAN_RAM_BUF_DLC_Pos 16
+#define MCAN_RAM_BUF_DLC_Msk (0xfu << MCAN_RAM_BUF_DLC_Pos) /**< \brief (T1, R1) Data Length Code */
+#define MCAN_RAM_BUF_DLC(value) ((MCAN_RAM_BUF_DLC_Msk & ((value) << MCAN_RAM_BUF_DLC_Pos)))
+#define MCAN_RAM_BUF_BRS (0x1u << 20) /**< \brief (T1, R1) Flag that signals a frame transmitted with bit rate switching */
+#define MCAN_RAM_BUF_FDF (0x1u << 21) /**< \brief (T1, R1) Flag that signals a frame in CAN FD format */
+#define MCAN_RAM_BUF_EFC (0x1u << 23) /**< \brief (T1) Event FIFO Control */
+#define MCAN_RAM_BUF_FIDX_Pos 24
+#define MCAN_RAM_BUF_FIDX_Msk (0x7fu << MCAN_RAM_BUF_FIDX_Pos) /**< \brief (R1) Filter Index */
+#define MCAN_RAM_BUF_MM_Pos 24
+#define MCAN_RAM_BUF_MM_Msk (0xffu << MCAN_RAM_BUF_MM_Pos) /**< \brief (T1) Message Marker */
+#define MCAN_RAM_BUF_MM(value) ((MCAN_RAM_BUF_MM_Msk & ((value) << MCAN_RAM_BUF_MM_Pos)))
+#define MCAN_RAM_BUF_ANMF (0x1u << 31) /**< \brief (R1) Flag that signals a received frame accepted without matching any Rx Filter Element */
+/* -------- MCAN Message RAM : Tx Event Element -------- */
+#define MCAN_RAM_TX_EVT_SIZE (2u) /**< \brief Size of the Tx Event Element, in words */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_MCAN_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_mpddrc.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_mpddrc.h
new file mode 100644
index 000000000..ed0e70f05
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_mpddrc.h
@@ -0,0 +1,768 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_MPDDRC_COMPONENT_
+#define _SAMA5D2_MPDDRC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR AHB Multi-port DDR-SDRAM Controller */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_MPDDRC AHB Multi-port DDR-SDRAM Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Mpddrc hardware registers */
+typedef struct {
+  __IO uint32_t MPDDRC_MR;              /**< \brief (Mpddrc Offset: 0x00) MPDDRC Mode Register */
+  __IO uint32_t MPDDRC_RTR;             /**< \brief (Mpddrc Offset: 0x04) MPDDRC Refresh Timer Register */
+  __IO uint32_t MPDDRC_CR;              /**< \brief (Mpddrc Offset: 0x08) MPDDRC Configuration Register */
+  __IO uint32_t MPDDRC_TPR0;            /**< \brief (Mpddrc Offset: 0x0C) MPDDRC Timing Parameter 0 Register */
+  __IO uint32_t MPDDRC_TPR1;            /**< \brief (Mpddrc Offset: 0x10) MPDDRC Timing Parameter 1 Register */
+  __IO uint32_t MPDDRC_TPR2;            /**< \brief (Mpddrc Offset: 0x14) MPDDRC Timing Parameter 2 Register */
+  __I  uint32_t Reserved1[1];
+  __IO uint32_t MPDDRC_LPR;             /**< \brief (Mpddrc Offset: 0x1C) MPDDRC Low-power Register */
+  __IO uint32_t MPDDRC_MD;              /**< \brief (Mpddrc Offset: 0x20) MPDDRC Memory Device Register */
+  __I  uint32_t Reserved2[1];
+  __IO uint32_t MPDDRC_LPDDR2_LPR;      /**< \brief (Mpddrc Offset: 0x28) MPDDRC LPDDR2 Low-power Register */
+  __IO uint32_t MPDDRC_LPDDR2_CAL_MR4;  /**< \brief (Mpddrc Offset: 0x2C) MPDDRC LPDDR2 Calibration and MR4 Register */
+  __IO uint32_t MPDDRC_LPDDR2_TIM_CAL;  /**< \brief (Mpddrc Offset: 0x30) MPDDRC LPDDR2 Timing Calibration Register */
+  __IO uint32_t MPDDRC_IO_CALIBR;       /**< \brief (Mpddrc Offset: 0x34) MPDDRC IO Calibration */
+  __IO uint32_t MPDDRC_OCMS;            /**< \brief (Mpddrc Offset: 0x38) MPDDRC OCMS Register */
+  __O  uint32_t MPDDRC_OCMS_KEY1;       /**< \brief (Mpddrc Offset: 0x3C) MPDDRC OCMS KEY1 Register */
+  __O  uint32_t MPDDRC_OCMS_KEY2;       /**< \brief (Mpddrc Offset: 0x40) MPDDRC OCMS KEY2 Register */
+  __IO uint32_t MPDDRC_CONF_ARBITER;    /**< \brief (Mpddrc Offset: 0x44) MPDDRC Configuration Arbiter Register */
+  __IO uint32_t MPDDRC_TIMEOUT;         /**< \brief (Mpddrc Offset: 0x48) MPDDRC Time-out Port 0/1/2/3 Register */
+  __IO uint32_t MPDDRC_REQ_PORT_0123;   /**< \brief (Mpddrc Offset: 0x4C) MPDDRC Request Port 0/1/2/3 Register */
+  __IO uint32_t MPDDRC_REQ_PORT_4567;   /**< \brief (Mpddrc Offset: 0x50) MPDDRC Request Port 4/5/6/7 Register */
+  __I  uint32_t MPDDRC_BDW_PORT_0123;   /**< \brief (Mpddrc Offset: 0x54) MPDDRC Bandwidth Port 0/1/2/3 Register */
+  __I  uint32_t MPDDRC_BDW_PORT_4567;   /**< \brief (Mpddrc Offset: 0x58) MPDDRC Bandwidth Port 4/5/6/7 Register */
+  __IO uint32_t MPDDRC_RD_DATA_PATH;    /**< \brief (Mpddrc Offset: 0x5C) MPDDRC Read Datapath Register */
+  __IO uint32_t MPDDRC_MCFGR;           /**< \brief (Mpddrc Offset: 0x60) MPDDRC Monitor Configuration */
+  __IO uint32_t MPDDRC_MADDR0;          /**< \brief (Mpddrc Offset: 0x64) MPDDRC Monitor Address High/Low port 0 */
+  __IO uint32_t MPDDRC_MADDR1;          /**< \brief (Mpddrc Offset: 0x68) MPDDRC Monitor Address High/Low port 1 */
+  __IO uint32_t MPDDRC_MADDR2;          /**< \brief (Mpddrc Offset: 0x6C) MPDDRC Monitor Address High/Low port 2 */
+  __IO uint32_t MPDDRC_MADDR3;          /**< \brief (Mpddrc Offset: 0x70) MPDDRC Monitor Address High/Low port 3 */
+  __IO uint32_t MPDDRC_MADDR4;          /**< \brief (Mpddrc Offset: 0x74) MPDDRC Monitor Address High/Low port 4 */
+  __IO uint32_t MPDDRC_MADDR5;          /**< \brief (Mpddrc Offset: 0x78) MPDDRC Monitor Address High/Low port 5 */
+  __IO uint32_t MPDDRC_MADDR6;          /**< \brief (Mpddrc Offset: 0x7C) MPDDRC Monitor Address High/Low port 6 */
+  __IO uint32_t MPDDRC_MADDR7;          /**< \brief (Mpddrc Offset: 0x80) MPDDRC Monitor Address High/Low port 7 */
+  __I  uint32_t MPDDRC_MINFO0;          /**< \brief (Mpddrc Offset: 0x84) MPDDRC Monitor Information port 0 */
+  __I  uint32_t MPDDRC_MINFO1;          /**< \brief (Mpddrc Offset: 0x88) MPDDRC Monitor Information port 1 */
+  __I  uint32_t MPDDRC_MINFO2;          /**< \brief (Mpddrc Offset: 0x8C) MPDDRC Monitor Information port 2 */
+  __I  uint32_t MPDDRC_MINFO3;          /**< \brief (Mpddrc Offset: 0x90) MPDDRC Monitor Information port 3 */
+  __I  uint32_t MPDDRC_MINFO4;          /**< \brief (Mpddrc Offset: 0x94) MPDDRC Monitor Information port 4 */
+  __I  uint32_t MPDDRC_MINFO5;          /**< \brief (Mpddrc Offset: 0x98) MPDDRC Monitor Information port 5 */
+  __I  uint32_t MPDDRC_MINFO6;          /**< \brief (Mpddrc Offset: 0x9C) MPDDRC Monitor Information port 6 */
+  __I  uint32_t MPDDRC_MINFO7;          /**< \brief (Mpddrc Offset: 0xA0) MPDDRC Monitor Information port 7 */
+  __I  uint32_t Reserved3[16];
+  __IO uint32_t MPDDRC_WPMR;            /**< \brief (Mpddrc Offset: 0xE4) MPDDRC Write Protection Mode Register */
+  __I  uint32_t MPDDRC_WPSR;            /**< \brief (Mpddrc Offset: 0xE8) MPDDRC Write Protection Status Register */
+} Mpddrc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- MPDDRC_MR : (MPDDRC Offset: 0x00) MPDDRC Mode Register -------- */
+#define MPDDRC_MR_MODE_Pos 0
+#define MPDDRC_MR_MODE_Msk (0x7u << MPDDRC_MR_MODE_Pos) /**< \brief (MPDDRC_MR) MPDDRC Command Mode */
+#define MPDDRC_MR_MODE(value) ((MPDDRC_MR_MODE_Msk & ((value) << MPDDRC_MR_MODE_Pos)))
+#define   MPDDRC_MR_MODE_NORMAL_CMD (0x0u << 0) /**< \brief (MPDDRC_MR) Normal Mode. Any access to the MPDDRC is decoded normally. To activate this mode, the command must be followed by a write to the DDR-SDRAM. */
+#define   MPDDRC_MR_MODE_NOP_CMD (0x1u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues a NOP command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. */
+#define   MPDDRC_MR_MODE_PRCGALL_CMD (0x2u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues the All Banks Precharge command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM. */
+#define   MPDDRC_MR_MODE_LMR_CMD (0x3u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues a Load Mode Register command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. */
+#define   MPDDRC_MR_MODE_RFSH_CMD (0x4u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues an Auto-Refresh command when the DDR-SDRAM device is accessed regardless of the cycle. Previously, an All Banks Precharge command must be issued. To activate this mode, the command must be followed by a write to the DDR-SDRAM. */
+#define   MPDDRC_MR_MODE_EXT_LMR_CMD (0x5u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues an Extended Load Mode Register command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. The write in the DDR-SDRAM must be done in the appropriate bank. */
+#define   MPDDRC_MR_MODE_DEEP_CMD (0x6u << 0) /**< \brief (MPDDRC_MR) Deep power mode: Access to deep power-down mode */
+#define   MPDDRC_MR_MODE_CALIB_CMD (0x6u << 0) /**< \brief (MPDDRC_MR) Calibration command: to calibrate RTT and RON values for the Process Voltage Temperature (PVT) (DDR3-SDRAM device) */
+#define   MPDDRC_MR_MODE_LPDDR2_CMD (0x7u << 0)	/**< \brief (MPDDRC_MR) The MPDDRC issues an LPDDR2 Mode Register command when the low-power DDR2-SDRAM device is accessed regardless of the cycle. To activate this mode, the Mode Register command must be followed by a write to the low-power DDR2-SDRAM. */
+#define   MPDDRC_MR_MODE_LPDDR3_CMD (0x7u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues an LPDDR3 Mode Register command when the low-power DDR3-SDRAM device is accessed regardless of the cycle. To activate this mode, the Mode Register command must be followed by a write to the low-power DDR3-SDRAM. */
+#define MPDDRC_MR_DAI (0x1u << 4) /**< \brief (MPDDRC_MR) Device Auto-Initialization Status */
+#define   MPDDRC_MR_DAI_DAI_COMPLETE (0x0u << 4) /**< \brief (MPDDRC_MR) DAI complete */
+#define   MPDDRC_MR_DAI_DAI_IN_PROGESSS (0x1u << 4) /**< \brief (MPDDRC_MR) DAI still in progress */
+#define MPDDRC_MR_MRS_Pos 8
+#define MPDDRC_MR_MRS_Msk (0xffu << MPDDRC_MR_MRS_Pos) /**< \brief (MPDDRC_MR) Mode Register Select LPDDR2 */
+#define MPDDRC_MR_MRS(value) ((MPDDRC_MR_MRS_Msk & ((value) << MPDDRC_MR_MRS_Pos)))
+/* -------- MPDDRC_RTR : (MPDDRC Offset: 0x04) MPDDRC Refresh Timer Register -------- */
+#define MPDDRC_RTR_COUNT_Pos 0
+#define MPDDRC_RTR_COUNT_Msk (0xfffu << MPDDRC_RTR_COUNT_Pos) /**< \brief (MPDDRC_RTR) MPDDRC Refresh Timer Count */
+#define MPDDRC_RTR_COUNT(value) ((MPDDRC_RTR_COUNT_Msk & ((value) << MPDDRC_RTR_COUNT_Pos)))
+#define MPDDRC_RTR_ADJ_REF (0x1u << 16) /**< \brief (MPDDRC_RTR) Adjust Refresh Rate */
+#define MPDDRC_RTR_REF_PB (0x1u << 17) /**< \brief (MPDDRC_RTR) Refresh Per Bank */
+#define MPDDRC_RTR_MR4_VALUE_Pos 20
+#define MPDDRC_RTR_MR4_VALUE_Msk (0x7u << MPDDRC_RTR_MR4_VALUE_Pos) /**< \brief (MPDDRC_RTR) Content of MR4 Register */
+#define MPDDRC_RTR_MR4_VALUE(value) ((MPDDRC_RTR_MR4_VALUE_Msk & ((value) << MPDDRC_RTR_MR4_VALUE_Pos)))
+/* -------- MPDDRC_CR : (MPDDRC Offset: 0x08) MPDDRC Configuration Register -------- */
+#define MPDDRC_CR_NC_Pos 0
+#define MPDDRC_CR_NC_Msk (0x3u << MPDDRC_CR_NC_Pos) /**< \brief (MPDDRC_CR) Number of Column Bits */
+#define MPDDRC_CR_NC(value) ((MPDDRC_CR_NC_Msk & ((value) << MPDDRC_CR_NC_Pos)))
+#define   MPDDRC_CR_NC_DDR_9_COL_BITS (0x0u << 0) /**< \brief (MPDDRC_CR) 9 bits for DDR */
+#define   MPDDRC_CR_NC_DDR_10_COL_BITS (0x1u << 0) /**< \brief (MPDDRC_CR) 10 bits for DDR */
+#define   MPDDRC_CR_NC_DDR_11_COL_BITS (0x2u << 0) /**< \brief (MPDDRC_CR) 11 bits for DDR */
+#define   MPDDRC_CR_NC_DDR_12_COL_BITS (0x3u << 0) /**< \brief (MPDDRC_CR) 12 bits for DDR */
+#define   MPDDRC_CR_NC_LPDDR1_8_COL_BITS (0x0u << 0) /**< \brief (MPDDRC_CR) 8-bit for low-power DDR1-SDRAM */
+#define   MPDDRC_CR_NC_LPDDR1_9_COL_BITS (0x1u << 0) /**< \brief (MPDDRC_CR) 9-bit for low-power DDR1-SDRAM */
+#define   MPDDRC_CR_NC_LPDDR1_10_COL_BITS (0x2u << 0) /**< \brief (MPDDRC_CR) 10-bit for low-power DDR1-SDRAM */
+#define   MPDDRC_CR_NC_LPDDR1_11_COL_BITS (0x3u << 0) /**< \brief (MPDDRC_CR) 11-bit for low-power DDR1-SDRAM */
+#define MPDDRC_CR_NR_Pos 2
+#define MPDDRC_CR_NR_Msk (0x3u << MPDDRC_CR_NR_Pos) /**< \brief (MPDDRC_CR) Number of Row Bits */
+#define MPDDRC_CR_NR(value) ((MPDDRC_CR_NR_Msk & ((value) << MPDDRC_CR_NR_Pos)))
+#define   MPDDRC_CR_NR_11_ROW_BITS (0x0u << 2) /**< \brief (MPDDRC_CR) 11 bits to define the row number, up to 2048 rows */
+#define   MPDDRC_CR_NR_12_ROW_BITS (0x1u << 2) /**< \brief (MPDDRC_CR) 12 bits to define the row number, up to 4096 rows */
+#define   MPDDRC_CR_NR_13_ROW_BITS (0x2u << 2) /**< \brief (MPDDRC_CR) 13 bits to define the row number, up to 8192 rows */
+#define   MPDDRC_CR_NR_14_ROW_BITS (0x3u << 2) /**< \brief (MPDDRC_CR) 14 bits to define the row number, up to 16384 rows */
+#define MPDDRC_CR_CAS_Pos 4
+#define MPDDRC_CR_CAS_Msk (0x7u << MPDDRC_CR_CAS_Pos) /**< \brief (MPDDRC_CR) CAS Latency */
+#define MPDDRC_CR_CAS(value) ((MPDDRC_CR_CAS_Msk & ((value) << MPDDRC_CR_CAS_Pos)))
+#define   MPDDRC_CR_CAS_DDR_CAS2 (0x2u << 4) /**< \brief (MPDDRC_CR) CAS Latency 2 */
+#define   MPDDRC_CR_CAS_DDR_CAS3 (0x3u << 4) /**< \brief (MPDDRC_CR) CAS Latency 3 */
+#define   MPDDRC_CR_CAS_DDR_CAS5 (0x5u << 4) /**< \brief (MPDDRC_CR) CAS Latency 5 */
+#define   MPDDRC_CR_CAS_DDR_CAS6 (0x6u << 4) /**< \brief (MPDDRC_CR) CAS Latency 6 */
+#define MPDDRC_CR_DLL (0x1u << 7) /**< \brief (MPDDRC_CR) Reset DLL */
+#define   MPDDRC_CR_DLL_RESET_DISABLED (0x0u << 7) /**< \brief (MPDDRC_CR) Disable DLL reset */
+#define   MPDDRC_CR_DLL_RESET_ENABLED (0x1u << 7) /**< \brief (MPDDRC_CR) Enable DLL reset */
+#define MPDDRC_CR_DIC_DS (0x1u << 8) /**< \brief (MPDDRC_CR) Output Driver Impedance Control (Drive Strength) */
+#define   MPDDRC_CR_DIC_DS_DDR2_NORMALSTRENGTH (0x0u << 8) /**< \brief (MPDDRC_CR) Normal driver strength (DDR2) */
+#define   MPDDRC_CR_DIC_DS_DDR2_WEAKSTRENGTH (0x1u << 8) /**< \brief (MPDDRC_CR) Weak driver strength (DDR2) */
+#define   MPDDRC_CR_DIC_DS_DDR3_RZQ6 (0x0u << 8) /**< \brief (MPDDRC_CR) RZQ/6 (40 [NOM], DDR3) */
+#define   MPDDRC_CR_DIC_DS_DDR3_RZQ7 (0x1u << 8) /**< \brief (MPDDRC_CR) RZQ/7 (34 [NOM], DDR3) */
+#define MPDDRC_CR_DIS_DLL (0x1u << 9) /**< \brief (MPDDRC_CR) Disable DLL */
+#define MPDDRC_CR_ZQ_Pos 10
+#define MPDDRC_CR_ZQ_Msk (0x3u << MPDDRC_CR_ZQ_Pos) /**< \brief (MPDDRC_CR) ZQ Calibration */
+#define MPDDRC_CR_ZQ(value) ((MPDDRC_CR_ZQ_Msk & ((value) << MPDDRC_CR_ZQ_Pos)))
+#define   MPDDRC_CR_ZQ_INIT (0x0u << 10) /**< \brief (MPDDRC_CR) Calibration command after initialization */
+#define   MPDDRC_CR_ZQ_LONG (0x1u << 10) /**< \brief (MPDDRC_CR) Long calibration */
+#define   MPDDRC_CR_ZQ_SHORT (0x2u << 10) /**< \brief (MPDDRC_CR) Short calibration */
+#define   MPDDRC_CR_ZQ_RESET (0x3u << 10) /**< \brief (MPDDRC_CR) ZQ Reset */
+#define MPDDRC_CR_OCD_Pos 12
+#define MPDDRC_CR_OCD_Msk (0x7u << MPDDRC_CR_OCD_Pos) /**< \brief (MPDDRC_CR) Off-chip Driver */
+#define MPDDRC_CR_OCD(value) ((MPDDRC_CR_OCD_Msk & ((value) << MPDDRC_CR_OCD_Pos)))
+#define   MPDDRC_CR_OCD_DDR2_EXITCALIB (0x0u << 12) /**< \brief (MPDDRC_CR) Exit from OCD calibration mode and maintain settings */
+#define   MPDDRC_CR_OCD_DDR2_DEFAULT_CALIB (0x7u << 12) /**< \brief (MPDDRC_CR) OCD calibration default */
+#define MPDDRC_CR_DQMS (0x1u << 16) /**< \brief (MPDDRC_CR) Mask Data is Shared */
+#define   MPDDRC_CR_DQMS_NOT_SHARED (0x0u << 16) /**< \brief (MPDDRC_CR) DQM is not shared with another controller */
+#define   MPDDRC_CR_DQMS_SHARED (0x1u << 16) /**< \brief (MPDDRC_CR) DQM is shared with another controller */
+#define MPDDRC_CR_ENRDM (0x1u << 17) /**< \brief (MPDDRC_CR) Enable Read Measure */
+#define   MPDDRC_CR_ENRDM_OFF (0x0u << 17) /**< \brief (MPDDRC_CR) DQS/DDR_DATA phase error correction is disabled */
+#define   MPDDRC_CR_ENRDM_ON (0x1u << 17) /**< \brief (MPDDRC_CR) DQS/DDR_DATA phase error correction is enabled */
+#define MPDDRC_CR_LC_LPDDR1 (0x1u << 19) /**< \brief (MPDDRC_CR) Low-cost Low-power DDR1 */
+#define   MPDDRC_CR_LC_LPDDR1_NOT_2_BANKS (0x0u << 19) /**< \brief (MPDDRC_CR) Any type of memory devices except of low cost, low density Low Power DDR1. */
+#define   MPDDRC_CR_LC_LPDDR1_2_BANKS_LPDDR1 (0x1u << 19) /**< \brief (MPDDRC_CR) Low-cost and low-density low-power DDR1. */
+#define MPDDRC_CR_NB (0x1u << 20) /**< \brief (MPDDRC_CR) Number of Banks */
+#define   MPDDRC_CR_NB_4_BANKS (0x0u << 20) /**< \brief (MPDDRC_CR) 4 banks */
+#define   MPDDRC_CR_NB_8_BANKS (0x1u << 20) /**< \brief (MPDDRC_CR) 8 banks */
+#define MPDDRC_CR_NDQS (0x1u << 21) /**< \brief (MPDDRC_CR) Not DQS */
+#define   MPDDRC_CR_NDQS_ENABLED (0x0u << 21) /**< \brief (MPDDRC_CR) Not DQS is enabled */
+#define   MPDDRC_CR_NDQS_DISABLED (0x1u << 21) /**< \brief (MPDDRC_CR) Not DQS is disabled */
+#define MPDDRC_CR_DECOD (0x1u << 22) /**< \brief (MPDDRC_CR) Type of Decoding */
+#define   MPDDRC_CR_DECOD_SEQUENTIAL (0x0u << 22) /**< \brief (MPDDRC_CR) Method for address mapping where banks alternate at each last DDR-SDRAM page of the current bank. */
+#define   MPDDRC_CR_DECOD_INTERLEAVED (0x1u << 22) /**< \brief (MPDDRC_CR) Method for address mapping where banks alternate at each SDRAM end page of the current bank. */
+#define MPDDRC_CR_UNAL (0x1u << 23) /**< \brief (MPDDRC_CR) Support Unaligned Access */
+#define   MPDDRC_CR_UNAL_UNSUPPORTED (0x0u << 23) /**< \brief (MPDDRC_CR) Unaligned access is not supported. */
+#define   MPDDRC_CR_UNAL_SUPPORTED (0x1u << 23) /**< \brief (MPDDRC_CR) Unaligned access is supported. */
+/* -------- MPDDRC_TPR0 : (MPDDRC Offset: 0x0C) MPDDRC Timing Parameter 0 Register -------- */
+#define MPDDRC_TPR0_TRAS_Pos 0
+#define MPDDRC_TPR0_TRAS_Msk (0xfu << MPDDRC_TPR0_TRAS_Pos) /**< \brief (MPDDRC_TPR0) Active to Precharge Delay */
+#define MPDDRC_TPR0_TRAS(value) ((MPDDRC_TPR0_TRAS_Msk & ((value) << MPDDRC_TPR0_TRAS_Pos)))
+#define MPDDRC_TPR0_TRCD_Pos 4
+#define MPDDRC_TPR0_TRCD_Msk (0xfu << MPDDRC_TPR0_TRCD_Pos) /**< \brief (MPDDRC_TPR0) Row to Column Delay */
+#define MPDDRC_TPR0_TRCD(value) ((MPDDRC_TPR0_TRCD_Msk & ((value) << MPDDRC_TPR0_TRCD_Pos)))
+#define MPDDRC_TPR0_TWR_Pos 8
+#define MPDDRC_TPR0_TWR_Msk (0xfu << MPDDRC_TPR0_TWR_Pos) /**< \brief (MPDDRC_TPR0) Write Recovery Delay */
+#define MPDDRC_TPR0_TWR(value) ((MPDDRC_TPR0_TWR_Msk & ((value) << MPDDRC_TPR0_TWR_Pos)))
+#define MPDDRC_TPR0_TRC_Pos 12
+#define MPDDRC_TPR0_TRC_Msk (0xfu << MPDDRC_TPR0_TRC_Pos) /**< \brief (MPDDRC_TPR0) Row Cycle Delay */
+#define MPDDRC_TPR0_TRC(value) ((MPDDRC_TPR0_TRC_Msk & ((value) << MPDDRC_TPR0_TRC_Pos)))
+#define MPDDRC_TPR0_TRP_Pos 16
+#define MPDDRC_TPR0_TRP_Msk (0xfu << MPDDRC_TPR0_TRP_Pos) /**< \brief (MPDDRC_TPR0) Row Precharge Delay */
+#define MPDDRC_TPR0_TRP(value) ((MPDDRC_TPR0_TRP_Msk & ((value) << MPDDRC_TPR0_TRP_Pos)))
+#define MPDDRC_TPR0_TRRD_Pos 20
+#define MPDDRC_TPR0_TRRD_Msk (0xfu << MPDDRC_TPR0_TRRD_Pos) /**< \brief (MPDDRC_TPR0) Active BankA to Active BankB */
+#define MPDDRC_TPR0_TRRD(value) ((MPDDRC_TPR0_TRRD_Msk & ((value) << MPDDRC_TPR0_TRRD_Pos)))
+#define MPDDRC_TPR0_TWTR_Pos 24
+#define MPDDRC_TPR0_TWTR_Msk (0xfu << MPDDRC_TPR0_TWTR_Pos) /**< \brief (MPDDRC_TPR0) Internal Write to Read Delay */
+#define MPDDRC_TPR0_TWTR(value) ((MPDDRC_TPR0_TWTR_Msk & ((value) << MPDDRC_TPR0_TWTR_Pos)))
+#define MPDDRC_TPR0_TMRD_Pos 28
+#define MPDDRC_TPR0_TMRD_Msk (0xfu << MPDDRC_TPR0_TMRD_Pos) /**< \brief (MPDDRC_TPR0) Load Mode Register Command to Activate or Refresh Command */
+#define MPDDRC_TPR0_TMRD(value) ((MPDDRC_TPR0_TMRD_Msk & ((value) << MPDDRC_TPR0_TMRD_Pos)))
+/* -------- MPDDRC_TPR1 : (MPDDRC Offset: 0x10) MPDDRC Timing Parameter 1 Register -------- */
+#define MPDDRC_TPR1_TRFC_Pos 0
+#define MPDDRC_TPR1_TRFC_Msk (0x7fu << MPDDRC_TPR1_TRFC_Pos) /**< \brief (MPDDRC_TPR1) Row Cycle Delay */
+#define MPDDRC_TPR1_TRFC(value) ((MPDDRC_TPR1_TRFC_Msk & ((value) << MPDDRC_TPR1_TRFC_Pos)))
+#define MPDDRC_TPR1_TXSNR_Pos 8
+#define MPDDRC_TPR1_TXSNR_Msk (0xffu << MPDDRC_TPR1_TXSNR_Pos) /**< \brief (MPDDRC_TPR1) Exit Self-refresh Delay to Non-Read Command */
+#define MPDDRC_TPR1_TXSNR(value) ((MPDDRC_TPR1_TXSNR_Msk & ((value) << MPDDRC_TPR1_TXSNR_Pos)))
+#define MPDDRC_TPR1_TXSRD_Pos 16
+#define MPDDRC_TPR1_TXSRD_Msk (0xffu << MPDDRC_TPR1_TXSRD_Pos) /**< \brief (MPDDRC_TPR1) Exit Self-refresh Delay to Read Command */
+#define MPDDRC_TPR1_TXSRD(value) ((MPDDRC_TPR1_TXSRD_Msk & ((value) << MPDDRC_TPR1_TXSRD_Pos)))
+#define MPDDRC_TPR1_TXP_Pos 24
+#define MPDDRC_TPR1_TXP_Msk (0xfu << MPDDRC_TPR1_TXP_Pos) /**< \brief (MPDDRC_TPR1) Exit Power-down Delay to First Command */
+#define MPDDRC_TPR1_TXP(value) ((MPDDRC_TPR1_TXP_Msk & ((value) << MPDDRC_TPR1_TXP_Pos)))
+/* -------- MPDDRC_TPR2 : (MPDDRC Offset: 0x14) MPDDRC Timing Parameter 2 Register -------- */
+#define MPDDRC_TPR2_TXARD_Pos 0
+#define MPDDRC_TPR2_TXARD_Msk (0xfu << MPDDRC_TPR2_TXARD_Pos) /**< \brief (MPDDRC_TPR2) Exit Active Power Down Delay to Read Command in Mode "Fast Exit" */
+#define MPDDRC_TPR2_TXARD(value) ((MPDDRC_TPR2_TXARD_Msk & ((value) << MPDDRC_TPR2_TXARD_Pos)))
+#define MPDDRC_TPR2_TXARDS_Pos 4
+#define MPDDRC_TPR2_TXARDS_Msk (0xfu << MPDDRC_TPR2_TXARDS_Pos) /**< \brief (MPDDRC_TPR2) Exit Active Power Down Delay to Read Command in Mode "Slow Exit" */
+#define MPDDRC_TPR2_TXARDS(value) ((MPDDRC_TPR2_TXARDS_Msk & ((value) << MPDDRC_TPR2_TXARDS_Pos)))
+#define MPDDRC_TPR2_TRPA_Pos 8
+#define MPDDRC_TPR2_TRPA_Msk (0xfu << MPDDRC_TPR2_TRPA_Pos) /**< \brief (MPDDRC_TPR2) Row Precharge All Delay */
+#define MPDDRC_TPR2_TRPA(value) ((MPDDRC_TPR2_TRPA_Msk & ((value) << MPDDRC_TPR2_TRPA_Pos)))
+#define MPDDRC_TPR2_TRTP_Pos 12
+#define MPDDRC_TPR2_TRTP_Msk (0x7u << MPDDRC_TPR2_TRTP_Pos) /**< \brief (MPDDRC_TPR2) Read to Precharge */
+#define MPDDRC_TPR2_TRTP(value) ((MPDDRC_TPR2_TRTP_Msk & ((value) << MPDDRC_TPR2_TRTP_Pos)))
+#define MPDDRC_TPR2_TFAW_Pos 16
+#define MPDDRC_TPR2_TFAW_Msk (0xfu << MPDDRC_TPR2_TFAW_Pos) /**< \brief (MPDDRC_TPR2) Four Active Windows */
+#define MPDDRC_TPR2_TFAW(value) ((MPDDRC_TPR2_TFAW_Msk & ((value) << MPDDRC_TPR2_TFAW_Pos)))
+/* -------- MPDDRC_LPR : (MPDDRC Offset: 0x1C) MPDDRC Low-power Register -------- */
+#define MPDDRC_LPR_LPCB_Pos 0
+#define MPDDRC_LPR_LPCB_Msk (0x3u << MPDDRC_LPR_LPCB_Pos) /**< \brief (MPDDRC_LPR) Low-power Command Bit */
+#define MPDDRC_LPR_LPCB(value) ((MPDDRC_LPR_LPCB_Msk & ((value) << MPDDRC_LPR_LPCB_Pos)))
+#define   MPDDRC_LPR_LPCB_NOLOWPOWER (0x0u << 0) /**< \brief (MPDDRC_LPR) Low-power feature is inhibited. No power-down, self-refresh and deep-power modes are issued to the DDR-SDRAM device. */
+#define   MPDDRC_LPR_LPCB_SELFREFRESH (0x1u << 0) /**< \brief (MPDDRC_LPR) The MPDDRC issues a self-refresh command to the DDR-SDRAM device, the clock(s) is/are deactivated and the CKE signal is set low. The DDR-SDRAM device leaves the self-refresh mode when accessed and reenters it after the access. */
+#define   MPDDRC_LPR_LPCB_POWERDOWN (0x2u << 0) /**< \brief (MPDDRC_LPR) The MPDDRC issues a Power-down command to the DDR-SDRAM device after each access, the CKE signal is set low. The DDR-SDRAM device leaves the power-down mode when accessed and reenters it after the access. */
+#define   MPDDRC_LPR_LPCB_DEEPPOWERDOWN (0x3u << 0) /**< \brief (MPDDRC_LPR) The MPDDRC issues a Deep Power-down command to the low-power DDR-SDRAM device. */
+#define MPDDRC_LPR_CLK_FR (0x1u << 2) /**< \brief (MPDDRC_LPR) Clock Frozen Command Bit */
+#define   MPDDRC_LPR_CLK_FR_DISABLED (0x0u << 2) /**< \brief (MPDDRC_LPR) Clock(s) is/are not frozen. */
+#define   MPDDRC_LPR_CLK_FR_ENABLED (0x1u << 2) /**< \brief (MPDDRC_LPR) Clock(s) is/are frozen. */
+#define MPDDRC_LPR_LPDDR2_PWOFF (0x1u << 3) /**< \brief (MPDDRC_LPR) LPDDR2 Power Off Bit */
+#define   MPDDRC_LPR_LPDDR2_PWOFF_DISABLED (0x0u << 3) /**< \brief (MPDDRC_LPR) No power off sequence applied to LPDDR2. */
+#define   MPDDRC_LPR_LPDDR2_PWOFF_ENABLED (0x1u << 3) /**< \brief (MPDDRC_LPR) A power off sequence is applied to the LPDDR2 device. CKE is forced low. */
+#define MPDDRC_LPR_PASR_Pos 4
+#define MPDDRC_LPR_PASR_Msk (0x7u << MPDDRC_LPR_PASR_Pos) /**< \brief (MPDDRC_LPR) Partial Array Self-refresh */
+#define MPDDRC_LPR_PASR(value) ((MPDDRC_LPR_PASR_Msk & ((value) << MPDDRC_LPR_PASR_Pos)))
+#define MPDDRC_LPR_DS_Pos 8
+#define MPDDRC_LPR_DS_Msk (0x7u << MPDDRC_LPR_DS_Pos) /**< \brief (MPDDRC_LPR) Drive Strength */
+#define MPDDRC_LPR_DS(value) ((MPDDRC_LPR_DS_Msk & ((value) << MPDDRC_LPR_DS_Pos)))
+#define MPDDRC_LPR_TIMEOUT_Pos 12
+#define MPDDRC_LPR_TIMEOUT_Msk (0x3u << MPDDRC_LPR_TIMEOUT_Pos) /**< \brief (MPDDRC_LPR) Time Between Last Transfer and Low-Power Mode */
+#define MPDDRC_LPR_TIMEOUT(value) ((MPDDRC_LPR_TIMEOUT_Msk & ((value) << MPDDRC_LPR_TIMEOUT_Pos)))
+#define   MPDDRC_LPR_TIMEOUT_NONE (0x0u << 12) /**< \brief (MPDDRC_LPR) SDRAM low-power mode is activated immediately after the end of the last transfer. */
+#define   MPDDRC_LPR_TIMEOUT_DELAY_64_CLK (0x1u << 12) /**< \brief (MPDDRC_LPR) SDRAM low-power mode is activated 64 clock cycles after the end of the last transfer. */
+#define   MPDDRC_LPR_TIMEOUT_DELAY_128_CLK (0x2u << 12)        /**< \brief (MPDDRC_LPR) SDRAM low-power mode is activated 128 clock cycles after the end of the last transfer. */
+#define MPDDRC_LPR_APDE (0x1u << 16) /**< \brief (MPDDRC_LPR) Active Power Down Exit Time */
+#define   MPDDRC_LPR_APDE_DDR2_FAST_EXIT (0x0u << 16) /**< \brief (MPDDRC_LPR) Fast Exit from Power Down. */
+#define   MPDDRC_LPR_APDE_DDR2_SLOW_EXIT (0x1u << 16) /**< \brief (MPDDRC_LPR) Slow Exit from Power Down. */
+#define MPDDRC_LPR_UPD_MR_Pos 20
+#define MPDDRC_LPR_UPD_MR_Msk (0x3u << MPDDRC_LPR_UPD_MR_Pos) /**< \brief (MPDDRC_LPR) Update Load Mode Register and Extended Mode Register */
+#define MPDDRC_LPR_UPD_MR(value) ((MPDDRC_LPR_UPD_MR_Msk & ((value) << MPDDRC_LPR_UPD_MR_Pos)))
+#define   MPDDRC_LPR_UPD_MR_NO_UPDATE (0x0u << 20) /**< \brief (MPDDRC_LPR) Update of Load Mode and Extended Mode registers is disabled. */
+#define   MPDDRC_LPR_UPD_MR_UPDATE_SHAREDBUS (0x1u << 20) /**< \brief (MPDDRC_LPR) MPDDRC shares an external bus. Automatic update is done during a refresh command and a pending read or write access in the SDRAM device. */
+#define   MPDDRC_LPR_UPD_MR_UPDATE_NOSHAREDBUS (0x2u << 20) /**< \brief (MPDDRC_LPR) MPDDRC does not share an external bus. Automatic update is done before entering Self-refresh mode. */
+#define MPDDRC_LPR_CHG_FRQ (0x1u << 24) /**< \brief (MPDDRC_LPR) Change Clock Frequency During Self-refresh Mode */
+#define MPDDRC_LPR_SELF_DONE (0x1u << 25) /**< \brief (MPDDRC_LPR) Self-refresh is done */
+/* -------- MPDDRC_MD : (MPDDRC Offset: 0x20) MPDDRC Memory Device Register -------- */
+#define MPDDRC_MD_MD_Pos 0
+#define MPDDRC_MD_MD_Msk (0x7u << MPDDRC_MD_MD_Pos) /**< \brief (MPDDRC_MD) Memory Device */
+#define MPDDRC_MD_MD(value) ((MPDDRC_MD_MD_Msk & ((value) << MPDDRC_MD_MD_Pos)))
+#define   MPDDRC_MD_MD_LPDDR_SDRAM (0x3u << 0) /**< \brief (MPDDRC_MD) Low-power DDR1-SDRAM */
+#define   MPDDRC_MD_MD_DDR3_SDRAM (0x4u << 0) /**< \brief (MPDDRC_MD) DDR3-SDRAM */
+#define   MPDDRC_MD_MD_LPDDR3_SDRAM (0x5u << 0) /**< \brief (MPDDRC_MD) Low-power DDR3-SDRAM */
+#define   MPDDRC_MD_MD_DDR2_SDRAM (0x6u << 0) /**< \brief (MPDDRC_MD) DDR2-SDRAM */
+#define   MPDDRC_MD_MD_LPDDR2_SDRAM (0x7u << 0) /**< \brief (MPDDRC_MD) Low-power DDR2-SDRAM */
+#define MPDDRC_MD_DBW (0x1u << 4) /**< \brief (MPDDRC_MD) Data Bus Width */
+#define   MPDDRC_MD_DBW_DBW_32_BITS (0x0u << 4) /**< \brief (MPDDRC_MD) Data bus width is 32 bits */
+#define   MPDDRC_MD_DBW_DBW_16_BITS (0x1u << 4) /**< \brief (MPDDRC_MD) Data bus width is 16 bits */
+#define MPDDRC_MD_WL (0x1u << 6) /**< \brief (MPDDRC_MD) Write Latency */
+#define   MPDDRC_MD_WL_WL_SETA (0x0u << 6) /**< \brief (MPDDRC_MD) Write Latency Set A */
+#define   MPDDRC_MD_WL_WL_SETB (0x1u << 6) /**< \brief (MPDDRC_MD) Write Latency Set B */
+#define MPDDRC_MD_RL3 (0x1u << 7) /**< \brief (MPDDRC_MD) Read Latency 3 Option Support */
+#define   MPDDRC_MD_RL3_RL3_SUPPORT (0x0u << 7) /**< \brief (MPDDRC_MD) Read latency of 3 is supported */
+#define   MPDDRC_MD_RL3_RL3_NOT_SUPPORTED (0x1u << 7) /**< \brief (MPDDRC_MD) Read latency of 3 is not supported */
+#define MPDDRC_MD_MANU_ID_Pos 8
+#define MPDDRC_MD_MANU_ID_Msk (0xffu << MPDDRC_MD_MANU_ID_Pos) /**< \brief (MPDDRC_MD) Manufacturer Identification */
+#define MPDDRC_MD_MANU_ID(value) ((MPDDRC_MD_MANU_ID_Msk & ((value) << MPDDRC_MD_MANU_ID_Pos)))
+#define MPDDRC_MD_REV_ID_Pos 16
+#define MPDDRC_MD_REV_ID_Msk (0xffu << MPDDRC_MD_REV_ID_Pos) /**< \brief (MPDDRC_MD) Revision Identification */
+#define MPDDRC_MD_REV_ID(value) ((MPDDRC_MD_REV_ID_Msk & ((value) << MPDDRC_MD_REV_ID_Pos)))
+#define MPDDRC_MD_TYPE_Pos 24
+#define MPDDRC_MD_TYPE_Msk (0x3u << MPDDRC_MD_TYPE_Pos) /**< \brief (MPDDRC_MD) DRAM Architecture */
+#define MPDDRC_MD_TYPE(value) ((MPDDRC_MD_TYPE_Msk & ((value) << MPDDRC_MD_TYPE_Pos)))
+#define   MPDDRC_MD_TYPE_S4_SDRAM (0x0u << 24) /**< \brief (MPDDRC_MD) 4n prefetch architecture */
+#define   MPDDRC_MD_TYPE_S2_SDRAM (0x1u << 24) /**< \brief (MPDDRC_MD) 2n prefetch architecture */
+#define   MPDDRC_MD_TYPE_NVM (0x2u << 24) /**< \brief (MPDDRC_MD) Non-volatile device */
+#define   MPDDRC_MD_TYPE_S8_SDRAM (0x3u << 24) /**< \brief (MPDDRC_MD) 8n prefetch architecture */
+#define MPDDRC_MD_DENSITY_Pos 26
+#define MPDDRC_MD_DENSITY_Msk (0xfu << MPDDRC_MD_DENSITY_Pos) /**< \brief (MPDDRC_MD) Density of Memory */
+#define MPDDRC_MD_DENSITY(value) ((MPDDRC_MD_DENSITY_Msk & ((value) << MPDDRC_MD_DENSITY_Pos)))
+#define   MPDDRC_MD_DENSITY_DENSITY_64MBITS (0x0u << 26) /**< \brief (MPDDRC_MD) The device density is 64 Mbits. */
+#define   MPDDRC_MD_DENSITY_DENSITY_128MBITS (0x1u << 26) /**< \brief (MPDDRC_MD) The device density is 128 Mbits. */
+#define   MPDDRC_MD_DENSITY_DENSITY_256MBITS (0x2u << 26) /**< \brief (MPDDRC_MD) The device density is 256 Mbits. */
+#define   MPDDRC_MD_DENSITY_DENSITY_512MBITS (0x3u << 26) /**< \brief (MPDDRC_MD) The device density is 512 Mbits. */
+#define   MPDDRC_MD_DENSITY_DENSITY_1GBITS (0x4u << 26) /**< \brief (MPDDRC_MD) The device density is 1 Gbit. */
+#define   MPDDRC_MD_DENSITY_DENSITY_2GBITS (0x5u << 26) /**< \brief (MPDDRC_MD) The device density is 2 Gbits. */
+#define   MPDDRC_MD_DENSITY_DENSITY_4GBITS (0x6u << 26) /**< \brief (MPDDRC_MD) The device density is 4 Gbits. */
+#define   MPDDRC_MD_DENSITY_DENSITY_8GBITS (0x7u << 26) /**< \brief (MPDDRC_MD) The device density is 8 Gbits. */
+#define   MPDDRC_MD_DENSITY_DENSITY_16GBITS (0x8u << 26) /**< \brief (MPDDRC_MD) The device density is 16 Gbits. */
+#define   MPDDRC_MD_DENSITY_DENSITY_32GBITS (0x9u << 26) /**< \brief (MPDDRC_MD) The device density is 32 Gbits. */
+#define MPDDRC_MD_IO_WIDTH_Pos 30
+#define MPDDRC_MD_IO_WIDTH_Msk (0x3u << MPDDRC_MD_IO_WIDTH_Pos) /**< \brief (MPDDRC_MD) Width of Memory */
+#define MPDDRC_MD_IO_WIDTH(value) ((MPDDRC_MD_IO_WIDTH_Msk & ((value) << MPDDRC_MD_IO_WIDTH_Pos)))
+#define   MPDDRC_MD_IO_WIDTH_WIDTH_32 (0x0u << 30) /**< \brief (MPDDRC_MD) The data bus width is 32 bits. */
+#define   MPDDRC_MD_IO_WIDTH_WIDTH_16 (0x1u << 30) /**< \brief (MPDDRC_MD) The data bus width is 16 bits. */
+#define   MPDDRC_MD_IO_WIDTH_WIDTH_8 (0x2u << 30) /**< \brief (MPDDRC_MD) The data bus width is 8 bits. */
+#define   MPDDRC_MD_IO_WIDTH_NOT_USED (0x3u << 30) /**< \brief (MPDDRC_MD) - */
+/* -------- MPDDRC_LPDDR2_LPR : (MPDDRC Offset: 0x28) MPDDRC LPDDR2 Low-power Register -------- */
+#define MPDDRC_LPDDR2_LPR_BK_MASK_PASR_Pos 0
+#define MPDDRC_LPDDR2_LPR_BK_MASK_PASR_Msk (0xffu << MPDDRC_LPDDR2_LPR_BK_MASK_PASR_Pos) /**< \brief (MPDDRC_LPDDR2_LPR) Bank Mask Bit/PASR */
+#define MPDDRC_LPDDR2_LPR_BK_MASK_PASR(value) ((MPDDRC_LPDDR2_LPR_BK_MASK_PASR_Msk & ((value) << MPDDRC_LPDDR2_LPR_BK_MASK_PASR_Pos)))
+#define MPDDRC_LPDDR2_LPR_SEG_MASK_Pos 8
+#define MPDDRC_LPDDR2_LPR_SEG_MASK_Msk (0xffffu << MPDDRC_LPDDR2_LPR_SEG_MASK_Pos) /**< \brief (MPDDRC_LPDDR2_LPR) Segment Mask Bit */
+#define MPDDRC_LPDDR2_LPR_SEG_MASK(value) ((MPDDRC_LPDDR2_LPR_SEG_MASK_Msk & ((value) << MPDDRC_LPDDR2_LPR_SEG_MASK_Pos)))
+#define MPDDRC_LPDDR2_LPR_DS_Pos 24
+#define MPDDRC_LPDDR2_LPR_DS_Msk (0xfu << MPDDRC_LPDDR2_LPR_DS_Pos) /**< \brief (MPDDRC_LPDDR2_LPR) Drive Strength */
+#define MPDDRC_LPDDR2_LPR_DS(value) ((MPDDRC_LPDDR2_LPR_DS_Msk & ((value) << MPDDRC_LPDDR2_LPR_DS_Pos)))
+/* -------- MPDDRC_LPDDR2_CAL_MR4 : (MPDDRC Offset: 0x2C) MPDDRC LPDDR2 Calibration and MR4 Register -------- */
+#define MPDDRC_LPDDR2_CAL_MR4_COUNT_CAL_Pos 0
+#define MPDDRC_LPDDR2_CAL_MR4_COUNT_CAL_Msk (0xffffu << MPDDRC_LPDDR2_CAL_MR4_COUNT_CAL_Pos) /**< \brief (MPDDRC_LPDDR2_CAL_MR4) LPDDR2 Calibration Timer Count */
+#define MPDDRC_LPDDR2_CAL_MR4_COUNT_CAL(value) ((MPDDRC_LPDDR2_CAL_MR4_COUNT_CAL_Msk & ((value) << MPDDRC_LPDDR2_CAL_MR4_COUNT_CAL_Pos)))
+#define MPDDRC_LPDDR2_CAL_MR4_MR4_READ_Pos 16
+#define MPDDRC_LPDDR2_CAL_MR4_MR4_READ_Msk (0xffffu << MPDDRC_LPDDR2_CAL_MR4_MR4_READ_Pos) /**< \brief (MPDDRC_LPDDR2_CAL_MR4) Mode Register 4 Read Interval */
+#define MPDDRC_LPDDR2_CAL_MR4_MR4_READ(value) ((MPDDRC_LPDDR2_CAL_MR4_MR4_READ_Msk & ((value) << MPDDRC_LPDDR2_CAL_MR4_MR4_READ_Pos)))
+/* -------- MPDDRC_LPDDR2_TIM_CAL : (MPDDRC Offset: 0x30) MPDDRC LPDDR2 Timing Calibration Register -------- */
+#define MPDDRC_LPDDR2_TIM_CAL_ZQCS_Pos 0
+#define MPDDRC_LPDDR2_TIM_CAL_ZQCS_Msk (0xffu << MPDDRC_LPDDR2_TIM_CAL_ZQCS_Pos) /**< \brief (MPDDRC_LPDDR2_TIM_CAL) ZQ Calibration Short */
+#define MPDDRC_LPDDR2_TIM_CAL_ZQCS(value) ((MPDDRC_LPDDR2_TIM_CAL_ZQCS_Msk & ((value) << MPDDRC_LPDDR2_TIM_CAL_ZQCS_Pos)))
+#define MPDDRC_LPDDR2_TIM_CAL_RZQI_Pos 16
+#define MPDDRC_LPDDR2_TIM_CAL_RZQI_Msk (0x3u << MPDDRC_LPDDR2_TIM_CAL_RZQI_Pos) /**< \brief (MPDDRC_LPDDR2_TIM_CAL) Built-in Self-Test for RZQ Information */
+#define MPDDRC_LPDDR2_TIM_CAL_RZQI(value) ((MPDDRC_LPDDR2_TIM_CAL_RZQI_Msk & ((value) << MPDDRC_LPDDR2_TIM_CAL_RZQI_Pos)))
+#define   MPDDRC_LPDDR2_TIM_CAL_RZQI_RZQ_NOT_SUPPORTED (0x0u << 16) /**< \brief (MPDDRC_LPDDR2_TIM_CAL) RZQ self test not supported */
+#define   MPDDRC_LPDDR2_TIM_CAL_RZQI_ZQ_VDDCA_FLOAT (0x1u << 16) /**< \brief (MPDDRC_LPDDR2_TIM_CAL) The ZQ pin can be connected to VDDCA or left floating. */
+#define   MPDDRC_LPDDR2_TIM_CAL_RZQI_ZQ_SHORTED_GROUND (0x2u << 16) /**< \brief (MPDDRC_LPDDR2_TIM_CAL) The ZQ pin can be shorted to ground. */
+#define   MPDDRC_LPDDR2_TIM_CAL_RZQI_ZQ_SELF_TEST_OK (0x3u << 16) /**< \brief (MPDDRC_LPDDR2_TIM_CAL) ZQ pin self test complete; no error condition detected */
+/* -------- MPDDRC_IO_CALIBR : (MPDDRC Offset: 0x34) MPDDRC IO Calibration -------- */
+#define MPDDRC_IO_CALIBR_RDIV_Pos 0
+#define MPDDRC_IO_CALIBR_RDIV_Msk (0x7u << MPDDRC_IO_CALIBR_RDIV_Pos) /**< \brief (MPDDRC_IO_CALIBR) Resistor Divider, Output Driver Impedance */
+#define MPDDRC_IO_CALIBR_RDIV(value) ((MPDDRC_IO_CALIBR_RDIV_Msk & ((value) << MPDDRC_IO_CALIBR_RDIV_Pos)))
+#define MPDDRC_IO_CALIBR_EN_CALIB (0x1u << 4) /**< \brief (MPDDRC_IO_CALIBR) Enable Calibration */
+#define   MPDDRC_IO_CALIBR_EN_CALIB_DISABLE_CALIBRATION (0x0u << 4) /**< \brief (MPDDRC_IO_CALIBR) Calibration is disabled. */
+#define   MPDDRC_IO_CALIBR_EN_CALIB_ENABLE_CALIBRATION (0x1u << 4) /**< \brief (MPDDRC_IO_CALIBR) Calibration is enabled. */
+#define MPDDRC_IO_CALIBR_TZQIO_Pos 8
+#define MPDDRC_IO_CALIBR_TZQIO_Msk (0x7fu << MPDDRC_IO_CALIBR_TZQIO_Pos) /**< \brief (MPDDRC_IO_CALIBR) IO Calibration */
+#define MPDDRC_IO_CALIBR_TZQIO(value) ((MPDDRC_IO_CALIBR_TZQIO_Msk & ((value) << MPDDRC_IO_CALIBR_TZQIO_Pos)))
+#define MPDDRC_IO_CALIBR_CALCODEP_Pos 16
+#define MPDDRC_IO_CALIBR_CALCODEP_Msk (0xfu << MPDDRC_IO_CALIBR_CALCODEP_Pos) /**< \brief (MPDDRC_IO_CALIBR) Number of Transistor P */
+#define MPDDRC_IO_CALIBR_CALCODEP(value) ((MPDDRC_IO_CALIBR_CALCODEP_Msk & ((value) << MPDDRC_IO_CALIBR_CALCODEP_Pos)))
+#define MPDDRC_IO_CALIBR_CALCODEN_Pos 20
+#define MPDDRC_IO_CALIBR_CALCODEN_Msk (0xfu << MPDDRC_IO_CALIBR_CALCODEN_Pos) /**< \brief (MPDDRC_IO_CALIBR) Number of Transistor N */
+#define MPDDRC_IO_CALIBR_CALCODEN(value) ((MPDDRC_IO_CALIBR_CALCODEN_Msk & ((value) << MPDDRC_IO_CALIBR_CALCODEN_Pos)))
+/* -------- MPDDRC_OCMS : (MPDDRC Offset: 0x38) MPDDRC OCMS Register -------- */
+#define MPDDRC_OCMS_SCR_EN (0x1u << 0) /**< \brief (MPDDRC_OCMS) Scrambling Enable */
+/* -------- MPDDRC_OCMS_KEY1 : (MPDDRC Offset: 0x3C) MPDDRC OCMS KEY1 Register -------- */
+#define MPDDRC_OCMS_KEY1_KEY1_Pos 0
+#define MPDDRC_OCMS_KEY1_KEY1_Msk (0xffffffffu << MPDDRC_OCMS_KEY1_KEY1_Pos) /**< \brief (MPDDRC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 */
+#define MPDDRC_OCMS_KEY1_KEY1(value) ((MPDDRC_OCMS_KEY1_KEY1_Msk & ((value) << MPDDRC_OCMS_KEY1_KEY1_Pos)))
+/* -------- MPDDRC_OCMS_KEY2 : (MPDDRC Offset: 0x40) MPDDRC OCMS KEY2 Register -------- */
+#define MPDDRC_OCMS_KEY2_KEY2_Pos 0
+#define MPDDRC_OCMS_KEY2_KEY2_Msk (0xffffffffu << MPDDRC_OCMS_KEY2_KEY2_Pos) /**< \brief (MPDDRC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 */
+#define MPDDRC_OCMS_KEY2_KEY2(value) ((MPDDRC_OCMS_KEY2_KEY2_Msk & ((value) << MPDDRC_OCMS_KEY2_KEY2_Pos)))
+/* -------- MPDDRC_CONF_ARBITER : (MPDDRC Offset: 0x44) MPDDRC Configuration Arbiter Register -------- */
+#define MPDDRC_CONF_ARBITER_ARB_Pos 0
+#define MPDDRC_CONF_ARBITER_ARB_Msk (0x3u << MPDDRC_CONF_ARBITER_ARB_Pos) /**< \brief (MPDDRC_CONF_ARBITER) Type of Arbitration */
+#define MPDDRC_CONF_ARBITER_ARB(value) ((MPDDRC_CONF_ARBITER_ARB_Msk & ((value) << MPDDRC_CONF_ARBITER_ARB_Pos)))
+#define   MPDDRC_CONF_ARBITER_ARB_ROUND (0x0u << 0) /**< \brief (MPDDRC_CONF_ARBITER) Round Robin */
+#define   MPDDRC_CONF_ARBITER_ARB_NB_REQUEST (0x1u << 0) /**< \brief (MPDDRC_CONF_ARBITER) Request Policy */
+#define   MPDDRC_CONF_ARBITER_ARB_BANDWIDTH (0x2u << 0) /**< \brief (MPDDRC_CONF_ARBITER) Bandwidth Policy */
+#define MPDDRC_CONF_ARBITER_BDW_MAX_CUR (0x1u << 3) /**< \brief (MPDDRC_CONF_ARBITER) Bandwidth Max or Current */
+#define MPDDRC_CONF_ARBITER_RQ_WD_P0 (0x1u << 8) /**< \brief (MPDDRC_CONF_ARBITER) Request or Word from Port X */
+#define MPDDRC_CONF_ARBITER_RQ_WD_P1 (0x1u << 9) /**< \brief (MPDDRC_CONF_ARBITER) Request or Word from Port X */
+#define MPDDRC_CONF_ARBITER_RQ_WD_P2 (0x1u << 10) /**< \brief (MPDDRC_CONF_ARBITER) Request or Word from Port X */
+#define MPDDRC_CONF_ARBITER_RQ_WD_P3 (0x1u << 11) /**< \brief (MPDDRC_CONF_ARBITER) Request or Word from Port X */
+#define MPDDRC_CONF_ARBITER_RQ_WD_P4 (0x1u << 12) /**< \brief (MPDDRC_CONF_ARBITER) Request or Word from Port X */
+#define MPDDRC_CONF_ARBITER_RQ_WD_P5 (0x1u << 13) /**< \brief (MPDDRC_CONF_ARBITER) Request or Word from Port X */
+#define MPDDRC_CONF_ARBITER_RQ_WD_P6 (0x1u << 14) /**< \brief (MPDDRC_CONF_ARBITER) Request or Word from Port X */
+#define MPDDRC_CONF_ARBITER_RQ_WD_P7 (0x1u << 15) /**< \brief (MPDDRC_CONF_ARBITER) Request or Word from Port X */
+#define MPDDRC_CONF_ARBITER_MA_PR_P0 (0x1u << 16) /**< \brief (MPDDRC_CONF_ARBITER) Master or Software Provide Information */
+#define MPDDRC_CONF_ARBITER_MA_PR_P1 (0x1u << 17) /**< \brief (MPDDRC_CONF_ARBITER) Master or Software Provide Information */
+#define MPDDRC_CONF_ARBITER_MA_PR_P2 (0x1u << 18) /**< \brief (MPDDRC_CONF_ARBITER) Master or Software Provide Information */
+#define MPDDRC_CONF_ARBITER_MA_PR_P3 (0x1u << 19) /**< \brief (MPDDRC_CONF_ARBITER) Master or Software Provide Information */
+#define MPDDRC_CONF_ARBITER_MA_PR_P4 (0x1u << 20) /**< \brief (MPDDRC_CONF_ARBITER) Master or Software Provide Information */
+#define MPDDRC_CONF_ARBITER_MA_PR_P5 (0x1u << 21) /**< \brief (MPDDRC_CONF_ARBITER) Master or Software Provide Information */
+#define MPDDRC_CONF_ARBITER_MA_PR_P6 (0x1u << 22) /**< \brief (MPDDRC_CONF_ARBITER) Master or Software Provide Information */
+#define MPDDRC_CONF_ARBITER_MA_PR_P7 (0x1u << 23) /**< \brief (MPDDRC_CONF_ARBITER) Master or Software Provide Information */
+#define MPDDRC_CONF_ARBITER_BDW_BURST_P0 (0x1u << 24) /**< \brief (MPDDRC_CONF_ARBITER) Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X */
+#define MPDDRC_CONF_ARBITER_BDW_BURST_P1 (0x1u << 25) /**< \brief (MPDDRC_CONF_ARBITER) Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X */
+#define MPDDRC_CONF_ARBITER_BDW_BURST_P2 (0x1u << 26) /**< \brief (MPDDRC_CONF_ARBITER) Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X */
+#define MPDDRC_CONF_ARBITER_BDW_BURST_P3 (0x1u << 27) /**< \brief (MPDDRC_CONF_ARBITER) Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X */
+#define MPDDRC_CONF_ARBITER_BDW_BURST_P4 (0x1u << 28) /**< \brief (MPDDRC_CONF_ARBITER) Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X */
+#define MPDDRC_CONF_ARBITER_BDW_BURST_P5 (0x1u << 29) /**< \brief (MPDDRC_CONF_ARBITER) Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X */
+#define MPDDRC_CONF_ARBITER_BDW_BURST_P6 (0x1u << 30) /**< \brief (MPDDRC_CONF_ARBITER) Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X */
+#define MPDDRC_CONF_ARBITER_BDW_BURST_P7 (0x1u << 31) /**< \brief (MPDDRC_CONF_ARBITER) Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X */
+/* -------- MPDDRC_TIMEOUT : (MPDDRC Offset: 0x48) MPDDRC Time-out Port 0/1/2/3 Register -------- */
+#define MPDDRC_TIMEOUT_TIMEOUT_P0_Pos 0
+#define MPDDRC_TIMEOUT_TIMEOUT_P0_Msk (0xfu << MPDDRC_TIMEOUT_TIMEOUT_P0_Pos) /**< \brief (MPDDRC_TIMEOUT) Time-out for Ports 0, 1, 2, 3, 4, 5, 6 and 7 */
+#define MPDDRC_TIMEOUT_TIMEOUT_P0(value) ((MPDDRC_TIMEOUT_TIMEOUT_P0_Msk & ((value) << MPDDRC_TIMEOUT_TIMEOUT_P0_Pos)))
+#define MPDDRC_TIMEOUT_TIMEOUT_P1_Pos 4
+#define MPDDRC_TIMEOUT_TIMEOUT_P1_Msk (0xfu << MPDDRC_TIMEOUT_TIMEOUT_P1_Pos) /**< \brief (MPDDRC_TIMEOUT) Time-out for Ports 0, 1, 2, 3, 4, 5, 6 and 7 */
+#define MPDDRC_TIMEOUT_TIMEOUT_P1(value) ((MPDDRC_TIMEOUT_TIMEOUT_P1_Msk & ((value) << MPDDRC_TIMEOUT_TIMEOUT_P1_Pos)))
+#define MPDDRC_TIMEOUT_TIMEOUT_P2_Pos 8
+#define MPDDRC_TIMEOUT_TIMEOUT_P2_Msk (0xfu << MPDDRC_TIMEOUT_TIMEOUT_P2_Pos) /**< \brief (MPDDRC_TIMEOUT) Time-out for Ports 0, 1, 2, 3, 4, 5, 6 and 7 */
+#define MPDDRC_TIMEOUT_TIMEOUT_P2(value) ((MPDDRC_TIMEOUT_TIMEOUT_P2_Msk & ((value) << MPDDRC_TIMEOUT_TIMEOUT_P2_Pos)))
+#define MPDDRC_TIMEOUT_TIMEOUT_P3_Pos 12
+#define MPDDRC_TIMEOUT_TIMEOUT_P3_Msk (0xfu << MPDDRC_TIMEOUT_TIMEOUT_P3_Pos) /**< \brief (MPDDRC_TIMEOUT) Time-out for Ports 0, 1, 2, 3, 4, 5, 6 and 7 */
+#define MPDDRC_TIMEOUT_TIMEOUT_P3(value) ((MPDDRC_TIMEOUT_TIMEOUT_P3_Msk & ((value) << MPDDRC_TIMEOUT_TIMEOUT_P3_Pos)))
+#define MPDDRC_TIMEOUT_TIMEOUT_P4_Pos 16
+#define MPDDRC_TIMEOUT_TIMEOUT_P4_Msk (0xfu << MPDDRC_TIMEOUT_TIMEOUT_P4_Pos) /**< \brief (MPDDRC_TIMEOUT) Time-out for Ports 0, 1, 2, 3, 4, 5, 6 and 7 */
+#define MPDDRC_TIMEOUT_TIMEOUT_P4(value) ((MPDDRC_TIMEOUT_TIMEOUT_P4_Msk & ((value) << MPDDRC_TIMEOUT_TIMEOUT_P4_Pos)))
+#define MPDDRC_TIMEOUT_TIMEOUT_P5_Pos 20
+#define MPDDRC_TIMEOUT_TIMEOUT_P5_Msk (0xfu << MPDDRC_TIMEOUT_TIMEOUT_P5_Pos) /**< \brief (MPDDRC_TIMEOUT) Time-out for Ports 0, 1, 2, 3, 4, 5, 6 and 7 */
+#define MPDDRC_TIMEOUT_TIMEOUT_P5(value) ((MPDDRC_TIMEOUT_TIMEOUT_P5_Msk & ((value) << MPDDRC_TIMEOUT_TIMEOUT_P5_Pos)))
+#define MPDDRC_TIMEOUT_TIMEOUT_P6_Pos 24
+#define MPDDRC_TIMEOUT_TIMEOUT_P6_Msk (0xfu << MPDDRC_TIMEOUT_TIMEOUT_P6_Pos) /**< \brief (MPDDRC_TIMEOUT) Time-out for Ports 0, 1, 2, 3, 4, 5, 6 and 7 */
+#define MPDDRC_TIMEOUT_TIMEOUT_P6(value) ((MPDDRC_TIMEOUT_TIMEOUT_P6_Msk & ((value) << MPDDRC_TIMEOUT_TIMEOUT_P6_Pos)))
+#define MPDDRC_TIMEOUT_TIMEOUT_P7_Pos 28
+#define MPDDRC_TIMEOUT_TIMEOUT_P7_Msk (0xfu << MPDDRC_TIMEOUT_TIMEOUT_P7_Pos) /**< \brief (MPDDRC_TIMEOUT) Time-out for Ports 0, 1, 2, 3, 4, 5, 6 and 7 */
+#define MPDDRC_TIMEOUT_TIMEOUT_P7(value) ((MPDDRC_TIMEOUT_TIMEOUT_P7_Msk & ((value) << MPDDRC_TIMEOUT_TIMEOUT_P7_Pos)))
+/* -------- MPDDRC_REQ_PORT_0123 : (MPDDRC Offset: 0x4C) MPDDRC Request Port 0/1/2/3 Register -------- */
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0_Pos 0
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0_Msk (0xffu << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0_Pos) /**< \brief (MPDDRC_REQ_PORT_0123) Number of Requests, Number of Words or Bandwidth Allocation from Port 0-1-2-3 */
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0(value) ((MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0_Msk & ((value) << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P0_Pos)))
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P1_Pos 8
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P1_Msk (0xffu << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P1_Pos) /**< \brief (MPDDRC_REQ_PORT_0123) Number of Requests, Number of Words or Bandwidth Allocation from Port 0-1-2-3 */
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P1(value) ((MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P1_Msk & ((value) << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P1_Pos)))
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P2_Pos 16
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P2_Msk (0xffu << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P2_Pos) /**< \brief (MPDDRC_REQ_PORT_0123) Number of Requests, Number of Words or Bandwidth Allocation from Port 0-1-2-3 */
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P2(value) ((MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P2_Msk & ((value) << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P2_Pos)))
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P3_Pos 24
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P3_Msk (0xffu << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P3_Pos) /**< \brief (MPDDRC_REQ_PORT_0123) Number of Requests, Number of Words or Bandwidth Allocation from Port 0-1-2-3 */
+#define MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P3(value) ((MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P3_Msk & ((value) << MPDDRC_REQ_PORT_0123_NRQ_NWD_BDW_P3_Pos)))
+/* -------- MPDDRC_REQ_PORT_4567 : (MPDDRC Offset: 0x50) MPDDRC Request Port 4/5/6/7 Register -------- */
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P4_Pos 0
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P4_Msk (0xffu << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P4_Pos) /**< \brief (MPDDRC_REQ_PORT_4567) Number of Requests, Number of Words or Bandwidth allocation from port 4-5-6-7 */
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P4(value) ((MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P4_Msk & ((value) << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P4_Pos)))
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P5_Pos 8
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P5_Msk (0xffu << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P5_Pos) /**< \brief (MPDDRC_REQ_PORT_4567) Number of Requests, Number of Words or Bandwidth allocation from port 4-5-6-7 */
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P5(value) ((MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P5_Msk & ((value) << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P5_Pos)))
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P6_Pos 16
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P6_Msk (0xffu << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P6_Pos) /**< \brief (MPDDRC_REQ_PORT_4567) Number of Requests, Number of Words or Bandwidth allocation from port 4-5-6-7 */
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P6(value) ((MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P6_Msk & ((value) << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P6_Pos)))
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P7_Pos 24
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P7_Msk (0xffu << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P7_Pos) /**< \brief (MPDDRC_REQ_PORT_4567) Number of Requests, Number of Words or Bandwidth allocation from port 4-5-6-7 */
+#define MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P7(value) ((MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P7_Msk & ((value) << MPDDRC_REQ_PORT_4567_NRQ_NWD_BDW_P7_Pos)))
+/* -------- MPDDRC_BDW_PORT_0123 : (MPDDRC Offset: 0x54) MPDDRC Bandwidth Port 0/1/2/3 Register -------- */
+#define MPDDRC_BDW_PORT_0123_BDW_P0_Pos 0
+#define MPDDRC_BDW_PORT_0123_BDW_P0_Msk (0x7fu << MPDDRC_BDW_PORT_0123_BDW_P0_Pos) /**< \brief (MPDDRC_BDW_PORT_0123) Current/Maximum Bandwidth from Port 0-1-2-3 */
+#define MPDDRC_BDW_PORT_0123_BDW_P1_Pos 8
+#define MPDDRC_BDW_PORT_0123_BDW_P1_Msk (0x7fu << MPDDRC_BDW_PORT_0123_BDW_P1_Pos) /**< \brief (MPDDRC_BDW_PORT_0123) Current/Maximum Bandwidth from Port 0-1-2-3 */
+#define MPDDRC_BDW_PORT_0123_BDW_P2_Pos 16
+#define MPDDRC_BDW_PORT_0123_BDW_P2_Msk (0x7fu << MPDDRC_BDW_PORT_0123_BDW_P2_Pos) /**< \brief (MPDDRC_BDW_PORT_0123) Current/Maximum Bandwidth from Port 0-1-2-3 */
+#define MPDDRC_BDW_PORT_0123_BDW_P3_Pos 24
+#define MPDDRC_BDW_PORT_0123_BDW_P3_Msk (0x7fu << MPDDRC_BDW_PORT_0123_BDW_P3_Pos) /**< \brief (MPDDRC_BDW_PORT_0123) Current/Maximum Bandwidth from Port 0-1-2-3 */
+/* -------- MPDDRC_BDW_PORT_4567 : (MPDDRC Offset: 0x58) MPDDRC Bandwidth Port 4/5/6/7 Register -------- */
+#define MPDDRC_BDW_PORT_4567_BDW_P4_Pos 0
+#define MPDDRC_BDW_PORT_4567_BDW_P4_Msk (0x7fu << MPDDRC_BDW_PORT_4567_BDW_P4_Pos) /**< \brief (MPDDRC_BDW_PORT_4567) Current/Maximum Bandwidth from Port 4-5-6-7 */
+#define MPDDRC_BDW_PORT_4567_BDW_P5_Pos 8
+#define MPDDRC_BDW_PORT_4567_BDW_P5_Msk (0x7fu << MPDDRC_BDW_PORT_4567_BDW_P5_Pos) /**< \brief (MPDDRC_BDW_PORT_4567) Current/Maximum Bandwidth from Port 4-5-6-7 */
+#define MPDDRC_BDW_PORT_4567_BDW_P6_Pos 16
+#define MPDDRC_BDW_PORT_4567_BDW_P6_Msk (0x7fu << MPDDRC_BDW_PORT_4567_BDW_P6_Pos) /**< \brief (MPDDRC_BDW_PORT_4567) Current/Maximum Bandwidth from Port 4-5-6-7 */
+#define MPDDRC_BDW_PORT_4567_BDW_P7_Pos 24
+#define MPDDRC_BDW_PORT_4567_BDW_P7_Msk (0x7fu << MPDDRC_BDW_PORT_4567_BDW_P7_Pos) /**< \brief (MPDDRC_BDW_PORT_4567) Current/Maximum Bandwidth from Port 4-5-6-7 */
+/* -------- MPDDRC_RD_DATA_PATH : (MPDDRC Offset: 0x5C) MPDDRC Read Datapath Register -------- */
+#define MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_Pos 0
+#define MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_Msk (0x3u << MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_Pos) /**< \brief (MPDDRC_RD_DATA_PATH) Shift Sampling Point of Data */
+#define MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING(value) ((MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_Msk & ((value) << MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_Pos)))
+#define   MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_NO_SHIFT (0x0u << 0) /**< \brief (MPDDRC_RD_DATA_PATH) Initial sampling point. */
+#define   MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_SHIFT_ONE_CYCLE (0x1u << 0) /**< \brief (MPDDRC_RD_DATA_PATH) Sampling point is shifted by one cycle. */
+#define   MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_SHIFT_TWO_CYCLES (0x2u << 0) /**< \brief (MPDDRC_RD_DATA_PATH) Sampling point is shifted by two cycles. */
+#define   MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING_SHIFT_THREE_CYCLES (0x3u << 0) /**< \brief (MPDDRC_RD_DATA_PATH) Sampling point is shifted by three cycles. */
+/* -------- MPDDRC_MCFGR : (MPDDRC Offset: 0x60) MPDDRC Monitor Configuration -------- */
+#define MPDDRC_MCFGR_EN_MONI (0x1u << 0) /**< \brief (MPDDRC_MCFGR) Enable Monitor */
+#define MPDDRC_MCFGR_SOFT_RESET (0x1u << 1) /**< \brief (MPDDRC_MCFGR) Soft Reset */
+#define MPDDRC_MCFGR_RUN (0x1u << 4) /**< \brief (MPDDRC_MCFGR) Control Monitor */
+#define MPDDRC_MCFGR_READ_WRITE_Pos 8
+#define MPDDRC_MCFGR_READ_WRITE_Msk (0x3u << MPDDRC_MCFGR_READ_WRITE_Pos) /**< \brief (MPDDRC_MCFGR) Read/Write Access */
+#define MPDDRC_MCFGR_READ_WRITE(value) ((MPDDRC_MCFGR_READ_WRITE_Msk & ((value) << MPDDRC_MCFGR_READ_WRITE_Pos)))
+#define   MPDDRC_MCFGR_READ_WRITE_TRIG_RD_WR (0x0u << 8) /**< \brief (MPDDRC_MCFGR) Read and Write accesses are triggered. */
+#define   MPDDRC_MCFGR_READ_WRITE_TRIG_WR (0x1u << 8) /**< \brief (MPDDRC_MCFGR) Only Write accesses are triggered. */
+#define   MPDDRC_MCFGR_READ_WRITE_TRIG_RD (0x2u << 8) /**< \brief (MPDDRC_MCFGR) Only Read accesses are triggered. */
+#define MPDDRC_MCFGR_REFR_CALIB (0x1u << 10) /**< \brief (MPDDRC_MCFGR) Refresh Calibration */
+#define MPDDRC_MCFGR_INFO_Pos 11
+#define MPDDRC_MCFGR_INFO_Msk (0x3u << MPDDRC_MCFGR_INFO_Pos) /**< \brief (MPDDRC_MCFGR) Information Type */
+#define MPDDRC_MCFGR_INFO(value) ((MPDDRC_MCFGR_INFO_Msk & ((value) << MPDDRC_MCFGR_INFO_Pos)))
+#define   MPDDRC_MCFGR_INFO_MAX_WAIT (0x0u << 11) /**< \brief (MPDDRC_MCFGR) Information concerning the transfer with the longest waiting time */
+#define   MPDDRC_MCFGR_INFO_NB_TRANSFERS (0x1u << 11) /**< \brief (MPDDRC_MCFGR) Number of transfers on the port */
+#define   MPDDRC_MCFGR_INFO_TOTAL_LATENCY (0x2u << 11) /**< \brief (MPDDRC_MCFGR) Total latency on the port */
+/* -------- MPDDRC_MADDR0 : (MPDDRC Offset: 0x64) MPDDRC Monitor Address High/Low port 0 -------- */
+#define MPDDRC_MADDR0_ADDR_LOW_PORT0_Pos 0
+#define MPDDRC_MADDR0_ADDR_LOW_PORT0_Msk (0xffffu << MPDDRC_MADDR0_ADDR_LOW_PORT0_Pos) /**< \brief (MPDDRC_MADDR0) Address Low on Port x [x =0..7] */
+#define MPDDRC_MADDR0_ADDR_LOW_PORT0(value) ((MPDDRC_MADDR0_ADDR_LOW_PORT0_Msk & ((value) << MPDDRC_MADDR0_ADDR_LOW_PORT0_Pos)))
+#define MPDDRC_MADDR0_ADDR_HIGH_PORT0_Pos 16
+#define MPDDRC_MADDR0_ADDR_HIGH_PORT0_Msk (0xffffu << MPDDRC_MADDR0_ADDR_HIGH_PORT0_Pos) /**< \brief (MPDDRC_MADDR0) Address High on Port x [x =0..7] */
+#define MPDDRC_MADDR0_ADDR_HIGH_PORT0(value) ((MPDDRC_MADDR0_ADDR_HIGH_PORT0_Msk & ((value) << MPDDRC_MADDR0_ADDR_HIGH_PORT0_Pos)))
+/* -------- MPDDRC_MADDR1 : (MPDDRC Offset: 0x68) MPDDRC Monitor Address High/Low port 1 -------- */
+#define MPDDRC_MADDR1_ADDR_LOW_PORT1_Pos 0
+#define MPDDRC_MADDR1_ADDR_LOW_PORT1_Msk (0xffffu << MPDDRC_MADDR1_ADDR_LOW_PORT1_Pos) /**< \brief (MPDDRC_MADDR1) Address Low on Port x [x =0..7] */
+#define MPDDRC_MADDR1_ADDR_LOW_PORT1(value) ((MPDDRC_MADDR1_ADDR_LOW_PORT1_Msk & ((value) << MPDDRC_MADDR1_ADDR_LOW_PORT1_Pos)))
+#define MPDDRC_MADDR1_ADDR_HIGH_PORT1_Pos 16
+#define MPDDRC_MADDR1_ADDR_HIGH_PORT1_Msk (0xffffu << MPDDRC_MADDR1_ADDR_HIGH_PORT1_Pos) /**< \brief (MPDDRC_MADDR1) Address High on Port x [x =0..7] */
+#define MPDDRC_MADDR1_ADDR_HIGH_PORT1(value) ((MPDDRC_MADDR1_ADDR_HIGH_PORT1_Msk & ((value) << MPDDRC_MADDR1_ADDR_HIGH_PORT1_Pos)))
+/* -------- MPDDRC_MADDR2 : (MPDDRC Offset: 0x6C) MPDDRC Monitor Address High/Low port 2 -------- */
+#define MPDDRC_MADDR2_ADDR_LOW_PORT2_Pos 0
+#define MPDDRC_MADDR2_ADDR_LOW_PORT2_Msk (0xffffu << MPDDRC_MADDR2_ADDR_LOW_PORT2_Pos) /**< \brief (MPDDRC_MADDR2) Address Low on Port x [x =0..7] */
+#define MPDDRC_MADDR2_ADDR_LOW_PORT2(value) ((MPDDRC_MADDR2_ADDR_LOW_PORT2_Msk & ((value) << MPDDRC_MADDR2_ADDR_LOW_PORT2_Pos)))
+#define MPDDRC_MADDR2_ADDR_HIGH_PORT2_Pos 16
+#define MPDDRC_MADDR2_ADDR_HIGH_PORT2_Msk (0xffffu << MPDDRC_MADDR2_ADDR_HIGH_PORT2_Pos) /**< \brief (MPDDRC_MADDR2) Address High on Port x [x =0..7] */
+#define MPDDRC_MADDR2_ADDR_HIGH_PORT2(value) ((MPDDRC_MADDR2_ADDR_HIGH_PORT2_Msk & ((value) << MPDDRC_MADDR2_ADDR_HIGH_PORT2_Pos)))
+/* -------- MPDDRC_MADDR3 : (MPDDRC Offset: 0x70) MPDDRC Monitor Address High/Low port 3 -------- */
+#define MPDDRC_MADDR3_ADDR_LOW_PORT3_Pos 0
+#define MPDDRC_MADDR3_ADDR_LOW_PORT3_Msk (0xffffu << MPDDRC_MADDR3_ADDR_LOW_PORT3_Pos) /**< \brief (MPDDRC_MADDR3) Address Low on Port x [x =0..7] */
+#define MPDDRC_MADDR3_ADDR_LOW_PORT3(value) ((MPDDRC_MADDR3_ADDR_LOW_PORT3_Msk & ((value) << MPDDRC_MADDR3_ADDR_LOW_PORT3_Pos)))
+#define MPDDRC_MADDR3_ADDR_HIGH_PORT3_Pos 16
+#define MPDDRC_MADDR3_ADDR_HIGH_PORT3_Msk (0xffffu << MPDDRC_MADDR3_ADDR_HIGH_PORT3_Pos) /**< \brief (MPDDRC_MADDR3) Address High on Port x [x =0..7] */
+#define MPDDRC_MADDR3_ADDR_HIGH_PORT3(value) ((MPDDRC_MADDR3_ADDR_HIGH_PORT3_Msk & ((value) << MPDDRC_MADDR3_ADDR_HIGH_PORT3_Pos)))
+/* -------- MPDDRC_MADDR4 : (MPDDRC Offset: 0x74) MPDDRC Monitor Address High/Low port 4 -------- */
+#define MPDDRC_MADDR4_ADDR_LOW_PORT4_Pos 0
+#define MPDDRC_MADDR4_ADDR_LOW_PORT4_Msk (0xffffu << MPDDRC_MADDR4_ADDR_LOW_PORT4_Pos) /**< \brief (MPDDRC_MADDR4) Address Low on Port x [x =0..7] */
+#define MPDDRC_MADDR4_ADDR_LOW_PORT4(value) ((MPDDRC_MADDR4_ADDR_LOW_PORT4_Msk & ((value) << MPDDRC_MADDR4_ADDR_LOW_PORT4_Pos)))
+#define MPDDRC_MADDR4_ADDR_HIGH_PORT4_Pos 16
+#define MPDDRC_MADDR4_ADDR_HIGH_PORT4_Msk (0xffffu << MPDDRC_MADDR4_ADDR_HIGH_PORT4_Pos) /**< \brief (MPDDRC_MADDR4) Address High on Port x [x =0..7] */
+#define MPDDRC_MADDR4_ADDR_HIGH_PORT4(value) ((MPDDRC_MADDR4_ADDR_HIGH_PORT4_Msk & ((value) << MPDDRC_MADDR4_ADDR_HIGH_PORT4_Pos)))
+/* -------- MPDDRC_MADDR5 : (MPDDRC Offset: 0x78) MPDDRC Monitor Address High/Low port 5 -------- */
+#define MPDDRC_MADDR5_ADDR_LOW_PORT5_Pos 0
+#define MPDDRC_MADDR5_ADDR_LOW_PORT5_Msk (0xffffu << MPDDRC_MADDR5_ADDR_LOW_PORT5_Pos) /**< \brief (MPDDRC_MADDR5) Address Low on Port x [x =0..7] */
+#define MPDDRC_MADDR5_ADDR_LOW_PORT5(value) ((MPDDRC_MADDR5_ADDR_LOW_PORT5_Msk & ((value) << MPDDRC_MADDR5_ADDR_LOW_PORT5_Pos)))
+#define MPDDRC_MADDR5_ADDR_HIGH_PORT5_Pos 16
+#define MPDDRC_MADDR5_ADDR_HIGH_PORT5_Msk (0xffffu << MPDDRC_MADDR5_ADDR_HIGH_PORT5_Pos) /**< \brief (MPDDRC_MADDR5) Address High on Port x [x =0..7] */
+#define MPDDRC_MADDR5_ADDR_HIGH_PORT5(value) ((MPDDRC_MADDR5_ADDR_HIGH_PORT5_Msk & ((value) << MPDDRC_MADDR5_ADDR_HIGH_PORT5_Pos)))
+/* -------- MPDDRC_MADDR6 : (MPDDRC Offset: 0x7C) MPDDRC Monitor Address High/Low port 6 -------- */
+#define MPDDRC_MADDR6_ADDR_LOW_PORT6_Pos 0
+#define MPDDRC_MADDR6_ADDR_LOW_PORT6_Msk (0xffffu << MPDDRC_MADDR6_ADDR_LOW_PORT6_Pos) /**< \brief (MPDDRC_MADDR6) Address Low on Port x [x =0..7] */
+#define MPDDRC_MADDR6_ADDR_LOW_PORT6(value) ((MPDDRC_MADDR6_ADDR_LOW_PORT6_Msk & ((value) << MPDDRC_MADDR6_ADDR_LOW_PORT6_Pos)))
+#define MPDDRC_MADDR6_ADDR_HIGH_PORT6_Pos 16
+#define MPDDRC_MADDR6_ADDR_HIGH_PORT6_Msk (0xffffu << MPDDRC_MADDR6_ADDR_HIGH_PORT6_Pos) /**< \brief (MPDDRC_MADDR6) Address High on Port x [x =0..7] */
+#define MPDDRC_MADDR6_ADDR_HIGH_PORT6(value) ((MPDDRC_MADDR6_ADDR_HIGH_PORT6_Msk & ((value) << MPDDRC_MADDR6_ADDR_HIGH_PORT6_Pos)))
+/* -------- MPDDRC_MADDR7 : (MPDDRC Offset: 0x80) MPDDRC Monitor Address High/Low port 7 -------- */
+#define MPDDRC_MADDR7_ADDR_LOW_PORT7_Pos 0
+#define MPDDRC_MADDR7_ADDR_LOW_PORT7_Msk (0xffffu << MPDDRC_MADDR7_ADDR_LOW_PORT7_Pos) /**< \brief (MPDDRC_MADDR7) Address Low on Port x [x =0..7] */
+#define MPDDRC_MADDR7_ADDR_LOW_PORT7(value) ((MPDDRC_MADDR7_ADDR_LOW_PORT7_Msk & ((value) << MPDDRC_MADDR7_ADDR_LOW_PORT7_Pos)))
+#define MPDDRC_MADDR7_ADDR_HIGH_PORT7_Pos 16
+#define MPDDRC_MADDR7_ADDR_HIGH_PORT7_Msk (0xffffu << MPDDRC_MADDR7_ADDR_HIGH_PORT7_Pos) /**< \brief (MPDDRC_MADDR7) Address High on Port x [x =0..7] */
+#define MPDDRC_MADDR7_ADDR_HIGH_PORT7(value) ((MPDDRC_MADDR7_ADDR_HIGH_PORT7_Msk & ((value) << MPDDRC_MADDR7_ADDR_HIGH_PORT7_Pos)))
+/* -------- MPDDRC_MINFO0 : (MPDDRC Offset: 0x84) MPDDRC Monitor Information port 0 -------- */
+#define MPDDRC_MINFO0_MAX_PORT0_WAITING_Pos 0
+#define MPDDRC_MINFO0_MAX_PORT0_WAITING_Msk (0xffffu << MPDDRC_MINFO0_MAX_PORT0_WAITING_Pos) /**< \brief (MPDDRC_MINFO0) Address High on Port x [x =0..7] */
+#define MPDDRC_MINFO0_BURST_Pos 16
+#define MPDDRC_MINFO0_BURST_Msk (0x7u << MPDDRC_MINFO0_BURST_Pos) /**< \brief (MPDDRC_MINFO0) Type of Burst on Port x [x =0..7] */
+#define   MPDDRC_MINFO0_BURST_SINGLE (0x0u << 16) /**< \brief (MPDDRC_MINFO0) Single transfer */
+#define   MPDDRC_MINFO0_BURST_INCR (0x1u << 16) /**< \brief (MPDDRC_MINFO0) Incrementing burst of unspecified length */
+#define   MPDDRC_MINFO0_BURST_WRAP4 (0x2u << 16) /**< \brief (MPDDRC_MINFO0) 4-beat wrapping burst */
+#define   MPDDRC_MINFO0_BURST_INCR4 (0x3u << 16) /**< \brief (MPDDRC_MINFO0) 4-beat incrementing burst */
+#define   MPDDRC_MINFO0_BURST_WRAP8 (0x4u << 16) /**< \brief (MPDDRC_MINFO0) 8-beat wrapping burst */
+#define   MPDDRC_MINFO0_BURST_INCR8 (0x5u << 16) /**< \brief (MPDDRC_MINFO0) 8-beat incrementing burst */
+#define   MPDDRC_MINFO0_BURST_WRAP16 (0x6u << 16) /**< \brief (MPDDRC_MINFO0) 16-beat wrapping burst */
+#define   MPDDRC_MINFO0_BURST_INCR16 (0x7u << 16) /**< \brief (MPDDRC_MINFO0) 16-beat incrementing burst */
+#define MPDDRC_MINFO0_SIZE_Pos 20
+#define MPDDRC_MINFO0_SIZE_Msk (0x7u << MPDDRC_MINFO0_SIZE_Pos) /**< \brief (MPDDRC_MINFO0) Transfer Size on Port x [x =0..7] */
+#define   MPDDRC_MINFO0_SIZE_8BITS (0x0u << 20) /**< \brief (MPDDRC_MINFO0) Byte transfer */
+#define   MPDDRC_MINFO0_SIZE_16BITS (0x1u << 20) /**< \brief (MPDDRC_MINFO0) Halfword transfer */
+#define   MPDDRC_MINFO0_SIZE_32BITS (0x2u << 20) /**< \brief (MPDDRC_MINFO0) Word transfer */
+#define   MPDDRC_MINFO0_SIZE_64BITS (0x3u << 20) /**< \brief (MPDDRC_MINFO0) Dword transfer */
+#define MPDDRC_MINFO0_READ_WRITE (0x1u << 24) /**< \brief (MPDDRC_MINFO0) Read or Write Access on Port x [x =0..7] */
+#define MPDDRC_MINFO0_P0_NB_TRANSFERS_Pos 0
+#define MPDDRC_MINFO0_P0_NB_TRANSFERS_Msk (0xffffffffu << MPDDRC_MINFO0_P0_NB_TRANSFERS_Pos) /**< \brief (MPDDRC_MINFO0) Number of Transfers on Port x [x =0..7] */
+#define MPDDRC_MINFO0_P0_TOTAL_LATENCY_Pos 0
+#define MPDDRC_MINFO0_P0_TOTAL_LATENCY_Msk (0xffffffffu << MPDDRC_MINFO0_P0_TOTAL_LATENCY_Pos) /**< \brief (MPDDRC_MINFO0) Total Latency on Port x [x =0..7] */
+/* -------- MPDDRC_MINFO1 : (MPDDRC Offset: 0x88) MPDDRC Monitor Information port 1 -------- */
+#define MPDDRC_MINFO1_MAX_PORT1_WAITING_Pos 0
+#define MPDDRC_MINFO1_MAX_PORT1_WAITING_Msk (0xffffu << MPDDRC_MINFO1_MAX_PORT1_WAITING_Pos) /**< \brief (MPDDRC_MINFO1) Address High on Port x [x =0..7] */
+#define MPDDRC_MINFO1_BURST_Pos 16
+#define MPDDRC_MINFO1_BURST_Msk (0x7u << MPDDRC_MINFO1_BURST_Pos) /**< \brief (MPDDRC_MINFO1) Type of Burst on Port x [x =0..7] */
+#define   MPDDRC_MINFO1_BURST_SINGLE (0x0u << 16) /**< \brief (MPDDRC_MINFO1) Single transfer */
+#define   MPDDRC_MINFO1_BURST_INCR (0x1u << 16) /**< \brief (MPDDRC_MINFO1) Incrementing burst of unspecified length */
+#define   MPDDRC_MINFO1_BURST_WRAP4 (0x2u << 16) /**< \brief (MPDDRC_MINFO1) 4-beat wrapping burst */
+#define   MPDDRC_MINFO1_BURST_INCR4 (0x3u << 16) /**< \brief (MPDDRC_MINFO1) 4-beat incrementing burst */
+#define   MPDDRC_MINFO1_BURST_WRAP8 (0x4u << 16) /**< \brief (MPDDRC_MINFO1) 8-beat wrapping burst */
+#define   MPDDRC_MINFO1_BURST_INCR8 (0x5u << 16) /**< \brief (MPDDRC_MINFO1) 8-beat incrementing burst */
+#define   MPDDRC_MINFO1_BURST_WRAP16 (0x6u << 16) /**< \brief (MPDDRC_MINFO1) 16-beat wrapping burst */
+#define   MPDDRC_MINFO1_BURST_INCR16 (0x7u << 16) /**< \brief (MPDDRC_MINFO1) 16-beat incrementing burst */
+#define MPDDRC_MINFO1_SIZE_Pos 20
+#define MPDDRC_MINFO1_SIZE_Msk (0x7u << MPDDRC_MINFO1_SIZE_Pos) /**< \brief (MPDDRC_MINFO1) Transfer Size on Port x [x =0..7] */
+#define   MPDDRC_MINFO1_SIZE_8BITS (0x0u << 20) /**< \brief (MPDDRC_MINFO1) Byte transfer */
+#define   MPDDRC_MINFO1_SIZE_16BITS (0x1u << 20) /**< \brief (MPDDRC_MINFO1) Halfword transfer */
+#define   MPDDRC_MINFO1_SIZE_32BITS (0x2u << 20) /**< \brief (MPDDRC_MINFO1) Word transfer */
+#define   MPDDRC_MINFO1_SIZE_64BITS (0x3u << 20) /**< \brief (MPDDRC_MINFO1) Dword transfer */
+#define MPDDRC_MINFO1_READ_WRITE (0x1u << 24) /**< \brief (MPDDRC_MINFO1) Read or Write Access on Port x [x =0..7] */
+#define MPDDRC_MINFO1_P1_NB_TRANSFERS_Pos 0
+#define MPDDRC_MINFO1_P1_NB_TRANSFERS_Msk (0xffffffffu << MPDDRC_MINFO1_P1_NB_TRANSFERS_Pos) /**< \brief (MPDDRC_MINFO1) Number of Transfers on Port x [x =0..7] */
+#define MPDDRC_MINFO1_P1_TOTAL_LATENCY_Pos 0
+#define MPDDRC_MINFO1_P1_TOTAL_LATENCY_Msk (0xffffffffu << MPDDRC_MINFO1_P1_TOTAL_LATENCY_Pos) /**< \brief (MPDDRC_MINFO1) Total Latency on Port x [x =0..7] */
+/* -------- MPDDRC_MINFO2 : (MPDDRC Offset: 0x8C) MPDDRC Monitor Information port 2 -------- */
+#define MPDDRC_MINFO2_MAX_PORT2_WAITING_Pos 0
+#define MPDDRC_MINFO2_MAX_PORT2_WAITING_Msk (0xffffu << MPDDRC_MINFO2_MAX_PORT2_WAITING_Pos) /**< \brief (MPDDRC_MINFO2) Address High on Port x [x =0..7] */
+#define MPDDRC_MINFO2_BURST_Pos 16
+#define MPDDRC_MINFO2_BURST_Msk (0x7u << MPDDRC_MINFO2_BURST_Pos) /**< \brief (MPDDRC_MINFO2) Type of Burst on Port x [x =0..7] */
+#define   MPDDRC_MINFO2_BURST_SINGLE (0x0u << 16) /**< \brief (MPDDRC_MINFO2) Single transfer */
+#define   MPDDRC_MINFO2_BURST_INCR (0x1u << 16) /**< \brief (MPDDRC_MINFO2) Incrementing burst of unspecified length */
+#define   MPDDRC_MINFO2_BURST_WRAP4 (0x2u << 16) /**< \brief (MPDDRC_MINFO2) 4-beat wrapping burst */
+#define   MPDDRC_MINFO2_BURST_INCR4 (0x3u << 16) /**< \brief (MPDDRC_MINFO2) 4-beat incrementing burst */
+#define   MPDDRC_MINFO2_BURST_WRAP8 (0x4u << 16) /**< \brief (MPDDRC_MINFO2) 8-beat wrapping burst */
+#define   MPDDRC_MINFO2_BURST_INCR8 (0x5u << 16) /**< \brief (MPDDRC_MINFO2) 8-beat incrementing burst */
+#define   MPDDRC_MINFO2_BURST_WRAP16 (0x6u << 16) /**< \brief (MPDDRC_MINFO2) 16-beat wrapping burst */
+#define   MPDDRC_MINFO2_BURST_INCR16 (0x7u << 16) /**< \brief (MPDDRC_MINFO2) 16-beat incrementing burst */
+#define MPDDRC_MINFO2_SIZE_Pos 20
+#define MPDDRC_MINFO2_SIZE_Msk (0x7u << MPDDRC_MINFO2_SIZE_Pos) /**< \brief (MPDDRC_MINFO2) Transfer Size on Port x [x =0..7] */
+#define   MPDDRC_MINFO2_SIZE_8BITS (0x0u << 20) /**< \brief (MPDDRC_MINFO2) Byte transfer */
+#define   MPDDRC_MINFO2_SIZE_16BITS (0x1u << 20) /**< \brief (MPDDRC_MINFO2) Halfword transfer */
+#define   MPDDRC_MINFO2_SIZE_32BITS (0x2u << 20) /**< \brief (MPDDRC_MINFO2) Word transfer */
+#define   MPDDRC_MINFO2_SIZE_64BITS (0x3u << 20) /**< \brief (MPDDRC_MINFO2) Dword transfer */
+#define MPDDRC_MINFO2_READ_WRITE (0x1u << 24) /**< \brief (MPDDRC_MINFO2) Read or Write Access on Port x [x =0..7] */
+#define MPDDRC_MINFO2_P2_NB_TRANSFERS_Pos 0
+#define MPDDRC_MINFO2_P2_NB_TRANSFERS_Msk (0xffffffffu << MPDDRC_MINFO2_P2_NB_TRANSFERS_Pos) /**< \brief (MPDDRC_MINFO2) Number of Transfers on Port x [x =0..7] */
+#define MPDDRC_MINFO2_P2_TOTAL_LATENCY_Pos 0
+#define MPDDRC_MINFO2_P2_TOTAL_LATENCY_Msk (0xffffffffu << MPDDRC_MINFO2_P2_TOTAL_LATENCY_Pos) /**< \brief (MPDDRC_MINFO2) Total Latency on Port x [x =0..7] */
+/* -------- MPDDRC_MINFO3 : (MPDDRC Offset: 0x90) MPDDRC Monitor Information port 3 -------- */
+#define MPDDRC_MINFO3_MAX_PORT3_WAITING_Pos 0
+#define MPDDRC_MINFO3_MAX_PORT3_WAITING_Msk (0xffffu << MPDDRC_MINFO3_MAX_PORT3_WAITING_Pos) /**< \brief (MPDDRC_MINFO3) Address High on Port x [x =0..7] */
+#define MPDDRC_MINFO3_BURST_Pos 16
+#define MPDDRC_MINFO3_BURST_Msk (0x7u << MPDDRC_MINFO3_BURST_Pos) /**< \brief (MPDDRC_MINFO3) Type of Burst on Port x [x =0..7] */
+#define   MPDDRC_MINFO3_BURST_SINGLE (0x0u << 16) /**< \brief (MPDDRC_MINFO3) Single transfer */
+#define   MPDDRC_MINFO3_BURST_INCR (0x1u << 16) /**< \brief (MPDDRC_MINFO3) Incrementing burst of unspecified length */
+#define   MPDDRC_MINFO3_BURST_WRAP4 (0x2u << 16) /**< \brief (MPDDRC_MINFO3) 4-beat wrapping burst */
+#define   MPDDRC_MINFO3_BURST_INCR4 (0x3u << 16) /**< \brief (MPDDRC_MINFO3) 4-beat incrementing burst */
+#define   MPDDRC_MINFO3_BURST_WRAP8 (0x4u << 16) /**< \brief (MPDDRC_MINFO3) 8-beat wrapping burst */
+#define   MPDDRC_MINFO3_BURST_INCR8 (0x5u << 16) /**< \brief (MPDDRC_MINFO3) 8-beat incrementing burst */
+#define   MPDDRC_MINFO3_BURST_WRAP16 (0x6u << 16) /**< \brief (MPDDRC_MINFO3) 16-beat wrapping burst */
+#define   MPDDRC_MINFO3_BURST_INCR16 (0x7u << 16) /**< \brief (MPDDRC_MINFO3) 16-beat incrementing burst */
+#define MPDDRC_MINFO3_SIZE_Pos 20
+#define MPDDRC_MINFO3_SIZE_Msk (0x7u << MPDDRC_MINFO3_SIZE_Pos) /**< \brief (MPDDRC_MINFO3) Transfer Size on Port x [x =0..7] */
+#define   MPDDRC_MINFO3_SIZE_8BITS (0x0u << 20) /**< \brief (MPDDRC_MINFO3) Byte transfer */
+#define   MPDDRC_MINFO3_SIZE_16BITS (0x1u << 20) /**< \brief (MPDDRC_MINFO3) Halfword transfer */
+#define   MPDDRC_MINFO3_SIZE_32BITS (0x2u << 20) /**< \brief (MPDDRC_MINFO3) Word transfer */
+#define   MPDDRC_MINFO3_SIZE_64BITS (0x3u << 20) /**< \brief (MPDDRC_MINFO3) Dword transfer */
+#define MPDDRC_MINFO3_READ_WRITE (0x1u << 24) /**< \brief (MPDDRC_MINFO3) Read or Write Access on Port x [x =0..7] */
+#define MPDDRC_MINFO3_P3_NB_TRANSFERS_Pos 0
+#define MPDDRC_MINFO3_P3_NB_TRANSFERS_Msk (0xffffffffu << MPDDRC_MINFO3_P3_NB_TRANSFERS_Pos) /**< \brief (MPDDRC_MINFO3) Number of Transfers on Port x [x =0..7] */
+#define MPDDRC_MINFO3_P3_TOTAL_LATENCY_Pos 0
+#define MPDDRC_MINFO3_P3_TOTAL_LATENCY_Msk (0xffffffffu << MPDDRC_MINFO3_P3_TOTAL_LATENCY_Pos) /**< \brief (MPDDRC_MINFO3) Total Latency on Port x [x =0..7] */
+/* -------- MPDDRC_MINFO4 : (MPDDRC Offset: 0x94) MPDDRC Monitor Information port 4 -------- */
+#define MPDDRC_MINFO4_MAX_PORT4_WAITING_Pos 0
+#define MPDDRC_MINFO4_MAX_PORT4_WAITING_Msk (0xffffu << MPDDRC_MINFO4_MAX_PORT4_WAITING_Pos) /**< \brief (MPDDRC_MINFO4) Address High on Port x [x =0..7] */
+#define MPDDRC_MINFO4_BURST_Pos 16
+#define MPDDRC_MINFO4_BURST_Msk (0x7u << MPDDRC_MINFO4_BURST_Pos) /**< \brief (MPDDRC_MINFO4) Type of Burst on Port x [x =0..7] */
+#define   MPDDRC_MINFO4_BURST_SINGLE (0x0u << 16) /**< \brief (MPDDRC_MINFO4) Single transfer */
+#define   MPDDRC_MINFO4_BURST_INCR (0x1u << 16) /**< \brief (MPDDRC_MINFO4) Incrementing burst of unspecified length */
+#define   MPDDRC_MINFO4_BURST_WRAP4 (0x2u << 16) /**< \brief (MPDDRC_MINFO4) 4-beat wrapping burst */
+#define   MPDDRC_MINFO4_BURST_INCR4 (0x3u << 16) /**< \brief (MPDDRC_MINFO4) 4-beat incrementing burst */
+#define   MPDDRC_MINFO4_BURST_WRAP8 (0x4u << 16) /**< \brief (MPDDRC_MINFO4) 8-beat wrapping burst */
+#define   MPDDRC_MINFO4_BURST_INCR8 (0x5u << 16) /**< \brief (MPDDRC_MINFO4) 8-beat incrementing burst */
+#define   MPDDRC_MINFO4_BURST_WRAP16 (0x6u << 16) /**< \brief (MPDDRC_MINFO4) 16-beat wrapping burst */
+#define   MPDDRC_MINFO4_BURST_INCR16 (0x7u << 16) /**< \brief (MPDDRC_MINFO4) 16-beat incrementing burst */
+#define MPDDRC_MINFO4_SIZE_Pos 20
+#define MPDDRC_MINFO4_SIZE_Msk (0x7u << MPDDRC_MINFO4_SIZE_Pos) /**< \brief (MPDDRC_MINFO4) Transfer Size on Port x [x =0..7] */
+#define   MPDDRC_MINFO4_SIZE_8BITS (0x0u << 20) /**< \brief (MPDDRC_MINFO4) Byte transfer */
+#define   MPDDRC_MINFO4_SIZE_16BITS (0x1u << 20) /**< \brief (MPDDRC_MINFO4) Halfword transfer */
+#define   MPDDRC_MINFO4_SIZE_32BITS (0x2u << 20) /**< \brief (MPDDRC_MINFO4) Word transfer */
+#define   MPDDRC_MINFO4_SIZE_64BITS (0x3u << 20) /**< \brief (MPDDRC_MINFO4) Dword transfer */
+#define MPDDRC_MINFO4_READ_WRITE (0x1u << 24) /**< \brief (MPDDRC_MINFO4) Read or Write Access on Port x [x =0..7] */
+#define MPDDRC_MINFO4_P4_NB_TRANSFERS_Pos 0
+#define MPDDRC_MINFO4_P4_NB_TRANSFERS_Msk (0xffffffffu << MPDDRC_MINFO4_P4_NB_TRANSFERS_Pos) /**< \brief (MPDDRC_MINFO4) Number of Transfers on Port x [x =0..7] */
+#define MPDDRC_MINFO4_P4_TOTAL_LATENCY_Pos 0
+#define MPDDRC_MINFO4_P4_TOTAL_LATENCY_Msk (0xffffffffu << MPDDRC_MINFO4_P4_TOTAL_LATENCY_Pos) /**< \brief (MPDDRC_MINFO4) Total Latency on Port x [x =0..7] */
+/* -------- MPDDRC_MINFO5 : (MPDDRC Offset: 0x98) MPDDRC Monitor Information port 5 -------- */
+#define MPDDRC_MINFO5_MAX_PORT5_WAITING_Pos 0
+#define MPDDRC_MINFO5_MAX_PORT5_WAITING_Msk (0xffffu << MPDDRC_MINFO5_MAX_PORT5_WAITING_Pos) /**< \brief (MPDDRC_MINFO5) Address High on Port x [x =0..7] */
+#define MPDDRC_MINFO5_BURST_Pos 16
+#define MPDDRC_MINFO5_BURST_Msk (0x7u << MPDDRC_MINFO5_BURST_Pos) /**< \brief (MPDDRC_MINFO5) Type of Burst on Port x [x =0..7] */
+#define   MPDDRC_MINFO5_BURST_SINGLE (0x0u << 16) /**< \brief (MPDDRC_MINFO5) Single transfer */
+#define   MPDDRC_MINFO5_BURST_INCR (0x1u << 16) /**< \brief (MPDDRC_MINFO5) Incrementing burst of unspecified length */
+#define   MPDDRC_MINFO5_BURST_WRAP4 (0x2u << 16) /**< \brief (MPDDRC_MINFO5) 4-beat wrapping burst */
+#define   MPDDRC_MINFO5_BURST_INCR4 (0x3u << 16) /**< \brief (MPDDRC_MINFO5) 4-beat incrementing burst */
+#define   MPDDRC_MINFO5_BURST_WRAP8 (0x4u << 16) /**< \brief (MPDDRC_MINFO5) 8-beat wrapping burst */
+#define   MPDDRC_MINFO5_BURST_INCR8 (0x5u << 16) /**< \brief (MPDDRC_MINFO5) 8-beat incrementing burst */
+#define   MPDDRC_MINFO5_BURST_WRAP16 (0x6u << 16) /**< \brief (MPDDRC_MINFO5) 16-beat wrapping burst */
+#define   MPDDRC_MINFO5_BURST_INCR16 (0x7u << 16) /**< \brief (MPDDRC_MINFO5) 16-beat incrementing burst */
+#define MPDDRC_MINFO5_SIZE_Pos 20
+#define MPDDRC_MINFO5_SIZE_Msk (0x7u << MPDDRC_MINFO5_SIZE_Pos) /**< \brief (MPDDRC_MINFO5) Transfer Size on Port x [x =0..7] */
+#define   MPDDRC_MINFO5_SIZE_8BITS (0x0u << 20) /**< \brief (MPDDRC_MINFO5) Byte transfer */
+#define   MPDDRC_MINFO5_SIZE_16BITS (0x1u << 20) /**< \brief (MPDDRC_MINFO5) Halfword transfer */
+#define   MPDDRC_MINFO5_SIZE_32BITS (0x2u << 20) /**< \brief (MPDDRC_MINFO5) Word transfer */
+#define   MPDDRC_MINFO5_SIZE_64BITS (0x3u << 20) /**< \brief (MPDDRC_MINFO5) Dword transfer */
+#define MPDDRC_MINFO5_READ_WRITE (0x1u << 24) /**< \brief (MPDDRC_MINFO5) Read or Write Access on Port x [x =0..7] */
+#define MPDDRC_MINFO5_P5_NB_TRANSFERS_Pos 0
+#define MPDDRC_MINFO5_P5_NB_TRANSFERS_Msk (0xffffffffu << MPDDRC_MINFO5_P5_NB_TRANSFERS_Pos) /**< \brief (MPDDRC_MINFO5) Number of Transfers on Port x [x =0..7] */
+#define MPDDRC_MINFO5_P5_TOTAL_LATENCY_Pos 0
+#define MPDDRC_MINFO5_P5_TOTAL_LATENCY_Msk (0xffffffffu << MPDDRC_MINFO5_P5_TOTAL_LATENCY_Pos) /**< \brief (MPDDRC_MINFO5) Total Latency on Port x [x =0..7] */
+/* -------- MPDDRC_MINFO6 : (MPDDRC Offset: 0x9C) MPDDRC Monitor Information port 6 -------- */
+#define MPDDRC_MINFO6_MAX_PORT6_WAITING_Pos 0
+#define MPDDRC_MINFO6_MAX_PORT6_WAITING_Msk (0xffffu << MPDDRC_MINFO6_MAX_PORT6_WAITING_Pos) /**< \brief (MPDDRC_MINFO6) Address High on Port x [x =0..7] */
+#define MPDDRC_MINFO6_BURST_Pos 16
+#define MPDDRC_MINFO6_BURST_Msk (0x7u << MPDDRC_MINFO6_BURST_Pos) /**< \brief (MPDDRC_MINFO6) Type of Burst on Port x [x =0..7] */
+#define   MPDDRC_MINFO6_BURST_SINGLE (0x0u << 16) /**< \brief (MPDDRC_MINFO6) Single transfer */
+#define   MPDDRC_MINFO6_BURST_INCR (0x1u << 16) /**< \brief (MPDDRC_MINFO6) Incrementing burst of unspecified length */
+#define   MPDDRC_MINFO6_BURST_WRAP4 (0x2u << 16) /**< \brief (MPDDRC_MINFO6) 4-beat wrapping burst */
+#define   MPDDRC_MINFO6_BURST_INCR4 (0x3u << 16) /**< \brief (MPDDRC_MINFO6) 4-beat incrementing burst */
+#define   MPDDRC_MINFO6_BURST_WRAP8 (0x4u << 16) /**< \brief (MPDDRC_MINFO6) 8-beat wrapping burst */
+#define   MPDDRC_MINFO6_BURST_INCR8 (0x5u << 16) /**< \brief (MPDDRC_MINFO6) 8-beat incrementing burst */
+#define   MPDDRC_MINFO6_BURST_WRAP16 (0x6u << 16) /**< \brief (MPDDRC_MINFO6) 16-beat wrapping burst */
+#define   MPDDRC_MINFO6_BURST_INCR16 (0x7u << 16) /**< \brief (MPDDRC_MINFO6) 16-beat incrementing burst */
+#define MPDDRC_MINFO6_SIZE_Pos 20
+#define MPDDRC_MINFO6_SIZE_Msk (0x7u << MPDDRC_MINFO6_SIZE_Pos) /**< \brief (MPDDRC_MINFO6) Transfer Size on Port x [x =0..7] */
+#define   MPDDRC_MINFO6_SIZE_8BITS (0x0u << 20) /**< \brief (MPDDRC_MINFO6) Byte transfer */
+#define   MPDDRC_MINFO6_SIZE_16BITS (0x1u << 20) /**< \brief (MPDDRC_MINFO6) Halfword transfer */
+#define   MPDDRC_MINFO6_SIZE_32BITS (0x2u << 20) /**< \brief (MPDDRC_MINFO6) Word transfer */
+#define   MPDDRC_MINFO6_SIZE_64BITS (0x3u << 20) /**< \brief (MPDDRC_MINFO6) Dword transfer */
+#define MPDDRC_MINFO6_READ_WRITE (0x1u << 24) /**< \brief (MPDDRC_MINFO6) Read or Write Access on Port x [x =0..7] */
+#define MPDDRC_MINFO6_P6_NB_TRANSFERS_Pos 0
+#define MPDDRC_MINFO6_P6_NB_TRANSFERS_Msk (0xffffffffu << MPDDRC_MINFO6_P6_NB_TRANSFERS_Pos) /**< \brief (MPDDRC_MINFO6) Number of Transfers on Port x [x =0..7] */
+#define MPDDRC_MINFO6_P6_TOTAL_LATENCY_Pos 0
+#define MPDDRC_MINFO6_P6_TOTAL_LATENCY_Msk (0xffffffffu << MPDDRC_MINFO6_P6_TOTAL_LATENCY_Pos) /**< \brief (MPDDRC_MINFO6) Total Latency on Port x [x =0..7] */
+/* -------- MPDDRC_MINFO7 : (MPDDRC Offset: 0xA0) MPDDRC Monitor Information port 7 -------- */
+#define MPDDRC_MINFO7_MAX_PORT7_WAITING_Pos 0
+#define MPDDRC_MINFO7_MAX_PORT7_WAITING_Msk (0xffffu << MPDDRC_MINFO7_MAX_PORT7_WAITING_Pos) /**< \brief (MPDDRC_MINFO7) Address High on Port x [x =0..7] */
+#define MPDDRC_MINFO7_BURST_Pos 16
+#define MPDDRC_MINFO7_BURST_Msk (0x7u << MPDDRC_MINFO7_BURST_Pos) /**< \brief (MPDDRC_MINFO7) Type of Burst on Port x [x =0..7] */
+#define   MPDDRC_MINFO7_BURST_SINGLE (0x0u << 16) /**< \brief (MPDDRC_MINFO7) Single transfer */
+#define   MPDDRC_MINFO7_BURST_INCR (0x1u << 16) /**< \brief (MPDDRC_MINFO7) Incrementing burst of unspecified length */
+#define   MPDDRC_MINFO7_BURST_WRAP4 (0x2u << 16) /**< \brief (MPDDRC_MINFO7) 4-beat wrapping burst */
+#define   MPDDRC_MINFO7_BURST_INCR4 (0x3u << 16) /**< \brief (MPDDRC_MINFO7) 4-beat incrementing burst */
+#define   MPDDRC_MINFO7_BURST_WRAP8 (0x4u << 16) /**< \brief (MPDDRC_MINFO7) 8-beat wrapping burst */
+#define   MPDDRC_MINFO7_BURST_INCR8 (0x5u << 16) /**< \brief (MPDDRC_MINFO7) 8-beat incrementing burst */
+#define   MPDDRC_MINFO7_BURST_WRAP16 (0x6u << 16) /**< \brief (MPDDRC_MINFO7) 16-beat wrapping burst */
+#define   MPDDRC_MINFO7_BURST_INCR16 (0x7u << 16) /**< \brief (MPDDRC_MINFO7) 16-beat incrementing burst */
+#define MPDDRC_MINFO7_SIZE_Pos 20
+#define MPDDRC_MINFO7_SIZE_Msk (0x7u << MPDDRC_MINFO7_SIZE_Pos) /**< \brief (MPDDRC_MINFO7) Transfer Size on Port x [x =0..7] */
+#define   MPDDRC_MINFO7_SIZE_8BITS (0x0u << 20) /**< \brief (MPDDRC_MINFO7) Byte transfer */
+#define   MPDDRC_MINFO7_SIZE_16BITS (0x1u << 20) /**< \brief (MPDDRC_MINFO7) Halfword transfer */
+#define   MPDDRC_MINFO7_SIZE_32BITS (0x2u << 20) /**< \brief (MPDDRC_MINFO7) Word transfer */
+#define   MPDDRC_MINFO7_SIZE_64BITS (0x3u << 20) /**< \brief (MPDDRC_MINFO7) Dword transfer */
+#define MPDDRC_MINFO7_READ_WRITE (0x1u << 24) /**< \brief (MPDDRC_MINFO7) Read or Write Access on Port x [x =0..7] */
+#define MPDDRC_MINFO7_P7_NB_TRANSFERS_Pos 0
+#define MPDDRC_MINFO7_P7_NB_TRANSFERS_Msk (0xffffffffu << MPDDRC_MINFO7_P7_NB_TRANSFERS_Pos) /**< \brief (MPDDRC_MINFO7) Number of Transfers on Port x [x =0..7] */
+#define MPDDRC_MINFO7_P7_TOTAL_LATENCY_Pos 0
+#define MPDDRC_MINFO7_P7_TOTAL_LATENCY_Msk (0xffffffffu << MPDDRC_MINFO7_P7_TOTAL_LATENCY_Pos) /**< \brief (MPDDRC_MINFO7) Total Latency on Port x [x =0..7] */
+/* -------- MPDDRC_WPMR : (MPDDRC Offset: 0xE4) MPDDRC Write Protection Mode Register -------- */
+#define MPDDRC_WPMR_WPEN (0x1u << 0) /**< \brief (MPDDRC_WPMR) Write Protection Enable */
+#define MPDDRC_WPMR_WPKEY_Pos 8
+#define MPDDRC_WPMR_WPKEY_Msk (0xffffffu << MPDDRC_WPMR_WPKEY_Pos) /**< \brief (MPDDRC_WPMR) Write Protection Key */
+#define MPDDRC_WPMR_WPKEY(value) ((MPDDRC_WPMR_WPKEY_Msk & ((value) << MPDDRC_WPMR_WPKEY_Pos)))
+#define   MPDDRC_WPMR_WPKEY_PASSWD (0x444452u << 8) /**< \brief (MPDDRC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
+/* -------- MPDDRC_WPSR : (MPDDRC Offset: 0xE8) MPDDRC Write Protection Status Register -------- */
+#define MPDDRC_WPSR_WPVS (0x1u << 0) /**< \brief (MPDDRC_WPSR) Write Protection Violation Status */
+#define MPDDRC_WPSR_WPVSRC_Pos 8
+#define MPDDRC_WPSR_WPVSRC_Msk (0xffffu << MPDDRC_WPSR_WPVSRC_Pos) /**< \brief (MPDDRC_WPSR) Write Protection Violation Source */
+
+/*@}*/
+
+#endif /* _SAMA5D2_MPDDRC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_pdmic.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_pdmic.h
new file mode 100644
index 000000000..e1202c88c
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_pdmic.h
@@ -0,0 +1,128 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_PDMIC_COMPONENT_
+#define _SAMA5D2_PDMIC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Pulse Density Modulation Interface Controller */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_PDMIC Pulse Density Modulation Interface Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pdmic hardware registers */
+typedef struct {
+  __IO uint32_t PDMIC_CR;      /**< \brief (Pdmic Offset: 0x00) Control Register */
+  __IO uint32_t PDMIC_MR;      /**< \brief (Pdmic Offset: 0x04) Mode Register */
+  __I  uint32_t Reserved1[3];
+  __I  uint32_t PDMIC_CDR;     /**< \brief (Pdmic Offset: 0x14) Converted Data Register */
+  __O  uint32_t PDMIC_IER;     /**< \brief (Pdmic Offset: 0x18) Interrupt Enable Register */
+  __O  uint32_t PDMIC_IDR;     /**< \brief (Pdmic Offset: 0x1C) Interrupt Disable Register */
+  __I  uint32_t PDMIC_IMR;     /**< \brief (Pdmic Offset: 0x20) Interrupt Mask Register */
+  __I  uint32_t PDMIC_ISR;     /**< \brief (Pdmic Offset: 0x24) Interrupt Status Register */
+  __I  uint32_t Reserved2[12];
+  __IO uint32_t PDMIC_DSPR0;   /**< \brief (Pdmic Offset: 0x58) DSP Configuration Register 0 */
+  __IO uint32_t PDMIC_DSPR1;   /**< \brief (Pdmic Offset: 0x5C) DSP Configuration Register 1 */
+  __I  uint32_t Reserved3[33];
+  __IO uint32_t PDMIC_WPMR;    /**< \brief (Pdmic Offset: 0xE4) Write Protection Mode Register */
+  __I  uint32_t PDMIC_WPSR;    /**< \brief (Pdmic Offset: 0xE8) Write Protection Status Register */
+  __I  uint32_t Reserved4[4];
+  __I  uint32_t PDMIC_VERSION; /**< \brief (Pdmic Offset: 0xFC) Version Register */
+} Pdmic;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PDMIC_CR : (PDMIC Offset: 0x00) Control Register -------- */
+#define PDMIC_CR_SWRST (0x1u << 0) /**< \brief (PDMIC_CR) Software Reset */
+#define PDMIC_CR_ENPDM (0x1u << 4) /**< \brief (PDMIC_CR) Enable PDM */
+/* -------- PDMIC_MR : (PDMIC Offset: 0x04) Mode Register -------- */
+#define PDMIC_MR_CLKS_PCLK (0x0u << 4) /**< \brief (PDMIC_MR) Clock Source Selection PCLK */
+#define PDMIC_MR_CLKS_GCLK (0x1u << 4) /**< \brief (PDMIC_MR) Clock Source Selection GCLK */
+#define PDMIC_MR_PRESCAL_Pos 8
+#define PDMIC_MR_PRESCAL_Msk (0x7fu << PDMIC_MR_PRESCAL_Pos) /**< \brief (PDMIC_MR) Prescaler Rate Selection */
+#define PDMIC_MR_PRESCAL(value) ((PDMIC_MR_PRESCAL_Msk & ((value) << PDMIC_MR_PRESCAL_Pos)))
+/* -------- PDMIC_CDR : (PDMIC Offset: 0x14) Converted Data Register -------- */
+#define PDMIC_CDR_DATA_Pos 0
+#define PDMIC_CDR_DATA_Msk (0xffffffffu << PDMIC_CDR_DATA_Pos) /**< \brief (PDMIC_CDR) Data Converted */
+/* -------- PDMIC_IER : (PDMIC Offset: 0x18) Interrupt Enable Register -------- */
+#define PDMIC_IER_DRDY (0x1u << 24) /**< \brief (PDMIC_IER) Data Ready Interrupt Enable */
+#define PDMIC_IER_OVRE (0x1u << 25) /**< \brief (PDMIC_IER) Overrun Error Interrupt Enable */
+/* -------- PDMIC_IDR : (PDMIC Offset: 0x1C) Interrupt Disable Register -------- */
+#define PDMIC_IDR_DRDY (0x1u << 24) /**< \brief (PDMIC_IDR) Data Ready Interrupt Disable */
+#define PDMIC_IDR_OVRE (0x1u << 25) /**< \brief (PDMIC_IDR) General Overrun Error Interrupt Disable */
+/* -------- PDMIC_IMR : (PDMIC Offset: 0x20) Interrupt Mask Register -------- */
+#define PDMIC_IMR_DRDY (0x1u << 24) /**< \brief (PDMIC_IMR) Data Ready Interrupt Mask */
+#define PDMIC_IMR_OVRE (0x1u << 25) /**< \brief (PDMIC_IMR) General Overrun Error Interrupt Mask */
+/* -------- PDMIC_ISR : (PDMIC Offset: 0x24) Interrupt Status Register -------- */
+#define PDMIC_ISR_FIFOCNT_Pos 16
+#define PDMIC_ISR_FIFOCNT_Msk (0xffu << PDMIC_ISR_FIFOCNT_Pos) /**< \brief (PDMIC_ISR) FIFO Count */
+#define PDMIC_ISR_DRDY (0x1u << 24) /**< \brief (PDMIC_ISR) Data Ready (cleared by reading PDMIC_CDR) */
+#define PDMIC_ISR_OVRE (0x1u << 25) /**< \brief (PDMIC_ISR) Overrun Error (cleared on read) */
+/* -------- PDMIC_DSPR0 : (PDMIC Offset: 0x58) DSP Configuration Register 0 -------- */
+#define PDMIC_DSPR0_HPFBYP (0x1u << 1) /**< \brief (PDMIC_DSPR0) High-Pass Filter Bypass */
+#define PDMIC_DSPR0_SINBYP (0x1u << 2) /**< \brief (PDMIC_DSPR0) SINCC Filter Bypass */
+#define PDMIC_DSPR0_SIZE_16 (0x0u << 3) /**< \brief (PDMIC_DSPR0) Data Size 16bit */
+#define PDMIC_DSPR0_SIZE_32 (0x1u << 3) /**< \brief (PDMIC_DSPR0) Data Size 32bit */
+#define PDMIC_DSPR0_OSR_Pos 4
+#define PDMIC_DSPR0_OSR_Msk (0x7u << PDMIC_DSPR0_OSR_Pos) /**< \brief (PDMIC_DSPR0) Oversampling Ratio */
+#define PDMIC_DSPR0_OSR(value) ((PDMIC_DSPR0_OSR_Msk & ((value) << PDMIC_DSPR0_OSR_Pos)))
+#define   PDMIC_DSPR0_OSR_128 (0x0u << 4) /**< \brief (PDMIC_DSPR0) Oversampling ratio is 128 */
+#define   PDMIC_DSPR0_OSR_64 (0x1u << 4) /**< \brief (PDMIC_DSPR0) Oversampling ratio is 64 */
+#define PDMIC_DSPR0_SCALE_Pos 8
+#define PDMIC_DSPR0_SCALE_Msk (0xfu << PDMIC_DSPR0_SCALE_Pos) /**< \brief (PDMIC_DSPR0) Data Scale */
+#define PDMIC_DSPR0_SCALE(value) ((PDMIC_DSPR0_SCALE_Msk & ((value) << PDMIC_DSPR0_SCALE_Pos)))
+#define PDMIC_DSPR0_SHIFT_Pos 12
+#define PDMIC_DSPR0_SHIFT_Msk (0xfu << PDMIC_DSPR0_SHIFT_Pos) /**< \brief (PDMIC_DSPR0) Data Shift */
+#define PDMIC_DSPR0_SHIFT(value) ((PDMIC_DSPR0_SHIFT_Msk & ((value) << PDMIC_DSPR0_SHIFT_Pos)))
+/* -------- PDMIC_DSPR1 : (PDMIC Offset: 0x5C) DSP Configuration Register 1 -------- */
+#define PDMIC_DSPR1_DGAIN_Pos 0
+#define PDMIC_DSPR1_DGAIN_Msk (0x7fffu << PDMIC_DSPR1_DGAIN_Pos) /**< \brief (PDMIC_DSPR1) Gain Correction */
+#define PDMIC_DSPR1_DGAIN(value) ((PDMIC_DSPR1_DGAIN_Msk & ((value) << PDMIC_DSPR1_DGAIN_Pos)))
+#define PDMIC_DSPR1_OFFSET_Pos 16
+#define PDMIC_DSPR1_OFFSET_Msk (0xffffu << PDMIC_DSPR1_OFFSET_Pos) /**< \brief (PDMIC_DSPR1) Offset Correction */
+#define PDMIC_DSPR1_OFFSET(value) ((PDMIC_DSPR1_OFFSET_Msk & ((value) << PDMIC_DSPR1_OFFSET_Pos)))
+/* -------- PDMIC_WPMR : (PDMIC Offset: 0xE4) Write Protection Mode Register -------- */
+#define PDMIC_WPMR_WPEN (0x1u << 0) /**< \brief (PDMIC_WPMR) Write Protection Enable */
+#define PDMIC_WPMR_WPKEY_Pos 8
+#define PDMIC_WPMR_WPKEY_Msk (0xffffffu << PDMIC_WPMR_WPKEY_Pos) /**< \brief (PDMIC_WPMR) Write Protection Key */
+#define PDMIC_WPMR_WPKEY(value) ((PDMIC_WPMR_WPKEY_Msk & ((value) << PDMIC_WPMR_WPKEY_Pos)))
+#define   PDMIC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (PDMIC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
+/* -------- PDMIC_WPSR : (PDMIC Offset: 0xE8) Write Protection Status Register -------- */
+#define PDMIC_WPSR_WPVS (0x1u << 0) /**< \brief (PDMIC_WPSR) Write Protection Violation Status */
+#define PDMIC_WPSR_WPVSRC_Pos 8
+#define PDMIC_WPSR_WPVSRC_Msk (0xffffu << PDMIC_WPSR_WPVSRC_Pos) /**< \brief (PDMIC_WPSR) Write Protection Violation Source */
+/* -------- PDMIC_VERSION : (PDMIC Offset: 0xFC) Version Register -------- */
+#define PDMIC_VERSION_VERSION_Pos 0
+#define PDMIC_VERSION_VERSION_Msk (0xfffu << PDMIC_VERSION_VERSION_Pos) /**< \brief (PDMIC_VERSION) Version of the Hardware Module */
+#define PDMIC_VERSION_MFN_Pos 16
+#define PDMIC_VERSION_MFN_Msk (0x7u << PDMIC_VERSION_MFN_Pos) /**< \brief (PDMIC_VERSION) Metal Fix Number */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_PDMIC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_pio.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_pio.h
new file mode 100644
index 000000000..9f8ef6536
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_pio.h
@@ -0,0 +1,1161 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_PIO_COMPONENT_
+#define _SAMA5D2_PIO_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_PIO Parallel Input/Output Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief PioIo_group hardware registers */
+typedef struct {
+  __IO uint32_t PIO_MSKR;     /**< \brief (PioIo_group Offset: 0x0) PIO Mask Register */
+  __IO uint32_t PIO_CFGR;     /**< \brief (PioIo_group Offset: 0x4) PIO Configuration Register */
+  __I  uint32_t PIO_PDSR;     /**< \brief (PioIo_group Offset: 0x8) PIO Pin Data Status Register */
+  __I  uint32_t PIO_LOCKSR;   /**< \brief (PioIo_group Offset: 0xC) PIO Lock Status Register */
+  __O  uint32_t PIO_SODR;     /**< \brief (PioIo_group Offset: 0x10) PIO Set Output Data Register */
+  __O  uint32_t PIO_CODR;     /**< \brief (PioIo_group Offset: 0x14) PIO Clear Output Data Register */
+  __IO uint32_t PIO_ODSR;     /**< \brief (PioIo_group Offset: 0x18) PIO Output Data Status Register */
+  __I  uint32_t Reserved1[1];
+  __O  uint32_t PIO_IER;      /**< \brief (PioIo_group Offset: 0x20) PIO Interrupt Enable Register */
+  __O  uint32_t PIO_IDR;      /**< \brief (PioIo_group Offset: 0x24) PIO Interrupt Disable Register */
+  __I  uint32_t PIO_IMR;      /**< \brief (PioIo_group Offset: 0x28) PIO Interrupt Mask Register */
+  __I  uint32_t PIO_ISR;      /**< \brief (PioIo_group Offset: 0x2C) PIO Interrupt Status Register */
+  __I  uint32_t Reserved2[3];
+  __O  uint32_t PIO_IOFR;     /**< \brief (PioIo_group Offset: 0x3C) PIO I/O Freeze Register */
+} PioIo_group;
+/** \brief PioPio_ hardware registers */
+typedef struct {
+  __IO uint32_t S_PIO_MSKR;   /**< \brief (PioPio_ Offset: 0x0) Secure PIO Mask Register */
+  __IO uint32_t S_PIO_CFGR;   /**< \brief (PioPio_ Offset: 0x4) Secure PIO Configuration Register */
+  __I  uint32_t S_PIO_PDSR;   /**< \brief (PioPio_ Offset: 0x8) Secure PIO Pin Data Status Register */
+  __I  uint32_t S_PIO_LOCKSR; /**< \brief (PioPio_ Offset: 0xC) Secure PIO Lock Status Register */
+  __O  uint32_t S_PIO_SODR;   /**< \brief (PioPio_ Offset: 0x10) Secure PIO Set Output Data Register */
+  __O  uint32_t S_PIO_CODR;   /**< \brief (PioPio_ Offset: 0x14) Secure PIO Clear Output Data Register */
+  __IO uint32_t S_PIO_ODSR;   /**< \brief (PioPio_ Offset: 0x18) Secure PIO Output Data Status Register */
+  __I  uint32_t Reserved3[1];
+  __O  uint32_t S_PIO_IER;    /**< \brief (PioPio_ Offset: 0x20) Secure PIO Interrupt Enable Register */
+  __O  uint32_t S_PIO_IDR;    /**< \brief (PioPio_ Offset: 0x24) Secure PIO Interrupt Disable Register */
+  __I  uint32_t S_PIO_IMR;    /**< \brief (PioPio_ Offset: 0x28) Secure PIO Interrupt Mask Register */
+  __I  uint32_t S_PIO_ISR;    /**< \brief (PioPio_ Offset: 0x2C) Secure PIO Interrupt Status Register */
+  __O  uint32_t S_PIO_SIONR;  /**< \brief (PioPio_ Offset: 0x30) Secure PIO Set I/O Non-Secure Register */
+  __O  uint32_t S_PIO_SIOSR;  /**< \brief (PioPio_ Offset: 0x34) Secure PIO Set I/O Secure Register */
+  __I  uint32_t S_PIO_IOSSR;  /**< \brief (PioPio_ Offset: 0x38) Secure PIO I/O Security Status Register */
+  __O  uint32_t S_PIO_IOFR;   /**< \brief (PioPio_ Offset: 0x3C) Secure PIO I/O Freeze Register */
+} PioPio_;
+/** \brief Pio hardware registers */
+#define PIOIO_GROUP_NUMBER 4
+#define PIOPIO__NUMBER 4
+typedef struct {
+       PioIo_group PIO_IO_GROUP[PIOIO_GROUP_NUMBER]; /**< \brief (Pio Offset: 0x0) io_group = 0 .. 3 */
+  __I  uint32_t    Reserved1[312];
+  __IO uint32_t    PIO_WPMR;                         /**< \brief (Pio Offset: 0x5E0) PIO Write Protection Mode Register */
+  __I  uint32_t    PIO_WPSR;                         /**< \brief (Pio Offset: 0x5E4) PIO Write Protection Status Register */
+  __I  uint32_t    Reserved2[5];
+  __I  uint32_t    PIO_VERSION;                      /**< \brief (Pio Offset: 0x5FC) Version Register */
+  __I  uint32_t    Reserved3[640];
+       PioPio_     PIO_PIO_[PIOPIO__NUMBER];         /**< \brief (Pio Offset: 0x1000) io_group = 0 .. 3 */
+  __I  uint32_t    Reserved4[256];
+  __IO uint32_t    S_PIO_SCDR;                       /**< \brief (Pio Offset: 0x1500) Secure PIO Slow Clock Divider Debouncing Register */
+  __I  uint32_t    Reserved5[55];
+  __IO uint32_t    S_PIO_WPMR;                       /**< \brief (Pio Offset: 0x15E0) Secure PIO Write Protection Mode Register */
+  __I  uint32_t    S_PIO_WPSR;                       /**< \brief (Pio Offset: 0x15E4) Secure PIO Write Protection Status Register */
+} Pio;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PIO_MSKR : (PIO Offset: N/A) PIO Mask Register -------- */
+#define PIO_MSKR_MSK0 (0x1u << 0) /**< \brief (PIO_MSKR) PIO Line 0 Mask */
+#define   PIO_MSKR_MSK0_DISABLED (0x0u << 0) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK0_ENABLED (0x1u << 0) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK1 (0x1u << 1) /**< \brief (PIO_MSKR) PIO Line 1 Mask */
+#define   PIO_MSKR_MSK1_DISABLED (0x0u << 1) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK1_ENABLED (0x1u << 1) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK2 (0x1u << 2) /**< \brief (PIO_MSKR) PIO Line 2 Mask */
+#define   PIO_MSKR_MSK2_DISABLED (0x0u << 2) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK2_ENABLED (0x1u << 2) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK3 (0x1u << 3) /**< \brief (PIO_MSKR) PIO Line 3 Mask */
+#define   PIO_MSKR_MSK3_DISABLED (0x0u << 3) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK3_ENABLED (0x1u << 3) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK4 (0x1u << 4) /**< \brief (PIO_MSKR) PIO Line 4 Mask */
+#define   PIO_MSKR_MSK4_DISABLED (0x0u << 4) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK4_ENABLED (0x1u << 4) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK5 (0x1u << 5) /**< \brief (PIO_MSKR) PIO Line 5 Mask */
+#define   PIO_MSKR_MSK5_DISABLED (0x0u << 5) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK5_ENABLED (0x1u << 5) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK6 (0x1u << 6) /**< \brief (PIO_MSKR) PIO Line 6 Mask */
+#define   PIO_MSKR_MSK6_DISABLED (0x0u << 6) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK6_ENABLED (0x1u << 6) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK7 (0x1u << 7) /**< \brief (PIO_MSKR) PIO Line 7 Mask */
+#define   PIO_MSKR_MSK7_DISABLED (0x0u << 7) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK7_ENABLED (0x1u << 7) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK8 (0x1u << 8) /**< \brief (PIO_MSKR) PIO Line 8 Mask */
+#define   PIO_MSKR_MSK8_DISABLED (0x0u << 8) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK8_ENABLED (0x1u << 8) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK9 (0x1u << 9) /**< \brief (PIO_MSKR) PIO Line 9 Mask */
+#define   PIO_MSKR_MSK9_DISABLED (0x0u << 9) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK9_ENABLED (0x1u << 9) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK10 (0x1u << 10) /**< \brief (PIO_MSKR) PIO Line 10 Mask */
+#define   PIO_MSKR_MSK10_DISABLED (0x0u << 10) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK10_ENABLED (0x1u << 10) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK11 (0x1u << 11) /**< \brief (PIO_MSKR) PIO Line 11 Mask */
+#define   PIO_MSKR_MSK11_DISABLED (0x0u << 11) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK11_ENABLED (0x1u << 11) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK12 (0x1u << 12) /**< \brief (PIO_MSKR) PIO Line 12 Mask */
+#define   PIO_MSKR_MSK12_DISABLED (0x0u << 12) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK12_ENABLED (0x1u << 12) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK13 (0x1u << 13) /**< \brief (PIO_MSKR) PIO Line 13 Mask */
+#define   PIO_MSKR_MSK13_DISABLED (0x0u << 13) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK13_ENABLED (0x1u << 13) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK14 (0x1u << 14) /**< \brief (PIO_MSKR) PIO Line 14 Mask */
+#define   PIO_MSKR_MSK14_DISABLED (0x0u << 14) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK14_ENABLED (0x1u << 14) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK15 (0x1u << 15) /**< \brief (PIO_MSKR) PIO Line 15 Mask */
+#define   PIO_MSKR_MSK15_DISABLED (0x0u << 15) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK15_ENABLED (0x1u << 15) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK16 (0x1u << 16) /**< \brief (PIO_MSKR) PIO Line 16 Mask */
+#define   PIO_MSKR_MSK16_DISABLED (0x0u << 16) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK16_ENABLED (0x1u << 16) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK17 (0x1u << 17) /**< \brief (PIO_MSKR) PIO Line 17 Mask */
+#define   PIO_MSKR_MSK17_DISABLED (0x0u << 17) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK17_ENABLED (0x1u << 17) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK18 (0x1u << 18) /**< \brief (PIO_MSKR) PIO Line 18 Mask */
+#define   PIO_MSKR_MSK18_DISABLED (0x0u << 18) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK18_ENABLED (0x1u << 18) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK19 (0x1u << 19) /**< \brief (PIO_MSKR) PIO Line 19 Mask */
+#define   PIO_MSKR_MSK19_DISABLED (0x0u << 19) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK19_ENABLED (0x1u << 19) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK20 (0x1u << 20) /**< \brief (PIO_MSKR) PIO Line 20 Mask */
+#define   PIO_MSKR_MSK20_DISABLED (0x0u << 20) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK20_ENABLED (0x1u << 20) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK21 (0x1u << 21) /**< \brief (PIO_MSKR) PIO Line 21 Mask */
+#define   PIO_MSKR_MSK21_DISABLED (0x0u << 21) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK21_ENABLED (0x1u << 21) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK22 (0x1u << 22) /**< \brief (PIO_MSKR) PIO Line 22 Mask */
+#define   PIO_MSKR_MSK22_DISABLED (0x0u << 22) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK22_ENABLED (0x1u << 22) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK23 (0x1u << 23) /**< \brief (PIO_MSKR) PIO Line 23 Mask */
+#define   PIO_MSKR_MSK23_DISABLED (0x0u << 23) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK23_ENABLED (0x1u << 23) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK24 (0x1u << 24) /**< \brief (PIO_MSKR) PIO Line 24 Mask */
+#define   PIO_MSKR_MSK24_DISABLED (0x0u << 24) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK24_ENABLED (0x1u << 24) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK25 (0x1u << 25) /**< \brief (PIO_MSKR) PIO Line 25 Mask */
+#define   PIO_MSKR_MSK25_DISABLED (0x0u << 25) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK25_ENABLED (0x1u << 25) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK26 (0x1u << 26) /**< \brief (PIO_MSKR) PIO Line 26 Mask */
+#define   PIO_MSKR_MSK26_DISABLED (0x0u << 26) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK26_ENABLED (0x1u << 26) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK27 (0x1u << 27) /**< \brief (PIO_MSKR) PIO Line 27 Mask */
+#define   PIO_MSKR_MSK27_DISABLED (0x0u << 27) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK27_ENABLED (0x1u << 27) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK28 (0x1u << 28) /**< \brief (PIO_MSKR) PIO Line 28 Mask */
+#define   PIO_MSKR_MSK28_DISABLED (0x0u << 28) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK28_ENABLED (0x1u << 28) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK29 (0x1u << 29) /**< \brief (PIO_MSKR) PIO Line 29 Mask */
+#define   PIO_MSKR_MSK29_DISABLED (0x0u << 29) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK29_ENABLED (0x1u << 29) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK30 (0x1u << 30) /**< \brief (PIO_MSKR) PIO Line 30 Mask */
+#define   PIO_MSKR_MSK30_DISABLED (0x0u << 30) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK30_ENABLED (0x1u << 30) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+#define PIO_MSKR_MSK31 (0x1u << 31) /**< \brief (PIO_MSKR) PIO Line 31 Mask */
+#define   PIO_MSKR_MSK31_DISABLED (0x0u << 31) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   PIO_MSKR_MSK31_ENABLED (0x1u << 31) /**< \brief (PIO_MSKR) Writing the PIO_CFGRx, PIO_ODSRx or PIO_IOFRx updates the corresponding I/O line configuration. */
+/* -------- PIO_CFGR : (PIO Offset: N/A) PIO Configuration Register -------- */
+#define PIO_CFGR_FUNC_Pos 0
+#define PIO_CFGR_FUNC_Msk (0x7u << PIO_CFGR_FUNC_Pos) /**< \brief (PIO_CFGR) I/O Line Function */
+#define PIO_CFGR_FUNC(value) ((PIO_CFGR_FUNC_Msk & ((value) << PIO_CFGR_FUNC_Pos)))
+#define   PIO_CFGR_FUNC_GPIO (0x0u << 0) /**< \brief (PIO_CFGR) Select the PIO mode for the selected I/O lines. */
+#define   PIO_CFGR_FUNC_PERIPH_A (0x1u << 0) /**< \brief (PIO_CFGR) Select the peripheral A for the selected I/O lines. */
+#define   PIO_CFGR_FUNC_PERIPH_B (0x2u << 0) /**< \brief (PIO_CFGR) Select the peripheral B for the selected I/O lines. */
+#define   PIO_CFGR_FUNC_PERIPH_C (0x3u << 0) /**< \brief (PIO_CFGR) Select the peripheral C for the selected I/O lines. */
+#define   PIO_CFGR_FUNC_PERIPH_D (0x4u << 0) /**< \brief (PIO_CFGR) Select the peripheral D for the selected I/O lines. */
+#define   PIO_CFGR_FUNC_PERIPH_E (0x5u << 0) /**< \brief (PIO_CFGR) Select the peripheral E for the selected I/O lines. */
+#define   PIO_CFGR_FUNC_PERIPH_F (0x6u << 0) /**< \brief (PIO_CFGR) Select the peripheral F for the selected I/O lines. */
+#define   PIO_CFGR_FUNC_PERIPH_G (0x7u << 0) /**< \brief (PIO_CFGR) Select the peripheral G for the selected I/O lines. */
+#define PIO_CFGR_DIR (0x1u << 8) /**< \brief (PIO_CFGR) Direction */
+#define   PIO_CFGR_DIR_INPUT (0x0u << 8) /**< \brief (PIO_CFGR) The selected I/O lines are pure inputs. */
+#define   PIO_CFGR_DIR_OUTPUT (0x1u << 8) /**< \brief (PIO_CFGR) The selected I/O lines are enabled in output. */
+#define PIO_CFGR_PUEN (0x1u << 9) /**< \brief (PIO_CFGR) Pull-Up Enable */
+#define   PIO_CFGR_PUEN_DISABLED (0x0u << 9) /**< \brief (PIO_CFGR) Pull-Up is disabled for the selected I/O lines. */
+#define   PIO_CFGR_PUEN_ENABLED (0x1u << 9) /**< \brief (PIO_CFGR) Pull-Up is enabled for the selected I/O lines. */
+#define PIO_CFGR_PDEN (0x1u << 10) /**< \brief (PIO_CFGR) Pull-Down Enable */
+#define   PIO_CFGR_PDEN_DISABLED (0x0u << 10) /**< \brief (PIO_CFGR) Pull-Down is disabled for the selected I/O lines. */
+#define   PIO_CFGR_PDEN_ENABLED (0x1u << 10) /**< \brief (PIO_CFGR) Pull-Down is enabled for the selected I/O lines only if PUEN is 0(1). */
+#define PIO_CFGR_IFEN (0x1u << 12) /**< \brief (PIO_CFGR) Input Filter Enable */
+#define   PIO_CFGR_IFEN_DISABLED (0x0u << 12) /**< \brief (PIO_CFGR) The input filter is disabled for the selected I/O lines. */
+#define   PIO_CFGR_IFEN_ENABLED (0x1u << 12) /**< \brief (PIO_CFGR) The input filter is enabled for the selected I/O lines. */
+#define PIO_CFGR_IFSCEN (0x1u << 13) /**< \brief (PIO_CFGR) Input Filter Slow Clock Enable */
+#define   PIO_CFGR_IFSCEN_DISABLED (0x0u << 13) /**< \brief (PIO_CFGR) The glitch filter is able to filter glitches with a duration < tmck/2 for the selected I/O lines. */
+#define   PIO_CFGR_IFSCEN_ENABLED (0x1u << 13) /**< \brief (PIO_CFGR) The debouncing filter is able to filter pulses with a duration < tdiv_slck/2 for the selected I/O lines. */
+#define PIO_CFGR_OPD (0x1u << 14) /**< \brief (PIO_CFGR) Open-Drain */
+#define   PIO_CFGR_OPD_DISABLED (0x0u << 14) /**< \brief (PIO_CFGR) The open-drain is disabled for the selected I/O lines. I/O lines are driven at high- and low-level. */
+#define   PIO_CFGR_OPD_ENABLED (0x1u << 14) /**< \brief (PIO_CFGR) The open-drain is enabled for the selected I/O lines. I/O lines are driven at low-level only. */
+#define PIO_CFGR_SCHMITT (0x1u << 15) /**< \brief (PIO_CFGR) Schmitt Trigger */
+#define   PIO_CFGR_SCHMITT_ENABLED (0x0u << 15) /**< \brief (PIO_CFGR) Schmitt trigger is enabled for the selected I/O lines. */
+#define   PIO_CFGR_SCHMITT_DISABLED (0x1u << 15) /**< \brief (PIO_CFGR) Schmitt trigger is disabled for the selected I/O lines. */
+#define PIO_CFGR_DRVSTR_Pos 16
+#define PIO_CFGR_DRVSTR_Msk (0x3u << PIO_CFGR_DRVSTR_Pos) /**< \brief (PIO_CFGR) Drive Strength */
+#define PIO_CFGR_DRVSTR(value) ((PIO_CFGR_DRVSTR_Msk & ((value) << PIO_CFGR_DRVSTR_Pos)))
+#define   PIO_CFGR_DRVSTR_LO (0x0u << 16) /**< \brief (PIO_CFGR) Low drive */
+#define   PIO_CFGR_DRVSTR_ME (0x2u << 16) /**< \brief (PIO_CFGR) Medium drive */
+#define   PIO_CFGR_DRVSTR_HI (0x3u << 16) /**< \brief (PIO_CFGR) High drive */
+#define PIO_CFGR_EVTSEL_Pos 24
+#define PIO_CFGR_EVTSEL_Msk (0x7u << PIO_CFGR_EVTSEL_Pos) /**< \brief (PIO_CFGR) Event Selection */
+#define PIO_CFGR_EVTSEL(value) ((PIO_CFGR_EVTSEL_Msk & ((value) << PIO_CFGR_EVTSEL_Pos)))
+#define   PIO_CFGR_EVTSEL_FALLING (0x0u << 24) /**< \brief (PIO_CFGR) Event detection on input falling edge */
+#define   PIO_CFGR_EVTSEL_RISING (0x1u << 24) /**< \brief (PIO_CFGR) Event detection on input rising edge */
+#define   PIO_CFGR_EVTSEL_BOTH (0x2u << 24) /**< \brief (PIO_CFGR) Event detection on input both edge */
+#define   PIO_CFGR_EVTSEL_LOW (0x3u << 24) /**< \brief (PIO_CFGR) Event detection on low level input */
+#define   PIO_CFGR_EVTSEL_HIGH (0x4u << 24) /**< \brief (PIO_CFGR) Event detection on high level input */
+#define PIO_CFGR_PCFS (0x1u << 29) /**< \brief (PIO_CFGR) Physical Configuration Freeze Status */
+#define   PIO_CFGR_PCFS_NOT_FROZEN (0x0u << 29) /**< \brief (PIO_CFGR) The fields are not frozen and can be written for this I/O line. */
+#define   PIO_CFGR_PCFS_FROZEN (0x1u << 29) /**< \brief (PIO_CFGR) The fields are frozen and can not be written for this I/O line. Only a hardware reset can release these fields. */
+#define PIO_CFGR_ICFS (0x1u << 30) /**< \brief (PIO_CFGR) Interrupt Configuration Freeze Status */
+#define   PIO_CFGR_ICFS_NOT_FROZEN (0x0u << 30) /**< \brief (PIO_CFGR) The fields are not frozen and can be written for this I/O line. */
+#define   PIO_CFGR_ICFS_FROZEN (0x1u << 30) /**< \brief (PIO_CFGR) The fields are frozen and can not be written for this I/O line. Only a hardware reset can release these fields. */
+/* -------- PIO_PDSR : (PIO Offset: N/A) PIO Pin Data Status Register -------- */
+#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Input Data Status */
+#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Input Data Status */
+/* -------- PIO_LOCKSR : (PIO Offset: N/A) PIO Lock Status Register -------- */
+#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status */
+#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status */
+/* -------- PIO_SODR : (PIO Offset: N/A) PIO Set Output Data Register -------- */
+#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */
+/* -------- PIO_CODR : (PIO Offset: N/A) PIO Clear Output Data Register -------- */
+#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */
+/* -------- PIO_ODSR : (PIO Offset: N/A) PIO Output Data Status Register -------- */
+#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */
+/* -------- PIO_IER : (PIO Offset: N/A) PIO Interrupt Enable Register -------- */
+#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+/* -------- PIO_IDR : (PIO Offset: N/A) PIO Interrupt Disable Register -------- */
+#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+/* -------- PIO_IMR : (PIO Offset: N/A) PIO Interrupt Mask Register -------- */
+#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+/* -------- PIO_ISR : (PIO Offset: N/A) PIO Interrupt Status Register -------- */
+#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+/* -------- PIO_IOFR : (PIO Offset: N/A) PIO I/O Freeze Register -------- */
+#define PIO_IOFR_FPHY (0x1u << 0) /**< \brief (PIO_IOFR) Freeze Physical Configuration */
+#define PIO_IOFR_FINT (0x1u << 1) /**< \brief (PIO_IOFR) Freeze Interrupt Configuration */
+#define PIO_IOFR_FRZKEY_Pos 8
+#define PIO_IOFR_FRZKEY_Msk (0xffffffu << PIO_IOFR_FRZKEY_Pos) /**< \brief (PIO_IOFR) Freeze Key */
+#define PIO_IOFR_FRZKEY(value) ((PIO_IOFR_FRZKEY_Msk & ((value) << PIO_IOFR_FRZKEY_Pos)))
+#define   PIO_IOFR_FRZKEY_PASSWD (0x494F46u << 8) /**< \brief (PIO_IOFR) Writing any other value in this field aborts the write operation of the WPEN bit. */
+/* -------- PIO_WPMR : (PIO Offset: 0x5E0) PIO Write Protection Mode Register -------- */
+#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protection Enable */
+#define PIO_WPMR_WPKEY_Pos 8
+#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protection Key */
+#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))
+#define   PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
+/* -------- PIO_WPSR : (PIO Offset: 0x5E4) PIO Write Protection Status Register -------- */
+#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protection Violation Status */
+#define PIO_WPSR_WPVSRC_Pos 8
+#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protection Violation Source */
+/* -------- PIO_VERSION : (PIO Offset: 0x5FC) Version Register -------- */
+#define PIO_VERSION_VERSION_Pos 0
+#define PIO_VERSION_VERSION_Msk (0xfffu << PIO_VERSION_VERSION_Pos) /**< \brief (PIO_VERSION) Hardware Module Version */
+#define PIO_VERSION_MFN_Pos 16
+#define PIO_VERSION_MFN_Msk (0x7u << PIO_VERSION_MFN_Pos) /**< \brief (PIO_VERSION) Metal Fix Number */
+/* -------- S_PIO_MSKR : (PIO Offset: N/A) Secure PIO Mask Register -------- */
+#define S_PIO_MSKR_MSK0 (0x1u << 0) /**< \brief (S_PIO_MSKR) PIO Line 0 Mask */
+#define   S_PIO_MSKR_MSK0_DISABLED (0x0u << 0) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK0_ENABLED (0x1u << 0) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK1 (0x1u << 1) /**< \brief (S_PIO_MSKR) PIO Line 1 Mask */
+#define   S_PIO_MSKR_MSK1_DISABLED (0x0u << 1) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK1_ENABLED (0x1u << 1) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK2 (0x1u << 2) /**< \brief (S_PIO_MSKR) PIO Line 2 Mask */
+#define   S_PIO_MSKR_MSK2_DISABLED (0x0u << 2) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK2_ENABLED (0x1u << 2) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK3 (0x1u << 3) /**< \brief (S_PIO_MSKR) PIO Line 3 Mask */
+#define   S_PIO_MSKR_MSK3_DISABLED (0x0u << 3) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK3_ENABLED (0x1u << 3) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK4 (0x1u << 4) /**< \brief (S_PIO_MSKR) PIO Line 4 Mask */
+#define   S_PIO_MSKR_MSK4_DISABLED (0x0u << 4) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK4_ENABLED (0x1u << 4) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK5 (0x1u << 5) /**< \brief (S_PIO_MSKR) PIO Line 5 Mask */
+#define   S_PIO_MSKR_MSK5_DISABLED (0x0u << 5) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK5_ENABLED (0x1u << 5) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK6 (0x1u << 6) /**< \brief (S_PIO_MSKR) PIO Line 6 Mask */
+#define   S_PIO_MSKR_MSK6_DISABLED (0x0u << 6) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK6_ENABLED (0x1u << 6) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK7 (0x1u << 7) /**< \brief (S_PIO_MSKR) PIO Line 7 Mask */
+#define   S_PIO_MSKR_MSK7_DISABLED (0x0u << 7) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK7_ENABLED (0x1u << 7) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK8 (0x1u << 8) /**< \brief (S_PIO_MSKR) PIO Line 8 Mask */
+#define   S_PIO_MSKR_MSK8_DISABLED (0x0u << 8) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK8_ENABLED (0x1u << 8) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK9 (0x1u << 9) /**< \brief (S_PIO_MSKR) PIO Line 9 Mask */
+#define   S_PIO_MSKR_MSK9_DISABLED (0x0u << 9) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK9_ENABLED (0x1u << 9) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK10 (0x1u << 10) /**< \brief (S_PIO_MSKR) PIO Line 10 Mask */
+#define   S_PIO_MSKR_MSK10_DISABLED (0x0u << 10) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK10_ENABLED (0x1u << 10) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK11 (0x1u << 11) /**< \brief (S_PIO_MSKR) PIO Line 11 Mask */
+#define   S_PIO_MSKR_MSK11_DISABLED (0x0u << 11) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK11_ENABLED (0x1u << 11) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK12 (0x1u << 12) /**< \brief (S_PIO_MSKR) PIO Line 12 Mask */
+#define   S_PIO_MSKR_MSK12_DISABLED (0x0u << 12) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK12_ENABLED (0x1u << 12) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK13 (0x1u << 13) /**< \brief (S_PIO_MSKR) PIO Line 13 Mask */
+#define   S_PIO_MSKR_MSK13_DISABLED (0x0u << 13) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK13_ENABLED (0x1u << 13) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK14 (0x1u << 14) /**< \brief (S_PIO_MSKR) PIO Line 14 Mask */
+#define   S_PIO_MSKR_MSK14_DISABLED (0x0u << 14) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK14_ENABLED (0x1u << 14) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK15 (0x1u << 15) /**< \brief (S_PIO_MSKR) PIO Line 15 Mask */
+#define   S_PIO_MSKR_MSK15_DISABLED (0x0u << 15) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK15_ENABLED (0x1u << 15) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK16 (0x1u << 16) /**< \brief (S_PIO_MSKR) PIO Line 16 Mask */
+#define   S_PIO_MSKR_MSK16_DISABLED (0x0u << 16) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK16_ENABLED (0x1u << 16) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK17 (0x1u << 17) /**< \brief (S_PIO_MSKR) PIO Line 17 Mask */
+#define   S_PIO_MSKR_MSK17_DISABLED (0x0u << 17) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK17_ENABLED (0x1u << 17) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK18 (0x1u << 18) /**< \brief (S_PIO_MSKR) PIO Line 18 Mask */
+#define   S_PIO_MSKR_MSK18_DISABLED (0x0u << 18) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK18_ENABLED (0x1u << 18) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK19 (0x1u << 19) /**< \brief (S_PIO_MSKR) PIO Line 19 Mask */
+#define   S_PIO_MSKR_MSK19_DISABLED (0x0u << 19) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK19_ENABLED (0x1u << 19) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK20 (0x1u << 20) /**< \brief (S_PIO_MSKR) PIO Line 20 Mask */
+#define   S_PIO_MSKR_MSK20_DISABLED (0x0u << 20) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK20_ENABLED (0x1u << 20) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK21 (0x1u << 21) /**< \brief (S_PIO_MSKR) PIO Line 21 Mask */
+#define   S_PIO_MSKR_MSK21_DISABLED (0x0u << 21) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK21_ENABLED (0x1u << 21) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK22 (0x1u << 22) /**< \brief (S_PIO_MSKR) PIO Line 22 Mask */
+#define   S_PIO_MSKR_MSK22_DISABLED (0x0u << 22) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK22_ENABLED (0x1u << 22) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK23 (0x1u << 23) /**< \brief (S_PIO_MSKR) PIO Line 23 Mask */
+#define   S_PIO_MSKR_MSK23_DISABLED (0x0u << 23) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK23_ENABLED (0x1u << 23) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK24 (0x1u << 24) /**< \brief (S_PIO_MSKR) PIO Line 24 Mask */
+#define   S_PIO_MSKR_MSK24_DISABLED (0x0u << 24) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK24_ENABLED (0x1u << 24) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK25 (0x1u << 25) /**< \brief (S_PIO_MSKR) PIO Line 25 Mask */
+#define   S_PIO_MSKR_MSK25_DISABLED (0x0u << 25) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK25_ENABLED (0x1u << 25) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK26 (0x1u << 26) /**< \brief (S_PIO_MSKR) PIO Line 26 Mask */
+#define   S_PIO_MSKR_MSK26_DISABLED (0x0u << 26) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK26_ENABLED (0x1u << 26) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK27 (0x1u << 27) /**< \brief (S_PIO_MSKR) PIO Line 27 Mask */
+#define   S_PIO_MSKR_MSK27_DISABLED (0x0u << 27) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK27_ENABLED (0x1u << 27) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK28 (0x1u << 28) /**< \brief (S_PIO_MSKR) PIO Line 28 Mask */
+#define   S_PIO_MSKR_MSK28_DISABLED (0x0u << 28) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK28_ENABLED (0x1u << 28) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK29 (0x1u << 29) /**< \brief (S_PIO_MSKR) PIO Line 29 Mask */
+#define   S_PIO_MSKR_MSK29_DISABLED (0x0u << 29) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK29_ENABLED (0x1u << 29) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK30 (0x1u << 30) /**< \brief (S_PIO_MSKR) PIO Line 30 Mask */
+#define   S_PIO_MSKR_MSK30_DISABLED (0x0u << 30) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK30_ENABLED (0x1u << 30) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+#define S_PIO_MSKR_MSK31 (0x1u << 31) /**< \brief (S_PIO_MSKR) PIO Line 31 Mask */
+#define   S_PIO_MSKR_MSK31_DISABLED (0x0u << 31) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRx does not affect the corresponding I/O line configuration. */
+#define   S_PIO_MSKR_MSK31_ENABLED (0x1u << 31) /**< \brief (S_PIO_MSKR) Writing the S_PIO_CFGRx, S_PIO_ODSRx or S_PIO_IOFRX updates the corresponding I/O line configuration. */
+/* -------- S_PIO_CFGR : (PIO Offset: N/A) Secure PIO Configuration Register -------- */
+#define S_PIO_CFGR_FUNC_Pos 0
+#define S_PIO_CFGR_FUNC_Msk (0x7u << S_PIO_CFGR_FUNC_Pos) /**< \brief (S_PIO_CFGR) I/O Line Function */
+#define S_PIO_CFGR_FUNC(value) ((S_PIO_CFGR_FUNC_Msk & ((value) << S_PIO_CFGR_FUNC_Pos)))
+#define   S_PIO_CFGR_FUNC_GPIO (0x0u << 0) /**< \brief (S_PIO_CFGR) Select the PIO mode for the selected I/O lines. */
+#define   S_PIO_CFGR_FUNC_PERIPH_A (0x1u << 0) /**< \brief (S_PIO_CFGR) Select the peripheral A for the selected I/O lines. */
+#define   S_PIO_CFGR_FUNC_PERIPH_B (0x2u << 0) /**< \brief (S_PIO_CFGR) Select the peripheral B for the selected I/O lines. */
+#define   S_PIO_CFGR_FUNC_PERIPH_C (0x3u << 0) /**< \brief (S_PIO_CFGR) Select the peripheral C for the selected I/O lines. */
+#define   S_PIO_CFGR_FUNC_PERIPH_D (0x4u << 0) /**< \brief (S_PIO_CFGR) Select the peripheral D for the selected I/O lines. */
+#define   S_PIO_CFGR_FUNC_PERIPH_E (0x5u << 0) /**< \brief (S_PIO_CFGR) Select the peripheral E for the selected I/O lines. */
+#define   S_PIO_CFGR_FUNC_PERIPH_F (0x6u << 0) /**< \brief (S_PIO_CFGR) Select the peripheral F for the selected I/O lines. */
+#define   S_PIO_CFGR_FUNC_PERIPH_G (0x7u << 0) /**< \brief (S_PIO_CFGR) Select the peripheral G for the selected I/O lines. */
+#define S_PIO_CFGR_DIR (0x1u << 8) /**< \brief (S_PIO_CFGR) Direction */
+#define   S_PIO_CFGR_DIR_INPUT (0x0u << 8) /**< \brief (S_PIO_CFGR) The selected I/O lines are pure inputs. */
+#define   S_PIO_CFGR_DIR_OUTPUT (0x1u << 8) /**< \brief (S_PIO_CFGR) The selected I/O lines are enabled in output. */
+#define S_PIO_CFGR_PUEN (0x1u << 9) /**< \brief (S_PIO_CFGR) Pull-Up Enable */
+#define   S_PIO_CFGR_PUEN_DISABLED (0x0u << 9) /**< \brief (S_PIO_CFGR) Pull-Up is disabled for the selected I/O lines. */
+#define   S_PIO_CFGR_PUEN_ENABLED (0x1u << 9) /**< \brief (S_PIO_CFGR) Pull-Up is enabled for the selected I/O lines. */
+#define S_PIO_CFGR_PDEN (0x1u << 10) /**< \brief (S_PIO_CFGR) Pull-Down Enable */
+#define   S_PIO_CFGR_PDEN_DISABLED (0x0u << 10) /**< \brief (S_PIO_CFGR) Pull-Down is disabled for the selected I/O lines. */
+#define   S_PIO_CFGR_PDEN_ENABLED (0x1u << 10) /**< \brief (S_PIO_CFGR) Pull-Down is enabled for the selected I/O lines only if PUEN is 0(1). */
+#define S_PIO_CFGR_IFEN (0x1u << 12) /**< \brief (S_PIO_CFGR) Input Filter Enable */
+#define   S_PIO_CFGR_IFEN_DISABLED (0x0u << 12) /**< \brief (S_PIO_CFGR) The input filter is disabled for the selected I/O lines. */
+#define   S_PIO_CFGR_IFEN_ENABLED (0x1u << 12) /**< \brief (S_PIO_CFGR) The input filter is enabled for the selected I/O lines. */
+#define S_PIO_CFGR_IFSCEN (0x1u << 13) /**< \brief (S_PIO_CFGR) Input Filter Slow Clock Enable */
+#define S_PIO_CFGR_OPD (0x1u << 14) /**< \brief (S_PIO_CFGR) Open-Drain */
+#define   S_PIO_CFGR_OPD_DISABLED (0x0u << 14) /**< \brief (S_PIO_CFGR) The open-drain is disabled for the selected I/O lines. I/O lines are driven at high- and low-level. */
+#define   S_PIO_CFGR_OPD_ENABLED (0x1u << 14) /**< \brief (S_PIO_CFGR) The open-drain is enabled for the selected I/O lines. I/O lines are driven at low-level only. */
+#define S_PIO_CFGR_SCHMITT (0x1u << 15) /**< \brief (S_PIO_CFGR) Schmitt Trigger */
+#define   S_PIO_CFGR_SCHMITT_ENABLED (0x0u << 15) /**< \brief (S_PIO_CFGR) Schmitt trigger is enabled for the selected I/O lines. */
+#define   S_PIO_CFGR_SCHMITT_DISABLED (0x1u << 15) /**< \brief (S_PIO_CFGR) Schmitt trigger is disabled for the selected I/O lines. */
+#define S_PIO_CFGR_DRVSTR_Pos 16
+#define S_PIO_CFGR_DRVSTR_Msk (0x3u << S_PIO_CFGR_DRVSTR_Pos) /**< \brief (S_PIO_CFGR)  */
+#define S_PIO_CFGR_DRVSTR(value) ((S_PIO_CFGR_DRVSTR_Msk & ((value) << S_PIO_CFGR_DRVSTR_Pos)))
+#define S_PIO_CFGR_EVTSEL_Pos 24
+#define S_PIO_CFGR_EVTSEL_Msk (0x7u << S_PIO_CFGR_EVTSEL_Pos) /**< \brief (S_PIO_CFGR) Event Selection */
+#define S_PIO_CFGR_EVTSEL(value) ((S_PIO_CFGR_EVTSEL_Msk & ((value) << S_PIO_CFGR_EVTSEL_Pos)))
+#define   S_PIO_CFGR_EVTSEL_FALLING (0x0u << 24) /**< \brief (S_PIO_CFGR) Event detection on input falling edge */
+#define   S_PIO_CFGR_EVTSEL_RISING (0x1u << 24) /**< \brief (S_PIO_CFGR) Event detection on input rising edge */
+#define   S_PIO_CFGR_EVTSEL_BOTH (0x2u << 24) /**< \brief (S_PIO_CFGR) Event detection on input both edge */
+#define   S_PIO_CFGR_EVTSEL_LOW (0x3u << 24) /**< \brief (S_PIO_CFGR) Event detection on low level input */
+#define   S_PIO_CFGR_EVTSEL_HIGH (0x4u << 24) /**< \brief (S_PIO_CFGR) Event detection on high level input */
+#define S_PIO_CFGR_PCFS (0x1u << 29) /**< \brief (S_PIO_CFGR) Physical Configuration Freeze Status */
+#define   S_PIO_CFGR_PCFS_NOT_FROZEN (0x0u << 29) /**< \brief (S_PIO_CFGR) The fields are not frozen and can be written for this I/O line. */
+#define   S_PIO_CFGR_PCFS_FROZEN (0x1u << 29) /**< \brief (S_PIO_CFGR) The fields are frozen and can not be written for this I/O line. Only a hardware reset can release these fields. */
+#define S_PIO_CFGR_ICFS (0x1u << 30) /**< \brief (S_PIO_CFGR) Interrupt Configuration Freeze Status */
+#define   S_PIO_CFGR_ICFS_NOT_FROZEN (0x0u << 30) /**< \brief (S_PIO_CFGR) The fields are not frozen and can be written for this I/O line. */
+#define   S_PIO_CFGR_ICFS_FROZEN (0x1u << 30) /**< \brief (S_PIO_CFGR) The fields are frozen and can not be written for this I/O line. Only a hardware reset can release these fields. */
+/* -------- S_PIO_PDSR : (PIO Offset: N/A) Secure PIO Pin Data Status Register -------- */
+#define S_PIO_PDSR_P0 (0x1u << 0) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P1 (0x1u << 1) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P2 (0x1u << 2) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P3 (0x1u << 3) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P4 (0x1u << 4) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P5 (0x1u << 5) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P6 (0x1u << 6) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P7 (0x1u << 7) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P8 (0x1u << 8) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P9 (0x1u << 9) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P10 (0x1u << 10) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P11 (0x1u << 11) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P12 (0x1u << 12) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P13 (0x1u << 13) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P14 (0x1u << 14) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P15 (0x1u << 15) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P16 (0x1u << 16) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P17 (0x1u << 17) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P18 (0x1u << 18) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P19 (0x1u << 19) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P20 (0x1u << 20) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P21 (0x1u << 21) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P22 (0x1u << 22) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P23 (0x1u << 23) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P24 (0x1u << 24) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P25 (0x1u << 25) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P26 (0x1u << 26) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P27 (0x1u << 27) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P28 (0x1u << 28) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P29 (0x1u << 29) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P30 (0x1u << 30) /**< \brief (S_PIO_PDSR) Input Data Status */
+#define S_PIO_PDSR_P31 (0x1u << 31) /**< \brief (S_PIO_PDSR) Input Data Status */
+/* -------- S_PIO_SODR : (PIO Offset: N/A) Secure PIO Set Output Data Register -------- */
+#define S_PIO_SODR_P0 (0x1u << 0) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P1 (0x1u << 1) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P2 (0x1u << 2) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P3 (0x1u << 3) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P4 (0x1u << 4) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P5 (0x1u << 5) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P6 (0x1u << 6) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P7 (0x1u << 7) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P8 (0x1u << 8) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P9 (0x1u << 9) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P10 (0x1u << 10) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P11 (0x1u << 11) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P12 (0x1u << 12) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P13 (0x1u << 13) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P14 (0x1u << 14) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P15 (0x1u << 15) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P16 (0x1u << 16) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P17 (0x1u << 17) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P18 (0x1u << 18) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P19 (0x1u << 19) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P20 (0x1u << 20) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P21 (0x1u << 21) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P22 (0x1u << 22) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P23 (0x1u << 23) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P24 (0x1u << 24) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P25 (0x1u << 25) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P26 (0x1u << 26) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P27 (0x1u << 27) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P28 (0x1u << 28) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P29 (0x1u << 29) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P30 (0x1u << 30) /**< \brief (S_PIO_SODR) Set Output Data */
+#define S_PIO_SODR_P31 (0x1u << 31) /**< \brief (S_PIO_SODR) Set Output Data */
+/* -------- S_PIO_CODR : (PIO Offset: N/A) Secure PIO Clear Output Data Register -------- */
+#define S_PIO_CODR_P0 (0x1u << 0) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P1 (0x1u << 1) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P2 (0x1u << 2) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P3 (0x1u << 3) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P4 (0x1u << 4) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P5 (0x1u << 5) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P6 (0x1u << 6) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P7 (0x1u << 7) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P8 (0x1u << 8) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P9 (0x1u << 9) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P10 (0x1u << 10) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P11 (0x1u << 11) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P12 (0x1u << 12) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P13 (0x1u << 13) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P14 (0x1u << 14) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P15 (0x1u << 15) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P16 (0x1u << 16) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P17 (0x1u << 17) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P18 (0x1u << 18) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P19 (0x1u << 19) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P20 (0x1u << 20) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P21 (0x1u << 21) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P22 (0x1u << 22) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P23 (0x1u << 23) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P24 (0x1u << 24) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P25 (0x1u << 25) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P26 (0x1u << 26) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P27 (0x1u << 27) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P28 (0x1u << 28) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P29 (0x1u << 29) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P30 (0x1u << 30) /**< \brief (S_PIO_CODR) Clear Output Data */
+#define S_PIO_CODR_P31 (0x1u << 31) /**< \brief (S_PIO_CODR) Clear Output Data */
+/* -------- S_PIO_ODSR : (PIO Offset: N/A) Secure PIO Output Data Status Register -------- */
+#define S_PIO_ODSR_P0 (0x1u << 0) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P1 (0x1u << 1) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P2 (0x1u << 2) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P3 (0x1u << 3) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P4 (0x1u << 4) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P5 (0x1u << 5) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P6 (0x1u << 6) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P7 (0x1u << 7) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P8 (0x1u << 8) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P9 (0x1u << 9) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P10 (0x1u << 10) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P11 (0x1u << 11) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P12 (0x1u << 12) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P13 (0x1u << 13) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P14 (0x1u << 14) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P15 (0x1u << 15) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P16 (0x1u << 16) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P17 (0x1u << 17) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P18 (0x1u << 18) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P19 (0x1u << 19) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P20 (0x1u << 20) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P21 (0x1u << 21) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P22 (0x1u << 22) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P23 (0x1u << 23) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P24 (0x1u << 24) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P25 (0x1u << 25) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P26 (0x1u << 26) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P27 (0x1u << 27) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P28 (0x1u << 28) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P29 (0x1u << 29) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P30 (0x1u << 30) /**< \brief (S_PIO_ODSR) Output Data Status */
+#define S_PIO_ODSR_P31 (0x1u << 31) /**< \brief (S_PIO_ODSR) Output Data Status */
+/* -------- S_PIO_IER : (PIO Offset: N/A) Secure PIO Interrupt Enable Register -------- */
+#define S_PIO_IER_P0 (0x1u << 0) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P1 (0x1u << 1) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P2 (0x1u << 2) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P3 (0x1u << 3) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P4 (0x1u << 4) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P5 (0x1u << 5) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P6 (0x1u << 6) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P7 (0x1u << 7) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P8 (0x1u << 8) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P9 (0x1u << 9) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P10 (0x1u << 10) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P11 (0x1u << 11) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P12 (0x1u << 12) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P13 (0x1u << 13) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P14 (0x1u << 14) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P15 (0x1u << 15) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P16 (0x1u << 16) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P17 (0x1u << 17) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P18 (0x1u << 18) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P19 (0x1u << 19) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P20 (0x1u << 20) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P21 (0x1u << 21) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P22 (0x1u << 22) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P23 (0x1u << 23) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P24 (0x1u << 24) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P25 (0x1u << 25) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P26 (0x1u << 26) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P27 (0x1u << 27) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P28 (0x1u << 28) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P29 (0x1u << 29) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P30 (0x1u << 30) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+#define S_PIO_IER_P31 (0x1u << 31) /**< \brief (S_PIO_IER) Input Change Interrupt Enable */
+/* -------- S_PIO_IDR : (PIO Offset: N/A) Secure PIO Interrupt Disable Register -------- */
+#define S_PIO_IDR_P0 (0x1u << 0) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P1 (0x1u << 1) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P2 (0x1u << 2) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P3 (0x1u << 3) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P4 (0x1u << 4) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P5 (0x1u << 5) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P6 (0x1u << 6) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P7 (0x1u << 7) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P8 (0x1u << 8) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P9 (0x1u << 9) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P10 (0x1u << 10) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P11 (0x1u << 11) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P12 (0x1u << 12) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P13 (0x1u << 13) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P14 (0x1u << 14) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P15 (0x1u << 15) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P16 (0x1u << 16) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P17 (0x1u << 17) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P18 (0x1u << 18) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P19 (0x1u << 19) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P20 (0x1u << 20) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P21 (0x1u << 21) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P22 (0x1u << 22) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P23 (0x1u << 23) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P24 (0x1u << 24) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P25 (0x1u << 25) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P26 (0x1u << 26) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P27 (0x1u << 27) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P28 (0x1u << 28) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P29 (0x1u << 29) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P30 (0x1u << 30) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+#define S_PIO_IDR_P31 (0x1u << 31) /**< \brief (S_PIO_IDR) Input Change Interrupt Disable */
+/* -------- S_PIO_IMR : (PIO Offset: N/A) Secure PIO Interrupt Mask Register -------- */
+#define S_PIO_IMR_P0 (0x1u << 0) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P1 (0x1u << 1) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P2 (0x1u << 2) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P3 (0x1u << 3) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P4 (0x1u << 4) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P5 (0x1u << 5) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P6 (0x1u << 6) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P7 (0x1u << 7) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P8 (0x1u << 8) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P9 (0x1u << 9) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P10 (0x1u << 10) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P11 (0x1u << 11) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P12 (0x1u << 12) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P13 (0x1u << 13) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P14 (0x1u << 14) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P15 (0x1u << 15) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P16 (0x1u << 16) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P17 (0x1u << 17) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P18 (0x1u << 18) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P19 (0x1u << 19) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P20 (0x1u << 20) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P21 (0x1u << 21) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P22 (0x1u << 22) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P23 (0x1u << 23) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P24 (0x1u << 24) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P25 (0x1u << 25) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P26 (0x1u << 26) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P27 (0x1u << 27) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P28 (0x1u << 28) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P29 (0x1u << 29) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P30 (0x1u << 30) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+#define S_PIO_IMR_P31 (0x1u << 31) /**< \brief (S_PIO_IMR) Input Change Interrupt Mask */
+/* -------- S_PIO_ISR : (PIO Offset: N/A) Secure PIO Interrupt Status Register -------- */
+#define S_PIO_ISR_P0 (0x1u << 0) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P1 (0x1u << 1) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P2 (0x1u << 2) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P3 (0x1u << 3) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P4 (0x1u << 4) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P5 (0x1u << 5) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P6 (0x1u << 6) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P7 (0x1u << 7) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P8 (0x1u << 8) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P9 (0x1u << 9) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P10 (0x1u << 10) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P11 (0x1u << 11) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P12 (0x1u << 12) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P13 (0x1u << 13) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P14 (0x1u << 14) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P15 (0x1u << 15) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P16 (0x1u << 16) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P17 (0x1u << 17) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P18 (0x1u << 18) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P19 (0x1u << 19) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P20 (0x1u << 20) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P21 (0x1u << 21) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P22 (0x1u << 22) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P23 (0x1u << 23) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P24 (0x1u << 24) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P25 (0x1u << 25) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P26 (0x1u << 26) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P27 (0x1u << 27) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P28 (0x1u << 28) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P29 (0x1u << 29) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P30 (0x1u << 30) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+#define S_PIO_ISR_P31 (0x1u << 31) /**< \brief (S_PIO_ISR) Input Change Interrupt Status */
+/* -------- S_PIO_SIONR : (PIO Offset: N/A) Secure PIO Set I/O Non-Secure Register -------- */
+#define S_PIO_SIONR_P0 (0x1u << 0) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P1 (0x1u << 1) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P2 (0x1u << 2) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P3 (0x1u << 3) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P4 (0x1u << 4) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P5 (0x1u << 5) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P6 (0x1u << 6) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P7 (0x1u << 7) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P8 (0x1u << 8) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P9 (0x1u << 9) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P10 (0x1u << 10) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P11 (0x1u << 11) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P12 (0x1u << 12) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P13 (0x1u << 13) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P14 (0x1u << 14) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P15 (0x1u << 15) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P16 (0x1u << 16) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P17 (0x1u << 17) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P18 (0x1u << 18) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P19 (0x1u << 19) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P20 (0x1u << 20) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P21 (0x1u << 21) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P22 (0x1u << 22) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P23 (0x1u << 23) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P24 (0x1u << 24) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P25 (0x1u << 25) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P26 (0x1u << 26) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P27 (0x1u << 27) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P28 (0x1u << 28) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P29 (0x1u << 29) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P30 (0x1u << 30) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+#define S_PIO_SIONR_P31 (0x1u << 31) /**< \brief (S_PIO_SIONR) Set I/O Non-Secure */
+/* -------- S_PIO_SIOSR : (PIO Offset: N/A) Secure PIO Set I/O Secure Register -------- */
+#define S_PIO_SIOSR_P0 (0x1u << 0) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P1 (0x1u << 1) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P2 (0x1u << 2) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P3 (0x1u << 3) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P4 (0x1u << 4) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P5 (0x1u << 5) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P6 (0x1u << 6) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P7 (0x1u << 7) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P8 (0x1u << 8) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P9 (0x1u << 9) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P10 (0x1u << 10) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P11 (0x1u << 11) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P12 (0x1u << 12) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P13 (0x1u << 13) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P14 (0x1u << 14) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P15 (0x1u << 15) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P16 (0x1u << 16) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P17 (0x1u << 17) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P18 (0x1u << 18) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P19 (0x1u << 19) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P20 (0x1u << 20) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P21 (0x1u << 21) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P22 (0x1u << 22) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P23 (0x1u << 23) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P24 (0x1u << 24) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P25 (0x1u << 25) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P26 (0x1u << 26) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P27 (0x1u << 27) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P28 (0x1u << 28) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P29 (0x1u << 29) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P30 (0x1u << 30) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+#define S_PIO_SIOSR_P31 (0x1u << 31) /**< \brief (S_PIO_SIOSR) Set I/O Secure */
+/* -------- S_PIO_IOSSR : (PIO Offset: N/A) Secure PIO I/O Security Status Register -------- */
+#define S_PIO_IOSSR_P0 (0x1u << 0) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P0_SECURE (0x0u << 0) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P0_NON_SECURE (0x1u << 0) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P1 (0x1u << 1) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P1_SECURE (0x0u << 1) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P1_NON_SECURE (0x1u << 1) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P2 (0x1u << 2) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P2_SECURE (0x0u << 2) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P2_NON_SECURE (0x1u << 2) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P3 (0x1u << 3) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P3_SECURE (0x0u << 3) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P3_NON_SECURE (0x1u << 3) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P4 (0x1u << 4) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P4_SECURE (0x0u << 4) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P4_NON_SECURE (0x1u << 4) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P5 (0x1u << 5) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P5_SECURE (0x0u << 5) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P5_NON_SECURE (0x1u << 5) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P6 (0x1u << 6) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P6_SECURE (0x0u << 6) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P6_NON_SECURE (0x1u << 6) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P7 (0x1u << 7) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P7_SECURE (0x0u << 7) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P7_NON_SECURE (0x1u << 7) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P8 (0x1u << 8) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P8_SECURE (0x0u << 8) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P8_NON_SECURE (0x1u << 8) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P9 (0x1u << 9) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P9_SECURE (0x0u << 9) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P9_NON_SECURE (0x1u << 9) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P10 (0x1u << 10) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P10_SECURE (0x0u << 10) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P10_NON_SECURE (0x1u << 10) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P11 (0x1u << 11) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P11_SECURE (0x0u << 11) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P11_NON_SECURE (0x1u << 11) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P12 (0x1u << 12) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P12_SECURE (0x0u << 12) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P12_NON_SECURE (0x1u << 12) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P13 (0x1u << 13) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P13_SECURE (0x0u << 13) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P13_NON_SECURE (0x1u << 13) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P14 (0x1u << 14) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P14_SECURE (0x0u << 14) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P14_NON_SECURE (0x1u << 14) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P15 (0x1u << 15) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P15_SECURE (0x0u << 15) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P15_NON_SECURE (0x1u << 15) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P16 (0x1u << 16) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P16_SECURE (0x0u << 16) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P16_NON_SECURE (0x1u << 16) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P17 (0x1u << 17) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P17_SECURE (0x0u << 17) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P17_NON_SECURE (0x1u << 17) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P18 (0x1u << 18) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P18_SECURE (0x0u << 18) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P18_NON_SECURE (0x1u << 18) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P19 (0x1u << 19) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P19_SECURE (0x0u << 19) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P19_NON_SECURE (0x1u << 19) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P20 (0x1u << 20) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P20_SECURE (0x0u << 20) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P20_NON_SECURE (0x1u << 20) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P21 (0x1u << 21) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P21_SECURE (0x0u << 21) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P21_NON_SECURE (0x1u << 21) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P22 (0x1u << 22) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P22_SECURE (0x0u << 22) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P22_NON_SECURE (0x1u << 22) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P23 (0x1u << 23) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P23_SECURE (0x0u << 23) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P23_NON_SECURE (0x1u << 23) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P24 (0x1u << 24) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P24_SECURE (0x0u << 24) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P24_NON_SECURE (0x1u << 24) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P25 (0x1u << 25) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P25_SECURE (0x0u << 25) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P25_NON_SECURE (0x1u << 25) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P26 (0x1u << 26) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P26_SECURE (0x0u << 26) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P26_NON_SECURE (0x1u << 26) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P27 (0x1u << 27) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P27_SECURE (0x0u << 27) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P27_NON_SECURE (0x1u << 27) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P28 (0x1u << 28) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P28_SECURE (0x0u << 28) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P28_NON_SECURE (0x1u << 28) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P29 (0x1u << 29) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P29_SECURE (0x0u << 29) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P29_NON_SECURE (0x1u << 29) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P30 (0x1u << 30) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P30_SECURE (0x0u << 30) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P30_NON_SECURE (0x1u << 30) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+#define S_PIO_IOSSR_P31 (0x1u << 31) /**< \brief (S_PIO_IOSSR) I/O Security Status */
+#define   S_PIO_IOSSR_P31_SECURE (0x0u << 31) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Secure mode. */
+#define   S_PIO_IOSSR_P31_NON_SECURE (0x1u << 31) /**< \brief (S_PIO_IOSSR) The I/O line of the I/O group x is in Non-Secure mode. */
+/* -------- S_PIO_IOFR : (PIO Offset: N/A) Secure PIO I/O Freeze Register -------- */
+#define S_PIO_IOFR_FPHY (0x1u << 0) /**< \brief (S_PIO_IOFR) Freeze Physical Configuration */
+#define S_PIO_IOFR_FINT (0x1u << 1) /**< \brief (S_PIO_IOFR) Freeze Interrupt Configuration */
+#define S_PIO_IOFR_FRZKEY_Pos 8
+#define S_PIO_IOFR_FRZKEY_Msk (0xffffffu << S_PIO_IOFR_FRZKEY_Pos) /**< \brief (S_PIO_IOFR) Freeze Key */
+#define S_PIO_IOFR_FRZKEY(value) ((S_PIO_IOFR_FRZKEY_Msk & ((value) << S_PIO_IOFR_FRZKEY_Pos)))
+#define   S_PIO_IOFR_FRZKEY_PASSWD (0x494F46u << 8) /**< \brief (S_PIO_IOFR) Writing any other value in this field aborts the write operation of the WPEN bit. */
+/* -------- S_PIO_SCDR : (PIO Offset: 0x1500) Secure PIO Slow Clock Divider Debouncing Register -------- */
+#define S_PIO_SCDR_DIV_Pos 0
+#define S_PIO_SCDR_DIV_Msk (0x3fffu << S_PIO_SCDR_DIV_Pos) /**< \brief (S_PIO_SCDR) Slow Clock Divider Selection for Debouncing */
+#define S_PIO_SCDR_DIV(value) ((S_PIO_SCDR_DIV_Msk & ((value) << S_PIO_SCDR_DIV_Pos)))
+/* -------- S_PIO_WPMR : (PIO Offset: 0x15E0) Secure PIO Write Protection Mode Register -------- */
+#define S_PIO_WPMR_WPEN (0x1u << 0) /**< \brief (S_PIO_WPMR) Write Protection Enable */
+#define S_PIO_WPMR_WPKEY_Pos 8
+#define S_PIO_WPMR_WPKEY_Msk (0xffffffu << S_PIO_WPMR_WPKEY_Pos) /**< \brief (S_PIO_WPMR) Write Protection Key */
+#define S_PIO_WPMR_WPKEY(value) ((S_PIO_WPMR_WPKEY_Msk & ((value) << S_PIO_WPMR_WPKEY_Pos)))
+#define   S_PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (S_PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
+/* -------- S_PIO_WPSR : (PIO Offset: 0x15E4) Secure PIO Write Protection Status Register -------- */
+#define S_PIO_WPSR_WPVS (0x1u << 0) /**< \brief (S_PIO_WPSR) Write Protection Violation Status */
+#define S_PIO_WPSR_WPVSRC_Pos 8
+#define S_PIO_WPSR_WPVSRC_Msk (0xffffu << S_PIO_WPSR_WPVSRC_Pos) /**< \brief (S_PIO_WPSR) Write Protection Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_PIO_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_pit.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_pit.h
new file mode 100644
index 000000000..fa179b722
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_pit.h
@@ -0,0 +1,70 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_PIT_COMPONENT_
+#define _SAMA5D2_PIT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Periodic Interval Timer */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_PIT Periodic Interval Timer */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pit hardware registers */
+typedef struct {
+  __IO uint32_t PIT_MR;   /**< \brief (Pit Offset: 0x00) Mode Register */
+  __I  uint32_t PIT_SR;   /**< \brief (Pit Offset: 0x04) Status Register */
+  __I  uint32_t PIT_PIVR; /**< \brief (Pit Offset: 0x08) Periodic Interval Value Register */
+  __I  uint32_t PIT_PIIR; /**< \brief (Pit Offset: 0x0C) Periodic Interval Image Register */
+} Pit;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PIT_MR : (PIT Offset: 0x00) Mode Register -------- */
+#define PIT_MR_PIV_Pos 0
+#define PIT_MR_PIV_Msk (0xfffffu << PIT_MR_PIV_Pos) /**< \brief (PIT_MR) Periodic Interval Value */
+#define PIT_MR_PIV(value) ((PIT_MR_PIV_Msk & ((value) << PIT_MR_PIV_Pos)))
+#define PIT_MR_PITEN (0x1u << 24) /**< \brief (PIT_MR) Period Interval Timer Enabled */
+#define PIT_MR_PITIEN (0x1u << 25) /**< \brief (PIT_MR) Periodic Interval Timer Interrupt Enable */
+/* -------- PIT_SR : (PIT Offset: 0x04) Status Register -------- */
+#define PIT_SR_PITS (0x1u << 0) /**< \brief (PIT_SR) Periodic Interval Timer Status */
+/* -------- PIT_PIVR : (PIT Offset: 0x08) Periodic Interval Value Register -------- */
+#define PIT_PIVR_CPIV_Pos 0
+#define PIT_PIVR_CPIV_Msk (0xfffffu << PIT_PIVR_CPIV_Pos) /**< \brief (PIT_PIVR) Current Periodic Interval Value */
+#define PIT_PIVR_PICNT_Pos 20
+#define PIT_PIVR_PICNT_Msk (0xfffu << PIT_PIVR_PICNT_Pos) /**< \brief (PIT_PIVR) Periodic Interval Counter */
+/* -------- PIT_PIIR : (PIT Offset: 0x0C) Periodic Interval Image Register -------- */
+#define PIT_PIIR_CPIV_Pos 0
+#define PIT_PIIR_CPIV_Msk (0xfffffu << PIT_PIIR_CPIV_Pos) /**< \brief (PIT_PIIR) Current Periodic Interval Value */
+#define PIT_PIIR_PICNT_Pos 20
+#define PIT_PIIR_PICNT_Msk (0xfffu << PIT_PIIR_PICNT_Pos) /**< \brief (PIT_PIIR) Periodic Interval Counter */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_PIT_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_pmc.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_pmc.h
new file mode 100644
index 000000000..f233a01fb
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_pmc.h
@@ -0,0 +1,579 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_PMC_COMPONENT_
+#define _SAMA5D2_PMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Power Management Controller */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_PMC Power Management Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pmc hardware registers */
+typedef struct {
+  __O  uint32_t PMC_SCER;       /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
+  __O  uint32_t PMC_SCDR;       /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
+  __I  uint32_t PMC_SCSR;       /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
+  __I  uint32_t Reserved1[1];
+  __O  uint32_t PMC_PCER0;      /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */
+  __O  uint32_t PMC_PCDR0;      /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */
+  __I  uint32_t PMC_PCSR0;      /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */
+  __IO uint32_t CKGR_UCKR;      /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */
+  __IO uint32_t CKGR_MOR;       /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
+  __IO uint32_t CKGR_MCFR;      /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
+  __IO uint32_t CKGR_PLLAR;     /**< \brief (Pmc Offset: 0x0028) PLLA Register */
+  __I  uint32_t Reserved2[1];
+  __IO uint32_t PMC_MCKR;       /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
+  __I  uint32_t Reserved3[1];
+  __IO uint32_t PMC_USB;        /**< \brief (Pmc Offset: 0x0038) USB Clock Register */
+  __I  uint32_t Reserved4[1];
+  __IO uint32_t PMC_PCK[3];     /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
+  __I  uint32_t Reserved5[5];
+  __O  uint32_t PMC_IER;        /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
+  __O  uint32_t PMC_IDR;        /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
+  __I  uint32_t PMC_SR;         /**< \brief (Pmc Offset: 0x0068) Status Register */
+  __I  uint32_t PMC_IMR;        /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
+  __IO uint32_t PMC_FSMR;       /**< \brief (Pmc Offset: 0x0070) PMC Fast Startup Mode Register */
+  __IO uint32_t PMC_FSPR;       /**< \brief (Pmc Offset: 0x0074) PMC Fast Startup Polarity Register */
+  __O  uint32_t PMC_FOCR;       /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
+  __I  uint32_t Reserved6[1];
+  __IO uint32_t PMC_PLLICPR;    /**< \brief (Pmc Offset: 0x0080) PLL Charge Pump Current Register */
+  __I  uint32_t Reserved7[24];
+  __IO uint32_t PMC_WPMR;       /**< \brief (Pmc Offset: 0x00E4) Write ProtectIon Mode Register */
+  __I  uint32_t PMC_WPSR;       /**< \brief (Pmc Offset: 0x00E8) Write Protection Status Register */
+  __I  uint32_t Reserved8[4];
+  __I  uint32_t PMC_VERSION;    /**< \brief (Pmc Offset: 0x00FC) Version Register */
+  __O  uint32_t PMC_PCER1;      /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */
+  __O  uint32_t PMC_PCDR1;      /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */
+  __I  uint32_t PMC_PCSR1;      /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */
+  __IO uint32_t PMC_PCR;        /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */
+  __IO uint32_t PMC_OCR;        /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */
+  __I  uint32_t Reserved9[12];
+  __I  uint32_t PMC_SLPWK_AIPR; /**< \brief (Pmc Offset: 0x0144) SleepWalking Activity In Progress Register */
+  __IO uint32_t PMC_SLPWKCR;    /**< \brief (Pmc Offset: 0x0148) SleepWalking Control Register */
+  __IO uint32_t PMC_AUDIO_PLL0; /**< \brief (Pmc Offset: 0x014C) Audio PLL Register 0 */
+  __IO uint32_t PMC_AUDIO_PLL1; /**< \brief (Pmc Offset: 0x0150) Audio PLL Register 1 */
+} Pmc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
+#define PMC_SCER_DDRCK (0x1u << 2) /**< \brief (PMC_SCER) DDR Clock Enable */
+#define PMC_SCER_LCDCK (0x1u << 3) /**< \brief (PMC_SCER) LCD2x Clock Enable */
+#define PMC_SCER_UHP (0x1u << 6) /**< \brief (PMC_SCER) USB Host OHCI Clocks Enable */
+#define PMC_SCER_UDP (0x1u << 7) /**< \brief (PMC_SCER) USB Device Clock Enable */
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
+#define PMC_SCER_ISCCK (0x1u << 18) /**< \brief (PMC_SCER) ISC Clock Enable */
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
+#define PMC_SCDR_DDRCK (0x1u << 2) /**< \brief (PMC_SCDR) DDR Clock Disable */
+#define PMC_SCDR_LCDCK (0x1u << 3) /**< \brief (PMC_SCDR) LCD2x Clock Disable */
+#define PMC_SCDR_UHP (0x1u << 6) /**< \brief (PMC_SCDR) USB Host OHCI Clock Disable */
+#define PMC_SCDR_UDP (0x1u << 7) /**< \brief (PMC_SCDR) USB Device Clock Enable */
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
+#define PMC_SCDR_ISCCK (0x1u << 18) /**< \brief (PMC_SCDR) ISC Clock Disable */
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
+#define PMC_SCSR_DDRCK (0x1u << 2) /**< \brief (PMC_SCSR) DDR Clock Status */
+#define PMC_SCSR_LCDCK (0x1u << 3) /**< \brief (PMC_SCSR) LCD2x Clock Status */
+#define PMC_SCSR_UHP (0x1u << 6) /**< \brief (PMC_SCSR) USB Host Port Clock Status */
+#define PMC_SCSR_UDP (0x1u << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
+#define PMC_SCSR_ISCCK (0x1u << 18) /**< \brief (PMC_SCSR) ISC Clock Status */
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
+#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */
+#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */
+#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */
+#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */
+#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */
+#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */
+#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */
+#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */
+#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */
+#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */
+#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */
+#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */
+#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
+#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */
+#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */
+#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */
+#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */
+#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */
+#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */
+#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */
+#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */
+#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */
+#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */
+#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */
+#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */
+#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
+#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */
+#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */
+#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */
+#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */
+#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */
+#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */
+#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */
+#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */
+#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */
+#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */
+#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */
+#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */
+#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */
+/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */
+#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */
+#define CKGR_UCKR_UPLLCOUNT_Pos 20
+#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */
+#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))
+#define CKGR_UCKR_BIASEN (0x1u << 24) /**< \brief (CKGR_UCKR) UTMI BIAS Enable */
+#define CKGR_UCKR_BIASCOUNT_Pos 28
+#define CKGR_UCKR_BIASCOUNT_Msk (0xfu << CKGR_UCKR_BIASCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI BIAS Start-up Time */
+#define CKGR_UCKR_BIASCOUNT(value) ((CKGR_UCKR_BIASCOUNT_Msk & ((value) << CKGR_UCKR_BIASCOUNT_Pos)))
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) 8 to 24MHz Crystal Oscillator Enable */
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) 8 to 24MHz Crystal Oscillator Bypass */
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) 12 MHz RC Oscillator Enable */
+#define CKGR_MOR_MOSCXTST_Pos 8
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) 8 to 24MHz Crystal Oscillator Startup Time */
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
+#define CKGR_MOR_KEY_Pos 16
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
+#define   CKGR_MOR_KEY_PASSWD (0x37u << 16) /**< \brief (CKGR_MOR) Writing any other value in this field aborts the write operation. */
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Clock Oscillator Selection */
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
+#define CKGR_MCFR_MAINF_Pos 0
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
+#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)))
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Frequency Measure Ready */
+#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */
+#define CKGR_MCFR_CCSS (0x1u << 24) /**< \brief (CKGR_MCFR) Counter Clock Source Selection */
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
+#define CKGR_PLLAR_DIVA_Pos 0
+#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider A */
+#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
+#define   CKGR_PLLAR_DIVA_0 (0x0u << 0) /**< \brief (CKGR_PLLAR) Divider output is 0 */
+#define   CKGR_PLLAR_DIVA_BYPASS (0x1u << 0) /**< \brief (CKGR_PLLAR) Divider is bypassed */
+#define CKGR_PLLAR_PLLACOUNT_Pos 8
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
+#define CKGR_PLLAR_OUTA_Pos 14
+#define CKGR_PLLAR_OUTA_Msk (0xfu << CKGR_PLLAR_OUTA_Pos) /**< \brief (CKGR_PLLAR) PLLA Clock Frequency Range */
+#define CKGR_PLLAR_OUTA(value) ((CKGR_PLLAR_OUTA_Msk & ((value) << CKGR_PLLAR_OUTA_Pos)))
+#define CKGR_PLLAR_MULA_Pos 18
+#define CKGR_PLLAR_MULA_Msk (0x7fu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
+#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
+#define PMC_MCKR_CSS_Pos 0
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master/Processor Clock Source Selection */
+#define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos)))
+#define   PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow clock is selected */
+#define   PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main clock is selected */
+#define   PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLACK is selected */
+#define   PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) UPLL Clock is selected */
+#define PMC_MCKR_PRES_Pos 4
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Master/Processor Clock Prescaler */
+#define PMC_MCKR_PRES(value) ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos)))
+#define   PMC_MCKR_PRES_CLOCK (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */
+#define   PMC_MCKR_PRES_CLOCK_DIV2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
+#define   PMC_MCKR_PRES_CLOCK_DIV4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
+#define   PMC_MCKR_PRES_CLOCK_DIV8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
+#define   PMC_MCKR_PRES_CLOCK_DIV16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
+#define   PMC_MCKR_PRES_CLOCK_DIV32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
+#define   PMC_MCKR_PRES_CLOCK_DIV64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
+#define PMC_MCKR_MDIV_Pos 8
+#define PMC_MCKR_MDIV_Msk (0x3u << PMC_MCKR_MDIV_Pos) /**< \brief (PMC_MCKR) Master Clock Division */
+#define PMC_MCKR_MDIV(value) ((PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos)))
+#define   PMC_MCKR_MDIV_EQ_PCK (0x0u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. WARNING: SysClk DDR and DDRCK are not available. */
+#define   PMC_MCKR_MDIV_PCK_DIV2 (0x1u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. */
+#define   PMC_MCKR_MDIV_PCK_DIV4 (0x2u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. */
+#define   PMC_MCKR_MDIV_PCK_DIV3 (0x3u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. */
+#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */
+#define PMC_MCKR_H32MXDIV (0x1u << 24) /**< \brief (PMC_MCKR) AHB 32-bit Matrix Divisor */
+#define   PMC_MCKR_H32MXDIV_H32MXDIV1 (0x0u << 24) /**< \brief (PMC_MCKR) The AHB 32-bit Matrix frequency is equal to the AHB 64-bit Matrix frequency. It is possible only if the AHB 64-bit Matrix frequency does not exceed 90 MHz. */
+#define   PMC_MCKR_H32MXDIV_H32MXDIV2 (0x1u << 24) /**< \brief (PMC_MCKR) The AHB 32-bit Matrix frequency is equal to the AHB 64-bit Matrix frequency divided by 2. */
+/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */
+#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB OHCI Input Clock Selection */
+#define PMC_USB_USBDIV_Pos 8
+#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB OHCI Clock */
+#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))
+/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
+#define PMC_PCK_CSS_Pos 0
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
+#define PMC_PCK_CSS(value) ((PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos)))
+#define   PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow clock is selected */
+#define   PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main clock is selected */
+#define   PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLACK is selected */
+#define   PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) UPLL Clock is selected */
+#define   PMC_PCK_CSS_MCK_CLK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */
+#define   PMC_PCK_CSS_AUDIO_CLK (0x5u << 0) /**< \brief (PMC_PCK[3]) Audio PLL clock is selected */
+#define PMC_PCK_PRES_Pos 4
+#define PMC_PCK_PRES_Msk (0xffu << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */
+#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos)))
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) 8 to 24MHz Crystal Oscillator Status Interrupt Enable */
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
+#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Clock Source Oscillator Selection Status Interrupt Enable */
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) 8 to 24MHz Crystal Oscillator Status Interrupt Disable */
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
+#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Enable */
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Clock Source Selection Status Interrupt Disable */
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) 8 to 24MHz Crystal Oscillator Status */
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
+#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UPLL Clock Status */
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) 12 MHz RC Oscillator Status */
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
+#define PMC_SR_GCKRDY (0x1u << 24) /**< \brief (PMC_SR) Generated Clocks Status */
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) 8 to 24MHz Crystal Oscillator Status Interrupt Mask */
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Clock Source Selection Status Interrupt Mask */
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) PMC Fast Startup Mode Register -------- */
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
+#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */
+#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low-power Mode */
+#define PMC_FSMR_RXLPAL (0x1u << 24) /**< \brief (PMC_FSMR) Lower-power Receiver Alarm */
+#define PMC_FSMR_ACCAL (0x1u << 25) /**< \brief (PMC_FSMR) Analog Comparator Controller Alarm */
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) PMC Fast Startup Polarity Register -------- */
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
+/* -------- PMC_PLLICPR : (PMC Offset: 0x0080) PLL Charge Pump Current Register -------- */
+#define PMC_PLLICPR_ICP_PLLA_Pos 0
+#define PMC_PLLICPR_ICP_PLLA_Msk (0x3u << PMC_PLLICPR_ICP_PLLA_Pos) /**< \brief (PMC_PLLICPR) Must Be Written to Zero */
+#define PMC_PLLICPR_ICP_PLLA(value) ((PMC_PLLICPR_ICP_PLLA_Msk & ((value) << PMC_PLLICPR_ICP_PLLA_Pos)))
+#define PMC_PLLICPR_ICP_PLLU_Pos 16
+#define PMC_PLLICPR_ICP_PLLU_Msk (0x3u << PMC_PLLICPR_ICP_PLLU_Pos) /**< \brief (PMC_PLLICPR) Charge Pump Current PLL UTMI */
+#define PMC_PLLICPR_ICP_PLLU(value) ((PMC_PLLICPR_ICP_PLLU_Msk & ((value) << PMC_PLLICPR_ICP_PLLU_Pos)))
+#define PMC_PLLICPR_IVCO_PLLU_Pos 24
+#define PMC_PLLICPR_IVCO_PLLU_Msk (0x3u << PMC_PLLICPR_IVCO_PLLU_Pos) /**< \brief (PMC_PLLICPR) Voltage Control Output Current PLL UTMI */
+#define PMC_PLLICPR_IVCO_PLLU(value) ((PMC_PLLICPR_IVCO_PLLU_Msk & ((value) << PMC_PLLICPR_IVCO_PLLU_Pos)))
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write ProtectIon Mode Register -------- */
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protection Enable */
+#define PMC_WPMR_WPKEY_Pos 8
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protection Key */
+#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
+#define   PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) /**< \brief (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protection Violation Status */
+#define PMC_WPSR_WPVSRC_Pos 8
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protection Violation Source */
+/* -------- PMC_VERSION : (PMC Offset: 0x00FC) Version Register -------- */
+#define PMC_VERSION_VERSION_Pos 0
+#define PMC_VERSION_VERSION_Msk (0xfffu << PMC_VERSION_VERSION_Pos) /**< \brief (PMC_VERSION) Version of the Hardware Module */
+#define PMC_VERSION_MFN_Pos 16
+#define PMC_VERSION_MFN_Msk (0x7u << PMC_VERSION_MFN_Pos) /**< \brief (PMC_VERSION) Metal Fix Number */
+/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */
+#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */
+#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */
+#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */
+#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */
+#define PMC_PCER1_PID36 (0x1u << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */
+#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */
+#define PMC_PCER1_PID38 (0x1u << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */
+#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */
+#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */
+#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */
+#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */
+#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */
+#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */
+#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */
+#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */
+#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */
+#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */
+#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */
+#define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */
+#define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */
+#define PMC_PCER1_PID52 (0x1u << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */
+#define PMC_PCER1_PID53 (0x1u << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */
+#define PMC_PCER1_PID54 (0x1u << 22) /**< \brief (PMC_PCER1) Peripheral Clock 54 Enable */
+#define PMC_PCER1_PID55 (0x1u << 23) /**< \brief (PMC_PCER1) Peripheral Clock 55 Enable */
+#define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */
+#define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */
+#define PMC_PCER1_PID58 (0x1u << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */
+#define PMC_PCER1_PID59 (0x1u << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */
+#define PMC_PCER1_PID60 (0x1u << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */
+#define PMC_PCER1_PID61 (0x1u << 29) /**< \brief (PMC_PCER1) Peripheral Clock 61 Enable */
+#define PMC_PCER1_PID62 (0x1u << 30) /**< \brief (PMC_PCER1) Peripheral Clock 62 Enable */
+#define PMC_PCER1_PID63 (0x1u << 31) /**< \brief (PMC_PCER1) Peripheral Clock 63 Enable */
+/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */
+#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */
+#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */
+#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */
+#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */
+#define PMC_PCDR1_PID36 (0x1u << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */
+#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */
+#define PMC_PCDR1_PID38 (0x1u << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */
+#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */
+#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */
+#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */
+#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */
+#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */
+#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */
+#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */
+#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */
+#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */
+#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */
+#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */
+#define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */
+#define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */
+#define PMC_PCDR1_PID52 (0x1u << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */
+#define PMC_PCDR1_PID53 (0x1u << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */
+#define PMC_PCDR1_PID54 (0x1u << 22) /**< \brief (PMC_PCDR1) Peripheral Clock 54 Disable */
+#define PMC_PCDR1_PID55 (0x1u << 23) /**< \brief (PMC_PCDR1) Peripheral Clock 55 Disable */
+#define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */
+#define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */
+#define PMC_PCDR1_PID58 (0x1u << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */
+#define PMC_PCDR1_PID59 (0x1u << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */
+#define PMC_PCDR1_PID60 (0x1u << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */
+#define PMC_PCDR1_PID61 (0x1u << 29) /**< \brief (PMC_PCDR1) Peripheral Clock 61 Disable */
+#define PMC_PCDR1_PID62 (0x1u << 30) /**< \brief (PMC_PCDR1) Peripheral Clock 62 Disable */
+#define PMC_PCDR1_PID63 (0x1u << 31) /**< \brief (PMC_PCDR1) Peripheral Clock 63 Disable */
+/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */
+#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */
+#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */
+#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */
+#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */
+#define PMC_PCSR1_PID36 (0x1u << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */
+#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */
+#define PMC_PCSR1_PID38 (0x1u << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */
+#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */
+#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */
+#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */
+#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */
+#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */
+#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */
+#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */
+#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */
+#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */
+#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */
+#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */
+#define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */
+#define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */
+#define PMC_PCSR1_PID52 (0x1u << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */
+#define PMC_PCSR1_PID53 (0x1u << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */
+#define PMC_PCSR1_PID54 (0x1u << 22) /**< \brief (PMC_PCSR1) Peripheral Clock 54 Status */
+#define PMC_PCSR1_PID55 (0x1u << 23) /**< \brief (PMC_PCSR1) Peripheral Clock 55 Status */
+#define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */
+#define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */
+#define PMC_PCSR1_PID58 (0x1u << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */
+#define PMC_PCSR1_PID59 (0x1u << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */
+#define PMC_PCSR1_PID60 (0x1u << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */
+#define PMC_PCSR1_PID61 (0x1u << 29) /**< \brief (PMC_PCSR1) Peripheral Clock 61 Status */
+#define PMC_PCSR1_PID62 (0x1u << 30) /**< \brief (PMC_PCSR1) Peripheral Clock 62 Status */
+#define PMC_PCSR1_PID63 (0x1u << 31) /**< \brief (PMC_PCSR1) Peripheral Clock 63 Status */
+/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */
+#define PMC_PCR_PID_Pos 0
+#define PMC_PCR_PID_Msk (0x7fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */
+#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)))
+#define PMC_PCR_GCKCSS_Pos 8
+#define PMC_PCR_GCKCSS_Msk (0x7u << PMC_PCR_GCKCSS_Pos) /**< \brief (PMC_PCR) GCK Clock Source Selection */
+#define PMC_PCR_GCKCSS(value) ((PMC_PCR_GCKCSS_Msk & ((value) << PMC_PCR_GCKCSS_Pos)))
+#define   PMC_PCR_GCKCSS_SLOW_CLK (0x0u << 8) /**< \brief (PMC_PCR) Slow clock is selected */
+#define   PMC_PCR_GCKCSS_MAIN_CLK (0x1u << 8) /**< \brief (PMC_PCR) Main clock is selected */
+#define   PMC_PCR_GCKCSS_PLLA_CLK (0x2u << 8) /**< \brief (PMC_PCR) PLLACK is selected */
+#define   PMC_PCR_GCKCSS_UPLL_CLK (0x3u << 8) /**< \brief (PMC_PCR) UPLL Clock is selected */
+#define   PMC_PCR_GCKCSS_MCK_CLK (0x4u << 8) /**< \brief (PMC_PCR) Master Clock is selected */
+#define   PMC_PCR_GCKCSS_AUDIO_CLK (0x5u << 8) /**< \brief (PMC_PCR) Audio PLL clock is selected */
+#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */
+#define PMC_PCR_GCKDIV_Pos 20
+#define PMC_PCR_GCKDIV_Msk (0xffu << PMC_PCR_GCKDIV_Pos) /**< \brief (PMC_PCR) Generated Clock Division Ratio */
+#define PMC_PCR_GCKDIV(value) ((PMC_PCR_GCKDIV_Msk & ((value) << PMC_PCR_GCKDIV_Pos)))
+#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */
+#define PMC_PCR_GCKEN (0x1u << 29) /**< \brief (PMC_PCR) GCK Enable */
+/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */
+#define PMC_OCR_CAL_Pos 0
+#define PMC_OCR_CAL_Msk (0x7fu << PMC_OCR_CAL_Pos) /**< \brief (PMC_OCR) 12 MHz RC Oscillator Calibration Bits */
+#define PMC_OCR_CAL(value) ((PMC_OCR_CAL_Msk & ((value) << PMC_OCR_CAL_Pos)))
+#define PMC_OCR_SEL (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration Bits */
+/* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x0144) SleepWalking Activity In Progress Register -------- */
+#define PMC_SLPWK_AIPR_AIP (0x1u << 0) /**< \brief (PMC_SLPWK_AIPR) Activity In Progress */
+/* -------- PMC_SLPWKCR : (PMC Offset: 0x0148) SleepWalking Control Register -------- */
+#define PMC_SLPWKCR_PID_Pos 0
+#define PMC_SLPWKCR_PID_Msk (0x7fu << PMC_SLPWKCR_PID_Pos) /**< \brief (PMC_SLPWKCR) Peripheral ID */
+#define PMC_SLPWKCR_PID(value) ((PMC_SLPWKCR_PID_Msk & ((value) << PMC_SLPWKCR_PID_Pos)))
+#define PMC_SLPWKCR_CMD (0x1u << 12) /**< \brief (PMC_SLPWKCR) Command */
+#define PMC_SLPWKCR_ASR (0x1u << 16) /**< \brief (PMC_SLPWKCR) Activity Status Register */
+#define PMC_SLPWKCR_SLPWKSR (0x1u << 28) /**< \brief (PMC_SLPWKCR) SleepWalking Status Register */
+/* -------- PMC_AUDIO_PLL0 : (PMC Offset: 0x014C) Audio PLL Register 0 -------- */
+#define PMC_AUDIO_PLL0_PLLEN (0x1u << 0) /**< \brief (PMC_AUDIO_PLL0) PLL Enable */
+#define PMC_AUDIO_PLL0_PADEN (0x1u << 1) /**< \brief (PMC_AUDIO_PLL0) Pad Clock Enable */
+#define PMC_AUDIO_PLL0_PMCEN (0x1u << 2) /**< \brief (PMC_AUDIO_PLL0) PMC Clock Enable */
+#define PMC_AUDIO_PLL0_RESETN (0x1u << 3) /**< \brief (PMC_AUDIO_PLL0) Audio PLL Reset */
+#define PMC_AUDIO_PLL0_PLLFLT_Pos 4
+#define PMC_AUDIO_PLL0_PLLFLT_Msk (0xfu << PMC_AUDIO_PLL0_PLLFLT_Pos) /**< \brief (PMC_AUDIO_PLL0) PLL Loop Filter Selection */
+#define PMC_AUDIO_PLL0_PLLFLT(value) ((PMC_AUDIO_PLL0_PLLFLT_Msk & ((value) << PMC_AUDIO_PLL0_PLLFLT_Pos)))
+#define   PMC_AUDIO_PLL0_PLLFLT_STD (0xdu << 4) /**< \brief (PMC_AUDIO_PLL0) Recommended value */
+#define PMC_AUDIO_PLL0_ND_Pos 8
+#define PMC_AUDIO_PLL0_ND_Msk (0x7fu << PMC_AUDIO_PLL0_ND_Pos) /**< \brief (PMC_AUDIO_PLL0) Loop Divider Ratio */
+#define PMC_AUDIO_PLL0_ND(value) ((PMC_AUDIO_PLL0_ND_Msk & ((value) << PMC_AUDIO_PLL0_ND_Pos)))
+#define PMC_AUDIO_PLL0_QDPMC_Pos 16
+#define PMC_AUDIO_PLL0_QDPMC_Msk (0x7fu << PMC_AUDIO_PLL0_QDPMC_Pos) /**< \brief (PMC_AUDIO_PLL0) Output Divider Ratio for PMC Clock */
+#define PMC_AUDIO_PLL0_QDPMC(value) ((PMC_AUDIO_PLL0_QDPMC_Msk & ((value) << PMC_AUDIO_PLL0_QDPMC_Pos)))
+#define PMC_AUDIO_PLL0_DCOFLT_Pos 24
+#define PMC_AUDIO_PLL0_DCOFLT_Msk (0xfu << PMC_AUDIO_PLL0_DCOFLT_Pos) /**< \brief (PMC_AUDIO_PLL0) Digitally Controlled Oscillator Filter Selection */
+#define PMC_AUDIO_PLL0_DCOFLT(value) ((PMC_AUDIO_PLL0_DCOFLT_Msk & ((value) << PMC_AUDIO_PLL0_DCOFLT_Pos)))
+#define PMC_AUDIO_PLL0_DCOGAIN_Pos 28
+#define PMC_AUDIO_PLL0_DCOGAIN_Msk (0x3u << PMC_AUDIO_PLL0_DCOGAIN_Pos) /**< \brief (PMC_AUDIO_PLL0) Digitally Controlled Oscillator Gain Selection */
+#define PMC_AUDIO_PLL0_DCOGAIN(value) ((PMC_AUDIO_PLL0_DCOGAIN_Msk & ((value) << PMC_AUDIO_PLL0_DCOGAIN_Pos)))
+#define   PMC_AUDIO_PLL0_DCOGAIN_STD (0x0u << 28) /**< \brief (PMC_AUDIO_PLL0) Default */
+#define   PMC_AUDIO_PLL0_DCOGAIN_MAX (0x1u << 28) /**< \brief (PMC_AUDIO_PLL0) Maximum */
+#define   PMC_AUDIO_PLL0_DCOGAIN_MIN (0x2u << 28) /**< \brief (PMC_AUDIO_PLL0) Minimum */
+#define   PMC_AUDIO_PLL0_DCOGAIN_HIGH (0x3u << 28) /**< \brief (PMC_AUDIO_PLL0) High */
+/* -------- PMC_AUDIO_PLL1 : (PMC Offset: 0x0150) Audio PLL Register 1 -------- */
+#define PMC_AUDIO_PLL1_FRACR_Pos 0
+#define PMC_AUDIO_PLL1_FRACR_Msk (0x3fffffu << PMC_AUDIO_PLL1_FRACR_Pos) /**< \brief (PMC_AUDIO_PLL1) Fractional Loop Divider Setting */
+#define PMC_AUDIO_PLL1_FRACR(value) ((PMC_AUDIO_PLL1_FRACR_Msk & ((value) << PMC_AUDIO_PLL1_FRACR_Pos)))
+#define PMC_AUDIO_PLL1_DIV_Pos 24
+#define PMC_AUDIO_PLL1_DIV_Msk (0x3u << PMC_AUDIO_PLL1_DIV_Pos) /**< \brief (PMC_AUDIO_PLL1) Divider Value */
+#define PMC_AUDIO_PLL1_DIV(value) ((PMC_AUDIO_PLL1_DIV_Msk & ((value) << PMC_AUDIO_PLL1_DIV_Pos)))
+#define PMC_AUDIO_PLL1_QDAUDIO_Pos 26
+#define PMC_AUDIO_PLL1_QDAUDIO_Msk (0x1fu << PMC_AUDIO_PLL1_QDAUDIO_Pos) /**< \brief (PMC_AUDIO_PLL1) Output Divider Ratio for Pad Clock */
+#define PMC_AUDIO_PLL1_QDAUDIO(value) ((PMC_AUDIO_PLL1_QDAUDIO_Msk & ((value) << PMC_AUDIO_PLL1_QDAUDIO_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_PMC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_pwm.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_pwm.h
new file mode 100644
index 000000000..eb19ab435
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_pwm.h
@@ -0,0 +1,651 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_PWM_COMPONENT_
+#define _SAMA5D2_PWM_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_PWM Pulse Width Modulation Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief PwmCh_num hardware registers */
+typedef struct {
+  __IO uint32_t PWM_CMR;     /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
+  __IO uint32_t PWM_CDTY;    /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
+  __O  uint32_t PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */
+  __IO uint32_t PWM_CPRD;    /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */
+  __O  uint32_t PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */
+  __I  uint32_t PWM_CCNT;    /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */
+  __IO uint32_t PWM_DT;      /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */
+  __O  uint32_t PWM_DTUPD;   /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */
+} PwmCh_num;
+/** \brief PwmCmp hardware registers */
+typedef struct {
+  __IO uint32_t PWM_CMPV;    /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */
+  __O  uint32_t PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */
+  __IO uint32_t PWM_CMPM;    /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */
+  __O  uint32_t PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */
+} PwmCmp;
+/** \brief Pwm hardware registers */
+#define PWMCMP_NUMBER 8
+#define PWMCH_NUM_NUMBER 4
+typedef struct {
+  __IO uint32_t  PWM_CLK;                      /**< \brief (Pwm Offset: 0x00) PWM Clock Register */
+  __O  uint32_t  PWM_ENA;                      /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
+  __O  uint32_t  PWM_DIS;                      /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
+  __I  uint32_t  PWM_SR;                       /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
+  __O  uint32_t  PWM_IER1;                     /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */
+  __O  uint32_t  PWM_IDR1;                     /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */
+  __I  uint32_t  PWM_IMR1;                     /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */
+  __I  uint32_t  PWM_ISR1;                     /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */
+  __IO uint32_t  PWM_SCM;                      /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */
+  __O  uint32_t  PWM_DMAR;                     /**< \brief (Pwm Offset: 0x24) PWM DMA Register */
+  __IO uint32_t  PWM_SCUC;                     /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */
+  __IO uint32_t  PWM_SCUP;                     /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */
+  __O  uint32_t  PWM_SCUPUPD;                  /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */
+  __O  uint32_t  PWM_IER2;                     /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */
+  __O  uint32_t  PWM_IDR2;                     /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */
+  __I  uint32_t  PWM_IMR2;                     /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */
+  __I  uint32_t  PWM_ISR2;                     /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */
+  __IO uint32_t  PWM_OOV;                      /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */
+  __IO uint32_t  PWM_OS;                       /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */
+  __O  uint32_t  PWM_OSS;                      /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */
+  __O  uint32_t  PWM_OSC;                      /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */
+  __O  uint32_t  PWM_OSSUPD;                   /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */
+  __O  uint32_t  PWM_OSCUPD;                   /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */
+  __IO uint32_t  PWM_FMR;                      /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */
+  __I  uint32_t  PWM_FSR;                      /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */
+  __O  uint32_t  PWM_FCR;                      /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */
+  __IO uint32_t  PWM_FPV1;                     /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register 1 */
+  __IO uint32_t  PWM_FPE;                      /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */
+  __I  uint32_t  Reserved1[3];
+  __IO uint32_t  PWM_ELMR[2];                  /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */
+  __I  uint32_t  Reserved2[7];
+  __IO uint32_t  PWM_SSPR;                     /**< \brief (Pwm Offset: 0xA0) PWM Spread Spectrum Register */
+  __O  uint32_t  PWM_SSPUP;                    /**< \brief (Pwm Offset: 0xA4) PWM Spread Spectrum Update Register */
+  __I  uint32_t  Reserved3[2];
+  __IO uint32_t  PWM_SMMR;                     /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */
+  __I  uint32_t  Reserved4[3];
+  __IO uint32_t  PWM_FPV2;                     /**< \brief (Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register */
+  __I  uint32_t  Reserved5[8];
+  __O  uint32_t  PWM_WPCR;                     /**< \brief (Pwm Offset: 0xE4) PWM Write Protection Control Register */
+  __I  uint32_t  PWM_WPSR;                     /**< \brief (Pwm Offset: 0xE8) PWM Write Protection Status Register */
+  __I  uint32_t  Reserved6[4];
+  __I  uint32_t  PWM_VERSION;                  /**< \brief (Pwm Offset: 0xFC) Version Register */
+  __I  uint32_t  Reserved7[12];
+       PwmCmp    PWM_CMP[PWMCMP_NUMBER];       /**< \brief (Pwm Offset: 0x130) 0 .. 7 */
+  __I  uint32_t  Reserved8[20];
+       PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */
+  __I  uint32_t  Reserved9[96];
+  __O  uint32_t  PWM_CMUPD0;                   /**< \brief (Pwm Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) */
+  __I  uint32_t  Reserved10[7];
+  __O  uint32_t  PWM_CMUPD1;                   /**< \brief (Pwm Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) */
+  __I  uint32_t  Reserved11[2];
+  __IO uint32_t  PWM_ETRG1;                    /**< \brief (Pwm Offset: 0x42C) PWM External Trigger Register (trg_num = 1) */
+  __IO uint32_t  PWM_LEBR1;                    /**< \brief (Pwm Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) */
+  __I  uint32_t  Reserved12[3];
+  __O  uint32_t  PWM_CMUPD2;                   /**< \brief (Pwm Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) */
+  __I  uint32_t  Reserved13[2];
+  __IO uint32_t  PWM_ETRG2;                    /**< \brief (Pwm Offset: 0x44C) PWM External Trigger Register (trg_num = 2) */
+  __IO uint32_t  PWM_LEBR2;                    /**< \brief (Pwm Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) */
+  __I  uint32_t  Reserved14[3];
+  __O  uint32_t  PWM_CMUPD3;                   /**< \brief (Pwm Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) */
+} Pwm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
+#define PWM_CLK_DIVA_Pos 0
+#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA Divide Factor */
+#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
+#define   PWM_CLK_DIVA_CLKA_POFF (0x0u << 0) /**< \brief (PWM_CLK) CLKA clock is turned off */
+#define   PWM_CLK_DIVA_PREA (0x1u << 0) /**< \brief (PWM_CLK) CLKA clock is clock selected by PREA */
+#define PWM_CLK_PREA_Pos 8
+#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA Source Clock Selection */
+#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
+#define   PWM_CLK_PREA_CLK (0x0u << 8) /**< \brief (PWM_CLK) Peripheral clock */
+#define   PWM_CLK_PREA_CLK_DIV2 (0x1u << 8) /**< \brief (PWM_CLK) Peripheral clock/2 */
+#define   PWM_CLK_PREA_CLK_DIV4 (0x2u << 8) /**< \brief (PWM_CLK) Peripheral clock/4 */
+#define   PWM_CLK_PREA_CLK_DIV8 (0x3u << 8) /**< \brief (PWM_CLK) Peripheral clock/8 */
+#define   PWM_CLK_PREA_CLK_DIV16 (0x4u << 8) /**< \brief (PWM_CLK) Peripheral clock/16 */
+#define   PWM_CLK_PREA_CLK_DIV32 (0x5u << 8) /**< \brief (PWM_CLK) Peripheral clock/32 */
+#define   PWM_CLK_PREA_CLK_DIV64 (0x6u << 8) /**< \brief (PWM_CLK) Peripheral clock/64 */
+#define   PWM_CLK_PREA_CLK_DIV128 (0x7u << 8) /**< \brief (PWM_CLK) Peripheral clock/128 */
+#define   PWM_CLK_PREA_CLK_DIV256 (0x8u << 8) /**< \brief (PWM_CLK) Peripheral clock/256 */
+#define   PWM_CLK_PREA_CLK_DIV512 (0x9u << 8) /**< \brief (PWM_CLK) Peripheral clock/512 */
+#define   PWM_CLK_PREA_CLK_DIV1024 (0xAu << 8) /**< \brief (PWM_CLK) Peripheral clock/1024 */
+#define PWM_CLK_DIVB_Pos 16
+#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKB Divide Factor */
+#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
+#define   PWM_CLK_DIVB_CLKB_POFF (0x0u << 16) /**< \brief (PWM_CLK) CLKB clock is turned off */
+#define   PWM_CLK_DIVB_PREB (0x1u << 16) /**< \brief (PWM_CLK) CLKB clock is clock selected by PREB */
+#define PWM_CLK_PREB_Pos 24
+#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKB Source Clock Selection */
+#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
+#define   PWM_CLK_PREB_CLK (0x0u << 24) /**< \brief (PWM_CLK) Peripheral clock */
+#define   PWM_CLK_PREB_CLK_DIV2 (0x1u << 24) /**< \brief (PWM_CLK) Peripheral clock/2 */
+#define   PWM_CLK_PREB_CLK_DIV4 (0x2u << 24) /**< \brief (PWM_CLK) Peripheral clock/4 */
+#define   PWM_CLK_PREB_CLK_DIV8 (0x3u << 24) /**< \brief (PWM_CLK) Peripheral clock/8 */
+#define   PWM_CLK_PREB_CLK_DIV16 (0x4u << 24) /**< \brief (PWM_CLK) Peripheral clock/16 */
+#define   PWM_CLK_PREB_CLK_DIV32 (0x5u << 24) /**< \brief (PWM_CLK) Peripheral clock/32 */
+#define   PWM_CLK_PREB_CLK_DIV64 (0x6u << 24) /**< \brief (PWM_CLK) Peripheral clock/64 */
+#define   PWM_CLK_PREB_CLK_DIV128 (0x7u << 24) /**< \brief (PWM_CLK) Peripheral clock/128 */
+#define   PWM_CLK_PREB_CLK_DIV256 (0x8u << 24) /**< \brief (PWM_CLK) Peripheral clock/256 */
+#define   PWM_CLK_PREB_CLK_DIV512 (0x9u << 24) /**< \brief (PWM_CLK) Peripheral clock/512 */
+#define   PWM_CLK_PREB_CLK_DIV1024 (0xAu << 24) /**< \brief (PWM_CLK) Peripheral clock/1024 */
+/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
+#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
+/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
+#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
+/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
+#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
+/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
+#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */
+#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */
+#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */
+#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */
+#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */
+#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */
+#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */
+#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */
+/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
+#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */
+#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */
+#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */
+#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */
+#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */
+#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */
+#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */
+#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */
+/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
+#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */
+#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */
+#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */
+#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */
+#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */
+#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */
+#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */
+#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */
+/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
+#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */
+#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */
+#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */
+#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */
+#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */
+#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */
+#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */
+#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */
+/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
+#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */
+#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */
+#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */
+#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */
+#define PWM_SCM_UPDM_Pos 16
+#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */
+#define PWM_SCM_UPDM(value) ((PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos)))
+#define   PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels */
+#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) DMA Controller Transfer Request Mode */
+#define PWM_SCM_PTRCS_Pos 21
+#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) DMA Controller Transfer Request Comparison Selection */
+#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
+/* -------- PWM_DMAR : (PWM Offset: 0x24) PWM DMA Register -------- */
+#define PWM_DMAR_DMADUTY_Pos 0
+#define PWM_DMAR_DMADUTY_Msk (0xffffffu << PWM_DMAR_DMADUTY_Pos) /**< \brief (PWM_DMAR) Duty-Cycle Holding Register for DMA Access */
+#define PWM_DMAR_DMADUTY(value) ((PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos)))
+/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
+#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */
+/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
+#define PWM_SCUP_UPR_Pos 0
+#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */
+#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
+#define PWM_SCUP_UPRCNT_Pos 4
+#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */
+#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
+/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
+#define PWM_SCUPUPD_UPRUPD_Pos 0
+#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */
+#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
+/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
+#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */
+#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */
+#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */
+#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */
+#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */
+#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */
+#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */
+#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */
+#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */
+#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */
+#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */
+#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */
+#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */
+#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */
+#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */
+#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */
+#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */
+#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */
+/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
+#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */
+#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */
+#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */
+#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */
+#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */
+#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */
+#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */
+#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */
+#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */
+#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */
+#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */
+#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */
+#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */
+#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */
+#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */
+#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */
+#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */
+#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */
+/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
+#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */
+#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */
+#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */
+#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */
+#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */
+#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */
+#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */
+#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */
+#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */
+#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */
+#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */
+#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */
+#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */
+#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */
+#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */
+#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */
+#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */
+#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */
+/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
+#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */
+#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */
+#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */
+#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */
+#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */
+#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */
+#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */
+#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */
+#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */
+#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */
+#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */
+#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */
+#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */
+#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */
+#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */
+#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */
+#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */
+#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */
+/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
+#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */
+#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */
+#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */
+#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */
+#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */
+#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */
+#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */
+#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */
+/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
+#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */
+#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */
+#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */
+#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */
+#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */
+#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */
+#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */
+#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */
+/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
+#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */
+/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
+#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */
+/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
+#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */
+/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
+#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */
+/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
+#define PWM_FMR_FPOL_Pos 0
+#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity */
+#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
+#define PWM_FMR_FMOD_Pos 8
+#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode */
+#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
+#define PWM_FMR_FFIL_Pos 16
+#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering */
+#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
+/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
+#define PWM_FSR_FIV_Pos 0
+#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value */
+#define PWM_FSR_FS_Pos 8
+#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status */
+/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
+#define PWM_FCR_FCLR_Pos 0
+#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear */
+#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
+/* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */
+#define PWM_FPV1_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 */
+#define PWM_FPV1_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 */
+#define PWM_FPV1_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 */
+#define PWM_FPV1_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 */
+#define PWM_FPV1_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 0 */
+#define PWM_FPV1_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 1 */
+#define PWM_FPV1_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 2 */
+#define PWM_FPV1_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 3 */
+/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */
+#define PWM_FPE_FPE0_Pos 0
+#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 */
+#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))
+#define PWM_FPE_FPE1_Pos 8
+#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 */
+#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))
+#define PWM_FPE_FPE2_Pos 16
+#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 */
+#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))
+#define PWM_FPE_FPE3_Pos 24
+#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 */
+#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))
+/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
+#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */
+#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */
+#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */
+#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */
+#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */
+#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */
+#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */
+#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */
+/* -------- PWM_SSPR : (PWM Offset: 0xA0) PWM Spread Spectrum Register -------- */
+#define PWM_SSPR_SPRD_Pos 0
+#define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos) /**< \brief (PWM_SSPR) Spread Spectrum Limit Value */
+#define PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos)))
+#define PWM_SSPR_SPRDM (0x1u << 24) /**< \brief (PWM_SSPR) Spread Spectrum Counter Mode */
+/* -------- PWM_SSPUP : (PWM Offset: 0xA4) PWM Spread Spectrum Update Register -------- */
+#define PWM_SSPUP_SPRDUP_Pos 0
+#define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos) /**< \brief (PWM_SSPUP) Spread Spectrum Limit Value Update */
+#define PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos)))
+/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */
+#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */
+#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */
+/* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */
+#define PWM_FPV2_FPZH0 (0x1u << 0) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 */
+#define PWM_FPV2_FPZH1 (0x1u << 1) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 */
+#define PWM_FPV2_FPZH2 (0x1u << 2) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 */
+#define PWM_FPV2_FPZH3 (0x1u << 3) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 */
+#define PWM_FPV2_FPZL0 (0x1u << 16) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 */
+#define PWM_FPV2_FPZL1 (0x1u << 17) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 */
+#define PWM_FPV2_FPZL2 (0x1u << 18) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 */
+#define PWM_FPV2_FPZL3 (0x1u << 19) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 */
+/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protection Control Register -------- */
+#define PWM_WPCR_WPCMD_Pos 0
+#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protection Command */
+#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
+#define   PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0) /**< \brief (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. */
+#define   PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0) /**< \brief (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. */
+#define   PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0) /**< \brief (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. */
+#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protection Register Group 0 */
+#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protection Register Group 1 */
+#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protection Register Group 2 */
+#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protection Register Group 3 */
+#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protection Register Group 4 */
+#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protection Register Group 5 */
+#define PWM_WPCR_WPKEY_Pos 8
+#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protection Key */
+#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
+#define   PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8) /**< \brief (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 */
+/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protection Status Register -------- */
+#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */
+#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPVSRC_Pos 16
+#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */
+/* -------- PWM_VERSION : (PWM Offset: 0xFC) Version Register -------- */
+#define PWM_VERSION_VERSION_Pos 0
+#define PWM_VERSION_VERSION_Msk (0xfffu << PWM_VERSION_VERSION_Pos) /**< \brief (PWM_VERSION) Version of the Hardware Module */
+#define PWM_VERSION_MFN_Pos 16
+#define PWM_VERSION_MFN_Msk (0x7u << PWM_VERSION_MFN_Pos) /**< \brief (PWM_VERSION) Metal Fix Number */
+/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
+#define PWM_CMPV_CV_Pos 0
+#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */
+#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
+#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */
+/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
+#define PWM_CMPVUPD_CVUPD_Pos 0
+#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */
+#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
+#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */
+/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
+#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */
+#define PWM_CMPM_CTR_Pos 4
+#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */
+#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
+#define PWM_CMPM_CPR_Pos 8
+#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */
+#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
+#define PWM_CMPM_CPRCNT_Pos 12
+#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */
+#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
+#define PWM_CMPM_CUPR_Pos 16
+#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */
+#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
+#define PWM_CMPM_CUPRCNT_Pos 20
+#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */
+#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
+/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
+#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */
+#define PWM_CMPMUPD_CTRUPD_Pos 4
+#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */
+#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
+#define PWM_CMPMUPD_CPRUPD_Pos 8
+#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */
+#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
+#define PWM_CMPMUPD_CUPRUPD_Pos 16
+#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */
+#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
+/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
+#define PWM_CMR_CPRE_Pos 0
+#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
+#define PWM_CMR_CPRE(value) ((PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos)))
+#define   PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Peripheral clock */
+#define   PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Peripheral clock/2 */
+#define   PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Peripheral clock/4 */
+#define   PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Peripheral clock/8 */
+#define   PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Peripheral clock/16 */
+#define   PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Peripheral clock/32 */
+#define   PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Peripheral clock/64 */
+#define   PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Peripheral clock/128 */
+#define   PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Peripheral clock/256 */
+#define   PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Peripheral clock/512 */
+#define   PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Peripheral clock/1024 */
+#define   PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
+#define   PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
+#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
+#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
+#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */
+#define PWM_CMR_UPDS (0x1u << 11) /**< \brief (PWM_CMR) Update Selection */
+#define PWM_CMR_DPOLI (0x1u << 12) /**< \brief (PWM_CMR) Disabled Polarity Inverted */
+#define PWM_CMR_TCTS (0x1u << 13) /**< \brief (PWM_CMR) Timer Counter Trigger Selection */
+#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */
+#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */
+#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */
+#define PWM_CMR_PPM (0x1u << 19) /**< \brief (PWM_CMR) Push-Pull Mode */
+/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
+#define PWM_CDTY_CDTY_Pos 0
+#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */
+#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
+/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
+#define PWM_CDTYUPD_CDTYUPD_Pos 0
+#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */
+#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
+/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
+#define PWM_CPRD_CPRD_Pos 0
+#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
+#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
+/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
+#define PWM_CPRDUPD_CPRDUPD_Pos 0
+#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */
+#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
+/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
+#define PWM_CCNT_CNT_Pos 0
+#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
+/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
+#define PWM_DT_DTH_Pos 0
+#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */
+#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
+#define PWM_DT_DTL_Pos 16
+#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */
+#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
+/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
+#define PWM_DTUPD_DTHUPD_Pos 0
+#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */
+#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
+#define PWM_DTUPD_DTLUPD_Pos 16
+#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */
+#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))
+/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) -------- */
+#define PWM_CMUPD0_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD0) Channel Polarity Update */
+#define PWM_CMUPD0_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD0) Channel Polarity Inversion Update */
+/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) -------- */
+#define PWM_CMUPD1_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD1) Channel Polarity Update */
+#define PWM_CMUPD1_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD1) Channel Polarity Inversion Update */
+/* -------- PWM_ETRG1 : (PWM Offset: 0x42C) PWM External Trigger Register (trg_num = 1) -------- */
+#define PWM_ETRG1_MAXCNT_Pos 0
+#define PWM_ETRG1_MAXCNT_Msk (0xffffffu << PWM_ETRG1_MAXCNT_Pos) /**< \brief (PWM_ETRG1) Maximum Counter value */
+#define PWM_ETRG1_MAXCNT(value) ((PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos)))
+#define PWM_ETRG1_TRGMODE_Pos 24
+#define PWM_ETRG1_TRGMODE_Msk (0x3u << PWM_ETRG1_TRGMODE_Pos) /**< \brief (PWM_ETRG1) External Trigger Mode */
+#define PWM_ETRG1_TRGMODE(value) ((PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos)))
+#define   PWM_ETRG1_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG1) External trigger is not enabled. */
+#define   PWM_ETRG1_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG1) External PWM Reset Mode */
+#define   PWM_ETRG1_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG1) External PWM Start Mode */
+#define   PWM_ETRG1_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG1) Cycle-by-cycle Duty Mode */
+#define PWM_ETRG1_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG1) Edge Selection */
+#define   PWM_ETRG1_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */
+#define   PWM_ETRG1_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */
+#define PWM_ETRG1_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG1) Filtered input */
+#define PWM_ETRG1_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG1) Trigger Source */
+#define PWM_ETRG1_RFEN (0x1u << 31) /**< \brief (PWM_ETRG1) Recoverable Fault Enable */
+/* -------- PWM_LEBR1 : (PWM Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */
+#define PWM_LEBR1_LEBDELAY_Pos 0
+#define PWM_LEBR1_LEBDELAY_Msk (0x7fu << PWM_LEBR1_LEBDELAY_Pos) /**< \brief (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx */
+#define PWM_LEBR1_LEBDELAY(value) ((PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos)))
+#define PWM_LEBR1_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR1) PWML Falling Edge Enable */
+#define PWM_LEBR1_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR1) PWML Rising Edge Enable */
+#define PWM_LEBR1_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR1) PWMH Falling Edge Enable */
+#define PWM_LEBR1_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR1) PWMH Rising Edge Enable */
+/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) -------- */
+#define PWM_CMUPD2_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD2) Channel Polarity Update */
+#define PWM_CMUPD2_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD2) Channel Polarity Inversion Update */
+/* -------- PWM_ETRG2 : (PWM Offset: 0x44C) PWM External Trigger Register (trg_num = 2) -------- */
+#define PWM_ETRG2_MAXCNT_Pos 0
+#define PWM_ETRG2_MAXCNT_Msk (0xffffffu << PWM_ETRG2_MAXCNT_Pos) /**< \brief (PWM_ETRG2) Maximum Counter value */
+#define PWM_ETRG2_MAXCNT(value) ((PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos)))
+#define PWM_ETRG2_TRGMODE_Pos 24
+#define PWM_ETRG2_TRGMODE_Msk (0x3u << PWM_ETRG2_TRGMODE_Pos) /**< \brief (PWM_ETRG2) External Trigger Mode */
+#define PWM_ETRG2_TRGMODE(value) ((PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos)))
+#define   PWM_ETRG2_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG2) External trigger is not enabled. */
+#define   PWM_ETRG2_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG2) External PWM Reset Mode */
+#define   PWM_ETRG2_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG2) External PWM Start Mode */
+#define   PWM_ETRG2_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG2) Cycle-by-cycle Duty Mode */
+#define PWM_ETRG2_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG2) Edge Selection */
+#define   PWM_ETRG2_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */
+#define   PWM_ETRG2_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */
+#define PWM_ETRG2_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG2) Filtered input */
+#define PWM_ETRG2_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG2) Trigger Source */
+#define PWM_ETRG2_RFEN (0x1u << 31) /**< \brief (PWM_ETRG2) Recoverable Fault Enable */
+/* -------- PWM_LEBR2 : (PWM Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */
+#define PWM_LEBR2_LEBDELAY_Pos 0
+#define PWM_LEBR2_LEBDELAY_Msk (0x7fu << PWM_LEBR2_LEBDELAY_Pos) /**< \brief (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx */
+#define PWM_LEBR2_LEBDELAY(value) ((PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos)))
+#define PWM_LEBR2_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR2) PWML Falling Edge Enable */
+#define PWM_LEBR2_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR2) PWML Rising Edge Enable */
+#define PWM_LEBR2_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR2) PWMH Falling Edge Enable */
+#define PWM_LEBR2_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR2) PWMH Rising Edge Enable */
+/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) -------- */
+#define PWM_CMUPD3_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD3) Channel Polarity Update */
+#define PWM_CMUPD3_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD3) Channel Polarity Inversion Update */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_PWM_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_qspi.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_qspi.h
new file mode 100644
index 000000000..6f6d65a0a
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_qspi.h
@@ -0,0 +1,224 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_QSPI_COMPONENT_
+#define _SAMA5D2_QSPI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Quad Serial Peripheral Interface */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_QSPI Quad Serial Peripheral Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Qspi hardware registers */
+typedef struct {
+  __O  uint32_t QSPI_CR;       /**< \brief (Qspi Offset: 0x00) Control Register */
+  __IO uint32_t QSPI_MR;       /**< \brief (Qspi Offset: 0x04) Mode Register */
+  __I  uint32_t QSPI_RDR;      /**< \brief (Qspi Offset: 0x08) Receive Data Register */
+  __O  uint32_t QSPI_TDR;      /**< \brief (Qspi Offset: 0x0C) Transmit Data Register */
+  __I  uint32_t QSPI_SR;       /**< \brief (Qspi Offset: 0x10) Status Register */
+  __O  uint32_t QSPI_IER;      /**< \brief (Qspi Offset: 0x14) Interrupt Enable Register */
+  __O  uint32_t QSPI_IDR;      /**< \brief (Qspi Offset: 0x18) Interrupt Disable Register */
+  __I  uint32_t QSPI_IMR;      /**< \brief (Qspi Offset: 0x1C) Interrupt Mask Register */
+  __IO uint32_t QSPI_SCR;      /**< \brief (Qspi Offset: 0x20) Serial Clock Register */
+  __I  uint32_t Reserved1[3];
+  __IO uint32_t QSPI_IAR;      /**< \brief (Qspi Offset: 0x30) Instruction Address Register */
+  __IO uint32_t QSPI_ICR;      /**< \brief (Qspi Offset: 0x34) Instruction Code Register */
+  __IO uint32_t QSPI_IFR;      /**< \brief (Qspi Offset: 0x38) Instruction Frame Register */
+  __I  uint32_t Reserved2[1];
+  __IO uint32_t QSPI_SMR;      /**< \brief (Qspi Offset: 0x40) Scrambling Mode Register */
+  __O  uint32_t QSPI_SKR;      /**< \brief (Qspi Offset: 0x44) Scrambling Key Register */
+  __I  uint32_t Reserved3[39];
+  __IO uint32_t QSPI_WPMR;     /**< \brief (Qspi Offset: 0xE4) Write Protection Mode Register */
+  __I  uint32_t QSPI_WPSR;     /**< \brief (Qspi Offset: 0xE8) Write Protection Status Register */
+  __I  uint32_t Reserved4[4];
+  __I  uint32_t QSPI_VERSION;  /**< \brief (Qspi Offset: 0x00FC) Version Register */
+} Qspi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- QSPI_CR : (QSPI Offset: 0x00) Control Register -------- */
+#define QSPI_CR_QSPIEN (0x1u << 0) /**< \brief (QSPI_CR) QSPI Enable */
+#define QSPI_CR_QSPIDIS (0x1u << 1) /**< \brief (QSPI_CR) QSPI Disable */
+#define QSPI_CR_SWRST (0x1u << 7) /**< \brief (QSPI_CR) QSPI Software Reset */
+#define QSPI_CR_LASTXFER (0x1u << 24) /**< \brief (QSPI_CR) Last Transfer */
+/* -------- QSPI_MR : (QSPI Offset: 0x04) Mode Register -------- */
+#define QSPI_MR_SMM (0x1u << 0) /**< \brief (QSPI_MR) Serial Memory Mode */
+#define   QSPI_MR_SMM_SPI (0x0u << 0) /**< \brief (QSPI_MR) The QSPI is in SPI mode. */
+#define   QSPI_MR_SMM_MEMORY (0x1u << 0) /**< \brief (QSPI_MR) The QSPI is in Serial Memory mode. */
+#define QSPI_MR_LLB (0x1u << 1) /**< \brief (QSPI_MR) Local Loopback Enable */
+#define   QSPI_MR_LLB_DISABLED (0x0u << 1) /**< \brief (QSPI_MR) Local loopback path disabled. */
+#define   QSPI_MR_LLB_ENABLED (0x1u << 1) /**< \brief (QSPI_MR) Local loopback path enabled. */
+#define QSPI_MR_WDRBT (0x1u << 2) /**< \brief (QSPI_MR) Wait Data Read Before Transfer */
+#define   QSPI_MR_WDRBT_DISABLED (0x0u << 2) /**< \brief (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. */
+#define   QSPI_MR_WDRBT_ENABLED (0x1u << 2) /**< \brief (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. */
+#define QSPI_MR_SMRM (0x1u << 3) /**< \brief (QSPI_MR) Serial Memory Register Mode */
+#define QSPI_MR_CSMODE_Pos 4
+#define QSPI_MR_CSMODE_Msk (0x3u << QSPI_MR_CSMODE_Pos) /**< \brief (QSPI_MR) Chip Select Mode */
+#define QSPI_MR_CSMODE(value) ((QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos)))
+#define   QSPI_MR_CSMODE_NOT_RELOADED (0x0u << 4) /**< \brief (QSPI_MR) The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. */
+#define   QSPI_MR_CSMODE_LASTXFER (0x1u << 4) /**< \brief (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. */
+#define   QSPI_MR_CSMODE_SYSTEMATICALLY (0x2u << 4) /**< \brief (QSPI_MR) The chip select is deasserted systematically after each transfer. */
+#define QSPI_MR_NBBITS_Pos 8
+#define QSPI_MR_NBBITS_Msk (0xfu << QSPI_MR_NBBITS_Pos) /**< \brief (QSPI_MR) Number Of Bits Per Transfer */
+#define QSPI_MR_NBBITS(value) ((QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos)))
+#define   QSPI_MR_NBBITS_8_BIT (0x0u << 8) /**< \brief (QSPI_MR) 8 bits for transfer */
+#define   QSPI_MR_NBBITS_16_BIT (0x8u << 8) /**< \brief (QSPI_MR) 16 bits for transfer */
+#define QSPI_MR_DLYBCT_Pos 16
+#define QSPI_MR_DLYBCT_Msk (0xffu << QSPI_MR_DLYBCT_Pos) /**< \brief (QSPI_MR) Delay Between Consecutive Transfers */
+#define QSPI_MR_DLYBCT(value) ((QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos)))
+#define QSPI_MR_DLYCS_Pos 24
+#define QSPI_MR_DLYCS_Msk (0xffu << QSPI_MR_DLYCS_Pos) /**< \brief (QSPI_MR) Minimum Inactive QCS Delay */
+#define QSPI_MR_DLYCS(value) ((QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos)))
+/* -------- QSPI_RDR : (QSPI Offset: 0x08) Receive Data Register -------- */
+#define QSPI_RDR_RD_Pos 0
+#define QSPI_RDR_RD_Msk (0xffffu << QSPI_RDR_RD_Pos) /**< \brief (QSPI_RDR) Receive Data */
+/* -------- QSPI_TDR : (QSPI Offset: 0x0C) Transmit Data Register -------- */
+#define QSPI_TDR_TD_Pos 0
+#define QSPI_TDR_TD_Msk (0xffffu << QSPI_TDR_TD_Pos) /**< \brief (QSPI_TDR) Transmit Data */
+#define QSPI_TDR_TD(value) ((QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos)))
+/* -------- QSPI_SR : (QSPI Offset: 0x10) Status Register -------- */
+#define QSPI_SR_RDRF (0x1u << 0) /**< \brief (QSPI_SR) Receive Data Register Full */
+#define QSPI_SR_TDRE (0x1u << 1) /**< \brief (QSPI_SR) Transmit Data Register Empty */
+#define QSPI_SR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_SR) Transmission Registers Empty */
+#define QSPI_SR_OVRES (0x1u << 3) /**< \brief (QSPI_SR) Overrun Error Status */
+#define QSPI_SR_CSR (0x1u << 8) /**< \brief (QSPI_SR) Chip Select Rise */
+#define QSPI_SR_CSS (0x1u << 9) /**< \brief (QSPI_SR) Chip Select Status */
+#define QSPI_SR_INSTRE (0x1u << 10) /**< \brief (QSPI_SR) Instruction End Status */
+#define QSPI_SR_QSPIENS (0x1u << 24) /**< \brief (QSPI_SR) QSPI Enable Status */
+/* -------- QSPI_IER : (QSPI Offset: 0x14) Interrupt Enable Register -------- */
+#define QSPI_IER_RDRF (0x1u << 0) /**< \brief (QSPI_IER) Receive Data Register Full Interrupt Enable */
+#define QSPI_IER_TDRE (0x1u << 1) /**< \brief (QSPI_IER) Transmit Data Register Empty Interrupt Enable */
+#define QSPI_IER_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IER) Transmission Registers Empty Enable */
+#define QSPI_IER_OVRES (0x1u << 3) /**< \brief (QSPI_IER) Overrun Error Interrupt Enable */
+#define QSPI_IER_CSR (0x1u << 8) /**< \brief (QSPI_IER) Chip Select Rise Interrupt Enable */
+#define QSPI_IER_CSS (0x1u << 9) /**< \brief (QSPI_IER) Chip Select Status Interrupt Enable */
+#define QSPI_IER_INSTRE (0x1u << 10) /**< \brief (QSPI_IER) Instruction End Interrupt Enable */
+/* -------- QSPI_IDR : (QSPI Offset: 0x18) Interrupt Disable Register -------- */
+#define QSPI_IDR_RDRF (0x1u << 0) /**< \brief (QSPI_IDR) Receive Data Register Full Interrupt Disable */
+#define QSPI_IDR_TDRE (0x1u << 1) /**< \brief (QSPI_IDR) Transmit Data Register Empty Interrupt Disable */
+#define QSPI_IDR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IDR) Transmission Registers Empty Disable */
+#define QSPI_IDR_OVRES (0x1u << 3) /**< \brief (QSPI_IDR) Overrun Error Interrupt Disable */
+#define QSPI_IDR_CSR (0x1u << 8) /**< \brief (QSPI_IDR) Chip Select Rise Interrupt Disable */
+#define QSPI_IDR_CSS (0x1u << 9) /**< \brief (QSPI_IDR) Chip Select Status Interrupt Disable */
+#define QSPI_IDR_INSTRE (0x1u << 10) /**< \brief (QSPI_IDR) Instruction End Interrupt Disable */
+/* -------- QSPI_IMR : (QSPI Offset: 0x1C) Interrupt Mask Register -------- */
+#define QSPI_IMR_RDRF (0x1u << 0) /**< \brief (QSPI_IMR) Receive Data Register Full Interrupt Mask */
+#define QSPI_IMR_TDRE (0x1u << 1) /**< \brief (QSPI_IMR) Transmit Data Register Empty Interrupt Mask */
+#define QSPI_IMR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IMR) Transmission Registers Empty Mask */
+#define QSPI_IMR_OVRES (0x1u << 3) /**< \brief (QSPI_IMR) Overrun Error Interrupt Mask */
+#define QSPI_IMR_CSR (0x1u << 8) /**< \brief (QSPI_IMR) Chip Select Rise Interrupt Mask */
+#define QSPI_IMR_CSS (0x1u << 9) /**< \brief (QSPI_IMR) Chip Select Status Interrupt Mask */
+#define QSPI_IMR_INSTRE (0x1u << 10) /**< \brief (QSPI_IMR) Instruction End Interrupt Mask */
+/* -------- QSPI_SCR : (QSPI Offset: 0x20) Serial Clock Register -------- */
+#define QSPI_SCR_CPOL (0x1u << 0) /**< \brief (QSPI_SCR) Clock Polarity */
+#define QSPI_SCR_CPHA (0x1u << 1) /**< \brief (QSPI_SCR) Clock Phase */
+#define QSPI_SCR_SCBR_Pos 8
+#define QSPI_SCR_SCBR_Msk (0xffu << QSPI_SCR_SCBR_Pos) /**< \brief (QSPI_SCR) Serial Clock Baud Rate */
+#define QSPI_SCR_SCBR(value) ((QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos)))
+#define QSPI_SCR_DLYBS_Pos 16
+#define QSPI_SCR_DLYBS_Msk (0xffu << QSPI_SCR_DLYBS_Pos) /**< \brief (QSPI_SCR) Delay Before QSCK */
+#define QSPI_SCR_DLYBS(value) ((QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos)))
+/* -------- QSPI_IAR : (QSPI Offset: 0x30) Instruction Address Register -------- */
+#define QSPI_IAR_ADDR_Pos 0
+#define QSPI_IAR_ADDR_Msk (0xffffffffu << QSPI_IAR_ADDR_Pos) /**< \brief (QSPI_IAR) Address */
+#define QSPI_IAR_ADDR(value) ((QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos)))
+/* -------- QSPI_ICR : (QSPI Offset: 0x34) Instruction Code Register -------- */
+#define QSPI_ICR_INST_Pos 0
+#define QSPI_ICR_INST_Msk (0xffu << QSPI_ICR_INST_Pos) /**< \brief (QSPI_ICR) Instruction Code */
+#define QSPI_ICR_INST(value) ((QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos)))
+#define QSPI_ICR_OPT_Pos 16
+#define QSPI_ICR_OPT_Msk (0xffu << QSPI_ICR_OPT_Pos) /**< \brief (QSPI_ICR) Option Code */
+#define QSPI_ICR_OPT(value) ((QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos)))
+/* -------- QSPI_IFR : (QSPI Offset: 0x38) Instruction Frame Register -------- */
+#define QSPI_IFR_WIDTH_Pos 0
+#define QSPI_IFR_WIDTH_Msk (0x7u << QSPI_IFR_WIDTH_Pos) /**< \brief (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data */
+#define QSPI_IFR_WIDTH(value) ((QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos)))
+#define   QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */
+#define   QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */
+#define   QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */
+#define   QSPI_IFR_WIDTH_DUAL_IO (0x3u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */
+#define   QSPI_IFR_WIDTH_QUAD_IO (0x4u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */
+#define   QSPI_IFR_WIDTH_DUAL_CMD (0x5u << 0) /**< \brief (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */
+#define   QSPI_IFR_WIDTH_QUAD_CMD (0x6u << 0) /**< \brief (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */
+#define QSPI_IFR_INSTEN (0x1u << 4) /**< \brief (QSPI_IFR) Instruction Enable */
+#define QSPI_IFR_ADDREN (0x1u << 5) /**< \brief (QSPI_IFR) Address Enable */
+#define QSPI_IFR_OPTEN (0x1u << 6) /**< \brief (QSPI_IFR) Option Enable */
+#define QSPI_IFR_DATAEN (0x1u << 7) /**< \brief (QSPI_IFR) Data Enable */
+#define QSPI_IFR_OPTL_Pos 8
+#define QSPI_IFR_OPTL_Msk (0x3u << QSPI_IFR_OPTL_Pos) /**< \brief (QSPI_IFR) Option Code Length */
+#define QSPI_IFR_OPTL(value) ((QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos)))
+#define   QSPI_IFR_OPTL_OPTION_1BIT (0x0u << 8) /**< \brief (QSPI_IFR) The option code is 1 bit long. */
+#define   QSPI_IFR_OPTL_OPTION_2BIT (0x1u << 8) /**< \brief (QSPI_IFR) The option code is 2 bits long. */
+#define   QSPI_IFR_OPTL_OPTION_4BIT (0x2u << 8) /**< \brief (QSPI_IFR) The option code is 4 bits long. */
+#define   QSPI_IFR_OPTL_OPTION_8BIT (0x3u << 8) /**< \brief (QSPI_IFR) The option code is 8 bits long. */
+#define QSPI_IFR_ADDRL (0x1u << 10) /**< \brief (QSPI_IFR) Address Length */
+#define   QSPI_IFR_ADDRL_24_BIT (0x0u << 10) /**< \brief (QSPI_IFR) The address is 24 bits long. */
+#define   QSPI_IFR_ADDRL_32_BIT (0x1u << 10) /**< \brief (QSPI_IFR) The address is 32 bits long. */
+#define QSPI_IFR_TFRTYP_Pos 12
+#define QSPI_IFR_TFRTYP_Msk (0x3u << QSPI_IFR_TFRTYP_Pos) /**< \brief (QSPI_IFR) Data Transfer Type */
+#define QSPI_IFR_TFRTYP(value) ((QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos)))
+#define   QSPI_IFR_TFRTYP_TRSFR_READ (0x0u << 12) /**< \brief (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. */
+#define   QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (0x1u << 12) /**< \brief (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. */
+#define   QSPI_IFR_TFRTYP_TRSFR_WRITE (0x2u << 12) /**< \brief (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. */
+#define   QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (0x3u << 12) /**< \brief (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. */
+#define QSPI_IFR_CRM (0x1u << 14) /**< \brief (QSPI_IFR) Continuous Read Mode */
+#define   QSPI_IFR_CRM_DISABLED (0x0u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is disabled. */
+#define   QSPI_IFR_CRM_ENABLED (0x1u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is enabled. */
+#define QSPI_IFR_NBDUM_Pos 16
+#define QSPI_IFR_NBDUM_Msk (0x1fu << QSPI_IFR_NBDUM_Pos) /**< \brief (QSPI_IFR) Number Of Dummy Cycles */
+#define QSPI_IFR_NBDUM(value) ((QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos)))
+/* -------- QSPI_SMR : (QSPI Offset: 0x40) Scrambling Mode Register -------- */
+#define QSPI_SMR_SCREN (0x1u << 0) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Enable */
+#define   QSPI_SMR_SCREN_DISABLED (0x0u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is disabled. */
+#define   QSPI_SMR_SCREN_ENABLED (0x1u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is enabled. */
+#define QSPI_SMR_RVDIS (0x1u << 1) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Random Value Disable */
+/* -------- QSPI_SKR : (QSPI Offset: 0x44) Scrambling Key Register -------- */
+#define QSPI_SKR_USRK_Pos 0
+#define QSPI_SKR_USRK_Msk (0xffffffffu << QSPI_SKR_USRK_Pos) /**< \brief (QSPI_SKR) Scrambling User Key */
+#define QSPI_SKR_USRK(value) ((QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos)))
+/* -------- QSPI_WPMR : (QSPI Offset: 0xE4) Write Protection Mode Register -------- */
+#define QSPI_WPMR_WPEN (0x1u << 0) /**< \brief (QSPI_WPMR) Write Protection Enable */
+#define QSPI_WPMR_WPKEY_Pos 8
+#define QSPI_WPMR_WPKEY_Msk (0xffffffu << QSPI_WPMR_WPKEY_Pos) /**< \brief (QSPI_WPMR) Write Protection Key */
+#define QSPI_WPMR_WPKEY(value) ((QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos)))
+#define   QSPI_WPMR_WPKEY_PASSWD (0x515350u << 8) /**< \brief (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
+/* -------- QSPI_WPSR : (QSPI Offset: 0xE8) Write Protection Status Register -------- */
+#define QSPI_WPSR_WPVS (0x1u << 0) /**< \brief (QSPI_WPSR) Write Protection Violation Status */
+#define QSPI_WPSR_WPVSRC_Pos 8
+#define QSPI_WPSR_WPVSRC_Msk (0xffu << QSPI_WPSR_WPVSRC_Pos) /**< \brief (QSPI_WPSR) Write Protection Violation Source */
+/* -------- QSPI_VERSION : (QSPI Offset: 0x00FC) Version Register -------- */
+#define QSPI_VERSION_VERSION_Pos 0
+#define QSPI_VERSION_VERSION_Msk (0xfffu << QSPI_VERSION_VERSION_Pos) /**< \brief (QSPI_VERSION) Hardware Module Version */
+#define QSPI_VERSION_MFN_Pos 16
+#define QSPI_VERSION_MFN_Msk (0x7u << QSPI_VERSION_MFN_Pos) /**< \brief (QSPI_VERSION) Metal Fix Number */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_QSPI_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_rstc.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_rstc.h
new file mode 100644
index 000000000..52a226c2f
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_rstc.h
@@ -0,0 +1,76 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_RSTC_COMPONENT_
+#define _SAMA5D2_RSTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Reset Controller */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_RSTC Reset Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rstc hardware registers */
+typedef struct {
+  __O  uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
+  __I  uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
+  __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
+} Rstc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
+#define RSTC_CR_KEY_Pos 24
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Write Access Password */
+#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
+#define   RSTC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_CR) Writing any other value in this field aborts the write operation.Always reads as 0. */
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
+#define RSTC_SR_RSTTYP_Pos 8
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
+#define   RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8) /**< \brief (RSTC_SR) Both VDDCORE and VDDBU rising */
+#define   RSTC_SR_RSTTYP_WKUP_RST (0x1u << 8) /**< \brief (RSTC_SR) VDDCORE rising */
+#define   RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */
+#define   RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */
+#define   RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
+#define RSTC_MR_KEY_Pos 24
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Write Access Password */
+#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
+#define   RSTC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_RSTC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_rtc.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_rtc.h
new file mode 100644
index 000000000..62e5bad95
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_rtc.h
@@ -0,0 +1,290 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_RTC_COMPONENT_
+#define _SAMA5D2_RTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Clock */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_RTC Real-time Clock */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief RtcTs hardware registers */
+typedef struct {
+  __I uint32_t RTC_TSTR; /**< \brief (RtcTs Offset: 0x0) TimeStamp Time Register 0 */
+  __I uint32_t RTC_TSDR; /**< \brief (RtcTs Offset: 0x4) TimeStamp Date Register 0 */
+  __I uint32_t RTC_TSSR; /**< \brief (RtcTs Offset: 0x8) TimeStamp Source Register 0 */
+} RtcTs;
+/** \brief Rtc hardware registers */
+#define RTCTS_NUMBER 2
+typedef struct {
+  __IO uint32_t RTC_CR;               /**< \brief (Rtc Offset: 0x00) Control Register */
+  __IO uint32_t RTC_MR;               /**< \brief (Rtc Offset: 0x04) Mode Register */
+  __IO uint32_t RTC_TIMR;             /**< \brief (Rtc Offset: 0x08) Time Register */
+  __IO uint32_t RTC_CALR;             /**< \brief (Rtc Offset: 0x0C) Calendar Register */
+  __IO uint32_t RTC_TIMALR;           /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
+  __IO uint32_t RTC_CALALR;           /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
+  __I  uint32_t RTC_SR;               /**< \brief (Rtc Offset: 0x18) Status Register */
+  __O  uint32_t RTC_SCCR;             /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
+  __O  uint32_t RTC_IER;              /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
+  __O  uint32_t RTC_IDR;              /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
+  __I  uint32_t RTC_IMR;              /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
+  __I  uint32_t RTC_VER;              /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
+  __I  uint32_t Reserved1[32];
+       RtcTs    RTC_TS[RTCTS_NUMBER]; /**< \brief (Rtc Offset: 0xB0) 0 .. 1 */
+  __I  uint32_t Reserved2[2];
+  __I  uint32_t RTC_MSR;              /**< \brief (Rtc Offset: 0xD0) Milliseconds Register */
+  __I  uint32_t Reserved3[4];
+  __IO uint32_t RTC_WPMR;             /**< \brief (Rtc Offset: 0xE4) Write Protection Mode Register */
+  __I  uint32_t Reserved4[5];
+  __I  uint32_t RTC_VERSION;          /**< \brief (Rtc Offset: 0xFC) Version Register */
+} Rtc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
+#define RTC_CR_TIMEVSEL_Pos 8
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
+#define RTC_CR_TIMEVSEL(value) ((RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos)))
+#define   RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
+#define   RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
+#define   RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
+#define   RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
+#define RTC_CR_CALEVSEL_Pos 16
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
+#define RTC_CR_CALEVSEL(value) ((RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos)))
+#define   RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
+#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */
+#define RTC_MR_UTC (0x1u << 2) /**< \brief (RTC_MR) UTC Time Format */
+#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */
+#define RTC_MR_CORRECTION_Pos 8
+#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) Slow Clock Correction */
+#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos)))
+#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */
+#define RTC_MR_OUT0_Pos 16
+#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) All ADC Channel Trigger Event Source Selection */
+#define RTC_MR_OUT0(value) ((RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos)))
+#define   RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) No waveform, stuck at '0' */
+#define   RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */
+#define   RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */
+#define   RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */
+#define   RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */
+#define   RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) Output is a copy of the alarm flag */
+#define RTC_MR_OUT1_Pos 20
+#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) ADC Last Channel Trigger Event Source Selection */
+#define RTC_MR_OUT1(value) ((RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos)))
+#define   RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) No waveform, stuck at '0' */
+#define   RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */
+#define   RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */
+#define   RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */
+#define   RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */
+#define   RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) Output is a copy of the alarm flag */
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
+#define RTC_TIMR_SEC_Pos 0
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
+#define RTC_TIMR_MIN_Pos 8
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
+#define RTC_TIMR_HOUR_Pos 16
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
+#define RTC_TIMR_UTC_TIME_Pos 0
+#define RTC_TIMR_UTC_TIME_Msk (0xffffffffu << RTC_TIMR_UTC_TIME_Pos) /**< \brief (RTC_TIMR) Current UTC Time */
+#define RTC_TIMR_UTC_TIME(value) ((RTC_TIMR_UTC_TIME_Msk & ((value) << RTC_TIMR_UTC_TIME_Pos)))
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
+#define RTC_CALR_CENT_Pos 0
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
+#define RTC_CALR_YEAR_Pos 8
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
+#define RTC_CALR_MONTH_Pos 16
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
+#define RTC_CALR_DAY_Pos 21
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
+#define RTC_CALR_DATE_Pos 24
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
+#define RTC_TIMALR_SEC_Pos 0
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
+#define RTC_TIMALR_MIN_Pos 8
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
+#define RTC_TIMALR_HOUR_Pos 16
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
+#define RTC_TIMALR_UTC_TIME_Pos 0
+#define RTC_TIMALR_UTC_TIME_Msk (0xffffffffu << RTC_TIMALR_UTC_TIME_Pos) /**< \brief (RTC_TIMALR) UTC_TIME Alarm */
+#define RTC_TIMALR_UTC_TIME(value) ((RTC_TIMALR_UTC_TIME_Msk & ((value) << RTC_TIMALR_UTC_TIME_Pos)))
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
+#define RTC_CALALR_MONTH_Pos 16
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
+#define RTC_CALALR_DATE_Pos 24
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
+#define RTC_CALALR_UTCEN (0x1u << 0) /**< \brief (RTC_CALALR) UTC Alarm Enable */
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
+#define   RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */
+#define   RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
+#define   RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */
+#define   RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
+#define   RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */
+#define   RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
+#define   RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */
+#define   RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
+#define   RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */
+#define   RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */
+#define RTC_SR_TDERR (0x1u << 5) /**< \brief (RTC_SR) Time and/or Date Free Running Error */
+#define   RTC_SR_TDERR_CORRECT (0x0u << 5) /**< \brief (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */
+#define   RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5) /**< \brief (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
+#define RTC_SCCR_TDERRCLR (0x1u << 5) /**< \brief (RTC_SCCR) Time and/or Date Free Running Error Clear */
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
+#define RTC_IER_TDERREN (0x1u << 5) /**< \brief (RTC_IER) Time and/or Date Error Interrupt Enable */
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
+#define RTC_IDR_TDERRDIS (0x1u << 5) /**< \brief (RTC_IDR) Time and/or Date Error Interrupt Disable */
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
+#define RTC_IMR_TDERR (0x1u << 5) /**< \brief (RTC_IMR) Time and/or Date Error Mask */
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
+/* -------- RTC_TSTR : (RTC Offset: N/A) TimeStamp Time Register 0 -------- */
+#define RTC_TSTR_SEC_Pos 0
+#define RTC_TSTR_SEC_Msk (0x7fu << RTC_TSTR_SEC_Pos) /**< \brief (RTC_TSTR) Seconds of the Tamper */
+#define RTC_TSTR_MIN_Pos 8
+#define RTC_TSTR_MIN_Msk (0x7fu << RTC_TSTR_MIN_Pos) /**< \brief (RTC_TSTR) Minutes of the Tamper */
+#define RTC_TSTR_HOUR_Pos 16
+#define RTC_TSTR_HOUR_Msk (0x3fu << RTC_TSTR_HOUR_Pos) /**< \brief (RTC_TSTR) Hours of the Tamper */
+#define RTC_TSTR_AMPM (0x1u << 22) /**< \brief (RTC_TSTR) AM/PM Indicator of the Tamper */
+#define RTC_TSTR_TEVCNT_Pos 24
+#define RTC_TSTR_TEVCNT_Msk (0xfu << RTC_TSTR_TEVCNT_Pos) /**< \brief (RTC_TSTR) Tamper Events Counter */
+#define RTC_TSTR_BACKUP (0x1u << 31) /**< \brief (RTC_TSTR) System Mode of the Tamper */
+/* -------- RTC_TSDR : (RTC Offset: N/A) TimeStamp Date Register 0 -------- */
+#define RTC_TSDR_CENT_Pos 0
+#define RTC_TSDR_CENT_Msk (0x7fu << RTC_TSDR_CENT_Pos) /**< \brief (RTC_TSDR) Century of the Tamper */
+#define RTC_TSDR_YEAR_Pos 8
+#define RTC_TSDR_YEAR_Msk (0xffu << RTC_TSDR_YEAR_Pos) /**< \brief (RTC_TSDR) Year of the Tamper */
+#define RTC_TSDR_MONTH_Pos 16
+#define RTC_TSDR_MONTH_Msk (0x1fu << RTC_TSDR_MONTH_Pos) /**< \brief (RTC_TSDR) Month of the Tamper */
+#define RTC_TSDR_DAY_Pos 21
+#define RTC_TSDR_DAY_Msk (0x7u << RTC_TSDR_DAY_Pos) /**< \brief (RTC_TSDR) Day of the Tamper */
+#define RTC_TSDR_DATE_Pos 24
+#define RTC_TSDR_DATE_Msk (0x3fu << RTC_TSDR_DATE_Pos) /**< \brief (RTC_TSDR) Date of the Tamper */
+#define RTC_TSDR_UTC_TIME_Pos 0
+#define RTC_TSDR_UTC_TIME_Msk (0xffffffffu << RTC_TSDR_UTC_TIME_Pos) /**< \brief (RTC_TSDR) Time of the Tamper (UTC format) */
+/* -------- RTC_TSSR : (RTC Offset: N/A) TimeStamp Source Register 0 -------- */
+#define RTC_TSSR_SHLDM (0x1u << 0) /**< \brief (RTC_TSSR) Shield Monitor */
+#define RTC_TSSR_DBLFM (0x1u << 1) /**< \brief (RTC_TSSR) Double Frequency Monitor */
+#define RTC_TSSR_TST (0x1u << 2) /**< \brief (RTC_TSSR) Test Pin Monitor */
+#define RTC_TSSR_JTAG (0x1u << 3) /**< \brief (RTC_TSSR) JTAG Pins Monitor */
+#define RTC_TSSR_REGUL (0x1u << 4) /**< \brief (RTC_TSSR) Core Regulator Disconnection Monitor */
+#define RTC_TSSR_MCKM (0x1u << 5) /**< \brief (RTC_TSSR) Master Clock Monitor */
+#define RTC_TSSR_TPML (0x1u << 6) /**< \brief (RTC_TSSR) Low Temperature Monitor */
+#define RTC_TSSR_TPMH (0x1u << 7) /**< \brief (RTC_TSSR) High Temperature Monitor */
+#define RTC_TSSR_VDDRL (0x1u << 8) /**< \brief (RTC_TSSR) Low VDDDDR Voltage Monitor */
+#define RTC_TSSR_VDDRH (0x1u << 9) /**< \brief (RTC_TSSR) High VDDDDR Voltage Monitor */
+#define RTC_TSSR_VDDBUL (0x1u << 10) /**< \brief (RTC_TSSR) Low VDDBU Voltage Monitor */
+#define RTC_TSSR_VDDBUH (0x1u << 11) /**< \brief (RTC_TSSR) High VDDBU Voltage Monitor */
+#define RTC_TSSR_VDDCOREL (0x1u << 12) /**< \brief (RTC_TSSR) Low VDDCORE Voltage Monitor */
+#define RTC_TSSR_VDDCOREH (0x1u << 13) /**< \brief (RTC_TSSR) High VDDCORE Voltage Monitor */
+#define RTC_TSSR_VDDIOL (0x1u << 14) /**< \brief (RTC_TSSR) Low VDDIO Voltage Monitor */
+#define RTC_TSSR_VDDIOH (0x1u << 15) /**< \brief (RTC_TSSR) High VDDIO Voltage Monitor */
+#define RTC_TSSR_DET0 (0x1u << 16) /**< \brief (RTC_TSSR) PIOBU Intrusion Detector */
+#define RTC_TSSR_DET1 (0x1u << 17) /**< \brief (RTC_TSSR) PIOBU Intrusion Detector */
+#define RTC_TSSR_DET2 (0x1u << 18) /**< \brief (RTC_TSSR) PIOBU Intrusion Detector */
+#define RTC_TSSR_DET3 (0x1u << 19) /**< \brief (RTC_TSSR) PIOBU Intrusion Detector */
+#define RTC_TSSR_DET4 (0x1u << 20) /**< \brief (RTC_TSSR) PIOBU Intrusion Detector */
+#define RTC_TSSR_DET5 (0x1u << 21) /**< \brief (RTC_TSSR) PIOBU Intrusion Detector */
+#define RTC_TSSR_DET6 (0x1u << 22) /**< \brief (RTC_TSSR) PIOBU Intrusion Detector */
+#define RTC_TSSR_DET7 (0x1u << 23) /**< \brief (RTC_TSSR) PIOBU Intrusion Detector */
+/* -------- RTC_MSR : (RTC Offset: 0xD0) Milliseconds Register -------- */
+#define RTC_MSR_MS_Pos 0
+#define RTC_MSR_MS_Msk (0x3ffu << RTC_MSR_MS_Pos) /**< \brief (RTC_MSR) Number of 1/1024 seconds elapsed within 1 second */
+/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protection Mode Register -------- */
+#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protection Enable */
+#define RTC_WPMR_WPKEY_Pos 8
+#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR) Write Protection Key */
+#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos)))
+#define   RTC_WPMR_WPKEY_PASSWD (0x525443u << 8) /**< \brief (RTC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
+/* -------- RTC_VERSION : (RTC Offset: 0xFC) Version Register -------- */
+#define RTC_VERSION_VERSION_Pos 0
+#define RTC_VERSION_VERSION_Msk (0xfffu << RTC_VERSION_VERSION_Pos) /**< \brief (RTC_VERSION) Version of the Hardware Module */
+#define RTC_VERSION_MFN_Pos 16
+#define RTC_VERSION_MFN_Msk (0x7u << RTC_VERSION_MFN_Pos) /**< \brief (RTC_VERSION) Metal Fix Number */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_RTC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_rxlp.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_rxlp.h
new file mode 100644
index 000000000..a5d6f1b04
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_rxlp.h
@@ -0,0 +1,100 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_RXLP_COMPONENT_
+#define _SAMA5D2_RXLP_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Low Power Asynchronous Receiver */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_RXLP Low Power Asynchronous Receiver */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rxlp hardware registers */
+typedef struct {
+  __O  uint32_t RXLP_CR;       /**< \brief (Rxlp Offset: 0x0000) Control Register */
+  __IO uint32_t RXLP_MR;       /**< \brief (Rxlp Offset: 0x0004) Mode Register */
+  __I  uint32_t Reserved1[4];
+  __I  uint32_t RXLP_RHR;      /**< \brief (Rxlp Offset: 0x0018) Receive Holding Register */
+  __I  uint32_t Reserved2[1];
+  __IO uint32_t RXLP_BRGR;     /**< \brief (Rxlp Offset: 0x0020) Baud Rate Generator Register */
+  __IO uint32_t RXLP_CMPR;     /**< \brief (Rxlp Offset: 0x0024) Comparison Register */
+  __I  uint32_t Reserved3[47];
+  __IO uint32_t RXLP_WPMR;     /**< \brief (Rxlp Offset: 0x00E4) Write Protection Mode Register */
+  __I  uint32_t Reserved4[5];
+  __I  uint32_t RXLP_VERSION;  /**< \brief (Rxlp Offset: 0x00FC) Version Register */
+} Rxlp;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RXLP_CR : (RXLP Offset: 0x0000) Control Register -------- */
+#define RXLP_CR_RSTRX (0x1u << 2) /**< \brief (RXLP_CR) Reset Receiver */
+#define RXLP_CR_RXEN (0x1u << 4) /**< \brief (RXLP_CR) Receiver Enable */
+#define RXLP_CR_RXDIS (0x1u << 5) /**< \brief (RXLP_CR) Receiver Disable */
+/* -------- RXLP_MR : (RXLP Offset: 0x0004) Mode Register -------- */
+#define RXLP_MR_FILTER (0x1u << 4) /**< \brief (RXLP_MR) Receiver Digital Filter */
+#define   RXLP_MR_FILTER_DISABLED (0x0u << 4) /**< \brief (RXLP_MR) RXLP does not filter the receive line. */
+#define   RXLP_MR_FILTER_ENABLED (0x1u << 4) /**< \brief (RXLP_MR) RXLP filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */
+#define RXLP_MR_PAR_Pos 9
+#define RXLP_MR_PAR_Msk (0x7u << RXLP_MR_PAR_Pos) /**< \brief (RXLP_MR) Parity Type */
+#define RXLP_MR_PAR(value) ((RXLP_MR_PAR_Msk & ((value) << RXLP_MR_PAR_Pos)))
+#define   RXLP_MR_PAR_EVEN (0x0u << 9) /**< \brief (RXLP_MR) Even Parity */
+#define   RXLP_MR_PAR_ODD (0x1u << 9) /**< \brief (RXLP_MR) Odd Parity */
+#define   RXLP_MR_PAR_SPACE (0x2u << 9) /**< \brief (RXLP_MR) Parity forced to 0 */
+#define   RXLP_MR_PAR_MARK (0x3u << 9) /**< \brief (RXLP_MR) Parity forced to 1 */
+#define   RXLP_MR_PAR_NO (0x4u << 9) /**< \brief (RXLP_MR) No parity */
+/* -------- RXLP_RHR : (RXLP Offset: 0x0018) Receive Holding Register -------- */
+#define RXLP_RHR_RXCHR_Pos 0
+#define RXLP_RHR_RXCHR_Msk (0xffu << RXLP_RHR_RXCHR_Pos) /**< \brief (RXLP_RHR) Received Character */
+/* -------- RXLP_BRGR : (RXLP Offset: 0x0020) Baud Rate Generator Register -------- */
+#define RXLP_BRGR_CD_Pos 0
+#define RXLP_BRGR_CD_Msk (0x3u << RXLP_BRGR_CD_Pos) /**< \brief (RXLP_BRGR) Clock Divisor */
+#define RXLP_BRGR_CD(value) ((RXLP_BRGR_CD_Msk & ((value) << RXLP_BRGR_CD_Pos)))
+/* -------- RXLP_CMPR : (RXLP Offset: 0x0024) Comparison Register -------- */
+#define RXLP_CMPR_VAL1_Pos 0
+#define RXLP_CMPR_VAL1_Msk (0xffu << RXLP_CMPR_VAL1_Pos) /**< \brief (RXLP_CMPR) First Comparison Value for Received Character */
+#define RXLP_CMPR_VAL1(value) ((RXLP_CMPR_VAL1_Msk & ((value) << RXLP_CMPR_VAL1_Pos)))
+#define RXLP_CMPR_VAL2_Pos 16
+#define RXLP_CMPR_VAL2_Msk (0xffu << RXLP_CMPR_VAL2_Pos) /**< \brief (RXLP_CMPR) Second Comparison Value for Received Character */
+#define RXLP_CMPR_VAL2(value) ((RXLP_CMPR_VAL2_Msk & ((value) << RXLP_CMPR_VAL2_Pos)))
+/* -------- RXLP_WPMR : (RXLP Offset: 0x00E4) Write Protection Mode Register -------- */
+#define RXLP_WPMR_WPEN (0x1u << 0) /**< \brief (RXLP_WPMR) Write Protection Enable */
+#define RXLP_WPMR_WPKEY_Pos 8
+#define RXLP_WPMR_WPKEY_Msk (0xffffffu << RXLP_WPMR_WPKEY_Pos) /**< \brief (RXLP_WPMR) Write Protection Key */
+#define RXLP_WPMR_WPKEY(value) ((RXLP_WPMR_WPKEY_Msk & ((value) << RXLP_WPMR_WPKEY_Pos)))
+#define   RXLP_WPMR_WPKEY_PASSWD (0x52584Cu << 8) /**< \brief (RXLP_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */
+/* -------- RXLP_VERSION : (RXLP Offset: 0x00FC) Version Register -------- */
+#define RXLP_VERSION_VERSION_Pos 0
+#define RXLP_VERSION_VERSION_Msk (0xfffu << RXLP_VERSION_VERSION_Pos) /**< \brief (RXLP_VERSION) Hardware Module Version */
+#define RXLP_VERSION_MFN_Pos 16
+#define RXLP_VERSION_MFN_Msk (0x7u << RXLP_VERSION_MFN_Pos) /**< \brief (RXLP_VERSION) Metal Fix Number */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_RXLP_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_sckc.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_sckc.h
new file mode 100644
index 000000000..e451a2ce4
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_sckc.h
@@ -0,0 +1,53 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_SCKC_COMPONENT_
+#define _SAMA5D2_SCKC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Slow Clock Controller */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_SCKC Slow Clock Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Sckc hardware registers */
+typedef struct {
+  __IO uint32_t SCKC_CR; /**< \brief (Sckc Offset: 0x0) Slow Clock Controller Configuration Register */
+} Sckc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SCKC_CR : (SCKC Offset: 0x0) Slow Clock Controller Configuration Register -------- */
+#define SCKC_CR_OSCSEL (0x1u << 3) /**< \brief (SCKC_CR) Slow Clock Selector */
+#define   SCKC_CR_OSCSEL_RC (0x0u << 3) /**< \brief (SCKC_CR) Slow clock is the embedded 64 kHz (typical) RC oscillator. */
+#define   SCKC_CR_OSCSEL_XTAL (0x1u << 3) /**< \brief (SCKC_CR) Slow clock is the 32.768 kHz crystal oscillator. */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_SCKC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_sdmmc.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_sdmmc.h
new file mode 100644
index 000000000..a2db6ce41
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_sdmmc.h
@@ -0,0 +1,525 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_SDMMC_COMPONENT_
+#define _SAMA5D2_SDMMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Secure Digital MultiMedia Card Controller       */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_SDMMC Secure Digital MultiMedia Card Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief SDMMC hardware registers */
+typedef struct {
+  __IO uint32_t SDMMC_SSAR;         /**< \brief (SDMMC Offset: 0x000) SDMA System Address - Argument 2 Register */
+  __IO uint16_t SDMMC_BSR;          /**< \brief (SDMMC Offset: 0x004) Block Size Register */
+  __IO uint16_t SDMMC_BCR;          /**< \brief (SDMMC Offset: 0x006) Block Count Register */
+  __IO uint32_t SDMMC_ARG1R;        /**< \brief (SDMMC Offset: 0x008) Argument 1 Register */
+  __IO uint16_t SDMMC_TMR;          /**< \brief (SDMMC Offset: 0x00C) Transfer Mode Register */
+  __IO uint16_t SDMMC_CR;           /**< \brief (SDMMC Offset: 0x00E) Command Register */
+  __I  uint32_t SDMMC_RR[4];        /**< \brief (SDMMC Offset: 0x010) Response Register */
+  __IO uint32_t SDMMC_BDPR;         /**< \brief (SDMMC Offset: 0x020) Buffer Data Port Register */
+  __I  uint32_t SDMMC_PSR;          /**< \brief (SDMMC Offset: 0x024) Present State Register */
+  __IO uint8_t  SDMMC_HC1R;         /**< \brief (SDMMC Offset: 0x028) Host Control 1 Register */
+  __IO uint8_t  SDMMC_PCR;          /**< \brief (SDMMC Offset: 0x029) Power Control Register */
+  __IO uint8_t  SDMMC_BGCR;         /**< \brief (SDMMC Offset: 0x02A) Block Gap Control Register */
+  __IO uint8_t  SDMMC_WCR;          /**< \brief (SDMMC Offset: 0x02B) Wakeup Control Register */
+  __IO uint16_t SDMMC_CCR;          /**< \brief (SDMMC Offset: 0x02C) Clock Control Register */
+  __IO uint8_t  SDMMC_TCR;          /**< \brief (SDMMC Offset: 0x02E) Timeout Control Register */
+  __IO uint8_t  SDMMC_SRR;          /**< \brief (SDMMC Offset: 0x02F) Software Reset Register */
+  __IO uint16_t SDMMC_NISTR;        /**< \brief (SDMMC Offset: 0x030) Normal Interrupt Status Register */
+  __IO uint16_t SDMMC_EISTR;        /**< \brief (SDMMC Offset: 0x032) Error Interrupt Status Register */
+  __IO uint16_t SDMMC_NISTER;       /**< \brief (SDMMC Offset: 0x034) Normal Interrupt Status Enable Register */
+  __IO uint16_t SDMMC_EISTER;       /**< \brief (SDMMC Offset: 0x036) Error Interrupt Status Enable Register */
+  __IO uint16_t SDMMC_NISIER;       /**< \brief (SDMMC Offset: 0x038) Normal Interrupt Signal Enable Register */
+  __IO uint16_t SDMMC_EISIER;       /**< \brief (SDMMC Offset: 0x03A) Error Interrupt Signal Enable Register */
+  __I  uint16_t SDMMC_ACESR;        /**< \brief (SDMMC Offset: 0x03C) Auto CMD Error Status Register */
+  __IO uint16_t SDMMC_HC2R;         /**< \brief (SDMMC Offset: 0x03E) Host Control 2 Register */
+  __IO uint32_t SDMMC_CA0R;         /**< \brief (SDMMC Offset: 0x040) Capabilities Register */
+  __IO uint32_t SDMMC_CA1R;         /**< \brief (SDMMC Offset: 0x044) Capabilities Register */
+  __IO uint32_t SDMMC_MCCAR;        /**< \brief (SDMMC Offset: 0x048) Maximum Current Capabilities Register */
+  __I  uint32_t SDMMC_RSVD1;        /**< \brief (SDMMC Offset: 0x04C) Reserved */
+  __O  uint16_t SDMMC_FERACES;      /**< \brief (SDMMC Offset: 0x050) Force Event Register for Auto CMD Error Status */
+  __O  uint16_t SDMMC_FEREIS;       /**< \brief (SDMMC Offset: 0x052) Force Event Register for Error Interrupt Status */
+  __I  uint8_t  SDMMC_AESR;         /**< \brief (SDMMC Offset: 0x054) ADMA Error Status Register */
+  __I  uint8_t  SDMMC_RSVD2[3];     /**< \brief (SDMMC Offset: 0x055 - 0x57) Reserved */
+  __IO uint32_t SDMMC_ASA0R;        /**< \brief (SDMMC Offset: 0x058) ADMA System Address Register */
+  __I  uint32_t SDMMC_RSVD3[1];     /**< \brief (SDMMC Offset: 0x05C) Reserved */
+  __IO uint16_t SDMMC_PVR[8];       /**< \brief (SDMMC Offset: 0x060) Preset Value Register */
+  __I  uint32_t SDMMC_RSVD4[35];    /**< \brief (SDMMC Offset: 0x070 - 0xF8) Reserved */
+  __I  uint16_t SDMMC_SISR;         /**< \brief (SDMMC Offset: 0x0FC) Slot Interrupt Status Register */
+  __I  uint16_t SDMMC_HCVR;         /**< \brief (SDMMC Offset: 0x0FE) Host Controller Version Register */
+
+  __I  uint32_t SDMMC_RSVD5[64];    /**< \brief (SDMMC Offset: 0x100 - 0x1FC) Reserved */
+
+  __I  uint32_t SDMMC_APSR;         /**< \brief (SDMMC Offset: 0x200) Additionnal Present State Register */
+  __IO uint8_t  SDMMC_MC1R;         /**< \brief (SDMMC Offset: 0x204) MMC Control 1 Register */
+  __O  uint8_t  SDMMC_MC2R;         /**< \brief (SDMMC Offset: 0x205) MMC Control 2 Register */
+  __I  uint8_t  SDMMC_RSVD6[2];     /**< \brief (SDMMC Offset: 0x206 - 0x207) Reserved */
+  __IO uint32_t SDMMC_ACR;          /**< \brief (SDMMC Offset: 0x208) AHB Control Register */
+  __IO uint32_t SDMMC_CC2R;         /**< \brief (SDMMC Offset: 0x20C) Clock Control 2 Register */
+  __IO uint8_t  SDMMC_RTC1R;        /**< \brief (SDMMC Offset: 0x210) Retuning Timer Control 1 Register */
+  __O  uint8_t  SDMMC_RTC2R;        /**< \brief (SDMMC Offset: 0x211) Retuning Timer Control 2 Register */
+  __I  uint8_t  SDMMC_RSVD7[2];     /**< \brief (SDMMC Offset: 0x212 - 0x213) Reserved */
+  __IO uint32_t SDMMC_RTCVR;        /**< \brief (SDMMC Offset: 0x214) Retuning Timer Counter Value Register */
+  __IO uint8_t  SDMMC_RTISTER;      /**< \brief (SDMMC Offset: 0x218) Retuning Timer Interrupt Status Enable Register */
+  __IO uint8_t  SDMMC_RTISIER;      /**< \brief (SDMMC Offset: 0x219) Retuning Timer Interrupt Signal Enable Register */
+  __I  uint8_t  SDMMC_RSVD11[2];    /**< \brief (SDMMC Offset: 0x21A - 0x21B) Reserved */
+  __IO uint8_t  SDMMC_RTISTR;       /**< \brief (SDMMC Offset: 0x21C) Retuning Timer Interrupt Status Register */
+  __I  uint8_t  SDMMC_RTSSR;        /**< \brief (SDMMC Offset: 0x21D) Retuning Timer Status Slots Register */
+  __I  uint8_t  SDMMC_RSVD12[2];    /**< \brief (SDMMC Offset: 0x21E - 0x21F) Reserved */
+  __IO uint32_t SDMMC_TUNCR;        /**< \brief (SDMMC Offset: 0x220) Tuning Control Register */
+  __I  uint32_t SDMMC_RSVD8[3];     /**< \brief (SDMMC Offset: 0x224 - 0x22C) Reserved */
+  __IO uint32_t SDMMC_CACR;         /**< \brief (SDMMC Offset: 0x230) Capabilities Control Register */
+  __I  uint32_t SDMMC_RSVD9[3];     /**< \brief (SDMMC Offset: 0x234 - 0x23C) Reserved */
+  __IO uint32_t SDMMC_CALCR;        /**< \brief (SDMMC Offset: 0x240) Calibration Control Register */
+  __I  uint32_t SDMMC_RSVD10[47];   /**< \brief (SDMMC Offset: 0x244 - 0x2FC) Reserved */
+} Sdmmc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* --------  SDMMC_SSAR (SDMMC Offset: 0x000) SDMA System Address - Argument 2 Register */
+#define SDMMC_SSAR_ADDR_Pos 0
+#define SDMMC_SSAR_ADDR_Msk (0xFFFFFFFFu << SDMMC_SSAR_ADDR_Pos)
+#define SDMMC_SSAR_ADDR(value) ((SDMMC_SSAR_ADDR_Msk & ((value) << SDMMC_SSAR_ADDR_Pos)))
+#define SDMMC_SSAR_ARG2_Pos 0
+#define SDMMC_SSAR_ARG2_Msk (0xFFFFFFFFu << SDMMC_SSAR_ARG2_Pos)
+#define SDMMC_SSAR_ARG2(value) ((SDMMC_SSAR_ARG2_Msk & ((value) << SDMMC_SSAR_ARG2_Pos)))
+/* --------  SDMMC_BSR (SDMMC Offset: 0x004) Block Size Register */
+#define SDMMC_BSR_BLKSIZE_Pos 0
+#define SDMMC_BSR_BLKSIZE_Msk (0xFFFu << SDMMC_BSR_BLKSIZE_Pos)
+#define SDMMC_BSR_BLKSIZE(value) ((SDMMC_BSR_BLKSIZE_Msk & ((value) << SDMMC_BSR_BLKSIZE_Pos)))
+#define SDMMC_BSR_BOUNDARY_Pos 12
+#define SDMMC_BSR_BOUNDARY_Msk (0x7u << SDMMC_BSR_BOUNDARY_Pos)
+#define SDMMC_BSR_BOUNDARY(value) ((SDMMC_BSR_BOUNDARY_Msk & ((value) << SDMMC_BSR_BOUNDARY_Pos)))
+/* --------  SDMMC_BCR (SDMMC Offset: 0x006) Block Count Register */
+#define SDMMC_BCR_BLKCNT_Pos 0
+#define SDMMC_BCR_BLKCNT_Msk (0xFFFFu << SDMMC_BCR_BLKCNT_Pos)
+#define SDMMC_BCR_BLKCNT(value) ((SDMMC_BCR_BLKCNT_Msk & ((value) << SDMMC_BCR_BLKCNT_Pos)))
+/* --------  SDMMC_ARG1R (SDMMC Offset: 0x008) Argument 1 Register */
+#define SDMMC_ARG1R_ARG1_Pos 0
+#define SDMMC_ARG1R_ARG1_Msk (0xFFFFFFFFu << SDMMC_ARG1R_ARG1_Pos)
+#define SDMMC_ARG1R_ARG1(value) ((SDMMC_ARG1R_ARG1_Msk & ((value) << SDMMC_ARG1R_ARG1_Pos)))
+/* --------  SDMMC_TMR (SDMMC Offset: 0x00C) Transfer Mode Register */
+#define SDMMC_TMR_DMAEN (0x1u << 0)
+#define SDMMC_TMR_BCEN (0x1u << 1)
+#define SDMMC_TMR_ACMDEN_Pos 2
+#define SDMMC_TMR_ACMDEN_Msk (0x3u << SDMMC_TMR_ACMDEN_Pos)
+#define   SDMMC_TMR_ACMDEN_DIS (0x0u << 2)
+#define   SDMMC_TMR_ACMDEN_ACMD12 (0x1u << 2)
+#define   SDMMC_TMR_ACMDEN_ACMD23 (0x2u << 2)
+#define SDMMC_TMR_DTDSEL (0x1u << 4)
+#define   SDMMC_TMR_DTDSEL_WR (0x0u << 4)
+#define   SDMMC_TMR_DTDSEL_RD (0x1u << 4)
+#define SDMMC_TMR_MSBSEL (0x1u << 5)
+/* --------  SDMMC_CR (SDMMC Offset: 0x00E) Command Register */
+#define SDMMC_CR_RESPTYP_Pos 0
+#define SDMMC_CR_RESPTYP_Msk (0x3u << SDMMC_CR_RESPTYP_Pos)
+#define   SDMMC_CR_RESPTYP_NORESP (0x0u << 0)
+#define   SDMMC_CR_RESPTYP_RL136 (0x1u << 0)
+#define   SDMMC_CR_RESPTYP_RL48 (0x2u << 0)
+#define   SDMMC_CR_RESPTYP_RL48BUSY (0x3u << 0)
+#define SDMMC_CR_CMDCCEN (0x1u << 3)
+#define SDMMC_CR_CMDICEN (0x1u << 4)
+#define SDMMC_CR_DPSEL (0x1u << 5)
+#define SDMMC_CR_CMDTYP_Pos 6
+#define SDMMC_CR_CMDTYP_Msk (0x3u << SDMMC_CR_CMDTYP_Pos)
+#define   SDMMC_CR_CMDTYP_NORMAL (0x0u << 6)
+#define   SDMMC_CR_CMDTYP_SUSPEND (0x1u << 6)
+#define   SDMMC_CR_CMDTYP_RESUME (0x2u << 6)
+#define   SDMMC_CR_CMDTYP_ABORT (0x3u << 6)
+#define SDMMC_CR_CMDIDX_Pos 8
+#define SDMMC_CR_CMDIDX_Msk (0x3F << SDMMC_CR_CMDIDX_Pos)
+#define SDMMC_CR_CMDIDX(value) ((SDMMC_CR_CMDIDX_Msk & ((value) << SDMMC_CR_CMDIDX_Pos)))
+/* --------  SDMMC_RR[4] (SDMMC Offset: 0x010) Response Register */
+#define SDMMC_RR_CMDRESP_Pos 0
+#define SDMMC_RR_CMDRESP_Msk (0xFFFFFFFFu << SDMMC_RR_CMDRESP_Pos)
+/* --------  SDMMC_BDPR Buffer Data Port Register */
+#define SDMMC_BDPR_BUFDATA_Pos 0
+#define SDMMC_BDPR_BUFDATA_Msk (0xFFFFFFFFu << SDMMC_BDPR_BUFDATA_Pos)
+#define SDMMC_BDPR_BUFDATA(value) ((SDMMC_BDPR_BUFDATA_Msk & ((value) << SDMMC_BDPR_BUFDATA_Pos)))
+/* --------  SDMMC_PSR (SDMMC Offset: 0x024) Present State Register */
+#define SDMMC_PSR_CMDINHC (0x1u << 0)
+#define SDMMC_PSR_CMDINHD (0x1u << 1)
+#define SDMMC_PSR_DLACT (0x1u << 2)
+#define SDMMC_PSR_RTREQ (0x1u << 3)
+#define SDMMC_PSR_WTACT (0x1u << 8)
+#define SDMMC_PSR_RTACT (0x1u << 9)
+#define SDMMC_PSR_BUFWREN (0x1u << 10)
+#define SDMMC_PSR_BUFRDEN (0x1u << 11)
+#define SDMMC_PSR_CARDINS (0x1u << 16)
+#define SDMMC_PSR_CARDSS (0x1u << 17)
+#define SDMMC_PSR_CARDDPL (0x1u << 18)
+#define SDMMC_PSR_WRPPL (0x1u << 19)
+#define SDMMC_PSR_DATLL_Pos 20
+#define SDMMC_PSR_DATLL_Msk (0xFu << SDMMC_PSR_DATLL_Pos)
+#define SDMMC_PSR_CMDLL (0x1u << 24)
+/* --------  SDMMC_HC1R (SDMMC Offset: 0x028) Host Control 1 Register */
+#define SDMMC_HC1R_LEDCTRL (0x1u << 0)
+#define SDMMC_HC1R_DW (0x1u << 1)
+#define SDMMC_HC1R_HSEN (0x1u << 2)
+#define SDMMC_HC1R_DMASEL_Pos 3
+#define SDMMC_HC1R_DMASEL_Msk (0x3u << SDMMC_HC1R_DMASEL_Pos)
+#define   SDMMC_HC1R_DMASEL_SDMA (0x0u << 3)
+#define   SDMMC_HC1R_DMASEL_ADMA32 (0x2u << 3)
+#define   SDMMC_HC1R_DMASEL_ADMA64 (0x3u << 3)
+#define SDMMC_HC1R_EXTDW (0x1u << 5)
+#define SDMMC_HC1R_CARDDTL (0x1u << 6)
+#define SDMMC_HC1R_CARDDSSEL (0x1u << 7)
+/* --------  SDMMC_PCR (SDMMC Offset: 0x029) Power Control Register */
+#define SDMMC_PCR_SDBPWR (0x1u << 0)
+#define SDMMC_PCR_SDBVSEL_Pos 1
+#define SDMMC_PCR_SDBVSEL_Msk (0x7u << SDMMC_PCR_SDBVSEL_Pos)
+#define SDMMC_PCR_SDBVSEL(value) ((SDMMC_PCR_SDBVSEL_Msk & ((value) << SDMMC_PCR_SDBVSEL_Pos)))
+#define   SDMMC_PCR_SDBVSEL_18V (0x5u << 1)
+#define   SDMMC_PCR_SDBVSEL_30V (0x6u << 1)
+#define   SDMMC_PCR_SDBVSEL_33V (0x7u << 1)
+/* --------  SDMMC_BGCR (SDMMC Offset: 0x02A) Block Gap Control Register */
+#define SDMMC_BGCR_STPBGR (0x1u << 0)
+#define SDMMC_BGCR_CONTR (0x1u << 1)
+#define SDMMC_BGCR_RWCTRL (0x1u << 2)
+#define SDMMC_BGCR_INTBG (0x1u << 3)
+/* --------  SDMMC_WCR (SDMMC Offset: 0x02B) Wakeup Control Register */
+#define SDMMC_WCR_WKENCINT (0x1u << 0)
+#define SDMMC_WCR_WKENCINS (0x1u << 1)
+#define SDMMC_WCR_WKENCREM (0x1u << 2)
+/* --------  SDMMC_CCR (SDMMC Offset: 0x02C) Clock Control Register */
+#define SDMMC_CCR_INTCLKEN (0x1u << 0)
+#define SDMMC_CCR_INTCLKS (0x1u << 1)
+#define SDMMC_CCR_SDCLKEN (0x1u << 2)
+#define SDMMC_CCR_CLKGSEL (0x1u << 5)
+#define SDMMC_CCR_USDCLKFSEL_Pos 6
+#define SDMMC_CCR_USDCLKFSEL_Msk (0x3u << SDMMC_CCR_USDCLKFSEL_Pos)
+#define SDMMC_CCR_USDCLKFSEL(value) ((SDMMC_CCR_USDCLKFSEL_Msk & ((value) << SDMMC_CCR_USDCLKFSEL_Pos)))
+#define SDMMC_CCR_SDCLKFSEL_Pos 8
+#define SDMMC_CCR_SDCLKFSEL_Msk (0xFFu << SDMMC_CCR_SDCLKFSEL_Pos)
+#define SDMMC_CCR_SDCLKFSEL(value) ((SDMMC_CCR_SDCLKFSEL_Msk & ((value) << SDMMC_CCR_SDCLKFSEL_Pos)))
+/* --------  SDMMC_TCR (SDMMC Offset: 0x02E) Timeout Control Register */
+#define SDMMC_TCR_DTCVAL_Pos 0
+#define SDMMC_TCR_DTCVAL_Msk (0xFu << SDMMC_TCR_DTCVAL_Pos)
+#define SDMMC_TCR_DTCVAL(value) ((SDMMC_TCR_DTCVAL_Msk & ((value) << SDMMC_TCR_DTCVAL_Pos)))
+/* --------  SDMMC_SRR (SDMMC Offset: 0x02F) Software Reset Register */
+#define SDMMC_SRR_SWRSTALL (0x1u << 0)
+#define SDMMC_SRR_SWRSTCMD (0x1u << 1)
+#define SDMMC_SRR_SWRSTDAT (0x1u << 2)
+/* --------  SDMMC_NISTR (SDMMC Offset: 0x030) Normal Interrupt Status Register */
+#define SDMMC_NISTR_CMDC (0x1u << 0)
+#define SDMMC_NISTR_TRFC (0x1u << 1)
+#define SDMMC_NISTR_BLKGE (0x1u << 2)
+#define SDMMC_NISTR_DMAINT (0x1u << 3)
+#define SDMMC_NISTR_BWRRDY (0x1u << 4)
+#define SDMMC_NISTR_BRDRDY (0x1u << 5)
+#define SDMMC_NISTR_CINS (0x1u << 6)
+#define SDMMC_NISTR_CREM (0x1u << 7)
+#define SDMMC_NISTR_CINT (0x1u << 8)
+#define SDMMC_NISTR_INTA (0x1u << 9)
+#define SDMMC_NISTR_INTB (0x1u << 10)
+#define SDMMC_NISTR_INTC (0x1u << 11)
+#define SDMMC_NISTR_RTEVT (0x1u << 12)
+#define SDMMC_NISTR_BOOTAR (0x1u << 14)
+#define SDMMC_NISTR_ERRINT (0x1u << 15)
+/* --------  SDMMC_EISTR (SDMMC Offset: 0x032) Error Interrupt Status Register */
+#define SDMMC_EISTR_CMDTEO (0x1u << 0)
+#define SDMMC_EISTR_CMDCRC (0x1u << 1)
+#define SDMMC_EISTR_CMDEND (0x1u << 2)
+#define SDMMC_EISTR_CMDIDX (0x1u << 3)
+#define SDMMC_EISTR_DATTEO (0x1u << 4)
+#define SDMMC_EISTR_DATCRC (0x1u << 5)
+#define SDMMC_EISTR_DATEND (0x1u << 6)
+#define SDMMC_EISTR_CURLIM (0x1u << 7)
+#define SDMMC_EISTR_ACMD   (0x1u << 8)
+#define SDMMC_EISTR_ADMA   (0x1u << 9)
+#define SDMMC_EISTR_TUNING (0x1u << 10)
+#define SDMMC_EISTR_BOOTAE (0x1u << 12)
+/* --------  SDMMC_NISTER (SDMMC Offset: 0x034) Normal Interrupt Status Enable Register */
+#define SDMMC_NISTER_CMDC (0x1u << 0)
+#define SDMMC_NISTER_TRFC (0x1u << 1)
+#define SDMMC_NISTER_BLKGE (0x1u << 2)
+#define SDMMC_NISTER_DMAINT (0x1u << 3)
+#define SDMMC_NISTER_BWRRDY (0x1u << 4)
+#define SDMMC_NISTER_BRDRDY (0x1u << 5)
+#define SDMMC_NISTER_CINS (0x1u << 6)
+#define SDMMC_NISTER_CREM (0x1u << 7)
+#define SDMMC_NISTER_CINT (0x1u << 8)
+#define SDMMC_NISTER_INTA (0x1u << 9)
+#define SDMMC_NISTER_INTB (0x1u << 10)
+#define SDMMC_NISTER_INTC (0x1u << 11)
+#define SDMMC_NISTER_RTEVT (0x1u << 12)
+#define SDMMC_NISTER_BOOTAR (0x1u << 14)
+/* --------  SDMMC_EISTER (SDMMC Offset: 0x036) Error Interrupt Status Enable Register */
+#define SDMMC_EISTER_CMDTEO (0x1u << 0)
+#define SDMMC_EISTER_CMDCRC (0x1u << 1)
+#define SDMMC_EISTER_CMDEND (0x1u << 2)
+#define SDMMC_EISTER_CMDIDX (0x1u << 3)
+#define SDMMC_EISTER_DATTEO (0x1u << 4)
+#define SDMMC_EISTER_DATCRC (0x1u << 5)
+#define SDMMC_EISTER_DATEND (0x1u << 6)
+#define SDMMC_EISTER_CURLIM (0x1u << 7)
+#define SDMMC_EISTER_ACMD (0x1u << 8)
+#define SDMMC_EISTER_ADMA (0x1u << 9)
+#define SDMMC_EISTER_TUNING (0x1u << 10)
+#define SDMMC_EISTER_BOOTAE (0x1u << 12)
+/* --------  SDMMC_NISIER (SDMMC Offset: 0x038) Normal Interrupt Signal Enable Register */
+#define SDMMC_NISIER_CMDC (0x1u << 0)
+#define SDMMC_NISIER_TRFC (0x1u << 1)
+#define SDMMC_NISIER_BLKGE (0x1u << 2)
+#define SDMMC_NISIER_DMAINT (0x1u << 3)
+#define SDMMC_NISIER_BWRRDY (0x1u << 4)
+#define SDMMC_NISIER_BRDRDY (0x1u << 5)
+#define SDMMC_NISIER_CINS (0x1u << 6)
+#define SDMMC_NISIER_CREM (0x1u << 7)
+#define SDMMC_NISIER_CINT (0x1u << 8)
+#define SDMMC_NISIER_INTA (0x1u << 9)
+#define SDMMC_NISIER_INTB (0x1u << 10)
+#define SDMMC_NISIER_INTC (0x1u << 11)
+#define SDMMC_NISIER_RTEVT (0x1u << 12)
+#define SDMMC_NISIER_BOOTAR (0x1u << 14)
+/* --------  SDMMC_EISIER (SDMMC Offset: 0x03A) Error Interrupt Signal Enable Register */
+#define SDMMC_EISIER_CMDTEO (0x1u << 0)
+#define SDMMC_EISIER_CMDCRC (0x1u << 1)
+#define SDMMC_EISIER_CMDEND (0x1u << 2)
+#define SDMMC_EISIER_CMDIDX (0x1u << 3)
+#define SDMMC_EISIER_DATTEO (0x1u << 4)
+#define SDMMC_EISIER_DATCRC (0x1u << 5)
+#define SDMMC_EISIER_DATEND (0x1u << 6)
+#define SDMMC_EISIER_CURLIM (0x1u << 7)
+#define SDMMC_EISIER_ACMD (0x1u << 8)
+#define SDMMC_EISIER_ADMA (0x1u << 9)
+#define SDMMC_EISIER_TUNING (0x1u << 10)
+#define SDMMC_EISIER_BOOTAE (0x1u << 12)
+/* --------  SDMMC_ACESR (SDMMC Offset: 0x03C) Auto CMD Error Status Register */
+#define SDMMC_ACESR_ACMD12NE (0x1u << 0)
+#define SDMMC_ACESR_ACMDTEO (0x1u << 1)
+#define SDMMC_ACESR_ACMDCRC (0x1u << 2)
+#define SDMMC_ACESR_ACMDEND (0x1u << 3)
+#define SDMMC_ACESR_ACMDIDX (0x1u << 4)
+#define SDMMC_ACESR_CMDNI (0x1u << 7)
+/* --------  SDMMC_HC2R (SDMMC Offset: 0x03E) Host Control 2 Register */
+#define SDMMC_HC2R_UHSMS_Pos 0
+#define SDMMC_HC2R_UHSMS_Msk (0x7u << SDMMC_HC2R_UHSMS_Pos)
+#define   SDMMC_HC2R_UHSMS_SDR12 (0x0u << 0)
+#define   SDMMC_HC2R_UHSMS_SDR25 (0x1u << 0)
+#define   SDMMC_HC2R_UHSMS_SDR50 (0x2u << 0)
+#define   SDMMC_HC2R_UHSMS_SDR104 (0x3u << 0)
+#define   SDMMC_HC2R_UHSMS_DDR50 (0x4u << 0)
+#define SDMMC_HC2R_VS18EN (0x1u << 3)
+#define SDMMC_HC2R_DRVSEL_Pos 4
+#define SDMMC_HC2R_DRVSEL_Msk (0x3u << SDMMC_HC2R_DRVSEL_Pos)
+#define   SDMMC_HC2R_DRVSEL_TYPEB (0x0u << 4)
+#define   SDMMC_HC2R_DRVSEL_TYPEA (0x1u << 4)
+#define   SDMMC_HC2R_DRVSEL_TYPEC (0x2u << 4)
+#define   SDMMC_HC2R_DRVSEL_TYPED (0x3u << 4)
+#define SDMMC_HC2R_EXTUN (0x1u << 6)
+#define SDMMC_HC2R_SCLKSEL (0x1u << 7)
+#define SDMMC_HC2R_ASINTEN (0x1u << 14)
+#define SDMMC_HC2R_PVALEN (0x1u << 15)
+/* --------  SDMMC_CA0R (SDMMC Offset: 0x040) Capabilities Register */
+#define SDMMC_CA0R_TEOCLKF_Pos 0
+#define SDMMC_CA0R_TEOCLKF_Msk (0x3Fu << SDMMC_CA0R_TEOCLKF_Pos)
+#define SDMMC_CA0R_TEOCLKF(value) ((SDMMC_CA0R_TEOCLKF_Msk & ((value) << SDMMC_CA0R_TEOCLKF_Pos)))
+#define SDMMC_CA0R_TEOCLKU (0x1u << 7)
+#define SDMMC_CA0R_BASECLKF_Pos 8
+#define SDMMC_CA0R_BASECLKF_Msk (0xFFu << SDMMC_CA0R_BASECLKF_Pos)
+#define SDMMC_CA0R_BASECLKF(value) ((SDMMC_CA0R_BASECLKF_Msk & ((value) << SDMMC_CA0R_BASECLKF_Pos)))
+#define SDMMC_CA0R_MAXBLKL_Pos 16
+#define SDMMC_CA0R_MAXBLKL_Msk (0x3u << SDMMC_CA0R_MAXBLKL_Pos)
+#define SDMMC_CA0R_MAXBLKL(value) ((SDMMC_CA0R_MAXBLKL_Msk & ((value) << SDMMC_CA0R_MAXBLKL_Pos)))
+#define SDMMC_CA0R_ED8SUP (0x1u << 18)
+#define SDMMC_CA0R_ADMA2SUP (0x1u << 19)
+#define SDMMC_CA0R_HSSUP (0x1u << 21)
+#define SDMMC_CA0R_SDMASUP (0x1u << 22)
+#define SDMMC_CA0R_SRSUP (0x1u << 23)
+#define SDMMC_CA0R_V33VSUP (0x1u << 24)
+#define SDMMC_CA0R_V30VSUP (0x1u << 25)
+#define SDMMC_CA0R_V18VSUP (0x1u << 26)
+#define SDMMC_CA0R_SB64SUP (0x1u << 28)
+#define SDMMC_CA0R_ASINTSUP (0x1u << 29)
+#define SDMMC_CA0R_SLTYPE_Pos 30
+#define SDMMC_CA0R_SLTYPE_Msk (0x3u << SDMMC_CA0R_SLTYPE_Pos)
+#define   SDMMC_CA0R_SLTYPE_REMOVABLECARD (0x0u << 30)
+#define   SDMMC_CA0R_SLTYPE_EMBEDDED (0x1u << 30)
+#define   SDMMC_CA0R_SLTYPE_SHAREDBUS (0x2u << 30)
+/* --------  SDMMC_CA1R (SDMMC Offset: 0x044) Capabilities Register */
+#define SDMMC_CA1R_SDR50SUP (0x1u << 0)
+#define SDMMC_CA1R_SDR104SUP (0x1u << 1)
+#define SDMMC_CA1R_DDR50SUP (0x1u << 2)
+#define SDMMC_CA1R_DRVASUP (0x1u << 4)
+#define SDMMC_CA1R_DRVCSUP (0x1u << 5)
+#define SDMMC_CA1R_DRVDSUP (0x1u << 6)
+#define SDMMC_CA1R_TCNTRT_Pos 8
+#define SDMMC_CA1R_TCNTRT_Msk (0xFu << SDMMC_CA1R_TCNTRT_Pos)
+#define SDMMC_CA1R_TSDR50 (0x1u << 13)
+#define SDMMC_CA1R_RTMOD_Pos 14
+#define SDMMC_CA1R_RTMOD_Msk (0x3u << SDMMC_CA1R_RTMOD_Pos)
+#define   SDMMC_CA1R_RTMOD_MODE1 (0x0u << 14)
+#define   SDMMC_CA1R_RTMOD_MODE2 (0x1u << 14)
+#define   SDMMC_CA1R_RTMOD_MODE3 (0x2u << 14)
+#define SDMMC_CA1R_CLKMULT_Pos 16
+#define SDMMC_CA1R_CLKMULT_Msk (0xFFu << SDMMC_CA1R_CLKMULT_Pos)
+/* --------  SDMMC_MCCAR (SDMMC Offset: 0x048) Maximum Current Capabilities Register */
+#define SDMMC_MCCAR_MAXCUR33V_Pos 0
+#define SDMMC_MCCAR_MAXCUR33V_Msk (0xFFu << SDMMC_MCCAR_MAXCUR33V_Pos)
+#define SDMMC_MCCAR_MAXCUR30V_Pos 8
+#define SDMMC_MCCAR_MAXCUR30V_Msk (0xFFu << SDMMC_MCCAR_MAXCUR30V_Pos)
+#define SDMMC_MCCAR_MAXCUR18V_Pos 16
+#define SDMMC_MCCAR_MAXCUR18V_Msk (0xFFu << SDMMC_MCCAR_MAXCUR18V_Pos)
+/* --------  SDMMC_FERACES (SDMMC Offset: 0x050) Force Event Register for Auto CMD Error Status */
+#define SDMMC_FERACES_ACMD12NE (0x1u << 0)
+#define SDMMC_FERACES_ACMDTEO (0x1u << 1)
+#define SDMMC_FERACES_ACMDCRC (0x1u << 2)
+#define SDMMC_FERACES_ACMDEND (0x1u << 3)
+#define SDMMC_FERACES_ACMDIDX (0x1u << 4)
+#define SDMMC_FERACES_CMDNI (0x1u << 7)
+/* --------  SDMMC_FEREIS (SDMMC Offset: 0x052) Force Event Register for Error Interrupt Status */
+#define SDMMC_FEREIS_CMDTEO (0x1u << 0)
+#define SDMMC_FEREIS_CMDCRC (0x1u << 1)
+#define SDMMC_FEREIS_CMDEND (0x1u << 2)
+#define SDMMC_FEREIS_CMDIDX (0x1u << 3)
+#define SDMMC_FEREIS_DATTEO (0x1u << 4)
+#define SDMMC_FEREIS_DATCRC (0x1u << 5)
+#define SDMMC_FEREIS_DATEND (0x1u << 6)
+#define SDMMC_FEREIS_CURLIM (0x1u << 7)
+#define SDMMC_FEREIS_ACMD (0x1u << 8)
+#define SDMMC_FEREIS_ADMA (0x1u << 9)
+/* --------  SDMMC_AESR (SDMMC Offset: 0x054) ADMA Error Status Register */
+#define SDMMC_AESR_ERRST_Pos 0
+#define SDMMC_AESR_ERRST_Msk (0x3u << SDMMC_AESR_ERRST_Pos)
+#define   SDMMC_AESR_ERRST_STOP (0x0u << 0)
+#define   SDMMC_AESR_ERRST_FDS (0x1u << 0)
+#define   SDMMC_AESR_ERRST_TFR (0x3u << 0)
+#define SDMMC_AESR_LMIS (0x1u << 2)
+/* --------  SDMMC_ASA0R (SDMMC Offset: 0x058) ADMA System Address Register */
+#define SDMMC_ASA0R_ADMASA_Pos 0
+#define SDMMC_ASA0R_ADMASA_Msk (0xFFFFFFFFu << SDMMC_ASA0R_ADMASA_Pos)
+#define SDMMC_ASA0R_ADMASA(value) ((SDMMC_ASA0R_ADMASA_Msk & ((value) << SDMMC_ASA0R_ADMASA_Pos)))
+/* --------  SDMMC_PVR[8] (SDMMC Offset: 0x060) Preset Value Register */
+#define SDMMC_PVR_SDCLKFSEL_Pos 0
+#define SDMMC_PVR_SDCLKFSEL_Msk (0x3FFu << SDMMC_PVR_SDCLKFSEL_Pos)
+#define SDMMC_PVR_SDCLKFSEL(value) ((SDMMC_PVR_SDCLKFSEL_Msk & ((value) << SDMMC_PVR_SDCLKFSEL_Pos)))
+#define SDMMC_PVR_CLKGSEL (0x1u << 10)
+#define SDMMC_PVR_DRVSEL_Pos 14
+#define SDMMC_PVR_DRVSEL_Msk (0x3u << SDMMC_PVR_DRVSEL_Pos)
+#define SDMMC_PVR_DRVSEL(value) ((SDMMC_PVR_DRVSEL_Msk & ((value) << SDMMC_PVR_DRVSEL_Pos)))
+/* --------  SDMMC_SISR (SDMMC Offset: 0x0FC) Slot Interrupt Status Register */
+#define SDMMC_SISR_INTSSL_Pos 0
+#define SDMMC_SISR_INTSSL_Msk (0xFFu << SDMMC_SISR_INTSIGSLOT_Pos)
+/* --------  SDMMC_HCVR (SDMMC Offset: 0x0FE) Host Controller Version Register */
+#define SDMMC_HCVR_SVER_Pos 0
+#define SDMMC_HCVR_SVER_Msk (0xFFu << SDMMC_HCVR_SVER_Pos)
+#define SDMMC_HCVR_VVER_Pos 8
+#define SDMMC_HCVR_VVER_Msk (0xFFu << SDMMC_HCVR_VVER_Pos)
+/* --------  SDMMC_APSR (SDMMC Offset: 0x200) Additionnal Present State Register */
+#define SDMMC_APSR_HDATLL_Pos 0
+#define SDMMC_APSR_HDATLL_Msk (0xFu << SDMMC_APSR_HDATLL_Pos)
+/* --------  SDMMC_MC1R (SDMMC Offset: 0x204) MMC Control 1 Register */
+#define SDMMC_MC1R_CMDTYP_Pos 0
+#define SDMMC_MC1R_CMDTYP_Msk (0x3u << SDMMC_MC1R_CMDTYP_Pos)
+#define   SDMMC_MC1R_CMDTYP_NORMAL (0x0u << 0)
+#define   SDMMC_MC1R_CMDTYP_WAITIRQ (0x1u << 0)
+#define   SDMMC_MC1R_CMDTYP_STREAM (0x2u << 0)
+#define   SDMMC_MC1R_CMDTYP_BOOT (0x3u << 0)
+#define SDMMC_MC1R_DDR (0x1u << 3)
+#define SDMMC_MC1R_OPD (0x1u << 4)
+#define SDMMC_MC1R_BOOTA (0x1u << 5)
+#define SDMMC_MC1R_RSTN (0x1u << 6)
+#define SDMMC_MC1R_FCD (0x1u << 7)
+/* --------  SDMMC_MC2R (SDMMC Offset: 0x205) MMC Control 2 Register */
+#define SDMMC_MC2R_SRESP (0x1u << 0)
+#define SDMMC_MC2R_ABOOT (0x1u << 1)
+/* --------  SDMMC_ACR (SDMMC Offset: 0x208) AHB Control Register */
+#define SDMMC_ACR_BMAX_Pos 0
+#define SDMMC_ACR_BMAX_Msk (0x3u << SDMMC_ACR_BMAX_Pos)
+#define   SDMMC_ACR_BMAX_INCR16 (0x0u << 0)
+#define   SDMMC_ACR_BMAX_INCR8 (0x1u << 0)
+#define   SDMMC_ACR_BMAX_INCR4 (0x2u << 0)
+#define   SDMMC_ACR_BMAX_SINGLE (0x3u << 0)
+#define SDMMC_ACR_HNBRDIS (0x1u << 4)
+#define SDMMC_ACR_B1KBDIS (0x1u << 5)
+/* --------  SDMMC_CC2R (SDMMC Offset: 0x20C) Clock Control 2 Register */
+#define SDMMC_CC2R_FSDCLKD (0x1u << 0)
+/* --------  SDMMC_RTC1R (SDMMC Offset: 0x210) Retuning Timer Control 1 Register */
+#define SDMMC_RTC1R_TMREN (0x1u << 0)
+/* --------  SDMMC_RTC2R (SDMMC Offset: 0x211) Retuning Timer Control 2 Register */
+#define SDMMC_RTC2R_RLD (0x1u << 0)
+/* --------  SDMMC_RTCVR (SDMMC Offset: 0x214) Retuning Timer Counter Value Register */
+#define SDMMC_RTCVR_TCVAL_Pos 0
+#define SDMMC_RTCVR_TCVAL_Msk (0xFu << SDMMC_RTCVR_TCVAL_Pos)
+#define SDMMC_RTCVR_TCVAL(value) ((SDMMC_RTCVR_TCVAL_Msk & ((value) << SDMMC_RTCVR_TCVAL_Pos)))
+/* --------  SDMMC_RTISTER (SDMMC Offset: 0x218) Retuning Timer Interrupt Status Enable Register */
+#define SDMMC_RTISTER_TEVT (0x1u << 0)
+/* --------  SDMMC_RTISIER (SDMMC Offset: 0x219) Retuning Timer Interrupt Signal Enable Register */
+#define SDMMC_RTISIER_TEVT (0x1u << 0)
+/* --------  SDMMC_RTISTR (SDMMC Offset: 0x21C) Retuning Timer Interrupt Status Register */
+#define SDMMC_RTISTR_TEVT (0x1u << 0)
+/* --------  SDMMC_RTSSR (SDMMC Offset: 0x21D) Retuning Timer Status Slots Register */
+#define SDMMC_RTSSR_TEVTSLOT (0x1u << 0)
+/* --------  SDMMC_TUNCR (SDMMC Offset: 0x220) Tuning Control Register */
+#define SDMMC_TUNCR_SMPLPT (0x1u << 0)
+/* --------  SDMMC_CACR (SDMMC Offset: 0x230) Capabilities Control Register */
+#define SDMMC_CACR_CAPWREN (0x1u << 0)
+#define SDMMC_CACR_KEY_Pos 8
+#define SDMMC_CACR_KEY_Msk (0xFFu << SDMMC_CACR_KEY_Pos)
+#define SDMMC_CACR_KEY(value) ((SDMMC_CACR_KEY_Msk & ((value) << SDMMC_CACR_KEY_Pos)))
+/* --------  SDMMC_CALCR (SDMMC Offset: 0x240) Calibration Control Register */
+#define SDMMC_CALCR_EN (0x1u << 0)
+#define SDMMC_CALCR_ALWYSON (0x1u << 4)
+#define SDMMC_CALCR_TUNDIS (0x1u << 5)
+#define SDMMC_CALCR_CNTVAL_Pos 8
+#define SDMMC_CALCR_CNTVAL_Msk (0xFFu << SDMMC_CALCR_CNTVAL_Pos)
+#define SDMMC_CALCR_CNTVAL(value) ((SDMMC_CALCR_CNTVAL_Msk & ((value) << SDMMC_CALCR_CNTVAL_Pos)))
+#define SDMMC_CALCR_CALN_Pos 16
+#define SDMMC_CALCR_CALN_Msk (0xFu << SDMMC_CALCR_CALN_Pos)
+#define SDMMC_CALCR_CALP_Pos 24
+#define SDMMC_CALCR_CALP_Msk (0xFu << SDMMC_CALCR_CALP_Pos)
+/* --------  SDMMC Descriptor Table for Advanced DMA 2 as pointed by SDMMC_ASA0R */
+#define SDMMC_DMADL_SIZE (2u) /**< \brief Size of a Descriptor Line in the ADMA2 Descriptor Table, in words */
+#define SDMMC_DMADL_TRAN_LEN_MIN (1u) /**< \brief Minimum data length per ADMA2 Descriptor Line, in bytes */
+#define SDMMC_DMADL_TRAN_LEN_MAX (65536ul) /**< \brief Maximum data length per ADMA2 Descriptor Line, in bytes */
+/* --------  SDMMC_DMADL[0] (Descriptor Line Offset: 0x0) ADMA2 Descriptor Line */
+#define SDMMC_DMA0DL_ATTR_VALID (0x1u << 0)
+#define SDMMC_DMA0DL_ATTR_END (0x1u << 1)
+#define SDMMC_DMA0DL_ATTR_INT (0x1u << 2)
+#define SDMMC_DMA0DL_ATTR_ACT_Pos 4
+#define SDMMC_DMA0DL_ATTR_ACT_Msk (0x3u << SDMMC_DMA0DL_ATTR_ACT_Pos)
+#define   SDMMC_DMA0DL_ATTR_ACT_NOP (0x0u << 4)
+#define   SDMMC_DMA0DL_ATTR_ACT_TRAN (0x2u << 4)
+#define   SDMMC_DMA0DL_ATTR_ACT_LINK (0x3u << 4)
+#define SDMMC_DMA0DL_LEN_Pos 16
+#define SDMMC_DMA0DL_LEN_Msk (0xFFFFu << SDMMC_DMA0DL_LEN_Pos)
+#define   SDMMC_DMA0DL_LEN_MAX (0x0u << 16)
+#define SDMMC_DMA0DL_LEN(value) ((SDMMC_DMA0DL_LEN_Msk & ((value) << SDMMC_DMA0DL_LEN_Pos)))
+/* --------  SDMMC_DMADL[1] (Descriptor Line Offset: 0x4) ADMA2 Descriptor Line */
+#define SDMMC_DMA1DL_ADDR_Pos 0
+#define SDMMC_DMA1DL_ADDR_Msk (0xFFFFFFFFu << SDMMC_DMA1DL_ADDR_Pos)
+#define SDMMC_DMA1DL_ADDR(value) ((SDMMC_DMA1DL_ADDR_Msk & ((value) << SDMMC_DMA1DL_ADDR_Pos)))
+
+/*@}*/
+
+#endif /* _SAMA5D2_SDMMC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_secumod.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_secumod.h
new file mode 100644
index 000000000..a68e83f49
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_secumod.h
@@ -0,0 +1,405 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_SECUMOD_COMPONENT_
+#define _SAMA5D2_SECUMOD_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Security Module */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_SECUMOD Security Module */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Secumod internal memory */
+typedef struct {
+  __IO uint32_t BUSRAM_LOWER[1024]; /**< \brief (Securam Offset: 0x0000) Lower 4KB auto-erased */
+  __IO uint32_t BUSRAM_HIGHER[256]; /**< \brief (Securam Offset: 0x1000) Higher 1KB not auto-erased */
+  __IO uint32_t BUREG[8];           /**< \brief (Securam Offset: 0x1400) BUREG 256 bits auto-erased */
+} Securam;
+
+/** \brief Secumod hardware registers */
+typedef struct {
+  __O  uint32_t SECUMOD_CR;       /**< \brief (Secumod Offset: 0x0000) Control Register */
+  __IO uint32_t SECUMOD_SYSR;     /**< \brief (Secumod Offset: 0x0004) System Status Register */
+  __I  uint32_t SECUMOD_SR;       /**< \brief (Secumod Offset: 0x0008) Status Register */
+  __I  uint32_t SECUMOD_ASR;      /**< \brief (Secumod Offset: 0x000C) Auxiliary Status Register */
+  __O  uint32_t SECUMOD_SCR;      /**< \brief (Secumod Offset: 0x0010) Status Clear Register */
+  __I  uint32_t SECUMOD_RAMRDY;   /**< \brief (Secumod Offset: 0x0014) RAM Access Ready Register */
+  __IO uint32_t SECUMOD_PIOBU[8]; /**< \brief (Secumod Offset: 0x0018) PIO Backup Register */
+  __I  uint32_t Reserved1[8];
+  __IO uint32_t SECUMOD_VBUFR;    /**< \brief (Secumod Offset: 0x0058) VDDBU Filter Register */
+  __I  uint32_t Reserved2[2];
+  __IO uint32_t SECUMOD_VCOREFR;  /**< \brief (Secumod Offset: 0x0064) VDDCORE Filter Register */
+  __IO uint32_t SECUMOD_JTAGCR;   /**< \brief (Secumod Offset: 0x0068) JTAG Protection Control Register */
+  __IO uint32_t SECUMOD_DYSTUNE;  /**< \brief (Secumod Offset: 0x006C) Dynamic Signatures Tuning Register */
+  __IO uint32_t SECUMOD_SCRKEY;   /**< \brief (Secumod Offset: 0x0070) Scrambling Key Register */
+  __IO uint32_t SECUMOD_RAMACC;   /**< \brief (Secumod Offset: 0x0074) RAM Access Rights Register */
+  __IO uint32_t SECUMOD_RAMACCSR; /**< \brief (Secumod Offset: 0x0078) RAM Access Rights Status Register */
+  __IO uint32_t SECUMOD_BMPR;     /**< \brief (Secumod Offset: 0x007C) Backup Mode Protection Register */
+  __IO uint32_t SECUMOD_NMPR;     /**< \brief (Secumod Offset: 0x0080) Normal Mode Protection Register */
+  __O  uint32_t SECUMOD_NIEPR;    /**< \brief (Secumod Offset: 0x0084) Normal Interrupt Enable Protection Register */
+  __O  uint32_t SECUMOD_NIDPR;    /**< \brief (Secumod Offset: 0x0088) Normal Interrupt Disable Protection Register */
+  __I  uint32_t SECUMOD_NIMPR;    /**< \brief (Secumod Offset: 0x008C) Normal Interrupt Mask Protection Register */
+  __IO uint32_t SECUMOD_WKPR;     /**< \brief (Secumod Offset: 0x0090) Wake Up Protection Register */
+} Secumod;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SECUMOD_CR : (SECUMOD Offset: 0x0000) Control Register -------- */
+#define SECUMOD_CR_BACKUP (0x1u << 0) /**< \brief (SECUMOD_CR) Backup Mode */
+#define SECUMOD_CR_NORMAL (0x1u << 1) /**< \brief (SECUMOD_CR) Normal Mode */
+#define SECUMOD_CR_SWPROT (0x1u << 2) /**< \brief (SECUMOD_CR) Software Protection */
+#define SECUMOD_CR_NIMP_EN_Pos 3
+#define SECUMOD_CR_NIMP_EN_Msk (0x3u << SECUMOD_CR_NIMP_EN_Pos) /**< \brief (SECUMOD_CR) Non-Imprinting Enable */
+#define SECUMOD_CR_NIMP_EN(value) ((SECUMOD_CR_NIMP_EN_Msk & ((value) << SECUMOD_CR_NIMP_EN_Pos)))
+#define SECUMOD_CR_NIMP_EN_DISABLE (0x2u << 3) /**< \brief (SECUMOD_CR) Non-imprinting mechanism is disabled (default) */
+#define SECUMOD_CR_NIMP_EN_ENABLE  (0x1u << 3) /**< \brief (SECUMOD_CR) Non-imprinting mechanism is authorized to start when the required conditions are met */
+#define SECUMOD_CR_AUTOBKP_Pos 5
+#define SECUMOD_CR_AUTOBKP_Msk (0x3u << SECUMOD_CR_AUTOBKP_Pos) /**< \brief (SECUMOD_CR) Automatic Normal to Backup Mode Switching */
+#define SECUMOD_CR_AUTOBKP(value) ((SECUMOD_CR_AUTOBKP_Msk & ((value) << SECUMOD_CR_AUTOBKP_Pos)))
+#define SECUMOD_CR_AUTOBKP_SW_SWITCH   (0x2u << 3) /**< \brief (SECUMOD_CR) When in Normal mode, software must switch to Backup mode before powering down the core */
+#define SECUMOD_CR_AUTOBKP_AUTO_SWITCH (0x1u << 3) /**< \brief (SECUMOD_CR) When in Normal mode, the power down of the core supply will automatically switch the mode to Backup mode, simultaneously with core to backup isolation barrier activation. (default) */
+#define SECUMOD_CR_SCRAMB_Pos 9
+#define SECUMOD_CR_SCRAMB_Msk (0x3u << SECUMOD_CR_SCRAMB_Pos) /**< \brief (SECUMOD_CR) Memory Scrambling Enable */
+#define SECUMOD_CR_SCRAMB(value) ((SECUMOD_CR_SCRAMB_Msk & ((value) << SECUMOD_CR_SCRAMB_Pos)))
+#define SECUMOD_CR_SCRAMB_DISABLE (0x2u << 3) /**< \brief (SECUMOD_CR) Memories are not scrambled */
+#define SECUMOD_CR_SCRAMB_ENABLE  (0x1u << 3) /**< \brief (SECUMOD_CR) Memories are scrambled (default) */
+#define SECUMOD_CR_KEY_Pos 16
+#define SECUMOD_CR_KEY_Msk (0xffffu << SECUMOD_CR_KEY_Pos) /**< \brief (SECUMOD_CR) Password */
+#define SECUMOD_CR_KEY(value) ((SECUMOD_CR_KEY_Msk & ((value) << SECUMOD_CR_KEY_Pos)))
+#define   SECUMOD_CR_KEY_TOGGLE (SECUMOD_CR_KEY(0x89CAu))
+/* -------- SECUMOD_SYSR : (SECUMOD Offset: 0x0004) System Status Register -------- */
+#define SECUMOD_SYSR_ERASE_DONE (0x1u << 0) /**< \brief (SECUMOD_SYSR) Erasable Memories State (RW) */
+#define SECUMOD_SYSR_ERASE_ON (0x1u << 1) /**< \brief (SECUMOD_SYSR) Erase Process Ongoing (RO) */
+#define SECUMOD_SYSR_BACKUP (0x1u << 2) /**< \brief (SECUMOD_SYSR) Backup Mode (RO) */
+#define SECUMOD_SYSR_SWKUP (0x1u << 3) /**< \brief (SECUMOD_SYSR) SWKUP State (RO) */
+#define SECUMOD_SYSR_NIMP_EN (0x1u << 5) /**< \brief (SECUMOD_SYSR) Non-Imprinting Enabled (RO) */
+#define SECUMOD_SYSR_AUTOBKP (0x1u << 6) /**< \brief (SECUMOD_SYSR) Automatic Backup Mode Enabled (RO) */
+#define SECUMOD_SYSR_SCRAMB (0x1u << 7) /**< \brief (SECUMOD_SYSR) Scrambling Enabled (RO) */
+/* -------- SECUMOD_SR : (SECUMOD Offset: 0x0008) Status Register -------- */
+#define SECUMOD_SR_SHLDM (0x1u << 0) /**< \brief (SECUMOD_SR) Shield Monitor */
+#define SECUMOD_SR_DBLFM (0x1u << 1) /**< \brief (SECUMOD_SR) Double Frequency Monitor */
+#define SECUMOD_SR_TST (0x1u << 2) /**< \brief (SECUMOD_SR) Test Pin Monitor */
+#define SECUMOD_SR_JTAG (0x1u << 3) /**< \brief (SECUMOD_SR) JTAG Pins Monitor */
+#define SECUMOD_SR_MCKM (0x1u << 5) /**< \brief (SECUMOD_SR) Master Clock Monitor */
+#define SECUMOD_SR_TPML (0x1u << 6) /**< \brief (SECUMOD_SR) Low Temperature Monitor */
+#define SECUMOD_SR_TPMH (0x1u << 7) /**< \brief (SECUMOD_SR) High Temperature Monitor */
+#define SECUMOD_SR_VDDBUL (0x1u << 10) /**< \brief (SECUMOD_SR) Low VDDBU Voltage Monitor */
+#define SECUMOD_SR_VDDBUH (0x1u << 11) /**< \brief (SECUMOD_SR) High VDDBU Voltage Monitor */
+#define SECUMOD_SR_VDDCOREL (0x1u << 12) /**< \brief (SECUMOD_SR) Low VDDCORE Voltage Monitor */
+#define SECUMOD_SR_VDDCOREH (0x1u << 13) /**< \brief (SECUMOD_SR) High VDDCORE Voltage Monitor */
+#define SECUMOD_SR_DET0 (0x1u << 16) /**< \brief (SECUMOD_SR) PIOBU Intrusion Detector */
+#define SECUMOD_SR_DET1 (0x1u << 17) /**< \brief (SECUMOD_SR) PIOBU Intrusion Detector */
+#define SECUMOD_SR_DET2 (0x1u << 18) /**< \brief (SECUMOD_SR) PIOBU Intrusion Detector */
+#define SECUMOD_SR_DET3 (0x1u << 19) /**< \brief (SECUMOD_SR) PIOBU Intrusion Detector */
+#define SECUMOD_SR_DET4 (0x1u << 20) /**< \brief (SECUMOD_SR) PIOBU Intrusion Detector */
+#define SECUMOD_SR_DET5 (0x1u << 21) /**< \brief (SECUMOD_SR) PIOBU Intrusion Detector */
+#define SECUMOD_SR_DET6 (0x1u << 22) /**< \brief (SECUMOD_SR) PIOBU Intrusion Detector */
+#define SECUMOD_SR_DET7 (0x1u << 23) /**< \brief (SECUMOD_SR) PIOBU Intrusion Detector */
+/* -------- SECUMOD_ASR : (SECUMOD Offset: 0x000C) Auxiliary Status Register -------- */
+#define SECUMOD_ASR_MCKM_LO (0x1u << 0) /**< \brief (SECUMOD_ASR) Low frequency limit reached is the cause of MCKM flag in SECUMOD_SR. */
+#define SECUMOD_ASR_MCKM_HI (0x1u << 1) /**< \brief (SECUMOD_ASR) High frequency limit reached is the cause of MCKM flag in SECUMOD_SR. */
+#define SECUMOD_ASR_JTAG (0x1u << 4) /**< \brief (SECUMOD_ASR) JTAGSEL, CA5 tap response or CA5 debug acknowledge is the cause of JTAG flag in SECUMOD_SR. */
+#define SECUMOD_ASR_TCK (0x1u << 5) /**< \brief (SECUMOD_ASR) TCK/TMS activity detected is the cause of JTAG flag in SECUMOD_SR. */
+#define SECUMOD_ASR_BULO (0x1u << 6) /**< \brief (SECUMOD_ASR) VDDBU low alarm detected is the cause of VDDBUL flag in SECUMOD_SR. */
+#define SECUMOD_ASR_PSWLO (0x1u << 7) /**< \brief (SECUMOD_ASR) VDDANA (used as secondary LDO power source through backup powerswitch) low alarm detected is the cause of VDDBUL flag in SECUMOD_SR. Refer to backup supply strategy described in product datasheet. */
+#define SECUMOD_ASR_BUHI (0x1u << 8) /**< \brief (SECUMOD_ASR) VDDBU high alarm detected is the cause of VDDBUH flag in SECUMOD_SR. */
+#define SECUMOD_ASR_PSWHI (0x1u << 9) /**< \brief (SECUMOD_ASR) VDDANA (used as secondary LDO power source through backup powerswitch) low alarm detected is the cause of VDDBUL flag in SECUMOD_SR. Refer to backup supply strategy described in product datasheet. */
+/* -------- SECUMOD_SCR : (SECUMOD Offset: 0x0010) Status Clear Register -------- */
+#define SECUMOD_SCR_SHLDM (0x1u << 0) /**< \brief (SECUMOD_SCR) Shield Monitor */
+#define SECUMOD_SCR_DBLFM (0x1u << 1) /**< \brief (SECUMOD_SCR) Double Frequency Monitor */
+#define SECUMOD_SCR_TST (0x1u << 2) /**< \brief (SECUMOD_SCR) Test Pin Monitor */
+#define SECUMOD_SCR_JTAG (0x1u << 3) /**< \brief (SECUMOD_SCR) JTAG Pins Monitor */
+#define SECUMOD_SCR_MCKM (0x1u << 5) /**< \brief (SECUMOD_SCR) Master Clock Monitor */
+#define SECUMOD_SCR_TPML (0x1u << 6) /**< \brief (SECUMOD_SCR) Low Temperature Monitor */
+#define SECUMOD_SCR_TPMH (0x1u << 7) /**< \brief (SECUMOD_SCR) High Temperature Monitor */
+#define SECUMOD_SCR_VDDBUL (0x1u << 10) /**< \brief (SECUMOD_SCR) Low VDDBU Voltage Monitor */
+#define SECUMOD_SCR_VDDBUH (0x1u << 11) /**< \brief (SECUMOD_SCR) High VDDBU Voltage Monitor */
+#define SECUMOD_SCR_VDDCOREL (0x1u << 12) /**< \brief (SECUMOD_SCR) Low VDDCORE Voltage Monitor */
+#define SECUMOD_SCR_VDDCOREH (0x1u << 13) /**< \brief (SECUMOD_SCR) High VDDCORE Voltage Monitor */
+#define SECUMOD_SCR_DET0 (0x1u << 16) /**< \brief (SECUMOD_SCR) PIOBU Intrusion Detector */
+#define SECUMOD_SCR_DET1 (0x1u << 17) /**< \brief (SECUMOD_SCR) PIOBU Intrusion Detector */
+#define SECUMOD_SCR_DET2 (0x1u << 18) /**< \brief (SECUMOD_SCR) PIOBU Intrusion Detector */
+#define SECUMOD_SCR_DET3 (0x1u << 19) /**< \brief (SECUMOD_SCR) PIOBU Intrusion Detector */
+#define SECUMOD_SCR_DET4 (0x1u << 20) /**< \brief (SECUMOD_SCR) PIOBU Intrusion Detector */
+#define SECUMOD_SCR_DET5 (0x1u << 21) /**< \brief (SECUMOD_SCR) PIOBU Intrusion Detector */
+#define SECUMOD_SCR_DET6 (0x1u << 22) /**< \brief (SECUMOD_SCR) PIOBU Intrusion Detector */
+#define SECUMOD_SCR_DET7 (0x1u << 23) /**< \brief (SECUMOD_SCR) PIOBU Intrusion Detector */
+/* -------- SECUMOD_RAMRDY : (SECUMOD Offset: 0x0014) RAM Access Ready Register -------- */
+#define SECUMOD_RAMRDY_READY (0x1u << 0) /**< \brief (SECUMOD_RAMRDY) Ready for system access flag */
+/* -------- SECUMOD_PIOBU[8] : (SECUMOD Offset: 0x0018) PIO Backup Register -------- */
+#define SECUMOD_PIOBU_AFV_Pos 0
+#define SECUMOD_PIOBU_AFV_Msk (0xfu << SECUMOD_PIOBU_AFV_Pos) /**< \brief (SECUMOD_PIOBU[8]) PIOBU Alarm Filter Value */
+#define SECUMOD_PIOBU_AFV_0   (0x0u << 0) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 0 */
+#define SECUMOD_PIOBU_AFV_2   (0x1u << 0) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 2 */
+#define SECUMOD_PIOBU_AFV_4   (0x2u << 0) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 4 */
+#define SECUMOD_PIOBU_AFV_8   (0x3u << 0) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 8 */
+#define SECUMOD_PIOBU_AFV_16  (0x4u << 0) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 16 */
+#define SECUMOD_PIOBU_AFV_32  (0x5u << 0) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 32 */
+#define SECUMOD_PIOBU_AFV_64  (0x6u << 0) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 64 */
+#define SECUMOD_PIOBU_AFV_128 (0x7u << 0) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 128 */
+#define SECUMOD_PIOBU_AFV_256 (0x8u << 0) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 256 */
+#define SECUMOD_PIOBU_AFV_512 (0x9u << 0) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 512 */
+#define SECUMOD_PIOBU_AFV_512 (0x9u << 0) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 512 */
+#define SECUMOD_PIOBU_AFV(value) ((SECUMOD_PIOBU_AFV_Msk & ((value) << SECUMOD_PIOBU_AFV_Pos)))
+#define SECUMOD_PIOBU_RFV_Pos 4
+#define SECUMOD_PIOBU_RFV_Msk (0xFu << SECUMOD_PIOBU_RFV_Pos) /**< \brief (SECUMOD_PIOBU) PIOBU Reset Filter Value */
+#define SECUMOD_PIOBU_RFV_0   (0x0u << 4) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 0 */
+#define SECUMOD_PIOBU_RFV_2   (0x1u << 4) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 2 */
+#define SECUMOD_PIOBU_RFV_4   (0x2u << 4) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 4 */
+#define SECUMOD_PIOBU_RFV_8   (0x3u << 4) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 8 */
+#define SECUMOD_PIOBU_RFV_16  (0x4u << 4) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 16 */
+#define SECUMOD_PIOBU_RFV_32  (0x5u << 4) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 32 */
+#define SECUMOD_PIOBU_RFV_64  (0x6u << 4) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 64 */
+#define SECUMOD_PIOBU_RFV_128 (0x7u << 4) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 128 */
+#define SECUMOD_PIOBU_RFV_256 (0x8u << 4) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 256 */
+#define SECUMOD_PIOBU_RFV_512 (0x9u << 4) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 512 */
+#define SECUMOD_PIOBU_RFV_512 (0x9u << 4) /**< \brief (SECUMOD_PIOBU) Maximun Counter Value is 512 */
+#define SECUMOD_PIOBU_RFV(value) ((SECUMOD_PIOBU_RFV_Msk & ((value) << SECUMOD_PIOBU_RFV_Pos)))
+#define SECUMOD_PIOBU_OUTPUT (0x1u << 8) /**< \brief (SECUMOD_PIOBU[8]) Configure I/O Line in Input/Output */
+#define SECUMOD_PIOBU_OUTPUT_PURE_INPUT     (0x0u << 8) /**< \brief (SECUMOD_PIOBU) The I/O is a pure input */
+#define SECUMOD_PIOBU_OUTPUT_ENABLED_OUTPUT (0x1u << 8) /**< \brief (SECUMOD_PIOBU) The I/O is enabled in output */
+#define SECUMOD_PIOBU_PIO_SOD (0x1u << 9) /**< \brief (SECUMOD_PIOBU[8]) Set/Clear the I/O Line when configured in Output Mode (OUTPUT =1) */
+#define SECUMOD_PIOBU_PIO_PDS (0x1u << 10) /**< \brief (SECUMOD_PIOBU[8]) Level on the Pin in Input Mode (OUTPUT = 0) (Read-only) */
+#define SECUMOD_PIOBU_PULLUP_Pos 12
+#define SECUMOD_PIOBU_PULLUP_Msk (0x3u << SECUMOD_PIOBU_PULLUP_Pos) /**< \brief (SECUMOD_PIOBU[8]) Programmable Pull-up State */
+#define SECUMOD_PIOBU_PULLUP(value) ((SECUMOD_PIOBU_PULLUP_Msk & ((value) << SECUMOD_PIOBU_PULLUP_Pos)))
+#define SECUMOD_PIOBU_PULLUP_NONE      (0x0u << 12) /**< \brief (SECUMOD_PIOBU) No pull-up/pull-down connected */
+#define SECUMOD_PIOBU_PULLUP_PULL_UP   (0x1u << 12) /**< \brief (SECUMOD_PIOBU) Pull-up connected */
+#define SECUMOD_PIOBU_PULLUP_PULL_DOWN (0x2u << 12) /**< \brief (SECUMOD_PIOBU) Pull-down connected */
+#define SECUMOD_PIOBU_SCHEDULE (0x1u << 14) /**< \brief (SECUMOD_PIOBU[8]) Pull-up/Down Scheduled */
+#define SECUMOD_PIOBU_SWITCH (0x1u << 15) /**< \brief (SECUMOD_PIOBU[8]) Switch State for Intrusion Detection */
+#define SECUMOD_PIOBU_DYNSTAT (0x1u << 20) /**< \brief (SECUMOD_PIOBU[8]) Switch for Static or Dynamic Detection Intrusion */
+#define SECUMOD_PIOBU_FILTER3_5 (0x1u << 21) /**< \brief (SECUMOD_PIOBU[8]) Filter for Dynamic Signatures Input */
+/* -------- SECUMOD_VBUFR : (SECUMOD Offset: 0x0058) VDDBU Filter Register -------- */
+#define SECUMOD_VBUFR_VDDBUFV_Pos 0
+#define SECUMOD_VBUFR_VDDBUFV_Msk (0x7u << SECUMOD_VBUFR_VDDBUFV_Pos) /**< \brief (SECUMOD_VBUFR) VDDBU Filter Value */
+#define SECUMOD_VBUFR_VDDBUFV(value) ((SECUMOD_VBUFR_VDDBUFV_Msk & ((value) << SECUMOD_VBUFR_VDDBUFV_Pos)))
+/* -------- SECUMOD_VCOREFR : (SECUMOD Offset: 0x0064) VDDCORE Filter Register -------- */
+#define SECUMOD_VCOREFR_VDDCORE_DBTV_Pos 0
+#define SECUMOD_VCOREFR_VDDCORE_DBTV_Msk (0x1fffu << SECUMOD_VCOREFR_VDDCORE_DBTV_Pos) /**< \brief (SECUMOD_VCOREFR) VDDCORE Programmable Debouncing Time Value */
+#define SECUMOD_VCOREFR_VDDCORE_DBTV(value) ((SECUMOD_VCOREFR_VDDCORE_DBTV_Msk & ((value) << SECUMOD_VCOREFR_VDDCORE_DBTV_Pos)))
+/* -------- SECUMOD_JTAGCR : (SECUMOD Offset: 0x0068) JTAG Protection Control Register -------- */
+#define SECUMOD_JTAGCR_FNTRST (0x1u << 0) /**< \brief (SECUMOD_JTAGCR) Force NTRST */
+#define SECUMOD_JTAGCR_CA5_DEBUG_MODE_Pos 1
+#define SECUMOD_JTAGCR_CA5_DEBUG_MODE_Msk (0x7u << SECUMOD_JTAGCR_CA5_DEBUG_MODE_Pos) /**< \brief (SECUMOD_JTAGCR) Cortex-A5 Invasive/Non-Invasive Secure/Non-Secure Debug Permissions */
+#define SECUMOD_JTAGCR_CA5_DEBUG_MODE(value) ((SECUMOD_JTAGCR_CA5_DEBUG_MODE_Msk & ((value) << SECUMOD_JTAGCR_CA5_DEBUG_MODE_Pos)))
+#define SECUMOD_JTAGCR_CA5_DEBUG_MODE_NO_DEBUG    (0x0u << 1) /**< \brief (SECUMOD_JTAGCR) No debug */
+#define SECUMOD_JTAGCR_CA5_DEBUG_MODE_NINS        (0x1u << 1) /**< \brief (SECUMOD_JTAGCR) Non-Invasive Non-Secure */
+#define SECUMOD_JTAGCR_CA5_DEBUG_MODE_FULL_NS     (0x2u << 1) /**< \brief (SECUMOD_JTAGCR) Full Non-Secure (Invasive and Non-Invasive) */
+#define SECUMOD_JTAGCR_CA5_DEBUG_MODE_FULL_NS_NIS (0x3u << 1) /**< \brief (SECUMOD_JTAGCR) Full Non-Secure + Non-Invasive Secure */
+#define SECUMOD_JTAGCR_CA5_DEBUG_MODE_FULL_DEBUG  (0x4u << 1) /**< \brief (SECUMOD_JTAGCR) Full debug allowed */
+#define SECUMOD_JTAGCR_CA5_DEBUG_MON (0x1u << 4) /**< \brief (SECUMOD_JTAGCR) Cortex-A5 Debug Acknowledge (DBGACK) Monitoring */
+/* -------- SECUMOD_DYSTUNE : (SECUMOD Offset: 0x006C) Dynamic Signatures Tuning Register -------- */
+#define SECUMOD_DYSTUNE_RX_ERROR_THRESHOLD_Pos 0
+#define SECUMOD_DYSTUNE_RX_ERROR_THRESHOLD_Msk (0x7fu << SECUMOD_DYSTUNE_RX_ERROR_THRESHOLD_Pos) /**< \brief (SECUMOD_DYSTUNE) Error Detection Threshold */
+#define SECUMOD_DYSTUNE_RX_ERROR_THRESHOLD(value) ((SECUMOD_DYSTUNE_RX_ERROR_THRESHOLD_Msk & ((value) << SECUMOD_DYSTUNE_RX_ERROR_THRESHOLD_Pos)))
+#define SECUMOD_DYSTUNE_NOPA (0x1u << 7) /**< \brief (SECUMOD_DYSTUNE) No Periodic Alarm */
+#define SECUMOD_DYSTUNE_RX_OK_CORREL_NUMBER_Pos 8
+#define SECUMOD_DYSTUNE_RX_OK_CORREL_NUMBER_Msk (0xffu << SECUMOD_DYSTUNE_RX_OK_CORREL_NUMBER_Pos) /**< \brief (SECUMOD_DYSTUNE) Error Counter Reset Threshold */
+#define SECUMOD_DYSTUNE_RX_OK_CORREL_NUMBER(value) ((SECUMOD_DYSTUNE_RX_OK_CORREL_NUMBER_Msk & ((value) << SECUMOD_DYSTUNE_RX_OK_CORREL_NUMBER_Pos)))
+#define SECUMOD_DYSTUNE_PERIOD_Pos 16
+#define SECUMOD_DYSTUNE_PERIOD_Msk (0xffffu << SECUMOD_DYSTUNE_PERIOD_Pos) /**< \brief (SECUMOD_DYSTUNE) Signature Clock Period */
+#define SECUMOD_DYSTUNE_PERIOD(value) ((SECUMOD_DYSTUNE_PERIOD_Msk & ((value) << SECUMOD_DYSTUNE_PERIOD_Pos)))
+/* -------- SECUMOD_SCRKEY : (SECUMOD Offset: 0x0070) Scrambling Key Register -------- */
+#define SECUMOD_SCRKEY_SCRKEY_Pos 0
+#define SECUMOD_SCRKEY_SCRKEY_Msk (0xffffffffu << SECUMOD_SCRKEY_SCRKEY_Pos) /**< \brief (SECUMOD_SCRKEY) Scrambling Key Value */
+#define SECUMOD_SCRKEY_SCRKEY(value) ((SECUMOD_SCRKEY_SCRKEY_Msk & ((value) << SECUMOD_SCRKEY_SCRKEY_Pos)))
+/* -------- SECUMOD_RAMACC : (SECUMOD Offset: 0x0074) RAM Access Rights Register -------- */
+#define SECUMOD_RAMACC_RW0_Pos 0
+#define SECUMOD_RAMACC_RW0_Msk (0x3u << SECUMOD_RAMACC_RW0_Pos) /**< \brief (SECUMOD_RAMACC) Access right for RAM region [0; 1 Kbyte] */
+#define SECUMOD_RAMACC_RW0(value) ((SECUMOD_RAMACC_RW0_Msk & ((value) << SECUMOD_RAMACC_RW0_Pos)))
+#define SECUMOD_RAMACC_RW1_Pos 2
+#define SECUMOD_RAMACC_RW1_Msk (0x3u << SECUMOD_RAMACC_RW1_Pos) /**< \brief (SECUMOD_RAMACC) Access right for RAM region [1 Kbyte; 2 Kbytes] */
+#define SECUMOD_RAMACC_RW1(value) ((SECUMOD_RAMACC_RW1_Msk & ((value) << SECUMOD_RAMACC_RW1_Pos)))
+#define SECUMOD_RAMACC_RW2_Pos 4
+#define SECUMOD_RAMACC_RW2_Msk (0x3u << SECUMOD_RAMACC_RW2_Pos) /**< \brief (SECUMOD_RAMACC) Access right for RAM region [2 Kbytes; 3 Kbytes] */
+#define SECUMOD_RAMACC_RW2(value) ((SECUMOD_RAMACC_RW2_Msk & ((value) << SECUMOD_RAMACC_RW2_Pos)))
+#define SECUMOD_RAMACC_RW3_Pos 6
+#define SECUMOD_RAMACC_RW3_Msk (0x3u << SECUMOD_RAMACC_RW3_Pos) /**< \brief (SECUMOD_RAMACC) Access right for RAM region [3 Kbytes; 4 Kbytes] */
+#define SECUMOD_RAMACC_RW3(value) ((SECUMOD_RAMACC_RW3_Msk & ((value) << SECUMOD_RAMACC_RW3_Pos)))
+#define SECUMOD_RAMACC_RW4_Pos 8
+#define SECUMOD_RAMACC_RW4_Msk (0x3u << SECUMOD_RAMACC_RW4_Pos) /**< \brief (SECUMOD_RAMACC) Access right for RAM region [4 Kbytes; 5 Kbytes] */
+#define SECUMOD_RAMACC_RW4(value) ((SECUMOD_RAMACC_RW4_Msk & ((value) << SECUMOD_RAMACC_RW4_Pos)))
+#define SECUMOD_RAMACC_RW5_Pos 10
+#define SECUMOD_RAMACC_RW5_Msk (0x3u << SECUMOD_RAMACC_RW5_Pos) /**< \brief (SECUMOD_RAMACC) Access right for RAM region [5 Kbytes; 6 Kbytes] (register bank BUREG256b) */
+#define SECUMOD_RAMACC_RW5(value) ((SECUMOD_RAMACC_RW5_Msk & ((value) << SECUMOD_RAMACC_RW5_Pos)))
+#define SECUMOD_RAMACC_RWx_Pos(x)          ( 2 * (x) )
+#define SECUMOD_RAMACC_RWx_Msk(x)          ( 0x3u << ( 2 * (x) ) ) /**< \brief (SECUMOD_RAMACC) Access right for RAM region */
+#define SECUMOD_RAMACC_RWx_NO_ACCESS(x)    ( 0x0u << ( 2 * (x) ) ) /**< \brief (SECUMOD_RAMACC) No access allowed */
+#define SECUMOD_RAMACC_RWx_WR_ACCESS(x)    ( 0x1u << ( 2 * (x) ) ) /**< \brief (SECUMOD_RAMACC) Only write access allowed */
+#define SECUMOD_RAMACC_RWx_RD_ACCESS(x)    ( 0x2u << ( 2 * (x) ) ) /**< \brief (SECUMOD_RAMACC) Only read access allowed */
+#define SECUMOD_RAMACC_RWx_RD_WR_ACCESS(x) ( 0x3u << ( 2 * (x) ) ) /**< \brief (SECUMOD_RAMACC) Read and write access allowed */
+/* -------- SECUMOD_RAMACCSR : (SECUMOD Offset: 0x0078) RAM Access Rights Status Register -------- */
+#define SECUMOD_RAMACCSR_RW0_Pos 0
+#define SECUMOD_RAMACCSR_RW0_Msk (0x3u << SECUMOD_RAMACCSR_RW0_Pos) /**< \brief (SECUMOD_RAMACCSR) Access right status for RAM region [0; 1 Kbyte] */
+#define SECUMOD_RAMACCSR_RW0(value) ((SECUMOD_RAMACCSR_RW0_Msk & ((value) << SECUMOD_RAMACCSR_RW0_Pos)))
+#define SECUMOD_RAMACCSR_RW1_Pos 2
+#define SECUMOD_RAMACCSR_RW1_Msk (0x3u << SECUMOD_RAMACCSR_RW1_Pos) /**< \brief (SECUMOD_RAMACCSR) Access right status for RAM region [1 Kbytes; 2 Kbytes] */
+#define SECUMOD_RAMACCSR_RW1(value) ((SECUMOD_RAMACCSR_RW1_Msk & ((value) << SECUMOD_RAMACCSR_RW1_Pos)))
+#define SECUMOD_RAMACCSR_RW2_Pos 4
+#define SECUMOD_RAMACCSR_RW2_Msk (0x3u << SECUMOD_RAMACCSR_RW2_Pos) /**< \brief (SECUMOD_RAMACCSR) Access right status for RAM region [2 Kbytes; 3 Kbytes] */
+#define SECUMOD_RAMACCSR_RW2(value) ((SECUMOD_RAMACCSR_RW2_Msk & ((value) << SECUMOD_RAMACCSR_RW2_Pos)))
+#define SECUMOD_RAMACCSR_RW3_Pos 6
+#define SECUMOD_RAMACCSR_RW3_Msk (0x3u << SECUMOD_RAMACCSR_RW3_Pos) /**< \brief (SECUMOD_RAMACCSR) Access right status for RAM region [3 Kbytes; 4 Kbytes] */
+#define SECUMOD_RAMACCSR_RW3(value) ((SECUMOD_RAMACCSR_RW3_Msk & ((value) << SECUMOD_RAMACCSR_RW3_Pos)))
+#define SECUMOD_RAMACCSR_RW4_Pos 8
+#define SECUMOD_RAMACCSR_RW4_Msk (0x3u << SECUMOD_RAMACCSR_RW4_Pos) /**< \brief (SECUMOD_RAMACCSR) Access right status for RAM region [4 Kbytes; 5 Kbytes] */
+#define SECUMOD_RAMACCSR_RW4(value) ((SECUMOD_RAMACCSR_RW4_Msk & ((value) << SECUMOD_RAMACCSR_RW4_Pos)))
+#define SECUMOD_RAMACCSR_RW5_Pos 10
+#define SECUMOD_RAMACCSR_RW5_Msk (0x3u << SECUMOD_RAMACCSR_RW5_Pos) /**< \brief (SECUMOD_RAMACCSR) Access right status for RAM region [5 Kbytes; 6 Kbytes] (register bank BUREG256b) */
+#define SECUMOD_RAMACCSR_RW5(value) ((SECUMOD_RAMACCSR_RW5_Msk & ((value) << SECUMOD_RAMACCSR_RW5_Pos)))
+#define SECUMOD_RAMACCSR_RWx_Pos(x)          ( 2 * (x) )
+#define SECUMOD_RAMACCSR_NO_VIOLATION        ( 0x0u ) /**< \brief (SECUMOD_RAMACCSR) No access violation occurred */
+#define SECUMOD_RAMACCSR_W_VIOLATION         ( 0x1u ) /**< \brief (SECUMOD_RAMACCSR) Only write access violation occurred */
+#define SECUMOD_RAMACCSR_R_VIOLATION         ( 0x2u ) /**< \brief (SECUMOD_RAMACCSR) Only read access violation occurred */
+#define SECUMOD_RAMACCSR_RW_VIOLATION        ( 0x3u ) /**< \brief (SECUMOD_RAMACCSR) Read and write access violation occurred */
+/* -------- SECUMOD_BMPR : (SECUMOD Offset: 0x007C) Backup Mode Protection Register -------- */
+#define SECUMOD_BMPR_ALL  (0x00FF0CCFu)
+#define SECUMOD_BMPR_SHLDM (0x1u << 0) /**< \brief (SECUMOD_BMPR) Shield Monitor Protection */
+#define SECUMOD_BMPR_DBLFM (0x1u << 1) /**< \brief (SECUMOD_BMPR) Double Frequency Monitor Protection */
+#define SECUMOD_BMPR_TST (0x1u << 2) /**< \brief (SECUMOD_BMPR) Test Pin Protection */
+#define SECUMOD_BMPR_JTAG (0x1u << 3) /**< \brief (SECUMOD_BMPR) JTAG Pins Protection */
+#define SECUMOD_BMPR_TPML (0x1u << 6) /**< \brief (SECUMOD_BMPR) Low Temperature Monitor Protection */
+#define SECUMOD_BMPR_TPMH (0x1u << 7) /**< \brief (SECUMOD_BMPR) High Temperature Monitor Protection */
+#define SECUMOD_BMPR_VDDBUL (0x1u << 10) /**< \brief (SECUMOD_BMPR) Low VDDBU Voltage Monitor Protection */
+#define SECUMOD_BMPR_VDDBUH (0x1u << 11) /**< \brief (SECUMOD_BMPR) High VDDBU Voltage Monitor Protection */
+#define SECUMOD_BMPR_DET0 (0x1u << 16) /**< \brief (SECUMOD_BMPR) PIOBU Intrusion Detector Protection */
+#define SECUMOD_BMPR_DET1 (0x1u << 17) /**< \brief (SECUMOD_BMPR) PIOBU Intrusion Detector Protection */
+#define SECUMOD_BMPR_DET2 (0x1u << 18) /**< \brief (SECUMOD_BMPR) PIOBU Intrusion Detector Protection */
+#define SECUMOD_BMPR_DET3 (0x1u << 19) /**< \brief (SECUMOD_BMPR) PIOBU Intrusion Detector Protection */
+#define SECUMOD_BMPR_DET4 (0x1u << 20) /**< \brief (SECUMOD_BMPR) PIOBU Intrusion Detector Protection */
+#define SECUMOD_BMPR_DET5 (0x1u << 21) /**< \brief (SECUMOD_BMPR) PIOBU Intrusion Detector Protection */
+#define SECUMOD_BMPR_DET6 (0x1u << 22) /**< \brief (SECUMOD_BMPR) PIOBU Intrusion Detector Protection */
+#define SECUMOD_BMPR_DET7 (0x1u << 23) /**< \brief (SECUMOD_BMPR) PIOBU Intrusion Detector Protection */
+/* -------- SECUMOD_NMPR : (SECUMOD Offset: 0x0080) Normal Mode Protection Register -------- */
+#define SECUMOD_NMPR_ALL  (0x00FF3CEFu)
+#define SECUMOD_NMPR_SHLDM (0x1u << 0) /**< \brief (SECUMOD_NMPR) Shield Monitor Protection */
+#define SECUMOD_NMPR_DBLFM (0x1u << 1) /**< \brief (SECUMOD_NMPR) Double Frequency Monitor Protection */
+#define SECUMOD_NMPR_TST (0x1u << 2) /**< \brief (SECUMOD_NMPR) Test Pin Protection */
+#define SECUMOD_NMPR_JTAG (0x1u << 3) /**< \brief (SECUMOD_NMPR) JTAG Pins Protection */
+#define SECUMOD_NMPR_MCKM (0x1u << 5) /**< \brief (SECUMOD_NMPR) Master Clock Monitor Protection */
+#define SECUMOD_NMPR_TPML (0x1u << 6) /**< \brief (SECUMOD_NMPR) Low Temperature Monitor Protection */
+#define SECUMOD_NMPR_TPMH (0x1u << 7) /**< \brief (SECUMOD_NMPR) High Temperature Monitor Protection */
+#define SECUMOD_NMPR_VDDBUL (0x1u << 10) /**< \brief (SECUMOD_NMPR) Low VDDBU Voltage Monitor Protection */
+#define SECUMOD_NMPR_VDDBUH (0x1u << 11) /**< \brief (SECUMOD_NMPR) High VDDBU Voltage Monitor Protection */
+#define SECUMOD_NMPR_VDDCOREL (0x1u << 12) /**< \brief (SECUMOD_NMPR) Low VDDCORE Voltage Monitor Protection */
+#define SECUMOD_NMPR_VDDCOREH (0x1u << 13) /**< \brief (SECUMOD_NMPR) High VDDCORE Voltage Monitor Protection */
+#define SECUMOD_NMPR_DET0 (0x1u << 16) /**< \brief (SECUMOD_NMPR) PIOBU Intrusion Detector Protection */
+#define SECUMOD_NMPR_DET1 (0x1u << 17) /**< \brief (SECUMOD_NMPR) PIOBU Intrusion Detector Protection */
+#define SECUMOD_NMPR_DET2 (0x1u << 18) /**< \brief (SECUMOD_NMPR) PIOBU Intrusion Detector Protection */
+#define SECUMOD_NMPR_DET3 (0x1u << 19) /**< \brief (SECUMOD_NMPR) PIOBU Intrusion Detector Protection */
+#define SECUMOD_NMPR_DET4 (0x1u << 20) /**< \brief (SECUMOD_NMPR) PIOBU Intrusion Detector Protection */
+#define SECUMOD_NMPR_DET5 (0x1u << 21) /**< \brief (SECUMOD_NMPR) PIOBU Intrusion Detector Protection */
+#define SECUMOD_NMPR_DET6 (0x1u << 22) /**< \brief (SECUMOD_NMPR) PIOBU Intrusion Detector Protection */
+#define SECUMOD_NMPR_DET7 (0x1u << 23) /**< \brief (SECUMOD_NMPR) PIOBU Intrusion Detector Protection */
+/* -------- SECUMOD_NIEPR : (SECUMOD Offset: 0x0084) Normal Interrupt Enable Protection Register -------- */
+#define SECUMOD_NIEPR_ALL  (0x00FF3CEFu)
+#define SECUMOD_NIEPR_SHLDM (0x1u << 0) /**< \brief (SECUMOD_NIEPR) Shield Monitor Protection Interrupt Enable */
+#define SECUMOD_NIEPR_DBLFM (0x1u << 1) /**< \brief (SECUMOD_NIEPR) Double Frequency Monitor Protection Interrupt Enable */
+#define SECUMOD_NIEPR_TST (0x1u << 2) /**< \brief (SECUMOD_NIEPR) Test Pin Protection Interrupt Enable */
+#define SECUMOD_NIEPR_JTAG (0x1u << 3) /**< \brief (SECUMOD_NIEPR) JTAG Pins Protection Interrupt Enable */
+#define SECUMOD_NIEPR_MCKM (0x1u << 5) /**< \brief (SECUMOD_NIEPR) Master Clock Monitor Protection Interrupt Enable */
+#define SECUMOD_NIEPR_TPML (0x1u << 6) /**< \brief (SECUMOD_NIEPR) Low Temperature Monitor Protection Interrupt Enable */
+#define SECUMOD_NIEPR_TPMH (0x1u << 7) /**< \brief (SECUMOD_NIEPR) High Temperature Monitor Protection Interrupt Enable */
+#define SECUMOD_NIEPR_VDDBUL (0x1u << 10) /**< \brief (SECUMOD_NIEPR) Low VDDBU Voltage Monitor Protection Interrupt Enable */
+#define SECUMOD_NIEPR_VDDBUH (0x1u << 11) /**< \brief (SECUMOD_NIEPR) High VDDBU Voltage Monitor Protection Interrupt Enable */
+#define SECUMOD_NIEPR_VDDCOREL (0x1u << 12) /**< \brief (SECUMOD_NIEPR) Low VDDCORE Voltage Monitor Protection Interrupt Enable */
+#define SECUMOD_NIEPR_VDDCOREH (0x1u << 13) /**< \brief (SECUMOD_NIEPR) High VDDCORE Voltage Monitor Protection Interrupt Enable */
+#define SECUMOD_NIEPR_DET0 (0x1u << 16) /**< \brief (SECUMOD_NIEPR) PIOBU Intrusion Detector Protection Interrupt Enable */
+#define SECUMOD_NIEPR_DET1 (0x1u << 17) /**< \brief (SECUMOD_NIEPR) PIOBU Intrusion Detector Protection Interrupt Enable */
+#define SECUMOD_NIEPR_DET2 (0x1u << 18) /**< \brief (SECUMOD_NIEPR) PIOBU Intrusion Detector Protection Interrupt Enable */
+#define SECUMOD_NIEPR_DET3 (0x1u << 19) /**< \brief (SECUMOD_NIEPR) PIOBU Intrusion Detector Protection Interrupt Enable */
+#define SECUMOD_NIEPR_DET4 (0x1u << 20) /**< \brief (SECUMOD_NIEPR) PIOBU Intrusion Detector Protection Interrupt Enable */
+#define SECUMOD_NIEPR_DET5 (0x1u << 21) /**< \brief (SECUMOD_NIEPR) PIOBU Intrusion Detector Protection Interrupt Enable */
+#define SECUMOD_NIEPR_DET6 (0x1u << 22) /**< \brief (SECUMOD_NIEPR) PIOBU Intrusion Detector Protection Interrupt Enable */
+#define SECUMOD_NIEPR_DET7 (0x1u << 23) /**< \brief (SECUMOD_NIEPR) PIOBU Intrusion Detector Protection Interrupt Enable */
+/* -------- SECUMOD_NIDPR : (SECUMOD Offset: 0x0088) Normal Interrupt Disable Protection Register -------- */
+#define SECUMOD_NIDPR_ALL  (0x00FF3CEFu)
+#define SECUMOD_NIDPR_SHLDM (0x1u << 0) /**< \brief (SECUMOD_NIDPR) Shield Monitor Protection Interrupt Disable */
+#define SECUMOD_NIDPR_DBLFM (0x1u << 1) /**< \brief (SECUMOD_NIDPR) Double Frequency Monitor Protection Interrupt Disable */
+#define SECUMOD_NIDPR_TST (0x1u << 2) /**< \brief (SECUMOD_NIDPR) Test Pin Protection Interrupt Disable */
+#define SECUMOD_NIDPR_JTAG (0x1u << 3) /**< \brief (SECUMOD_NIDPR) JTAG Pins Protection Interrupt Disable */
+#define SECUMOD_NIDPR_MCKM (0x1u << 5) /**< \brief (SECUMOD_NIDPR) Master Clock Monitor Protection Interrupt Disable */
+#define SECUMOD_NIDPR_TPML (0x1u << 6) /**< \brief (SECUMOD_NIDPR) Low Temperature Monitor Protection Interrupt Disable */
+#define SECUMOD_NIDPR_TPMH (0x1u << 7) /**< \brief (SECUMOD_NIDPR) High Temperature Monitor Protection Interrupt Disable */
+#define SECUMOD_NIDPR_VDDBUL (0x1u << 10) /**< \brief (SECUMOD_NIDPR) Low VDDBU Voltage Monitor Protection Interrupt Disable */
+#define SECUMOD_NIDPR_VDDBUH (0x1u << 11) /**< \brief (SECUMOD_NIDPR) High VDDBU Voltage Monitor Protection Interrupt Disable */
+#define SECUMOD_NIDPR_VDDCOREL (0x1u << 12) /**< \brief (SECUMOD_NIDPR) Low VDDCORE Voltage Monitor Protection Interrupt Disable */
+#define SECUMOD_NIDPR_VDDCOREH (0x1u << 13) /**< \brief (SECUMOD_NIDPR) High VDDCORE Voltage Monitor Protection Interrupt Disable */
+#define SECUMOD_NIDPR_DET0 (0x1u << 16) /**< \brief (SECUMOD_NIDPR) PIOBU Intrusion Detector Protection Interrupt Disable */
+#define SECUMOD_NIDPR_DET1 (0x1u << 17) /**< \brief (SECUMOD_NIDPR) PIOBU Intrusion Detector Protection Interrupt Disable */
+#define SECUMOD_NIDPR_DET2 (0x1u << 18) /**< \brief (SECUMOD_NIDPR) PIOBU Intrusion Detector Protection Interrupt Disable */
+#define SECUMOD_NIDPR_DET3 (0x1u << 19) /**< \brief (SECUMOD_NIDPR) PIOBU Intrusion Detector Protection Interrupt Disable */
+#define SECUMOD_NIDPR_DET4 (0x1u << 20) /**< \brief (SECUMOD_NIDPR) PIOBU Intrusion Detector Protection Interrupt Disable */
+#define SECUMOD_NIDPR_DET5 (0x1u << 21) /**< \brief (SECUMOD_NIDPR) PIOBU Intrusion Detector Protection Interrupt Disable */
+#define SECUMOD_NIDPR_DET6 (0x1u << 22) /**< \brief (SECUMOD_NIDPR) PIOBU Intrusion Detector Protection Interrupt Disable */
+#define SECUMOD_NIDPR_DET7 (0x1u << 23) /**< \brief (SECUMOD_NIDPR) PIOBU Intrusion Detector Protection Interrupt Disable */
+/* -------- SECUMOD_NIMPR : (SECUMOD Offset: 0x008C) Normal Interrupt Mask Protection Register -------- */
+#define SECUMOD_NIMPR_ALL  (0x00FF3CEFu)
+#define SECUMOD_NIMPR_SHLDM (0x1u << 0) /**< \brief (SECUMOD_NIMPR) Shield Monitor Protection Interrupt Mask */
+#define SECUMOD_NIMPR_DBLFM (0x1u << 1) /**< \brief (SECUMOD_NIMPR) Double Frequency Monitor Protection Interrupt Mask */
+#define SECUMOD_NIMPR_TST (0x1u << 2) /**< \brief (SECUMOD_NIMPR) Test Pin Protection Interrupt Mask */
+#define SECUMOD_NIMPR_JTAG (0x1u << 3) /**< \brief (SECUMOD_NIMPR) JTAG Pins Protection Interrupt Mask */
+#define SECUMOD_NIMPR_MCKM (0x1u << 5) /**< \brief (SECUMOD_NIMPR) Master Clock Monitor Protection Interrupt Mask */
+#define SECUMOD_NIMPR_TPML (0x1u << 6) /**< \brief (SECUMOD_NIMPR) Low Temperature Monitor Protection Interrupt Mask */
+#define SECUMOD_NIMPR_TPMH (0x1u << 7) /**< \brief (SECUMOD_NIMPR) High Temperature Monitor Protection Interrupt Mask */
+#define SECUMOD_NIMPR_VDDBUL (0x1u << 10) /**< \brief (SECUMOD_NIMPR) Low VDDBU Voltage Monitor Protection Interrupt Mask */
+#define SECUMOD_NIMPR_VDDBUH (0x1u << 11) /**< \brief (SECUMOD_NIMPR) High VDDBU Voltage Monitor Protection Interrupt Mask */
+#define SECUMOD_NIMPR_VDDCOREL (0x1u << 12) /**< \brief (SECUMOD_NIMPR) Low VDDCORE Voltage Monitor Protection Interrupt Mask */
+#define SECUMOD_NIMPR_VDDCOREH (0x1u << 13) /**< \brief (SECUMOD_NIMPR) High VDDCORE Voltage Monitor Protection Interrupt Mask */
+#define SECUMOD_NIMPR_DET0 (0x1u << 16) /**< \brief (SECUMOD_NIMPR) PIOBU Intrusion Detector Protection Interrupt Mask */
+#define SECUMOD_NIMPR_DET1 (0x1u << 17) /**< \brief (SECUMOD_NIMPR) PIOBU Intrusion Detector Protection Interrupt Mask */
+#define SECUMOD_NIMPR_DET2 (0x1u << 18) /**< \brief (SECUMOD_NIMPR) PIOBU Intrusion Detector Protection Interrupt Mask */
+#define SECUMOD_NIMPR_DET3 (0x1u << 19) /**< \brief (SECUMOD_NIMPR) PIOBU Intrusion Detector Protection Interrupt Mask */
+#define SECUMOD_NIMPR_DET4 (0x1u << 20) /**< \brief (SECUMOD_NIMPR) PIOBU Intrusion Detector Protection Interrupt Mask */
+#define SECUMOD_NIMPR_DET5 (0x1u << 21) /**< \brief (SECUMOD_NIMPR) PIOBU Intrusion Detector Protection Interrupt Mask */
+#define SECUMOD_NIMPR_DET6 (0x1u << 22) /**< \brief (SECUMOD_NIMPR) PIOBU Intrusion Detector Protection Interrupt Mask */
+#define SECUMOD_NIMPR_DET7 (0x1u << 23) /**< \brief (SECUMOD_NIMPR) PIOBU Intrusion Detector Protection Interrupt Mask */
+/* -------- SECUMOD_WKPR : (SECUMOD Offset: 0x0090) Wake Up Protection Register -------- */
+#define SECUMOD_WKPR_ALL (0x00FF3CEFu)
+#define SECUMOD_WKPR_SHLDM (0x1u << 0) /**< \brief (SECUMOD_WKPR) Shield Monitor Protection */
+#define SECUMOD_WKPR_DBLFM (0x1u << 1) /**< \brief (SECUMOD_WKPR) Double Frequency Monitor Protection */
+#define SECUMOD_WKPR_TST (0x1u << 2) /**< \brief (SECUMOD_WKPR) Test Pin Protection */
+#define SECUMOD_WKPR_JTAG (0x1u << 3) /**< \brief (SECUMOD_WKPR) JTAG Pins Protection */
+#define SECUMOD_WKPR_TPML (0x1u << 6) /**< \brief (SECUMOD_WKPR) Low Temperature Monitor Protection */
+#define SECUMOD_WKPR_TPMH (0x1u << 7) /**< \brief (SECUMOD_WKPR) High Temperature Monitor Protection */
+#define SECUMOD_WKPR_VDDBUL (0x1u << 10) /**< \brief (SECUMOD_WKPR) Low VDDBU Voltage Monitor Protection */
+#define SECUMOD_WKPR_VDDBUH (0x1u << 11) /**< \brief (SECUMOD_WKPR) High VDDBU Voltage Monitor Protection */
+#define SECUMOD_WKPR_DET0 (0x1u << 16) /**< \brief (SECUMOD_WKPR) PIOBU Intrusion Detector Protection */
+#define SECUMOD_WKPR_DET1 (0x1u << 17) /**< \brief (SECUMOD_WKPR) PIOBU Intrusion Detector Protection */
+#define SECUMOD_WKPR_DET2 (0x1u << 18) /**< \brief (SECUMOD_WKPR) PIOBU Intrusion Detector Protection */
+#define SECUMOD_WKPR_DET3 (0x1u << 19) /**< \brief (SECUMOD_WKPR) PIOBU Intrusion Detector Protection */
+#define SECUMOD_WKPR_DET4 (0x1u << 20) /**< \brief (SECUMOD_WKPR) PIOBU Intrusion Detector Protection */
+#define SECUMOD_WKPR_DET5 (0x1u << 21) /**< \brief (SECUMOD_WKPR) PIOBU Intrusion Detector Protection */
+#define SECUMOD_WKPR_DET6 (0x1u << 22) /**< \brief (SECUMOD_WKPR) PIOBU Intrusion Detector Protection */
+#define SECUMOD_WKPR_DET7 (0x1u << 23) /**< \brief (SECUMOD_WKPR) PIOBU Intrusion Detector Protection */
+
+/*@}*/
+
+#endif /* _SAMA5D2_SECUMOD_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_sfc.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_sfc.h
new file mode 100644
index 000000000..1d3b4fc52
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_sfc.h
@@ -0,0 +1,88 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_SFC_COMPONENT_
+#define _SAMA5D2_SFC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Secure Fuse Controller */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_SFC Secure Fuse Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Sfc hardware registers */
+typedef struct {
+  __O  uint32_t SFC_KR;        /**< \brief (Sfc Offset: 0x00) SFC Key Register */
+  __IO uint32_t SFC_MR;        /**< \brief (Sfc Offset: 0x04) SFC Mode Register */
+  __I  uint32_t Reserved1[2];
+  __IO uint32_t SFC_IER;       /**< \brief (Sfc Offset: 0x10) SFC Interrupt Enable Register */
+  __IO uint32_t SFC_IDR;       /**< \brief (Sfc Offset: 0x14) SFC Interrupt Disable Register */
+  __I  uint32_t SFC_IMR;       /**< \brief (Sfc Offset: 0x18) SFC Interrupt Mask Register */
+  __I  uint32_t SFC_SR;        /**< \brief (Sfc Offset: 0x1C) SFC Status Register */
+  __IO uint32_t SFC_DR[24];    /**< \brief (Sfc Offset: 0x20) SFC Data Register */
+} Sfc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SFC_KR : (SFC Offset: 0x00) SFC Key Register -------- */
+#define SFC_KR_KEY_Pos 0
+#define SFC_KR_KEY_Msk (0xffu << SFC_KR_KEY_Pos) /**< \brief (SFC_KR) Key Code */
+#define SFC_KR_KEY(value) ((SFC_KR_KEY_Msk & ((value) << SFC_KR_KEY_Pos)))
+/* -------- SFC_MR : (SFC Offset: 0x04) SFC Mode Register -------- */
+#define SFC_MR_MSK (0x1u << 0) /**< \brief (SFC_MR) Mask Data Registers */
+#define SFC_MR_SASEL (0x1u << 4) /**< \brief (SFC_MR) Sense Amplifier Selection */
+/* -------- SFC_IER : (SFC Offset: 0x10) SFC Interrupt Enable Register -------- */
+#define SFC_IER_PGMC (0x1u << 0) /**< \brief (SFC_IER) Programming Sequence Completed Interrupt Enable */
+#define SFC_IER_PGMF (0x1u << 1) /**< \brief (SFC_IER) Programming Sequence Failed Interrupt Enable */
+#define SFC_IER_LCHECK (0x1u << 4) /**< \brief (SFC_IER) Live Integrity Check Error Interrupt Enable */
+#define SFC_IER_ACE (0x1u << 17) /**< \brief (SFC_IER) Atmel Check Error Interrupt Enable */
+/* -------- SFC_IDR : (SFC Offset: 0x14) SFC Interrupt Disable Register -------- */
+#define SFC_IDR_PGMC (0x1u << 0) /**< \brief (SFC_IDR) Programming Sequence Completed Interrupt Disable */
+#define SFC_IDR_PGMF (0x1u << 1) /**< \brief (SFC_IDR) Programming Sequence Failed Interrupt Disable */
+#define SFC_IDR_LCHECK (0x1u << 4) /**< \brief (SFC_IDR) Live Integrity Check Error Interrupt Disable */
+#define SFC_IDR_ACE (0x1u << 17) /**< \brief (SFC_IDR) Atmel Check Error Interrupt Disable */
+/* -------- SFC_IMR : (SFC Offset: 0x18) SFC Interrupt Mask Register -------- */
+#define SFC_IMR_PGMC (0x1u << 0) /**< \brief (SFC_IMR) Programming Sequence Completed Interrupt Mask */
+#define SFC_IMR_PGMF (0x1u << 1) /**< \brief (SFC_IMR) Programming Sequence Failed Interrupt Mask */
+#define SFC_IMR_LCHECK (0x1u << 4) /**< \brief (SFC_IMR) Live Integrity Checking Error Interrupt Mask */
+#define SFC_IMR_ACE (0x1u << 17) /**< \brief (SFC_IMR) Atmel Check Error Interrupt Mask */
+/* -------- SFC_SR : (SFC Offset: 0x1C) SFC Status Register -------- */
+#define SFC_SR_PGMC (0x1u << 0) /**< \brief (SFC_SR) Programming Sequence Completed (cleared on read) */
+#define SFC_SR_PGMF (0x1u << 1) /**< \brief (SFC_SR) Programming Sequence Failed (cleared on read) */
+#define SFC_SR_LCHECK (0x1u << 4) /**< \brief (SFC_SR) Live Integrity Checking Error (cleared on read) */
+#define SFC_SR_APLE (0x1u << 16) /**< \brief (SFC_SR) Atmel Programming Lock Error (cleared on read) */
+#define SFC_SR_ACE (0x1u << 17) /**< \brief (SFC_SR) Atmel Check Error (cleared on read) */
+/* -------- SFC_DR[24] : (SFC Offset: 0x20) SFC Data Register -------- */
+#define SFC_DR_DATA_Pos 0
+#define SFC_DR_DATA_Msk (0xffffffffu << SFC_DR_DATA_Pos) /**< \brief (SFC_DR[24]) Fuse Data */
+#define SFC_DR_DATA(value) ((SFC_DR_DATA_Msk & ((value) << SFC_DR_DATA_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_SFC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_sfr.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_sfr.h
new file mode 100644
index 000000000..cea3e8ec7
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_sfr.h
@@ -0,0 +1,195 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_SFR_COMPONENT_
+#define _SAMA5D2_SFR_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Special Function Registers */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_SFR Special Function Registers */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Sfr hardware registers */
+typedef struct {
+  __I  uint32_t Reserved0[1];
+  __IO uint32_t SFR_DDRCFG;     /**< \brief (Sfr Offset: 0x04) DDR Configuration Register */
+  __I  uint32_t Reserved1[2];
+  __IO uint32_t SFR_OHCIICR;    /**< \brief (Sfr Offset: 0x10) OHCI Interrupt Configuration Register */
+  __I  uint32_t SFR_OHCIISR;    /**< \brief (Sfr Offset: 0x14) OHCI Interrupt Status Register */
+  __I  uint32_t Reserved2[4];
+  __IO uint32_t SFR_SECURE;     /**< \brief (Sfr Offset: 0x28) Security Configuration Register */
+  __I  uint32_t Reserved3[1];
+  __IO uint32_t SFR_UTMICKTRIM; /**< \brief (Sfr Offset: 0x30) UTMI Clock Trimming Register */
+  __IO uint32_t SFR_UTMIHSTRIM; /**< \brief (Sfr Offset: 0x34) UTMI High Speed Trimming Register */
+  __IO uint32_t SFR_UTMIFSTRIM; /**< \brief (Sfr Offset: 0x38) UTMI Full Speed Trimming Register */
+  __IO uint32_t SFR_UTMISWAP;   /**< \brief (Sfr Offset: 0x3C) UTMI DP/DM Pin Swapping Register */
+  __IO uint32_t SFR_EBICFG;     /**< \brief (Sfr Offset: 0x40) EBI Configuration Register */
+  __I  uint32_t Reserved4[1];
+  __IO uint32_t SFR_CAN;        /**< \brief (Sfr Offset: 0x48) CAN Memories Address-based Register */
+  __I  uint32_t SFR_SN0;        /**< \brief (Sfr Offset: 0x4C) Serial Number 0 Register */
+  __I  uint32_t SFR_SN1;        /**< \brief (Sfr Offset: 0x50) Serial Number 1 Register */
+  __IO uint32_t SFR_AICREDIR;   /**< \brief (Sfr Offset: 0x54) AIC interrupt Redirection Register */
+  __IO uint32_t SFR_L2CC_HRAMC; /**< \brief (Sfr Offset: 0x58) L2CC_HRAMC1 */
+  __I  uint32_t Reserved5[13];
+  __IO uint32_t SFR_I2SCLKSEL;  /**< \brief (Sfr Offset: 0x90) I2SC Register */
+  __IO uint32_t QSPICLK_REG;    /**< \brief (Sfr Offset: 0x94) QSPI Clock Pad Supply Select Register */
+} Sfr;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SFR_DDRCFG : (SFR Offset: 0x04) DDR Configuration Register -------- */
+#define SFR_DDRCFG_FDQIEN (0x1u << 16) /**< \brief (SFR_DDRCFG) Force DDR_DQ Input Buffer Always On */
+#define SFR_DDRCFG_FDQSIEN (0x1u << 17) /**< \brief (SFR_DDRCFG) Force DDR_DQS Input Buffer Always On */
+/* -------- SFR_OHCIICR : (SFR Offset: 0x10) OHCI Interrupt Configuration Register -------- */
+#define SFR_OHCIICR_RES0 (0x1u << 0) /**< \brief (SFR_OHCIICR) USB PORTx RESET */
+#define SFR_OHCIICR_RES1 (0x1u << 1) /**< \brief (SFR_OHCIICR) USB PORTx RESET */
+#define SFR_OHCIICR_RES2 (0x1u << 2) /**< \brief (SFR_OHCIICR) USB PORTx RESET */
+#define SFR_OHCIICR_ARIE (0x1u << 4) /**< \brief (SFR_OHCIICR) OHCI Asynchronous Resume Interrupt Enable */
+#define SFR_OHCIICR_APPSTART (0x1u << 5) /**< \brief (SFR_OHCIICR) Reserved */
+#define SFR_OHCIICR_SUSPEND_A (0x1u << 8) /**< \brief (SFR_OHCIICR) USB PORT A */
+#define SFR_OHCIICR_SUSPEND_B (0x1u << 9) /**< \brief (SFR_OHCIICR) USB PORT B */
+#define SFR_OHCIICR_SUSPEND_C (0x1u << 10) /**< \brief (SFR_OHCIICR) USB PORT C */
+#define SFR_OHCIICR_UDPPUDIS (0x1u << 23) /**< \brief (SFR_OHCIICR) USB DEVICE PULL-UP DISABLE */
+#define SFR_OHCIICR_HSIC_SEL (0x1u << 27) /**< \brief (SFR_OHCIICR) Reserved */
+/* -------- SFR_OHCIISR : (SFR Offset: 0x14) OHCI Interrupt Status Register -------- */
+#define SFR_OHCIISR_RIS0 (0x1u << 0) /**< \brief (SFR_OHCIISR) OHCI Resume Interrupt Status Port 0 */
+#define SFR_OHCIISR_RIS1 (0x1u << 1) /**< \brief (SFR_OHCIISR) OHCI Resume Interrupt Status Port 1 */
+#define SFR_OHCIISR_RIS2 (0x1u << 2) /**< \brief (SFR_OHCIISR) OHCI Resume Interrupt Status Port 2 */
+/* -------- SFR_SECURE : (SFR Offset: 0x28) Security Configuration Register -------- */
+#define SFR_SECURE_ROM (0x1u << 0) /**< \brief (SFR_SECURE) Disable Access to ROM Code */
+#define SFR_SECURE_FUSE (0x1u << 8) /**< \brief (SFR_SECURE) Disable Access to Fuse Controller */
+/* -------- SFR_UTMICKTRIM : (SFR Offset: 0x30) UTMI Clock Trimming Register -------- */
+#define SFR_UTMICKTRIM_FREQ_Pos 0
+#define SFR_UTMICKTRIM_FREQ_Msk (0x3u << SFR_UTMICKTRIM_FREQ_Pos) /**< \brief (SFR_UTMICKTRIM) UTMI Reference Clock Frequency */
+#define SFR_UTMICKTRIM_FREQ(value) ((SFR_UTMICKTRIM_FREQ_Msk & ((value) << SFR_UTMICKTRIM_FREQ_Pos)))
+#define   SFR_UTMICKTRIM_FREQ_12 (0x0u << 0) /**< \brief (SFR_UTMICKTRIM) 12 MHz reference clock */
+#define   SFR_UTMICKTRIM_FREQ_16 (0x1u << 0) /**< \brief (SFR_UTMICKTRIM) 16 MHz reference clock */
+#define   SFR_UTMICKTRIM_FREQ_24 (0x2u << 0) /**< \brief (SFR_UTMICKTRIM) 24 MHz reference clock */
+#define SFR_UTMICKTRIM_VBG_Pos 16
+#define SFR_UTMICKTRIM_VBG_Msk (0xfu << SFR_UTMICKTRIM_VBG_Pos) /**< \brief (SFR_UTMICKTRIM) UTMI Band Gap Voltage Trimming */
+#define SFR_UTMICKTRIM_VBG(value) ((SFR_UTMICKTRIM_VBG_Msk & ((value) << SFR_UTMICKTRIM_VBG_Pos)))
+/* -------- SFR_UTMIHSTRIM : (SFR Offset: 0x34) UTMI High Speed Trimming Register -------- */
+#define SFR_UTMIHSTRIM_SQUELCH_Pos 0
+#define SFR_UTMIHSTRIM_SQUELCH_Msk (0x7u << SFR_UTMIHSTRIM_SQUELCH_Pos) /**< \brief (SFR_UTMIHSTRIM) UTMI HS SQUELCH Voltage Trimming */
+#define SFR_UTMIHSTRIM_SQUELCH(value) ((SFR_UTMIHSTRIM_SQUELCH_Msk & ((value) << SFR_UTMIHSTRIM_SQUELCH_Pos)))
+#define SFR_UTMIHSTRIM_DISC_Pos 4
+#define SFR_UTMIHSTRIM_DISC_Msk (0x7u << SFR_UTMIHSTRIM_DISC_Pos) /**< \brief (SFR_UTMIHSTRIM) UTMI Disconnect Voltage Trimming */
+#define SFR_UTMIHSTRIM_DISC(value) ((SFR_UTMIHSTRIM_DISC_Msk & ((value) << SFR_UTMIHSTRIM_DISC_Pos)))
+#define SFR_UTMIHSTRIM_SLOPE0_Pos 8
+#define SFR_UTMIHSTRIM_SLOPE0_Msk (0x7u << SFR_UTMIHSTRIM_SLOPE0_Pos) /**< \brief (SFR_UTMIHSTRIM) UTMI HS PORTx Transceiver Slope Trimming */
+#define SFR_UTMIHSTRIM_SLOPE0(value) ((SFR_UTMIHSTRIM_SLOPE0_Msk & ((value) << SFR_UTMIHSTRIM_SLOPE0_Pos)))
+#define SFR_UTMIHSTRIM_SLOPE1_Pos 12
+#define SFR_UTMIHSTRIM_SLOPE1_Msk (0x7u << SFR_UTMIHSTRIM_SLOPE1_Pos) /**< \brief (SFR_UTMIHSTRIM) UTMI HS PORTx Transceiver Slope Trimming */
+#define SFR_UTMIHSTRIM_SLOPE1(value) ((SFR_UTMIHSTRIM_SLOPE1_Msk & ((value) << SFR_UTMIHSTRIM_SLOPE1_Pos)))
+#define SFR_UTMIHSTRIM_SLOPE2_Pos 16
+#define SFR_UTMIHSTRIM_SLOPE2_Msk (0x7u << SFR_UTMIHSTRIM_SLOPE2_Pos) /**< \brief (SFR_UTMIHSTRIM) UTMI HS PORTx Transceiver Slope Trimming */
+#define SFR_UTMIHSTRIM_SLOPE2(value) ((SFR_UTMIHSTRIM_SLOPE2_Msk & ((value) << SFR_UTMIHSTRIM_SLOPE2_Pos)))
+/* -------- SFR_UTMIFSTRIM : (SFR Offset: 0x38) UTMI Full Speed Trimming Register -------- */
+#define SFR_UTMIFSTRIM_RISE_Pos 0
+#define SFR_UTMIFSTRIM_RISE_Msk (0x7u << SFR_UTMIFSTRIM_RISE_Pos) /**< \brief (SFR_UTMIFSTRIM) FS Transceiver Output Rising Slope Trimming */
+#define SFR_UTMIFSTRIM_RISE(value) ((SFR_UTMIFSTRIM_RISE_Msk & ((value) << SFR_UTMIFSTRIM_RISE_Pos)))
+#define SFR_UTMIFSTRIM_FALL_Pos 4
+#define SFR_UTMIFSTRIM_FALL_Msk (0x7u << SFR_UTMIFSTRIM_FALL_Pos) /**< \brief (SFR_UTMIFSTRIM) FS Transceiver Output Falling Slope Trimming */
+#define SFR_UTMIFSTRIM_FALL(value) ((SFR_UTMIFSTRIM_FALL_Msk & ((value) << SFR_UTMIFSTRIM_FALL_Pos)))
+#define SFR_UTMIFSTRIM_XCVR_Pos 8
+#define SFR_UTMIFSTRIM_XCVR_Msk (0x3u << SFR_UTMIFSTRIM_XCVR_Pos) /**< \brief (SFR_UTMIFSTRIM) FS Transceiver Crossover Voltage Trimming */
+#define SFR_UTMIFSTRIM_XCVR(value) ((SFR_UTMIFSTRIM_XCVR_Msk & ((value) << SFR_UTMIFSTRIM_XCVR_Pos)))
+#define SFR_UTMIFSTRIM_ZN_Pos 16
+#define SFR_UTMIFSTRIM_ZN_Msk (0x7u << SFR_UTMIFSTRIM_ZN_Pos) /**< \brief (SFR_UTMIFSTRIM) FS Transceiver NMOS Impedance Trimming */
+#define SFR_UTMIFSTRIM_ZN(value) ((SFR_UTMIFSTRIM_ZN_Msk & ((value) << SFR_UTMIFSTRIM_ZN_Pos)))
+#define SFR_UTMIFSTRIM_ZP_Pos 20
+#define SFR_UTMIFSTRIM_ZP_Msk (0x7u << SFR_UTMIFSTRIM_ZP_Pos) /**< \brief (SFR_UTMIFSTRIM) FS Transceiver PMOS Impedance Trimming */
+#define SFR_UTMIFSTRIM_ZP(value) ((SFR_UTMIFSTRIM_ZP_Msk & ((value) << SFR_UTMIFSTRIM_ZP_Pos)))
+/* -------- SFR_UTMISWAP : (SFR Offset: 0x3C) UTMI DP/DM Pin Swapping Register -------- */
+#define SFR_UTMISWAP_PORT0 (0x1u << 0) /**< \brief (SFR_UTMISWAP) PORT 0 DP/DM Pin Swapping */
+#define   SFR_UTMISWAP_PORT0_NORMAL (0x0u << 0) /**< \brief (SFR_UTMISWAP) DP/DM normal pinout. */
+#define   SFR_UTMISWAP_PORT0_SWAPPED (0x1u << 0) /**< \brief (SFR_UTMISWAP) DP/DM swapped pinout. */
+#define SFR_UTMISWAP_PORT1 (0x1u << 1) /**< \brief (SFR_UTMISWAP) PORT 1 DP/DM Pin Swapping */
+#define   SFR_UTMISWAP_PORT1_NORMAL (0x0u << 1) /**< \brief (SFR_UTMISWAP) DP/DM normal pinout. */
+#define   SFR_UTMISWAP_PORT1_SWAPPED (0x1u << 1) /**< \brief (SFR_UTMISWAP) DP/DM swapped pinout. */
+#define SFR_UTMISWAP_PORT2 (0x1u << 2) /**< \brief (SFR_UTMISWAP) PORT 2 DP/DM Pin Swapping */
+#define   SFR_UTMISWAP_PORT2_NORMAL (0x0u << 2) /**< \brief (SFR_UTMISWAP) DP/DM normal pinout. */
+#define   SFR_UTMISWAP_PORT2_SWAPPED (0x1u << 2) /**< \brief (SFR_UTMISWAP) DP/DM swapped pinout. */
+/* -------- SFR_EBICFG : (SFR Offset: 0x40) EBI Configuration Register -------- */
+#define SFR_EBICFG_DRIVE0_Pos 0
+#define SFR_EBICFG_DRIVE0_Msk (0x3u << SFR_EBICFG_DRIVE0_Pos) /**< \brief (SFR_EBICFG) EBI Pins Drive Level */
+#define SFR_EBICFG_DRIVE0(value) ((SFR_EBICFG_DRIVE0_Msk & ((value) << SFR_EBICFG_DRIVE0_Pos)))
+#define   SFR_EBICFG_DRIVE0_LOW (0x0u << 0) /**< \brief (SFR_EBICFG) Low drive level */
+#define   SFR_EBICFG_DRIVE0_MEDIUM (0x2u << 0) /**< \brief (SFR_EBICFG) Medium drive level */
+#define   SFR_EBICFG_DRIVE0_HIGH (0x3u << 0) /**< \brief (SFR_EBICFG) High drive level */
+#define SFR_EBICFG_PULL0_Pos 2
+#define SFR_EBICFG_PULL0_Msk (0x3u << SFR_EBICFG_PULL0_Pos) /**< \brief (SFR_EBICFG) EBI Pins Pull Value */
+#define SFR_EBICFG_PULL0(value) ((SFR_EBICFG_PULL0_Msk & ((value) << SFR_EBICFG_PULL0_Pos)))
+#define   SFR_EBICFG_PULL0_UP (0x0u << 2) /**< \brief (SFR_EBICFG) Pull-up */
+#define   SFR_EBICFG_PULL0_NONE (0x1u << 2) /**< \brief (SFR_EBICFG) No Pull */
+#define   SFR_EBICFG_PULL0_DOWN (0x3u << 2) /**< \brief (SFR_EBICFG) Pull-down */
+#define SFR_EBICFG_SCH0 (0x1u << 4) /**< \brief (SFR_EBICFG) EBI Pins Schmitt Trigger */
+#define SFR_EBICFG_DRIVE1_Pos 8
+#define SFR_EBICFG_DRIVE1_Msk (0x3u << SFR_EBICFG_DRIVE1_Pos) /**< \brief (SFR_EBICFG) EBI Pins Drive Level */
+#define SFR_EBICFG_DRIVE1(value) ((SFR_EBICFG_DRIVE1_Msk & ((value) << SFR_EBICFG_DRIVE1_Pos)))
+#define   SFR_EBICFG_DRIVE1_LOW (0x0u << 8) /**< \brief (SFR_EBICFG) Low drive level */
+#define   SFR_EBICFG_DRIVE1_MEDIUM (0x2u << 8) /**< \brief (SFR_EBICFG) Medium drive level */
+#define   SFR_EBICFG_DRIVE1_HIGH (0x3u << 8) /**< \brief (SFR_EBICFG) High drive level */
+#define SFR_EBICFG_PULL1_Pos 10
+#define SFR_EBICFG_PULL1_Msk (0x3u << SFR_EBICFG_PULL1_Pos) /**< \brief (SFR_EBICFG) EBI Pins Pull Value */
+#define SFR_EBICFG_PULL1(value) ((SFR_EBICFG_PULL1_Msk & ((value) << SFR_EBICFG_PULL1_Pos)))
+#define   SFR_EBICFG_PULL1_UP (0x0u << 10) /**< \brief (SFR_EBICFG) Pull-up */
+#define   SFR_EBICFG_PULL1_NONE (0x1u << 10) /**< \brief (SFR_EBICFG) No Pull */
+#define   SFR_EBICFG_PULL1_DOWN (0x3u << 10) /**< \brief (SFR_EBICFG) Pull-down */
+#define SFR_EBICFG_SCH1 (0x1u << 12) /**< \brief (SFR_EBICFG) EBI Pins Schmitt Trigger */
+/* -------- SFR_CAN : (SFR Offset: 0x48) CAN Memories Address-based Register -------- */
+#define SFR_CAN_EXT_MEM_CAN0_ADDR_Pos 0
+#define SFR_CAN_EXT_MEM_CAN0_ADDR_Msk (0xffffu << SFR_CAN_EXT_MEM_CAN0_ADDR_Pos) /**< \brief (SFR_CAN) MSB CAN0 DMA Base Address */
+#define SFR_CAN_EXT_MEM_CAN0_ADDR(value) ((SFR_CAN_EXT_MEM_CAN0_ADDR_Msk & ((value) << SFR_CAN_EXT_MEM_CAN0_ADDR_Pos)))
+#define SFR_CAN_EXT_MEM_CAN1_ADDR_Pos 16
+#define SFR_CAN_EXT_MEM_CAN1_ADDR_Msk (0xffffu << SFR_CAN_EXT_MEM_CAN1_ADDR_Pos) /**< \brief (SFR_CAN) MSB CAN1 DMA Base Address */
+#define SFR_CAN_EXT_MEM_CAN1_ADDR(value) ((SFR_CAN_EXT_MEM_CAN1_ADDR_Msk & ((value) << SFR_CAN_EXT_MEM_CAN1_ADDR_Pos)))
+/* -------- SFR_SN0 : (SFR Offset: 0x4C) Serial Number 0 Register -------- */
+#define SFR_SN0_SN0_Pos 0
+#define SFR_SN0_SN0_Msk (0xffffffffu << SFR_SN0_SN0_Pos) /**< \brief (SFR_SN0) Serial Number 0 */
+/* -------- SFR_SN1 : (SFR Offset: 0x50) Serial Number 1 Register -------- */
+#define SFR_SN1_SN1_Pos 0
+#define SFR_SN1_SN1_Msk (0xffffffffu << SFR_SN1_SN1_Pos) /**< \brief (SFR_SN1) Serial Number 1 */
+/* -------- SFR_AICREDIR : (SFR Offset: 0x54) AIC interrupt Redirection Register -------- */
+#define SFR_AICREDIR_NSAIC (0x1u << 0) /**< \brief (SFR_AICREDIR) Interrupt redirection to Non-Secure AIC */
+#define SFR_AICREDIR_AICREDIRKEY_Pos 1
+#define SFR_AICREDIR_AICREDIRKEY_Msk (0x7fffffffu << SFR_AICREDIR_AICREDIRKEY_Pos) /**< \brief (SFR_AICREDIR) Unlock Key */
+#define SFR_AICREDIR_AICREDIRKEY(value) ((SFR_AICREDIR_AICREDIRKEY_Msk & ((value) << SFR_AICREDIR_AICREDIRKEY_Pos)))
+/* -------- SFR_L2CC_HRAMC : (SFR Offset: 0x58) L2CC_HRAMC1 -------- */
+#define SFR_L2CC_HRAMC_SRAM_SEL (0x1u << 0) /**< \brief (SFR_L2CC_HRAMC) SRAM Selector */
+/* -------- SFR_I2SCLKSEL : (SFR Offset: 0x90) I2SC Register -------- */
+#define SFR_I2SCLKSEL_CLKSEL0 (0x1u << 0) /**< \brief (SFR_I2SCLKSEL) Clock Selection 0 */
+#define SFR_I2SCLKSEL_CLKSEL1 (0x1u << 1) /**< \brief (SFR_I2SCLKSEL) Clock Selection 1 */
+/* -------- QSPICLK_REG : (SFR Offset: 0x94) QSPI Clock Pad Supply Select Register -------- */
+#define QSPICLK_REG_SUP_SEL (0x1u << 0) /**< \brief (QSPICLK_REG) Supply Selection */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_SFR_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_sfrbu.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_sfrbu.h
new file mode 100644
index 000000000..d38f260be
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_sfrbu.h
@@ -0,0 +1,59 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_SFRBU_COMPONENT_
+#define _SAMA5D2_SFRBU_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Special Function Registers */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_SFRBU Special Function Registers */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Sfrbu hardware registers */
+typedef struct {
+  __IO uint32_t SFRBU_PSWBUCTRL; /**< \brief (Sfrbu Offset: 0x00) Power Switch BU Control Register */
+  __IO uint32_t SFRBU_TSRANGECFG;/**< \brief (Sfrbu Offset: 0x04) TS Range Configuration Register */
+  __I  uint32_t Reserved1[2];
+  __IO uint32_t SFRBU_DDRBUMCR;  /**< \brief (Sfrbu Offset: 0x10) DDR BU Mode Control Register */
+  __IO uint32_t SFRBU_RXLPPUCR;  /**< \brief (Sfrbu Offset: 0x14) RXLP Pull-Up Control Register */
+} Sfrbu;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* -------- SFRBU_DDRBUMCR : (Sfrbu Offset: 0x10) DDR BU Mode Control Register -------- */
+/* This bit is used to isolate the DDR Pads from the CPU domain (VCCCORE).
+ * It has to be set after enabling the Self-refresh mode on the DDR memory
+ * and before doing power-down on VCCCORE
+ */
+#define SFRBU_DDRBUMCR_BUMEN (0x1<<0) /**< \brief (SFRBU_DDRBUMCR) DDR BU Mode Enable */
+
+/*@}*/
+
+#endif /* _SAMA5D2_SFRBU_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_sha.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_sha.h
new file mode 100644
index 000000000..a5f3f290d
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_sha.h
@@ -0,0 +1,147 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_SHA_COMPONENT_
+#define _SAMA5D2_SHA_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Secure Hash Algorithm */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_SHA Secure Hash Algorithm */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Sha hardware registers */
+typedef struct {
+  __O  uint32_t SHA_CR;          /**< \brief (Sha Offset: 0x00) Control Register */
+  __IO uint32_t SHA_MR;          /**< \brief (Sha Offset: 0x04) Mode Register */
+  __I  uint32_t Reserved1[2];
+  __O  uint32_t SHA_IER;         /**< \brief (Sha Offset: 0x10) Interrupt Enable Register */
+  __O  uint32_t SHA_IDR;         /**< \brief (Sha Offset: 0x14) Interrupt Disable Register */
+  __I  uint32_t SHA_IMR;         /**< \brief (Sha Offset: 0x18) Interrupt Mask Register */
+  __I  uint32_t SHA_ISR;         /**< \brief (Sha Offset: 0x1C) Interrupt Status Register */
+  __IO uint32_t SHA_MSR;         /**< \brief (Sha Offset: 0x20) Message Size Register */
+  __I  uint32_t Reserved2[3];
+  __IO uint32_t SHA_BCR;         /**< \brief (Sha Offset: 0x30) Bytes Count Register */
+  __I  uint32_t Reserved3[3];
+  __O  uint32_t SHA_IDATAR[16];  /**< \brief (Sha Offset: 0x40) Input Data 0 Register */
+  __IO uint32_t SHA_IODATAR[16]; /**< \brief (Sha Offset: 0x80) Input/Output Data 0 Register */
+  __I  uint32_t SHA_VERSION;     /**< \brief (Sha Offset: 0xFC) Version Register */
+} Sha;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SHA_CR : (SHA Offset: 0x00) Control Register -------- */
+#define SHA_CR_START (0x1u << 0) /**< \brief (SHA_CR) Start Processing */
+#define SHA_CR_FIRST (0x1u << 4) /**< \brief (SHA_CR) First Block of a Message */
+#define SHA_CR_SWRST (0x1u << 8) /**< \brief (SHA_CR) Software Reset */
+#define SHA_CR_WUIHV (0x1u << 12) /**< \brief (SHA_CR) Write User Initial Hash Values */
+#define SHA_CR_WUIEHV (0x1u << 13) /**< \brief (SHA_CR) Write User Initial or Expected Hash Values */
+/* -------- SHA_MR : (SHA Offset: 0x04) Mode Register -------- */
+#define SHA_MR_SMOD_Pos 0
+#define SHA_MR_SMOD_Msk (0x3u << SHA_MR_SMOD_Pos) /**< \brief (SHA_MR) Start Mode */
+#define SHA_MR_SMOD(value) ((SHA_MR_SMOD_Msk & ((value) << SHA_MR_SMOD_Pos)))
+#define   SHA_MR_SMOD_MANUAL_START (0x0u << 0) /**< \brief (SHA_MR) Manual Mode */
+#define   SHA_MR_SMOD_AUTO_START (0x1u << 0) /**< \brief (SHA_MR) Auto Mode */
+#define   SHA_MR_SMOD_IDATAR0_START (0x2u << 0) /**< \brief (SHA_MR) SHA_IDATAR0 access only Auto Mode */
+#define SHA_MR_PROCDLY (0x1u << 4) /**< \brief (SHA_MR) Processing Delay */
+#define   SHA_MR_PROCDLY_SHORTEST (0x0u << 4) /**< \brief (SHA_MR) SHA processing runtime is the shortest one */
+#define   SHA_MR_PROCDLY_LONGEST (0x1u << 4) /**< \brief (SHA_MR) SHA processing runtime is the longest one (reduces the SHA bandwidth requirement, reduces the system bus overload) */
+#define SHA_MR_UIHV (0x1u << 5) /**< \brief (SHA_MR) User Initial Hash Value Registers */
+#define SHA_MR_UIEHV (0x1u << 6) /**< \brief (SHA_MR) User Initial or Expected Hash Value Registers */
+#define SHA_MR_ALGO_Pos 8
+#define SHA_MR_ALGO_Msk (0xfu << SHA_MR_ALGO_Pos) /**< \brief (SHA_MR) SHA Algorithm */
+#define SHA_MR_ALGO(value) ((SHA_MR_ALGO_Msk & ((value) << SHA_MR_ALGO_Pos)))
+#define   SHA_MR_ALGO_SHA1 (0x0u << 8) /**< \brief (SHA_MR) SHA1 algorithm processed */
+#define   SHA_MR_ALGO_SHA256 (0x1u << 8) /**< \brief (SHA_MR) SHA256 algorithm processed */
+#define   SHA_MR_ALGO_SHA384 (0x2u << 8) /**< \brief (SHA_MR) SHA384 algorithm processed */
+#define   SHA_MR_ALGO_SHA512 (0x3u << 8) /**< \brief (SHA_MR) SHA512 algorithm processed */
+#define   SHA_MR_ALGO_SHA224 (0x4u << 8) /**< \brief (SHA_MR) SHA224 algorithm processed */
+#define   SHA_MR_ALGO_HMAC_SHA1 (0x8u << 8) /**< \brief (SHA_MR) HMAC algorithm with SHA1 Hash processed */
+#define   SHA_MR_ALGO_HMAC_SHA256 (0x9u << 8) /**< \brief (SHA_MR) HMAC algorithm with SHA256 Hash processed */
+#define   SHA_MR_ALGO_HMAC_SHA384 (0xAu << 8) /**< \brief (SHA_MR) HMAC algorithm with SHA384 Hash processed */
+#define   SHA_MR_ALGO_HMAC_SHA512 (0xBu << 8) /**< \brief (SHA_MR) HMAC algorithm with SHA512 Hash processed */
+#define   SHA_MR_ALGO_HMAC_SHA224 (0xCu << 8) /**< \brief (SHA_MR) HMAC algorithm with SHA224 Hash processed */
+#define SHA_MR_DUALBUFF (0x1u << 16) /**< \brief (SHA_MR) Dual Input Buffer */
+#define   SHA_MR_DUALBUFF_INACTIVE (0x0u << 16) /**< \brief (SHA_MR) SHA_IDATARx and SHA_IODATARx cannot be written during processing of previous block. */
+#define   SHA_MR_DUALBUFF_ACTIVE (0x1u << 16) /**< \brief (SHA_MR) SHA_IDATARx and SHA_IODATARx can be written during processing of previous block when SMOD value = 2. It speeds up the overall runtime of large files. */
+#define SHA_MR_CHECK_Pos 24
+#define SHA_MR_CHECK_Msk (0x3u << SHA_MR_CHECK_Pos) /**< \brief (SHA_MR) Hash Check */
+#define SHA_MR_CHECK(value) ((SHA_MR_CHECK_Msk & ((value) << SHA_MR_CHECK_Pos)))
+#define   SHA_MR_CHECK_NO_CHECK (0x0u << 24) /**< \brief (SHA_MR) No check is performed */
+#define   SHA_MR_CHECK_CHECK_EHV (0x1u << 24) /**< \brief (SHA_MR) Check is performed with expected hash stored in internal expected hash value registers. */
+#define   SHA_MR_CHECK_CHECK_MESSAGE (0x2u << 24) /**< \brief (SHA_MR) Check is performed with expected hash provided after the message. */
+#define SHA_MR_CHKCNT_Pos 28
+#define SHA_MR_CHKCNT_Msk (0xfu << SHA_MR_CHKCNT_Pos) /**< \brief (SHA_MR) Check Counter */
+#define SHA_MR_CHKCNT(value) ((SHA_MR_CHKCNT_Msk & ((value) << SHA_MR_CHKCNT_Pos)))
+/* -------- SHA_IER : (SHA Offset: 0x10) Interrupt Enable Register -------- */
+#define SHA_IER_DATRDY (0x1u << 0) /**< \brief (SHA_IER) Data Ready Interrupt Enable */
+#define SHA_IER_URAD (0x1u << 8) /**< \brief (SHA_IER) Unspecified Register Access Detection Interrupt Enable */
+#define SHA_IER_CHECKF (0x1u << 16) /**< \brief (SHA_IER) Check Done Interrupt Enable */
+/* -------- SHA_IDR : (SHA Offset: 0x14) Interrupt Disable Register -------- */
+#define SHA_IDR_DATRDY (0x1u << 0) /**< \brief (SHA_IDR) Data Ready Interrupt Disable */
+#define SHA_IDR_URAD (0x1u << 8) /**< \brief (SHA_IDR) Unspecified Register Access Detection Interrupt Disable */
+#define SHA_IDR_CHECKF (0x1u << 16) /**< \brief (SHA_IDR) Check Done Interrupt Disable */
+/* -------- SHA_IMR : (SHA Offset: 0x18) Interrupt Mask Register -------- */
+#define SHA_IMR_DATRDY (0x1u << 0) /**< \brief (SHA_IMR) Data Ready Interrupt Mask */
+#define SHA_IMR_URAD (0x1u << 8) /**< \brief (SHA_IMR) Unspecified Register Access Detection Interrupt Mask */
+#define SHA_IMR_CHECKF (0x1u << 16) /**< \brief (SHA_IMR) Check Done Interrupt Mask */
+/* -------- SHA_ISR : (SHA Offset: 0x1C) Interrupt Status Register -------- */
+#define SHA_ISR_DATRDY (0x1u << 0) /**< \brief (SHA_ISR) Data Ready (cleared by writing a 1 to bit SWRST or START in SHA_CR, or by reading SHA_IODATARx) */
+#define SHA_ISR_WRDY (0x1u << 4) /**< \brief (SHA_ISR) Input Data Register Write Ready */
+#define SHA_ISR_URAD (0x1u << 8) /**< \brief (SHA_ISR) Unspecified Register Access Detection Status (cleared by writing a 1 to SWRST bit in SHA_CR) */
+#define SHA_ISR_URAT_Pos 12
+#define SHA_ISR_URAT_Msk (0x7u << SHA_ISR_URAT_Pos) /**< \brief (SHA_ISR) Unspecified Register Access Type (cleared by writing a 1 to SWRST bit in SHA_CR) */
+#define SHA_ISR_CHECKF (0x1u << 16) /**< \brief (SHA_ISR) Check Done Status (cleared by writing START or SWRST bits in SHA_CR or by reading SHA_IODATARx) */
+#define SHA_ISR_CHKST_Pos 20
+#define SHA_ISR_CHKST_Msk (0xfu << SHA_ISR_CHKST_Pos) /**< \brief (SHA_ISR) Check Status (cleared by writing START or SWRST bits in SHA_CR or by reading SHA_IODATARx) */
+/* -------- SHA_MSR : (SHA Offset: 0x20) Message Size Register -------- */
+#define SHA_MSR_MSGSIZE_Pos 0
+#define SHA_MSR_MSGSIZE_Msk (0xffffffffu << SHA_MSR_MSGSIZE_Pos) /**< \brief (SHA_MSR) Message Size */
+#define SHA_MSR_MSGSIZE(value) ((SHA_MSR_MSGSIZE_Msk & ((value) << SHA_MSR_MSGSIZE_Pos)))
+/* -------- SHA_BCR : (SHA Offset: 0x30) Bytes Count Register -------- */
+#define SHA_BCR_BYTCNT_Pos 0
+#define SHA_BCR_BYTCNT_Msk (0xffffffffu << SHA_BCR_BYTCNT_Pos) /**< \brief (SHA_BCR) Remaining Byte Count Before Auto Padding */
+#define SHA_BCR_BYTCNT(value) ((SHA_BCR_BYTCNT_Msk & ((value) << SHA_BCR_BYTCNT_Pos)))
+/* -------- SHA_IDATAR[16] : (SHA Offset: 0x40) Input Data 0 Register -------- */
+#define SHA_IDATAR_IDATA_Pos 0
+#define SHA_IDATAR_IDATA_Msk (0xffffffffu << SHA_IDATAR_IDATA_Pos) /**< \brief (SHA_IDATAR[16]) Input Data */
+#define SHA_IDATAR_IDATA(value) ((SHA_IDATAR_IDATA_Msk & ((value) << SHA_IDATAR_IDATA_Pos)))
+/* -------- SHA_IODATAR[16] : (SHA Offset: 0x80) Input/Output Data 0 Register -------- */
+#define SHA_IODATAR_IODATA_Pos 0
+#define SHA_IODATAR_IODATA_Msk (0xffffffffu << SHA_IODATAR_IODATA_Pos) /**< \brief (SHA_IODATAR[16]) Input/Output Data */
+#define SHA_IODATAR_IODATA(value) ((SHA_IODATAR_IODATA_Msk & ((value) << SHA_IODATAR_IODATA_Pos)))
+/* -------- SHA_VERSION : (SHA Offset: 0xFC) Version Register -------- */
+#define SHA_VERSION_VERSION_Pos 0
+#define SHA_VERSION_VERSION_Msk (0xfffu << SHA_VERSION_VERSION_Pos) /**< \brief (SHA_VERSION) Version of the Hardware Module */
+#define SHA_VERSION_MFN_Pos 16
+#define SHA_VERSION_MFN_Msk (0x7u << SHA_VERSION_MFN_Pos) /**< \brief (SHA_VERSION) Metal Fix Number */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_SHA_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_shdwc.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_shdwc.h
new file mode 100644
index 000000000..5538759a1
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_shdwc.h
@@ -0,0 +1,177 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_SHDWC_COMPONENT_
+#define _SAMA5D2_SHDWC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Shutdown Controller */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_SHDWC Shutdown Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Shdwc hardware registers */
+typedef struct {
+  __O  uint32_t SHDW_CR;   /**< \brief (Shdwc Offset: 0x00) Shutdown Control Register */
+  __IO uint32_t SHDW_MR;   /**< \brief (Shdwc Offset: 0x04) Shutdown Mode Register */
+  __I  uint32_t SHDW_SR;   /**< \brief (Shdwc Offset: 0x08) Shutdown Status Register */
+  __IO uint32_t SHDW_WUIR; /**< \brief (Shdwc Offset: 0x0C) Shutdown Wake-up Inputs Register */
+} Shdwc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SHDW_CR : (SHDWC Offset: 0x00) Shutdown Control Register -------- */
+#define SHDW_CR_SHDW (0x1u << 0) /**< \brief (SHDW_CR) Shutdown Command */
+#define SHDW_CR_KEY_Pos 24
+#define SHDW_CR_KEY_Msk (0xffu << SHDW_CR_KEY_Pos) /**< \brief (SHDW_CR) Password */
+#define SHDW_CR_KEY(value) ((SHDW_CR_KEY_Msk & ((value) << SHDW_CR_KEY_Pos)))
+#define   SHDW_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (SHDW_CR) Writing any other value in this field aborts the write operation. */
+/* -------- SHDW_MR : (SHDWC Offset: 0x04) Shutdown Mode Register -------- */
+#define SHDW_MR_LPDBCEN0 (0x1u << 0) /**< \brief (SHDW_MR) Low-Power Debouncer Enable WKUP0 */
+#define   SHDW_MR_LPDBCEN0_NOT_ENABLE (0x0u << 0) /**< \brief (SHDW_MR) The WKUP0 input pin is not connected to the low-power debouncer. */
+#define   SHDW_MR_LPDBCEN0_ENABLE (0x1u << 0) /**< \brief (SHDW_MR) The WKUP0 input pin is connected to the low-power debouncer and can force a system wake-up. */
+#define SHDW_MR_LPDBCEN1 (0x1u << 1) /**< \brief (SHDW_MR) Low-Power Debouncer Enable WKUP1 */
+#define   SHDW_MR_LPDBCEN1_NOT_ENABLE (0x0u << 1) /**< \brief (SHDW_MR) The WKUP1 input pin is not connected to the low-power debouncer. */
+#define   SHDW_MR_LPDBCEN1_ENABLE (0x1u << 1) /**< \brief (SHDW_MR) The WKUP1 input pin is connected to the low-power debouncer and can force a system wake-up. */
+#define SHDW_MR_LPDBC_Pos 8
+#define SHDW_MR_LPDBC_Msk (0x7u << SHDW_MR_LPDBC_Pos) /**< \brief (SHDW_MR) Low Power Debouncer Period */
+#define SHDW_MR_LPDBC(value) ((SHDW_MR_LPDBC_Msk & ((value) << SHDW_MR_LPDBC_Pos)))
+#define   SHDW_MR_LPDBC_DISABLE (0x0u << 8) /**< \brief (SHDW_MR) Disable the low-power debouncers */
+#define   SHDW_MR_LPDBC_2_RTCOUT0 (0x1u << 8) /**< \brief (SHDW_MR) WKUP0/1 in active state for at least 2 RTCOUT0 periods */
+#define   SHDW_MR_LPDBC_3_RTCOUT0 (0x2u << 8) /**< \brief (SHDW_MR) WKUP0/1 in active state for at least 3 RTCOUT0 periods */
+#define   SHDW_MR_LPDBC_4_RTCOUT0 (0x3u << 8) /**< \brief (SHDW_MR) WKUP0/1 in active state for at least 4 RTCOUT0 periods */
+#define   SHDW_MR_LPDBC_5_RTCOUT0 (0x4u << 8) /**< \brief (SHDW_MR) WKUP0/1 in active state for at least 5 RTCOUT0 periods */
+#define   SHDW_MR_LPDBC_6_RTCOUT0 (0x5u << 8) /**< \brief (SHDW_MR) WKUP0/1 in active state for at least 6 RTCOUT0 periods */
+#define   SHDW_MR_LPDBC_7_RTCOUT0 (0x6u << 8) /**< \brief (SHDW_MR) WKUP0/1 in active state for at least 7 RTCOUT0 periods */
+#define   SHDW_MR_LPDBC_8_RTCOUT0 (0x7u << 8) /**< \brief (SHDW_MR) WKUP0/1 in active state for at least 8 RTCOUT0 periods */
+#define SHDW_MR_RTTWKEN (0x1u << 16) /**< \brief (SHDW_MR)  */
+#define SHDW_MR_RTCWKEN (0x1u << 17) /**< \brief (SHDW_MR) Analog Comparator Controller Wake-up Enable */
+#define SHDW_MR_ACCWKEN (0x1u << 18) /**< \brief (SHDW_MR) Analog Comparator Controller Wake-up Enable */
+#define SHDW_MR_RXLPWKEN (0x1u << 19) /**< \brief (SHDW_MR) Debug Unit Wake-up Enable */
+#define SHDW_MR_WKUPDBC_Pos 24
+#define SHDW_MR_WKUPDBC_Msk (0x7u << SHDW_MR_WKUPDBC_Pos) /**< \brief (SHDW_MR) Wake-up Inputs Debouncer Period */
+#define SHDW_MR_WKUPDBC(value) ((SHDW_MR_WKUPDBC_Msk & ((value) << SHDW_MR_WKUPDBC_Pos)))
+#define   SHDW_MR_WKUPDBC_IMMEDIATE (0x0u << 24) /**< \brief (SHDW_MR) Immediate, no debouncing, detected active at least on one Slow Clock edge */
+#define   SHDW_MR_WKUPDBC_3_SLCK (0x1u << 24) /**< \brief (SHDW_MR) WKUPx shall be in its active state for at least 3 SLCK periods */
+#define   SHDW_MR_WKUPDBC_32_SLCK (0x2u << 24) /**< \brief (SHDW_MR) WKUPx shall be in its active state for at least 32 SLCK periods */
+#define   SHDW_MR_WKUPDBC_512_SLCK (0x3u << 24) /**< \brief (SHDW_MR) WKUPx shall be in its active state for at least 512 SLCK periods */
+#define   SHDW_MR_WKUPDBC_4096_SLCK (0x4u << 24) /**< \brief (SHDW_MR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
+#define   SHDW_MR_WKUPDBC_32768_SLCK (0x5u << 24) /**< \brief (SHDW_MR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
+/* -------- SHDW_SR : (SHDWC Offset: 0x08) Shutdown Status Register -------- */
+#define SHDW_SR_WKUPS (0x1u << 0) /**< \brief (SHDW_SR) WKUP Wake-up Status */
+#define   SHDW_SR_WKUPS_NO (0x0u << 0) /**< \brief (SHDW_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define   SHDW_SR_WKUPS_PRESENT (0x1u << 0) /**< \brief (SHDW_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define SHDW_SR_ACCWK (0x1u << 6) /**< \brief (SHDW_SR) Analog Comparator Controller Wake-up */
+#define SHDW_SR_RXLPWK (0x1u << 7) /**< \brief (SHDW_SR) Debug Unit Wake-up */
+#define SHDW_SR_WKUPIS0 (0x1u << 16) /**< \brief (SHDW_SR) Wake-up 0 Input Status */
+#define   SHDW_SR_WKUPIS0_DISABLE (0x0u << 16) /**< \brief (SHDW_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define   SHDW_SR_WKUPIS0_ENABLE (0x1u << 16) /**< \brief (SHDW_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SHDW_SR_WKUPIS1 (0x1u << 17) /**< \brief (SHDW_SR) Wake-up 1 Input Status */
+#define   SHDW_SR_WKUPIS1_DISABLE (0x0u << 17) /**< \brief (SHDW_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define   SHDW_SR_WKUPIS1_ENABLE (0x1u << 17) /**< \brief (SHDW_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SHDW_SR_WKUPIS2 (0x1u << 18) /**< \brief (SHDW_SR) Wake-up 2 Input Status */
+#define   SHDW_SR_WKUPIS2_DISABLE (0x0u << 18) /**< \brief (SHDW_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define   SHDW_SR_WKUPIS2_ENABLE (0x1u << 18) /**< \brief (SHDW_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SHDW_SR_WKUPIS3 (0x1u << 19) /**< \brief (SHDW_SR) Wake-up 3 Input Status */
+#define   SHDW_SR_WKUPIS3_DISABLE (0x0u << 19) /**< \brief (SHDW_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define   SHDW_SR_WKUPIS3_ENABLE (0x1u << 19) /**< \brief (SHDW_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SHDW_SR_WKUPIS4 (0x1u << 20) /**< \brief (SHDW_SR) Wake-up 4 Input Status */
+#define   SHDW_SR_WKUPIS4_DISABLE (0x0u << 20) /**< \brief (SHDW_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define   SHDW_SR_WKUPIS4_ENABLE (0x1u << 20) /**< \brief (SHDW_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SHDW_SR_WKUPIS5 (0x1u << 21) /**< \brief (SHDW_SR) Wake-up 5 Input Status */
+#define   SHDW_SR_WKUPIS5_DISABLE (0x0u << 21) /**< \brief (SHDW_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define   SHDW_SR_WKUPIS5_ENABLE (0x1u << 21) /**< \brief (SHDW_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SHDW_SR_WKUPIS6 (0x1u << 22) /**< \brief (SHDW_SR) Wake-up 6 Input Status */
+#define   SHDW_SR_WKUPIS6_DISABLE (0x0u << 22) /**< \brief (SHDW_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define   SHDW_SR_WKUPIS6_ENABLE (0x1u << 22) /**< \brief (SHDW_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SHDW_SR_WKUPIS7 (0x1u << 23) /**< \brief (SHDW_SR) Wake-up 7 Input Status */
+#define   SHDW_SR_WKUPIS7_DISABLE (0x0u << 23) /**< \brief (SHDW_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define   SHDW_SR_WKUPIS7_ENABLE (0x1u << 23) /**< \brief (SHDW_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+#define SHDW_SR_WKUPIS8 (0x1u << 24) /**< \brief (SHDW_SR) Wake-up 8 Input Status */
+#define   SHDW_SR_WKUPIS8_DISABLE (0x0u << 24) /**< \brief (SHDW_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
+#define   SHDW_SR_WKUPIS8_ENABLE (0x1u << 24) /**< \brief (SHDW_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */
+/* -------- SHDW_WUIR : (SHDWC Offset: 0x0C) Shutdown Wake-up Inputs Register -------- */
+#define SHDW_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SHDW_WUIR) Wake-up 0 Input Enable */
+#define   SHDW_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SHDW_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define   SHDW_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SHDW_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SHDW_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SHDW_WUIR) Wake-up 1 Input Enable */
+#define   SHDW_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SHDW_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define   SHDW_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SHDW_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SHDW_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SHDW_WUIR) Wake-up 2 Input Enable */
+#define   SHDW_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SHDW_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define   SHDW_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SHDW_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SHDW_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SHDW_WUIR) Wake-up 3 Input Enable */
+#define   SHDW_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SHDW_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define   SHDW_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SHDW_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SHDW_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SHDW_WUIR) Wake-up 4 Input Enable */
+#define   SHDW_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SHDW_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define   SHDW_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SHDW_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SHDW_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SHDW_WUIR) Wake-up 5 Input Enable */
+#define   SHDW_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SHDW_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define   SHDW_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SHDW_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SHDW_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SHDW_WUIR) Wake-up 6 Input Enable */
+#define   SHDW_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SHDW_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define   SHDW_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SHDW_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SHDW_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SHDW_WUIR) Wake-up 7 Input Enable */
+#define   SHDW_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SHDW_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define   SHDW_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SHDW_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SHDW_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SHDW_WUIR) Wake-up 8 Input Enable */
+#define   SHDW_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SHDW_WUIR) The corresponding wake-up input has no wake-up effect. */
+#define   SHDW_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SHDW_WUIR) The corresponding wake-up input forces the wake-up of the core power supply. */
+#define SHDW_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SHDW_WUIR) Wake-up 0 Input Type */
+#define   SHDW_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SHDW_WUIR) A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define   SHDW_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SHDW_WUIR) A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SHDW_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SHDW_WUIR) Wake-up 1 Input Type */
+#define   SHDW_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SHDW_WUIR) A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define   SHDW_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SHDW_WUIR) A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SHDW_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SHDW_WUIR) Wake-up 2 Input Type */
+#define   SHDW_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SHDW_WUIR) A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define   SHDW_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SHDW_WUIR) A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SHDW_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SHDW_WUIR) Wake-up 3 Input Type */
+#define   SHDW_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SHDW_WUIR) A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define   SHDW_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SHDW_WUIR) A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SHDW_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SHDW_WUIR) Wake-up 4 Input Type */
+#define   SHDW_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SHDW_WUIR) A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define   SHDW_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SHDW_WUIR) A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SHDW_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SHDW_WUIR) Wake-up 5 Input Type */
+#define   SHDW_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SHDW_WUIR) A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define   SHDW_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SHDW_WUIR) A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SHDW_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SHDW_WUIR) Wake-up 6 Input Type */
+#define   SHDW_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SHDW_WUIR) A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define   SHDW_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SHDW_WUIR) A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SHDW_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SHDW_WUIR) Wake-up 7 Input Type */
+#define   SHDW_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SHDW_WUIR) A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define   SHDW_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SHDW_WUIR) A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define SHDW_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SHDW_WUIR) Wake-up 8 Input Type */
+#define   SHDW_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SHDW_WUIR) A falling edge followed by a low level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */
+#define   SHDW_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SHDW_WUIR) A rising edge followed by a high level, for a period defined by WKUPDBC, on the corresponding wake-up input forces the wake-up of the core power supply. */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_SHDWC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_smc.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_smc.h
new file mode 100644
index 000000000..a874ff72c
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_smc.h
@@ -0,0 +1,483 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_SMC_COMPONENT_
+#define _SAMA5D2_SMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Static Memory Controller */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_SMC Static Memory Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief SmcCs_number hardware registers */
+typedef struct {
+  __IO uint32_t HSMC_SETUP;   /**< \brief (SmcCs_number Offset: 0x0) HSMC Setup Register */
+  __IO uint32_t HSMC_PULSE;   /**< \brief (SmcCs_number Offset: 0x4) HSMC Pulse Register */
+  __IO uint32_t HSMC_CYCLE;   /**< \brief (SmcCs_number Offset: 0x8) HSMC Cycle Register */
+  __IO uint32_t HSMC_TIMINGS; /**< \brief (SmcCs_number Offset: 0xC) HSMC Timings Register */
+  __IO uint32_t HSMC_MODE;    /**< \brief (SmcCs_number Offset: 0x10) HSMC Mode Register */
+} SmcCs_number;
+/** \brief SmcPmecc hardware registers */
+typedef struct {
+  __I uint32_t HSMC_PMECC[14]; /**< \brief (SmcPmecc Offset: 0x0) PMECC Redundancy x Register */
+  __I uint32_t Reserved1[2];
+} SmcPmecc;
+/** \brief SmcRem hardware registers */
+typedef struct {
+  __I uint32_t HSMC_REM0_;  /**< \brief (SmcRem Offset: 0x0) PMECC Remainder 0 Register */
+  __I uint32_t HSMC_REM1_;  /**< \brief (SmcRem Offset: 0x4) PMECC Remainder 1 Register */
+  __I uint32_t HSMC_REM2_;  /**< \brief (SmcRem Offset: 0x8) PMECC Remainder 2 Register */
+  __I uint32_t HSMC_REM3_;  /**< \brief (SmcRem Offset: 0xC) PMECC Remainder 3 Register */
+  __I uint32_t HSMC_REM4_;  /**< \brief (SmcRem Offset: 0x10) PMECC Remainder 4 Register */
+  __I uint32_t HSMC_REM5_;  /**< \brief (SmcRem Offset: 0x14) PMECC Remainder 5 Register */
+  __I uint32_t HSMC_REM6_;  /**< \brief (SmcRem Offset: 0x18) PMECC Remainder 6 Register */
+  __I uint32_t HSMC_REM7_;  /**< \brief (SmcRem Offset: 0x1C) PMECC Remainder 7 Register */
+  __I uint32_t HSMC_REM8_;  /**< \brief (SmcRem Offset: 0x20) PMECC Remainder 8 Register */
+  __I uint32_t HSMC_REM9_;  /**< \brief (SmcRem Offset: 0x24) PMECC Remainder 9 Register */
+  __I uint32_t HSMC_REM10_; /**< \brief (SmcRem Offset: 0x28) PMECC Remainder 10 Register */
+  __I uint32_t HSMC_REM11_; /**< \brief (SmcRem Offset: 0x2C) PMECC Remainder 11 Register */
+  __I uint32_t HSMC_REM12_; /**< \brief (SmcRem Offset: 0x30) PMECC Remainder 12 Register */
+  __I uint32_t HSMC_REM13_; /**< \brief (SmcRem Offset: 0x34) PMECC Remainder 13 Register */
+  __I uint32_t HSMC_REM14_; /**< \brief (SmcRem Offset: 0x38) PMECC Remainder 14 Register */
+  __I uint32_t HSMC_REM15_; /**< \brief (SmcRem Offset: 0x3C) PMECC Remainder 15 Register */
+} SmcRem;
+/** \brief Smc hardware registers */
+#define SMCPMECC_NUMBER 8
+#define SMCREM_NUMBER 8
+#define SMCCS_NUMBER_NUMBER 4
+typedef struct {
+  __IO uint32_t     HSMC_CFG;                           /**< \brief (Smc Offset: 0x000) HSMC NFC Configuration Register */
+  __O  uint32_t     HSMC_CTRL;                          /**< \brief (Smc Offset: 0x004) HSMC NFC Control Register */
+  __I  uint32_t     HSMC_SR;                            /**< \brief (Smc Offset: 0x008) HSMC NFC Status Register */
+  __O  uint32_t     HSMC_IER;                           /**< \brief (Smc Offset: 0x00C) HSMC NFC Interrupt Enable Register */
+  __O  uint32_t     HSMC_IDR;                           /**< \brief (Smc Offset: 0x010) HSMC NFC Interrupt Disable Register */
+  __I  uint32_t     HSMC_IMR;                           /**< \brief (Smc Offset: 0x014) HSMC NFC Interrupt Mask Register */
+  __IO uint32_t     HSMC_ADDR;                          /**< \brief (Smc Offset: 0x018) HSMC NFC Address Cycle Zero Register */
+  __IO uint32_t     HSMC_BANK;                          /**< \brief (Smc Offset: 0x01C) HSMC Bank Address Register */
+  __I  uint32_t     Reserved1[20];
+  __IO uint32_t     HSMC_PMECCFG;                       /**< \brief (Smc Offset: 0x070) PMECC Configuration Register */
+  __IO uint32_t     HSMC_PMECCSAREA;                    /**< \brief (Smc Offset: 0x074) PMECC Spare Area Size Register */
+  __IO uint32_t     HSMC_PMECCSADDR;                    /**< \brief (Smc Offset: 0x078) PMECC Start Address Register */
+  __IO uint32_t     HSMC_PMECCEADDR;                    /**< \brief (Smc Offset: 0x07C) PMECC End Address Register */
+  __I  uint32_t     Reserved2[1];
+  __O  uint32_t     HSMC_PMECCTRL;                      /**< \brief (Smc Offset: 0x084) PMECC Control Register */
+  __I  uint32_t     HSMC_PMECCSR;                       /**< \brief (Smc Offset: 0x088) PMECC Status Register */
+  __O  uint32_t     HSMC_PMECCIER;                      /**< \brief (Smc Offset: 0x08C) PMECC Interrupt Enable register */
+  __O  uint32_t     HSMC_PMECCIDR;                      /**< \brief (Smc Offset: 0x090) PMECC Interrupt Disable Register */
+  __I  uint32_t     HSMC_PMECCIMR;                      /**< \brief (Smc Offset: 0x094) PMECC Interrupt Mask Register */
+  __I  uint32_t     HSMC_PMECCISR;                      /**< \brief (Smc Offset: 0x098) PMECC Interrupt Status Register */
+  __I  uint32_t     Reserved3[5];
+       SmcPmecc     SMC_PMECC[SMCPMECC_NUMBER];         /**< \brief (Smc Offset: 0xB0) sec_num = 0 .. 7 */
+       SmcRem       SMC_REM[SMCREM_NUMBER];             /**< \brief (Smc Offset: 0x2B0) sec_num = 0 .. 7 */
+  __I  uint32_t     Reserved4[20];
+  __IO uint32_t     HSMC_ELCFG;                         /**< \brief (Smc Offset: 0x500) PMECC Error Location Configuration Register */
+  __I  uint32_t     HSMC_ELPRIM;                        /**< \brief (Smc Offset: 0x504) PMECC Error Location Primitive Register */
+  __O  uint32_t     HSMC_ELEN;                          /**< \brief (Smc Offset: 0x508) PMECC Error Location Enable Register */
+  __O  uint32_t     HSMC_ELDIS;                         /**< \brief (Smc Offset: 0x50C) PMECC Error Location Disable Register */
+  __I  uint32_t     HSMC_ELSR;                          /**< \brief (Smc Offset: 0x510) PMECC Error Location Status Register */
+  __O  uint32_t     HSMC_ELIER;                         /**< \brief (Smc Offset: 0x514) PMECC Error Location Interrupt Enable register */
+  __O  uint32_t     HSMC_ELIDR;                         /**< \brief (Smc Offset: 0x518) PMECC Error Location Interrupt Disable Register */
+  __I  uint32_t     HSMC_ELIMR;                         /**< \brief (Smc Offset: 0x51C) PMECC Error Location Interrupt Mask Register */
+  __I  uint32_t     HSMC_ELISR;                         /**< \brief (Smc Offset: 0x520) PMECC Error Location Interrupt Status Register */
+  __I  uint32_t     Reserved5[1];
+  __IO uint32_t     HSMC_SIGMA[33];                     /**< \brief (Smc Offset: 0x528) PMECC Error Location SIGMA x Register */
+  __I  uint32_t     HSMC_ERRLOC[32];                    /**< \brief (Smc Offset: 0x5AC) PMECC Error Location x Register */
+  __I  uint32_t     Reserved6[53];
+       SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x700) CS_number = 0 .. 3 */
+  __I  uint32_t     Reserved7[20];
+  __IO uint32_t     HSMC_OCMS;                          /**< \brief (Smc Offset: 0x7A0) HSMC Off Chip Memory Scrambling Register */
+  __O  uint32_t     HSMC_KEY1;                          /**< \brief (Smc Offset: 0x7A4) HSMC Off Chip Memory Scrambling KEY1 Register */
+  __O  uint32_t     HSMC_KEY2;                          /**< \brief (Smc Offset: 0x7A8) HSMC Off Chip Memory Scrambling KEY2 Register */
+  __I  uint32_t     Reserved8[14];
+  __IO uint32_t     HSMC_WPMR;                          /**< \brief (Smc Offset: 0x7E4) HSMC Write Protection Mode Register */
+  __I  uint32_t     HSMC_WPSR;                          /**< \brief (Smc Offset: 0x7E8) HSMC Write Protection Status Register */
+  __I  uint32_t     Reserved9[4];
+  __I  uint32_t     HSMC_VERSION;                       /**< \brief (Smc Offset: 0x7FC) HSMC Version Register */
+} Smc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- HSMC_CFG : (SMC Offset: 0x000) HSMC NFC Configuration Register -------- */
+#define HSMC_CFG_PAGESIZE_Pos 0
+#define HSMC_CFG_PAGESIZE_Msk (0x7u << HSMC_CFG_PAGESIZE_Pos) /**< \brief (HSMC_CFG) Page Size of the NAND Flash Device */
+#define HSMC_CFG_PAGESIZE(value) ((HSMC_CFG_PAGESIZE_Msk & ((value) << HSMC_CFG_PAGESIZE_Pos)))
+#define   HSMC_CFG_PAGESIZE_PS512 (0x0u << 0) /**< \brief (HSMC_CFG) Main area 512 bytes */
+#define   HSMC_CFG_PAGESIZE_PS1024 (0x1u << 0) /**< \brief (HSMC_CFG) Main area 1024 bytes */
+#define   HSMC_CFG_PAGESIZE_PS2048 (0x2u << 0) /**< \brief (HSMC_CFG) Main area 2048 bytes */
+#define   HSMC_CFG_PAGESIZE_PS4096 (0x3u << 0) /**< \brief (HSMC_CFG) Main area 4096 bytes */
+#define   HSMC_CFG_PAGESIZE_PS8192 (0x4u << 0) /**< \brief (HSMC_CFG) Main area 8192 bytes */
+#define HSMC_CFG_WSPARE (0x1u << 8) /**< \brief (HSMC_CFG) Write Spare Area */
+#define HSMC_CFG_RSPARE (0x1u << 9) /**< \brief (HSMC_CFG) Read Spare Area */
+#define HSMC_CFG_EDGECTRL (0x1u << 12) /**< \brief (HSMC_CFG) Rising/Falling Edge Detection Control */
+#define HSMC_CFG_RBEDGE (0x1u << 13) /**< \brief (HSMC_CFG) Ready/Busy Signal Edge Detection */
+#define HSMC_CFG_DTOCYC_Pos 16
+#define HSMC_CFG_DTOCYC_Msk (0xfu << HSMC_CFG_DTOCYC_Pos) /**< \brief (HSMC_CFG) Data Timeout Cycle Number */
+#define HSMC_CFG_DTOCYC(value) ((HSMC_CFG_DTOCYC_Msk & ((value) << HSMC_CFG_DTOCYC_Pos)))
+#define HSMC_CFG_DTOMUL_Pos 20
+#define HSMC_CFG_DTOMUL_Msk (0x7u << HSMC_CFG_DTOMUL_Pos) /**< \brief (HSMC_CFG) Data Timeout Multiplier */
+#define HSMC_CFG_DTOMUL(value) ((HSMC_CFG_DTOMUL_Msk & ((value) << HSMC_CFG_DTOMUL_Pos)))
+#define   HSMC_CFG_DTOMUL_X1 (0x0u << 20) /**< \brief (HSMC_CFG) DTOCYC */
+#define   HSMC_CFG_DTOMUL_X16 (0x1u << 20) /**< \brief (HSMC_CFG) DTOCYC x 16 */
+#define   HSMC_CFG_DTOMUL_X128 (0x2u << 20) /**< \brief (HSMC_CFG) DTOCYC x 128 */
+#define   HSMC_CFG_DTOMUL_X256 (0x3u << 20) /**< \brief (HSMC_CFG) DTOCYC x 256 */
+#define   HSMC_CFG_DTOMUL_X1024 (0x4u << 20) /**< \brief (HSMC_CFG) DTOCYC x 1024 */
+#define   HSMC_CFG_DTOMUL_X4096 (0x5u << 20) /**< \brief (HSMC_CFG) DTOCYC x 4096 */
+#define   HSMC_CFG_DTOMUL_X65536 (0x6u << 20) /**< \brief (HSMC_CFG) DTOCYC x 65536 */
+#define   HSMC_CFG_DTOMUL_X1048576 (0x7u << 20) /**< \brief (HSMC_CFG) DTOCYC x 1048576 */
+#define HSMC_CFG_NFCSPARESIZE_Pos 24
+#define HSMC_CFG_NFCSPARESIZE_Msk (0x7fu << HSMC_CFG_NFCSPARESIZE_Pos) /**< \brief (HSMC_CFG) NAND Flash Spare Area Size Retrieved by the Host Controller */
+#define HSMC_CFG_NFCSPARESIZE(value) ((HSMC_CFG_NFCSPARESIZE_Msk & ((value) << HSMC_CFG_NFCSPARESIZE_Pos)))
+/* -------- HSMC_CTRL : (SMC Offset: 0x004) HSMC NFC Control Register -------- */
+#define HSMC_CTRL_NFCEN (0x1u << 0) /**< \brief (HSMC_CTRL) NAND Flash Controller Enable */
+#define HSMC_CTRL_NFCDIS (0x1u << 1) /**< \brief (HSMC_CTRL) NAND Flash Controller Disable */
+/* -------- HSMC_SR : (SMC Offset: 0x008) HSMC NFC Status Register -------- */
+#define HSMC_SR_SMCSTS (0x1u << 0) /**< \brief (HSMC_SR) NAND Flash Controller Status (this field cannot be reset) */
+#define HSMC_SR_RB_RISE (0x1u << 4) /**< \brief (HSMC_SR) Selected Ready Busy Rising Edge Detected */
+#define HSMC_SR_RB_FALL (0x1u << 5) /**< \brief (HSMC_SR) Selected Ready Busy Falling Edge Detected */
+#define HSMC_SR_NFCBUSY (0x1u << 8) /**< \brief (HSMC_SR) NFC Busy (this field cannot be reset) */
+#define HSMC_SR_NFCWR (0x1u << 11) /**< \brief (HSMC_SR) NFC Write/Read Operation (this field cannot be reset) */
+#define HSMC_SR_NFCSID_Pos 12
+#define HSMC_SR_NFCSID_Msk (0x7u << HSMC_SR_NFCSID_Pos) /**< \brief (HSMC_SR) NFC Chip Select ID (this field cannot be reset) */
+#define HSMC_SR_XFRDONE (0x1u << 16) /**< \brief (HSMC_SR) NFC Data Transfer Terminated */
+#define HSMC_SR_CMDDONE (0x1u << 17) /**< \brief (HSMC_SR) Command Done */
+#define HSMC_SR_DTOE (0x1u << 20) /**< \brief (HSMC_SR) Data Timeout Error */
+#define HSMC_SR_UNDEF (0x1u << 21) /**< \brief (HSMC_SR) Undefined Area Error */
+#define HSMC_SR_AWB (0x1u << 22) /**< \brief (HSMC_SR) Accessing While Busy */
+#define HSMC_SR_NFCASE (0x1u << 23) /**< \brief (HSMC_SR) NFC Access Size Error */
+#define HSMC_SR_RB_EDGE3 (0x1u << 27) /**< \brief (HSMC_SR) Ready/Busy Line 3 Edge Detected */
+/* -------- HSMC_IER : (SMC Offset: 0x00C) HSMC NFC Interrupt Enable Register -------- */
+#define HSMC_IER_RB_RISE (0x1u << 4) /**< \brief (HSMC_IER) Ready Busy Rising Edge Detection Interrupt Enable */
+#define HSMC_IER_RB_FALL (0x1u << 5) /**< \brief (HSMC_IER) Ready Busy Falling Edge Detection Interrupt Enable */
+#define HSMC_IER_XFRDONE (0x1u << 16) /**< \brief (HSMC_IER) Transfer Done Interrupt Enable */
+#define HSMC_IER_CMDDONE (0x1u << 17) /**< \brief (HSMC_IER) Command Done Interrupt Enable */
+#define HSMC_IER_DTOE (0x1u << 20) /**< \brief (HSMC_IER) Data Timeout Error Interrupt Enable */
+#define HSMC_IER_UNDEF (0x1u << 21) /**< \brief (HSMC_IER) Undefined Area Access Interrupt Enable */
+#define HSMC_IER_AWB (0x1u << 22) /**< \brief (HSMC_IER) Accessing While Busy Interrupt Enable */
+#define HSMC_IER_NFCASE (0x1u << 23) /**< \brief (HSMC_IER) NFC Access Size Error Interrupt Enable */
+#define HSMC_IER_RB_EDGE3 (0x1u << 27) /**< \brief (HSMC_IER) Ready/Busy Line 3 Interrupt Enable */
+/* -------- HSMC_IDR : (SMC Offset: 0x010) HSMC NFC Interrupt Disable Register -------- */
+#define HSMC_IDR_RB_RISE (0x1u << 4) /**< \brief (HSMC_IDR) Ready Busy Rising Edge Detection Interrupt Disable */
+#define HSMC_IDR_RB_FALL (0x1u << 5) /**< \brief (HSMC_IDR) Ready Busy Falling Edge Detection Interrupt Disable */
+#define HSMC_IDR_XFRDONE (0x1u << 16) /**< \brief (HSMC_IDR) Transfer Done Interrupt Disable */
+#define HSMC_IDR_CMDDONE (0x1u << 17) /**< \brief (HSMC_IDR) Command Done Interrupt Disable */
+#define HSMC_IDR_DTOE (0x1u << 20) /**< \brief (HSMC_IDR) Data Timeout Error Interrupt Disable */
+#define HSMC_IDR_UNDEF (0x1u << 21) /**< \brief (HSMC_IDR) Undefined Area Access Interrupt Disable */
+#define HSMC_IDR_AWB (0x1u << 22) /**< \brief (HSMC_IDR) Accessing While Busy Interrupt Disable */
+#define HSMC_IDR_NFCASE (0x1u << 23) /**< \brief (HSMC_IDR) NFC Access Size Error Interrupt Disable */
+#define HSMC_IDR_RB_EDGE3 (0x1u << 27) /**< \brief (HSMC_IDR) Ready/Busy Line 3 Interrupt Disable */
+/* -------- HSMC_IMR : (SMC Offset: 0x014) HSMC NFC Interrupt Mask Register -------- */
+#define HSMC_IMR_RB_RISE (0x1u << 4) /**< \brief (HSMC_IMR) Ready Busy Rising Edge Detection Interrupt Mask */
+#define HSMC_IMR_RB_FALL (0x1u << 5) /**< \brief (HSMC_IMR) Ready Busy Falling Edge Detection Interrupt Mask */
+#define HSMC_IMR_XFRDONE (0x1u << 16) /**< \brief (HSMC_IMR) Transfer Done Interrupt Mask */
+#define HSMC_IMR_CMDDONE (0x1u << 17) /**< \brief (HSMC_IMR) Command Done Interrupt Mask */
+#define HSMC_IMR_DTOE (0x1u << 20) /**< \brief (HSMC_IMR) Data Timeout Error Interrupt Mask */
+#define HSMC_IMR_UNDEF (0x1u << 21) /**< \brief (HSMC_IMR) Undefined Area Access Interrupt Mask5 */
+#define HSMC_IMR_AWB (0x1u << 22) /**< \brief (HSMC_IMR) Accessing While Busy Interrupt Mask */
+#define HSMC_IMR_NFCASE (0x1u << 23) /**< \brief (HSMC_IMR) NFC Access Size Error Interrupt Mask */
+#define HSMC_IMR_RB_EDGE3 (0x1u << 27) /**< \brief (HSMC_IMR) Ready/Busy Line 3 Interrupt Mask */
+/* -------- HSMC_ADDR : (SMC Offset: 0x018) HSMC NFC Address Cycle Zero Register -------- */
+#define HSMC_ADDR_ADDR_CYCLE0_Pos 0
+#define HSMC_ADDR_ADDR_CYCLE0_Msk (0xffu << HSMC_ADDR_ADDR_CYCLE0_Pos) /**< \brief (HSMC_ADDR) NAND Flash Array Address Cycle 0 */
+#define HSMC_ADDR_ADDR_CYCLE0(value) ((HSMC_ADDR_ADDR_CYCLE0_Msk & ((value) << HSMC_ADDR_ADDR_CYCLE0_Pos)))
+/* -------- HSMC_BANK : (SMC Offset: 0x01C) HSMC Bank Address Register -------- */
+#define HSMC_BANK_BANK (0x1u << 0) /**< \brief (HSMC_BANK) Bank Identifier */
+/* -------- HSMC_PMECCFG : (SMC Offset: 0x070) PMECC Configuration Register -------- */
+#define HSMC_PMECCFG_BCH_ERR_Pos 0
+#define HSMC_PMECCFG_BCH_ERR_Msk (0x7u << HSMC_PMECCFG_BCH_ERR_Pos) /**< \brief (HSMC_PMECCFG) Error Correcting Capability */
+#define HSMC_PMECCFG_BCH_ERR(value) ((HSMC_PMECCFG_BCH_ERR_Msk & ((value) << HSMC_PMECCFG_BCH_ERR_Pos)))
+#define   HSMC_PMECCFG_BCH_ERR_BCH_ERR2 (0x0u << 0) /**< \brief (HSMC_PMECCFG) 2 errors */
+#define   HSMC_PMECCFG_BCH_ERR_BCH_ERR4 (0x1u << 0) /**< \brief (HSMC_PMECCFG) 4 errors */
+#define   HSMC_PMECCFG_BCH_ERR_BCH_ERR8 (0x2u << 0) /**< \brief (HSMC_PMECCFG) 8 errors */
+#define   HSMC_PMECCFG_BCH_ERR_BCH_ERR12 (0x3u << 0) /**< \brief (HSMC_PMECCFG) 12 errors */
+#define   HSMC_PMECCFG_BCH_ERR_BCH_ERR24 (0x4u << 0) /**< \brief (HSMC_PMECCFG) 24 errors */
+#define   HSMC_PMECCFG_BCH_ERR_BCH_ERR32 (0x5u << 0) /**< \brief (HSMC_PMECCFG) 32 errors */
+#define HSMC_PMECCFG_SECTORSZ (0x1u << 4) /**< \brief (HSMC_PMECCFG) Sector Size */
+#define HSMC_PMECCFG_PAGESIZE_Pos 8
+#define HSMC_PMECCFG_PAGESIZE_Msk (0x3u << HSMC_PMECCFG_PAGESIZE_Pos) /**< \brief (HSMC_PMECCFG) Number of Sectors in the Page */
+#define HSMC_PMECCFG_PAGESIZE(value) ((HSMC_PMECCFG_PAGESIZE_Msk & ((value) << HSMC_PMECCFG_PAGESIZE_Pos)))
+#define   HSMC_PMECCFG_PAGESIZE_PAGESIZE_1SEC (0x0u << 8) /**< \brief (HSMC_PMECCFG) 1 sector for main area (512 or 1024 bytes) */
+#define   HSMC_PMECCFG_PAGESIZE_PAGESIZE_2SEC (0x1u << 8) /**< \brief (HSMC_PMECCFG) 2 sectors for main area (1024 or 2048 bytes) */
+#define   HSMC_PMECCFG_PAGESIZE_PAGESIZE_4SEC (0x2u << 8) /**< \brief (HSMC_PMECCFG) 4 sectors for main area (2048 or 4096 bytes) */
+#define   HSMC_PMECCFG_PAGESIZE_PAGESIZE_8SEC (0x3u << 8) /**< \brief (HSMC_PMECCFG) 8 sectors for main area (4096 or 8192 bytes) */
+#define HSMC_PMECCFG_NANDWR (0x1u << 12) /**< \brief (HSMC_PMECCFG) NAND Write Access */
+#define HSMC_PMECCFG_SPAREEN (0x1u << 16) /**< \brief (HSMC_PMECCFG) Spare Enable */
+#define HSMC_PMECCFG_AUTO (0x1u << 20) /**< \brief (HSMC_PMECCFG) Automatic Mode Enable */
+/* -------- HSMC_PMECCSAREA : (SMC Offset: 0x074) PMECC Spare Area Size Register -------- */
+#define HSMC_PMECCSAREA_SPARESIZE_Pos 0
+#define HSMC_PMECCSAREA_SPARESIZE_Msk (0x1ffu << HSMC_PMECCSAREA_SPARESIZE_Pos) /**< \brief (HSMC_PMECCSAREA) Spare Area Size */
+#define HSMC_PMECCSAREA_SPARESIZE(value) ((HSMC_PMECCSAREA_SPARESIZE_Msk & ((value) << HSMC_PMECCSAREA_SPARESIZE_Pos)))
+/* -------- HSMC_PMECCSADDR : (SMC Offset: 0x078) PMECC Start Address Register -------- */
+#define HSMC_PMECCSADDR_STARTADDR_Pos 0
+#define HSMC_PMECCSADDR_STARTADDR_Msk (0x1ffu << HSMC_PMECCSADDR_STARTADDR_Pos) /**< \brief (HSMC_PMECCSADDR) ECC Area Start Address */
+#define HSMC_PMECCSADDR_STARTADDR(value) ((HSMC_PMECCSADDR_STARTADDR_Msk & ((value) << HSMC_PMECCSADDR_STARTADDR_Pos)))
+/* -------- HSMC_PMECCEADDR : (SMC Offset: 0x07C) PMECC End Address Register -------- */
+#define HSMC_PMECCEADDR_ENDADDR_Pos 0
+#define HSMC_PMECCEADDR_ENDADDR_Msk (0x1ffu << HSMC_PMECCEADDR_ENDADDR_Pos) /**< \brief (HSMC_PMECCEADDR) ECC Area End Address */
+#define HSMC_PMECCEADDR_ENDADDR(value) ((HSMC_PMECCEADDR_ENDADDR_Msk & ((value) << HSMC_PMECCEADDR_ENDADDR_Pos)))
+/* -------- HSMC_PMECCTRL : (SMC Offset: 0x084) PMECC Control Register -------- */
+#define HSMC_PMECCTRL_RST (0x1u << 0) /**< \brief (HSMC_PMECCTRL) Reset the PMECC Module */
+#define HSMC_PMECCTRL_DATA (0x1u << 1) /**< \brief (HSMC_PMECCTRL) Start a Data Phase */
+#define HSMC_PMECCTRL_USER (0x1u << 2) /**< \brief (HSMC_PMECCTRL) Start a User Mode Phase */
+#define HSMC_PMECCTRL_ENABLE (0x1u << 4) /**< \brief (HSMC_PMECCTRL) PMECC Enable */
+#define HSMC_PMECCTRL_DISABLE (0x1u << 5) /**< \brief (HSMC_PMECCTRL) PMECC Enable */
+/* -------- HSMC_PMECCSR : (SMC Offset: 0x088) PMECC Status Register -------- */
+#define HSMC_PMECCSR_BUSY (0x1u << 0) /**< \brief (HSMC_PMECCSR) The kernel of the PMECC is busy */
+#define HSMC_PMECCSR_ENABLE (0x1u << 4) /**< \brief (HSMC_PMECCSR) PMECC Enable bit */
+/* -------- HSMC_PMECCIER : (SMC Offset: 0x08C) PMECC Interrupt Enable register -------- */
+#define HSMC_PMECCIER_ERRIE (0x1u << 0) /**< \brief (HSMC_PMECCIER) Error Interrupt Enable */
+/* -------- HSMC_PMECCIDR : (SMC Offset: 0x090) PMECC Interrupt Disable Register -------- */
+#define HSMC_PMECCIDR_ERRID (0x1u << 0) /**< \brief (HSMC_PMECCIDR) Error Interrupt Disable */
+/* -------- HSMC_PMECCIMR : (SMC Offset: 0x094) PMECC Interrupt Mask Register -------- */
+#define HSMC_PMECCIMR_ERRIM (0x1u << 0) /**< \brief (HSMC_PMECCIMR) Error Interrupt Mask */
+/* -------- HSMC_PMECCISR : (SMC Offset: 0x098) PMECC Interrupt Status Register -------- */
+#define HSMC_PMECCISR_ERRIS_Pos 0
+#define HSMC_PMECCISR_ERRIS_Msk (0xffu << HSMC_PMECCISR_ERRIS_Pos) /**< \brief (HSMC_PMECCISR) Error Interrupt Status Register */
+/* -------- HSMC_PMECC[14] : (SMC Offset: N/A) PMECC Redundancy x Register -------- */
+#define HSMC_PMECC_ECC_Pos 0
+#define HSMC_PMECC_ECC_Msk (0xffffffffu << HSMC_PMECC_ECC_Pos) /**< \brief (HSMC_PMECC[14]) BCH Redundancy */
+/* -------- HSMC_REM0_ : (SMC Offset: N/A) PMECC Remainder 0 Register -------- */
+#define HSMC_REM0__REM2NP1_Pos 0
+#define HSMC_REM0__REM2NP1_Msk (0x3fffu << HSMC_REM0__REM2NP1_Pos) /**< \brief (HSMC_REM0_) BCH Remainder 2 * N + 1 */
+#define HSMC_REM0__REM2NP3_Pos 16
+#define HSMC_REM0__REM2NP3_Msk (0x3fffu << HSMC_REM0__REM2NP3_Pos) /**< \brief (HSMC_REM0_) BCH Remainder 2 * N + 3 */
+/* -------- HSMC_REM1_ : (SMC Offset: N/A) PMECC Remainder 1 Register -------- */
+#define HSMC_REM1__REM2NP1_Pos 0
+#define HSMC_REM1__REM2NP1_Msk (0x3fffu << HSMC_REM1__REM2NP1_Pos) /**< \brief (HSMC_REM1_) BCH Remainder 2 * N + 1 */
+#define HSMC_REM1__REM2NP3_Pos 16
+#define HSMC_REM1__REM2NP3_Msk (0x3fffu << HSMC_REM1__REM2NP3_Pos) /**< \brief (HSMC_REM1_) BCH Remainder 2 * N + 3 */
+/* -------- HSMC_REM2_ : (SMC Offset: N/A) PMECC Remainder 2 Register -------- */
+#define HSMC_REM2__REM2NP1_Pos 0
+#define HSMC_REM2__REM2NP1_Msk (0x3fffu << HSMC_REM2__REM2NP1_Pos) /**< \brief (HSMC_REM2_) BCH Remainder 2 * N + 1 */
+#define HSMC_REM2__REM2NP3_Pos 16
+#define HSMC_REM2__REM2NP3_Msk (0x3fffu << HSMC_REM2__REM2NP3_Pos) /**< \brief (HSMC_REM2_) BCH Remainder 2 * N + 3 */
+/* -------- HSMC_REM3_ : (SMC Offset: N/A) PMECC Remainder 3 Register -------- */
+#define HSMC_REM3__REM2NP1_Pos 0
+#define HSMC_REM3__REM2NP1_Msk (0x3fffu << HSMC_REM3__REM2NP1_Pos) /**< \brief (HSMC_REM3_) BCH Remainder 2 * N + 1 */
+#define HSMC_REM3__REM2NP3_Pos 16
+#define HSMC_REM3__REM2NP3_Msk (0x3fffu << HSMC_REM3__REM2NP3_Pos) /**< \brief (HSMC_REM3_) BCH Remainder 2 * N + 3 */
+/* -------- HSMC_REM4_ : (SMC Offset: N/A) PMECC Remainder 4 Register -------- */
+#define HSMC_REM4__REM2NP1_Pos 0
+#define HSMC_REM4__REM2NP1_Msk (0x3fffu << HSMC_REM4__REM2NP1_Pos) /**< \brief (HSMC_REM4_) BCH Remainder 2 * N + 1 */
+#define HSMC_REM4__REM2NP3_Pos 16
+#define HSMC_REM4__REM2NP3_Msk (0x3fffu << HSMC_REM4__REM2NP3_Pos) /**< \brief (HSMC_REM4_) BCH Remainder 2 * N + 3 */
+/* -------- HSMC_REM5_ : (SMC Offset: N/A) PMECC Remainder 5 Register -------- */
+#define HSMC_REM5__REM2NP1_Pos 0
+#define HSMC_REM5__REM2NP1_Msk (0x3fffu << HSMC_REM5__REM2NP1_Pos) /**< \brief (HSMC_REM5_) BCH Remainder 2 * N + 1 */
+#define HSMC_REM5__REM2NP3_Pos 16
+#define HSMC_REM5__REM2NP3_Msk (0x3fffu << HSMC_REM5__REM2NP3_Pos) /**< \brief (HSMC_REM5_) BCH Remainder 2 * N + 3 */
+/* -------- HSMC_REM6_ : (SMC Offset: N/A) PMECC Remainder 6 Register -------- */
+#define HSMC_REM6__REM2NP1_Pos 0
+#define HSMC_REM6__REM2NP1_Msk (0x3fffu << HSMC_REM6__REM2NP1_Pos) /**< \brief (HSMC_REM6_) BCH Remainder 2 * N + 1 */
+#define HSMC_REM6__REM2NP3_Pos 16
+#define HSMC_REM6__REM2NP3_Msk (0x3fffu << HSMC_REM6__REM2NP3_Pos) /**< \brief (HSMC_REM6_) BCH Remainder 2 * N + 3 */
+/* -------- HSMC_REM7_ : (SMC Offset: N/A) PMECC Remainder 7 Register -------- */
+#define HSMC_REM7__REM2NP1_Pos 0
+#define HSMC_REM7__REM2NP1_Msk (0x3fffu << HSMC_REM7__REM2NP1_Pos) /**< \brief (HSMC_REM7_) BCH Remainder 2 * N + 1 */
+#define HSMC_REM7__REM2NP3_Pos 16
+#define HSMC_REM7__REM2NP3_Msk (0x3fffu << HSMC_REM7__REM2NP3_Pos) /**< \brief (HSMC_REM7_) BCH Remainder 2 * N + 3 */
+/* -------- HSMC_REM8_ : (SMC Offset: N/A) PMECC Remainder 8 Register -------- */
+#define HSMC_REM8__REM2NP1_Pos 0
+#define HSMC_REM8__REM2NP1_Msk (0x3fffu << HSMC_REM8__REM2NP1_Pos) /**< \brief (HSMC_REM8_) BCH Remainder 2 * N + 1 */
+#define HSMC_REM8__REM2NP3_Pos 16
+#define HSMC_REM8__REM2NP3_Msk (0x3fffu << HSMC_REM8__REM2NP3_Pos) /**< \brief (HSMC_REM8_) BCH Remainder 2 * N + 3 */
+/* -------- HSMC_REM9_ : (SMC Offset: N/A) PMECC Remainder 9 Register -------- */
+#define HSMC_REM9__REM2NP1_Pos 0
+#define HSMC_REM9__REM2NP1_Msk (0x3fffu << HSMC_REM9__REM2NP1_Pos) /**< \brief (HSMC_REM9_) BCH Remainder 2 * N + 1 */
+#define HSMC_REM9__REM2NP3_Pos 16
+#define HSMC_REM9__REM2NP3_Msk (0x3fffu << HSMC_REM9__REM2NP3_Pos) /**< \brief (HSMC_REM9_) BCH Remainder 2 * N + 3 */
+/* -------- HSMC_REM10_ : (SMC Offset: N/A) PMECC Remainder 10 Register -------- */
+#define HSMC_REM10__REM2NP1_Pos 0
+#define HSMC_REM10__REM2NP1_Msk (0x3fffu << HSMC_REM10__REM2NP1_Pos) /**< \brief (HSMC_REM10_) BCH Remainder 2 * N + 1 */
+#define HSMC_REM10__REM2NP3_Pos 16
+#define HSMC_REM10__REM2NP3_Msk (0x3fffu << HSMC_REM10__REM2NP3_Pos) /**< \brief (HSMC_REM10_) BCH Remainder 2 * N + 3 */
+/* -------- HSMC_REM11_ : (SMC Offset: N/A) PMECC Remainder 11 Register -------- */
+#define HSMC_REM11__REM2NP1_Pos 0
+#define HSMC_REM11__REM2NP1_Msk (0x3fffu << HSMC_REM11__REM2NP1_Pos) /**< \brief (HSMC_REM11_) BCH Remainder 2 * N + 1 */
+#define HSMC_REM11__REM2NP3_Pos 16
+#define HSMC_REM11__REM2NP3_Msk (0x3fffu << HSMC_REM11__REM2NP3_Pos) /**< \brief (HSMC_REM11_) BCH Remainder 2 * N + 3 */
+/* -------- HSMC_REM12_ : (SMC Offset: N/A) PMECC Remainder 12 Register -------- */
+#define HSMC_REM12__REM2NP1_Pos 0
+#define HSMC_REM12__REM2NP1_Msk (0x3fffu << HSMC_REM12__REM2NP1_Pos) /**< \brief (HSMC_REM12_) BCH Remainder 2 * N + 1 */
+#define HSMC_REM12__REM2NP3_Pos 16
+#define HSMC_REM12__REM2NP3_Msk (0x3fffu << HSMC_REM12__REM2NP3_Pos) /**< \brief (HSMC_REM12_) BCH Remainder 2 * N + 3 */
+/* -------- HSMC_REM13_ : (SMC Offset: N/A) PMECC Remainder 13 Register -------- */
+#define HSMC_REM13__REM2NP1_Pos 0
+#define HSMC_REM13__REM2NP1_Msk (0x3fffu << HSMC_REM13__REM2NP1_Pos) /**< \brief (HSMC_REM13_) BCH Remainder 2 * N + 1 */
+#define HSMC_REM13__REM2NP3_Pos 16
+#define HSMC_REM13__REM2NP3_Msk (0x3fffu << HSMC_REM13__REM2NP3_Pos) /**< \brief (HSMC_REM13_) BCH Remainder 2 * N + 3 */
+/* -------- HSMC_REM14_ : (SMC Offset: N/A) PMECC Remainder 14 Register -------- */
+#define HSMC_REM14__REM2NP1_Pos 0
+#define HSMC_REM14__REM2NP1_Msk (0x3fffu << HSMC_REM14__REM2NP1_Pos) /**< \brief (HSMC_REM14_) BCH Remainder 2 * N + 1 */
+#define HSMC_REM14__REM2NP3_Pos 16
+#define HSMC_REM14__REM2NP3_Msk (0x3fffu << HSMC_REM14__REM2NP3_Pos) /**< \brief (HSMC_REM14_) BCH Remainder 2 * N + 3 */
+/* -------- HSMC_REM15_ : (SMC Offset: N/A) PMECC Remainder 15 Register -------- */
+#define HSMC_REM15__REM2NP1_Pos 0
+#define HSMC_REM15__REM2NP1_Msk (0x3fffu << HSMC_REM15__REM2NP1_Pos) /**< \brief (HSMC_REM15_) BCH Remainder 2 * N + 1 */
+#define HSMC_REM15__REM2NP3_Pos 16
+#define HSMC_REM15__REM2NP3_Msk (0x3fffu << HSMC_REM15__REM2NP3_Pos) /**< \brief (HSMC_REM15_) BCH Remainder 2 * N + 3 */
+/* -------- HSMC_ELCFG : (SMC Offset: 0x500) PMECC Error Location Configuration Register -------- */
+#define HSMC_ELCFG_SECTORSZ (0x1u << 0) /**< \brief (HSMC_ELCFG) Sector Size */
+#define HSMC_ELCFG_ERRNUM_Pos 16
+#define HSMC_ELCFG_ERRNUM_Msk (0x1fu << HSMC_ELCFG_ERRNUM_Pos) /**< \brief (HSMC_ELCFG) Number of Errors */
+#define HSMC_ELCFG_ERRNUM(value) ((HSMC_ELCFG_ERRNUM_Msk & ((value) << HSMC_ELCFG_ERRNUM_Pos)))
+/* -------- HSMC_ELPRIM : (SMC Offset: 0x504) PMECC Error Location Primitive Register -------- */
+#define HSMC_ELPRIM_PRIMITIV_Pos 0
+#define HSMC_ELPRIM_PRIMITIV_Msk (0xffffu << HSMC_ELPRIM_PRIMITIV_Pos) /**< \brief (HSMC_ELPRIM) Primitive Polynomial */
+/* -------- HSMC_ELEN : (SMC Offset: 0x508) PMECC Error Location Enable Register -------- */
+#define HSMC_ELEN_ENINIT_Pos 0
+#define HSMC_ELEN_ENINIT_Msk (0x3fffu << HSMC_ELEN_ENINIT_Pos) /**< \brief (HSMC_ELEN) Error Location Enable */
+#define HSMC_ELEN_ENINIT(value) ((HSMC_ELEN_ENINIT_Msk & ((value) << HSMC_ELEN_ENINIT_Pos)))
+/* -------- HSMC_ELDIS : (SMC Offset: 0x50C) PMECC Error Location Disable Register -------- */
+#define HSMC_ELDIS_DIS (0x1u << 0) /**< \brief (HSMC_ELDIS) Disable Error Location Engine */
+/* -------- HSMC_ELSR : (SMC Offset: 0x510) PMECC Error Location Status Register -------- */
+#define HSMC_ELSR_BUSY (0x1u << 0) /**< \brief (HSMC_ELSR) Error Location Engine Busy */
+/* -------- HSMC_ELIER : (SMC Offset: 0x514) PMECC Error Location Interrupt Enable register -------- */
+#define HSMC_ELIER_DONE (0x1u << 0) /**< \brief (HSMC_ELIER) Computation Terminated Interrupt Enable */
+/* -------- HSMC_ELIDR : (SMC Offset: 0x518) PMECC Error Location Interrupt Disable Register -------- */
+#define HSMC_ELIDR_DONE (0x1u << 0) /**< \brief (HSMC_ELIDR) Computation Terminated Interrupt Disable */
+/* -------- HSMC_ELIMR : (SMC Offset: 0x51C) PMECC Error Location Interrupt Mask Register -------- */
+#define HSMC_ELIMR_DONE (0x1u << 0) /**< \brief (HSMC_ELIMR) Computation Terminated Interrupt Mask */
+/* -------- HSMC_ELISR : (SMC Offset: 0x520) PMECC Error Location Interrupt Status Register -------- */
+#define HSMC_ELISR_DONE (0x1u << 0) /**< \brief (HSMC_ELISR) Computation Terminated Interrupt Status */
+#define HSMC_ELISR_ERR_CNT_Pos 8
+#define HSMC_ELISR_ERR_CNT_Msk (0x3fu << HSMC_ELISR_ERR_CNT_Pos) /**< \brief (HSMC_ELISR) Error Counter value */
+/* -------- HSMC_SIGMA[33] : (SMC Offset: 0x528) PMECC Error Location SIGMA 0 Registers -------- */
+#define HSMC_SIGMA_SIGMA_Pos 0
+#define HSMC_SIGMA_SIGMA_Msk (0x3fffu << HSMC_SIGMA_SIGMA_Pos) /**< \brief (HSMC_SIGMA[33]) Coefficient of degree x in the SIGMA polynomial */
+/* -------- HSMC_ERRLOC[32] : (SMC Offset: 0x5AC) PMECC Error Location 0 Register -------- */
+#define HSMC_ERRLOC_ERRLOCN_Pos 0
+#define HSMC_ERRLOC_ERRLOCN_Msk (0x3fffu << HSMC_ERRLOC_ERRLOCN_Pos) /**< \brief (HSMC_ERRLOC[32]) Error Position within the Set {sector area, spare area} */
+/* -------- HSMC_SETUP : (SMC Offset: N/A) HSMC Setup Register -------- */
+#define HSMC_SETUP_NWE_SETUP_Pos 0
+#define HSMC_SETUP_NWE_SETUP_Msk (0x3fu << HSMC_SETUP_NWE_SETUP_Pos) /**< \brief (HSMC_SETUP) NWE Setup Length */
+#define HSMC_SETUP_NWE_SETUP(value) ((HSMC_SETUP_NWE_SETUP_Msk & ((value) << HSMC_SETUP_NWE_SETUP_Pos)))
+#define HSMC_SETUP_NCS_WR_SETUP_Pos 8
+#define HSMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << HSMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (HSMC_SETUP) NCS Setup Length in Write Access */
+#define HSMC_SETUP_NCS_WR_SETUP(value) ((HSMC_SETUP_NCS_WR_SETUP_Msk & ((value) << HSMC_SETUP_NCS_WR_SETUP_Pos)))
+#define HSMC_SETUP_NRD_SETUP_Pos 16
+#define HSMC_SETUP_NRD_SETUP_Msk (0x3fu << HSMC_SETUP_NRD_SETUP_Pos) /**< \brief (HSMC_SETUP) NRD Setup Length */
+#define HSMC_SETUP_NRD_SETUP(value) ((HSMC_SETUP_NRD_SETUP_Msk & ((value) << HSMC_SETUP_NRD_SETUP_Pos)))
+#define HSMC_SETUP_NCS_RD_SETUP_Pos 24
+#define HSMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << HSMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (HSMC_SETUP) NCS Setup Length in Read Access */
+#define HSMC_SETUP_NCS_RD_SETUP(value) ((HSMC_SETUP_NCS_RD_SETUP_Msk & ((value) << HSMC_SETUP_NCS_RD_SETUP_Pos)))
+/* -------- HSMC_PULSE : (SMC Offset: N/A) HSMC Pulse Register -------- */
+#define HSMC_PULSE_NWE_PULSE_Pos 0
+#define HSMC_PULSE_NWE_PULSE_Msk (0x7fu << HSMC_PULSE_NWE_PULSE_Pos) /**< \brief (HSMC_PULSE) NWE Pulse Length */
+#define HSMC_PULSE_NWE_PULSE(value) ((HSMC_PULSE_NWE_PULSE_Msk & ((value) << HSMC_PULSE_NWE_PULSE_Pos)))
+#define HSMC_PULSE_NCS_WR_PULSE_Pos 8
+#define HSMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << HSMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (HSMC_PULSE) NCS Pulse Length in WRITE Access */
+#define HSMC_PULSE_NCS_WR_PULSE(value) ((HSMC_PULSE_NCS_WR_PULSE_Msk & ((value) << HSMC_PULSE_NCS_WR_PULSE_Pos)))
+#define HSMC_PULSE_NRD_PULSE_Pos 16
+#define HSMC_PULSE_NRD_PULSE_Msk (0x7fu << HSMC_PULSE_NRD_PULSE_Pos) /**< \brief (HSMC_PULSE) NRD Pulse Length */
+#define HSMC_PULSE_NRD_PULSE(value) ((HSMC_PULSE_NRD_PULSE_Msk & ((value) << HSMC_PULSE_NRD_PULSE_Pos)))
+#define HSMC_PULSE_NCS_RD_PULSE_Pos 24
+#define HSMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << HSMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (HSMC_PULSE) NCS Pulse Length in READ Access */
+#define HSMC_PULSE_NCS_RD_PULSE(value) ((HSMC_PULSE_NCS_RD_PULSE_Msk & ((value) << HSMC_PULSE_NCS_RD_PULSE_Pos)))
+/* -------- HSMC_CYCLE : (SMC Offset: N/A) HSMC Cycle Register -------- */
+#define HSMC_CYCLE_NWE_CYCLE_Pos 0
+#define HSMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << HSMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (HSMC_CYCLE) Total Write Cycle Length */
+#define HSMC_CYCLE_NWE_CYCLE(value) ((HSMC_CYCLE_NWE_CYCLE_Msk & ((value) << HSMC_CYCLE_NWE_CYCLE_Pos)))
+#define HSMC_CYCLE_NRD_CYCLE_Pos 16
+#define HSMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << HSMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (HSMC_CYCLE) Total Read Cycle Length */
+#define HSMC_CYCLE_NRD_CYCLE(value) ((HSMC_CYCLE_NRD_CYCLE_Msk & ((value) << HSMC_CYCLE_NRD_CYCLE_Pos)))
+/* -------- HSMC_TIMINGS : (SMC Offset: N/A) HSMC Timings Register -------- */
+#define HSMC_TIMINGS_TCLR_Pos 0
+#define HSMC_TIMINGS_TCLR_Msk (0xfu << HSMC_TIMINGS_TCLR_Pos) /**< \brief (HSMC_TIMINGS) CLE to REN Low Delay */
+#define HSMC_TIMINGS_TCLR(value) ((HSMC_TIMINGS_TCLR_Msk & ((value) << HSMC_TIMINGS_TCLR_Pos)))
+#define HSMC_TIMINGS_TADL_Pos 4
+#define HSMC_TIMINGS_TADL_Msk (0xfu << HSMC_TIMINGS_TADL_Pos) /**< \brief (HSMC_TIMINGS) ALE to Data Start */
+#define HSMC_TIMINGS_TADL(value) ((HSMC_TIMINGS_TADL_Msk & ((value) << HSMC_TIMINGS_TADL_Pos)))
+#define HSMC_TIMINGS_TAR_Pos 8
+#define HSMC_TIMINGS_TAR_Msk (0xfu << HSMC_TIMINGS_TAR_Pos) /**< \brief (HSMC_TIMINGS) ALE to REN Low Delay */
+#define HSMC_TIMINGS_TAR(value) ((HSMC_TIMINGS_TAR_Msk & ((value) << HSMC_TIMINGS_TAR_Pos)))
+#define HSMC_TIMINGS_OCMS (0x1u << 12) /**< \brief (HSMC_TIMINGS) Off Chip Memory Scrambling Enable */
+#define HSMC_TIMINGS_TRR_Pos 16
+#define HSMC_TIMINGS_TRR_Msk (0xfu << HSMC_TIMINGS_TRR_Pos) /**< \brief (HSMC_TIMINGS) Ready to REN Low Delay */
+#define HSMC_TIMINGS_TRR(value) ((HSMC_TIMINGS_TRR_Msk & ((value) << HSMC_TIMINGS_TRR_Pos)))
+#define HSMC_TIMINGS_TWB_Pos 24
+#define HSMC_TIMINGS_TWB_Msk (0xfu << HSMC_TIMINGS_TWB_Pos) /**< \brief (HSMC_TIMINGS) WEN High to REN to Busy */
+#define HSMC_TIMINGS_TWB(value) ((HSMC_TIMINGS_TWB_Msk & ((value) << HSMC_TIMINGS_TWB_Pos)))
+#define HSMC_TIMINGS_RBNSEL_Pos 28
+#define HSMC_TIMINGS_RBNSEL_Msk (0x7u << HSMC_TIMINGS_RBNSEL_Pos) /**< \brief (HSMC_TIMINGS) Ready/Busy Line Selection */
+#define HSMC_TIMINGS_RBNSEL(value) ((HSMC_TIMINGS_RBNSEL_Msk & ((value) << HSMC_TIMINGS_RBNSEL_Pos)))
+#define HSMC_TIMINGS_NFSEL (0x1u << 31) /**< \brief (HSMC_TIMINGS) NAND Flash Selection */
+/* -------- HSMC_MODE : (SMC Offset: N/A) HSMC Mode Register -------- */
+#define HSMC_MODE_READ_MODE (0x1u << 0) /**< \brief (HSMC_MODE) Selection of the Control Signal for Read Operation */
+#define   HSMC_MODE_READ_MODE_NCS_CTRL (0x0u << 0) /**< \brief (HSMC_MODE) The Read operation is controlled by the NCS signal. */
+#define   HSMC_MODE_READ_MODE_NRD_CTRL (0x1u << 0) /**< \brief (HSMC_MODE) The Read operation is controlled by the NRD signal. */
+#define HSMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (HSMC_MODE) Selection of the Control Signal for Write Operation */
+#define   HSMC_MODE_WRITE_MODE_NCS_CTRL (0x0u << 1) /**< \brief (HSMC_MODE) The Write operation is controller by the NCS signal. */
+#define   HSMC_MODE_WRITE_MODE_NWE_CTRL (0x1u << 1) /**< \brief (HSMC_MODE) The Write operation is controlled by the NWE signal */
+#define HSMC_MODE_EXNW_MODE_Pos 4
+#define HSMC_MODE_EXNW_MODE_Msk (0x3u << HSMC_MODE_EXNW_MODE_Pos) /**< \brief (HSMC_MODE) NWAIT Mode */
+#define HSMC_MODE_EXNW_MODE(value) ((HSMC_MODE_EXNW_MODE_Msk & ((value) << HSMC_MODE_EXNW_MODE_Pos)))
+#define   HSMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (HSMC_MODE) Disabled-The NWAIT input signal is ignored on the corresponding Chip Select. */
+#define   HSMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (HSMC_MODE) Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. */
+#define   HSMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (HSMC_MODE) Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. */
+#define HSMC_MODE_BAT (0x1u << 8) /**< \brief (HSMC_MODE) Byte Access Type */
+#define   HSMC_MODE_BAT_BYTE_SELECT (0x0u << 8) /**< \brief (HSMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. */
+#define   HSMC_MODE_BAT_BYTE_WRITE (0x1u << 8) /**< \brief (HSMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. */
+#define HSMC_MODE_DBW (0x1u << 12) /**< \brief (HSMC_MODE) Data Bus Width */
+#define   HSMC_MODE_DBW_BIT_8 (0x0u << 12) /**< \brief (HSMC_MODE) 8-bit bus */
+#define   HSMC_MODE_DBW_BIT_16 (0x1u << 12) /**< \brief (HSMC_MODE) 16-bit bus */
+#define HSMC_MODE_TDF_CYCLES_Pos 16
+#define HSMC_MODE_TDF_CYCLES_Msk (0xfu << HSMC_MODE_TDF_CYCLES_Pos) /**< \brief (HSMC_MODE) Data Float Time */
+#define HSMC_MODE_TDF_CYCLES(value) ((HSMC_MODE_TDF_CYCLES_Msk & ((value) << HSMC_MODE_TDF_CYCLES_Pos)))
+#define HSMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (HSMC_MODE) TDF Optimization */
+/* -------- HSMC_OCMS : (SMC Offset: 0x7A0) HSMC Off Chip Memory Scrambling Register -------- */
+#define HSMC_OCMS_SMSE (0x1u << 0) /**< \brief (HSMC_OCMS) Static Memory Controller Scrambling Enable */
+#define HSMC_OCMS_SRSE (0x1u << 1) /**< \brief (HSMC_OCMS) NFC Internal SRAM Scrambling Enable */
+/* -------- HSMC_KEY1 : (SMC Offset: 0x7A4) HSMC Off Chip Memory Scrambling KEY1 Register -------- */
+#define HSMC_KEY1_KEY1_Pos 0
+#define HSMC_KEY1_KEY1_Msk (0xffffffffu << HSMC_KEY1_KEY1_Pos) /**< \brief (HSMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
+#define HSMC_KEY1_KEY1(value) ((HSMC_KEY1_KEY1_Msk & ((value) << HSMC_KEY1_KEY1_Pos)))
+/* -------- HSMC_KEY2 : (SMC Offset: 0x7A8) HSMC Off Chip Memory Scrambling KEY2 Register -------- */
+#define HSMC_KEY2_KEY2_Pos 0
+#define HSMC_KEY2_KEY2_Msk (0xffffffffu << HSMC_KEY2_KEY2_Pos) /**< \brief (HSMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
+#define HSMC_KEY2_KEY2(value) ((HSMC_KEY2_KEY2_Msk & ((value) << HSMC_KEY2_KEY2_Pos)))
+/* -------- HSMC_WPMR : (SMC Offset: 0x7E4) HSMC Write Protection Mode Register -------- */
+#define HSMC_WPMR_WPEN (0x1u << 0) /**< \brief (HSMC_WPMR) Write Protection Enable */
+#define HSMC_WPMR_WPKEY_Pos 8
+#define HSMC_WPMR_WPKEY_Msk (0xffffffu << HSMC_WPMR_WPKEY_Pos) /**< \brief (HSMC_WPMR) Write Protection Key */
+#define HSMC_WPMR_WPKEY(value) ((HSMC_WPMR_WPKEY_Msk & ((value) << HSMC_WPMR_WPKEY_Pos)))
+#define   HSMC_WPMR_WPKEY_PASSWD (0x534D43u << 8) /**< \brief (HSMC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */
+/* -------- HSMC_WPSR : (SMC Offset: 0x7E8) HSMC Write Protection Status Register -------- */
+#define HSMC_WPSR_WPVS (0x1u << 0) /**< \brief (HSMC_WPSR) Write Protection Violation Status */
+#define HSMC_WPSR_WPVSRC_Pos 8
+#define HSMC_WPSR_WPVSRC_Msk (0xffffu << HSMC_WPSR_WPVSRC_Pos) /**< \brief (HSMC_WPSR) Write Protection Violation Source */
+/* -------- HSMC_VERSION : (SMC Offset: 0x7FC) HSMC Version Register -------- */
+#define HSMC_VERSION_VERSION_Pos 0
+#define HSMC_VERSION_VERSION_Msk (0xfffu << HSMC_VERSION_VERSION_Pos) /**< \brief (HSMC_VERSION) Hardware Version Number */
+#define HSMC_VERSION_MFN_Pos 16
+#define HSMC_VERSION_MFN_Msk (0x7u << HSMC_VERSION_MFN_Pos) /**< \brief (HSMC_VERSION) Metal Fix Number */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_SMC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_spi.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_spi.h
new file mode 100644
index 000000000..2ddc075ee
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_spi.h
@@ -0,0 +1,260 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_SPI_COMPONENT_
+#define _SAMA5D2_SPI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_SPI Serial Peripheral Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Spi hardware registers */
+typedef struct {
+  __O  uint32_t SPI_CR;        /**< \brief (Spi Offset: 0x00) Control Register */
+  __IO uint32_t SPI_MR;        /**< \brief (Spi Offset: 0x04) Mode Register */
+  __I  uint32_t SPI_RDR;       /**< \brief (Spi Offset: 0x08) Receive Data Register */
+  __O  uint32_t SPI_TDR;       /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
+  __I  uint32_t SPI_SR;        /**< \brief (Spi Offset: 0x10) Status Register */
+  __O  uint32_t SPI_IER;       /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
+  __O  uint32_t SPI_IDR;       /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
+  __I  uint32_t SPI_IMR;       /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
+  __I  uint32_t Reserved1[4];
+  __IO uint32_t SPI_CSR[4];    /**< \brief (Spi Offset: 0x30) Chip Select Register */
+  __IO uint32_t SPI_FMR;       /**< \brief (Spi Offset: 0x40) FIFO Mode Register */
+  __I  uint32_t SPI_FLR;       /**< \brief (Spi Offset: 0x44) FIFO Level Register */
+  __IO uint32_t SPI_CMPR;      /**< \brief (Spi Offset: 0x48) Comparison Register */
+  __I  uint32_t Reserved2[38];
+  __IO uint32_t SPI_WPMR;      /**< \brief (Spi Offset: 0xE4) Write Protection Mode Register */
+  __I  uint32_t SPI_WPSR;      /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
+} Spi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
+#define SPI_CR_REQCLR (0x1u << 12) /**< \brief (SPI_CR) Request to Clear the Comparison Trigger */
+#define SPI_CR_TXFCLR (0x1u << 16) /**< \brief (SPI_CR) Transmit FIFO Clear */
+#define SPI_CR_RXFCLR (0x1u << 17) /**< \brief (SPI_CR) Receive FIFO Clear */
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
+#define SPI_CR_FIFOEN (0x1u << 30) /**< \brief (SPI_CR) FIFO Enable */
+#define SPI_CR_FIFODIS (0x1u << 31) /**< \brief (SPI_CR) FIFO Disable */
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
+#define SPI_MR_BRSRCCLK (0x1u << 3) /**< \brief (SPI_MR) Bit Rate Source Clock */
+#define   SPI_MR_BRSRCCLK_PERIPH_CLK (0x0u << 3) /**< \brief (SPI_MR) The peripheral clock is the source clock for the bit rate generation. */
+#define   SPI_MR_BRSRCCLK_PMC_PCK (0x1u << 3) /**< \brief (SPI_MR) PMC PCKx is the source clock for the bit rate generation, thus the bit rate can be independent of the core/peripheral clock. */
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
+#define SPI_MR_CMPMODE (0x1u << 12) /**< \brief (SPI_MR) Comparison Mode */
+#define   SPI_MR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (SPI_MR) Any character is received and comparison function drives CMP flag. */
+#define   SPI_MR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (SPI_MR) Comparison condition must be met to start reception of all incoming characters until REQCLR is set. */
+#define SPI_MR_PCS_Pos 16
+#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
+#define SPI_MR_DLYBCS_Pos 24
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
+#define SPI_RDR_RD_Pos 0
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
+#define SPI_RDR_PCS_Pos 16
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
+#define SPI_RDR_RD0_Pos 0
+#define SPI_RDR_RD0_Msk (0xffu << SPI_RDR_RD0_Pos) /**< \brief (SPI_RDR) Receive Data */
+#define SPI_RDR_RD1_Pos 8
+#define SPI_RDR_RD1_Msk (0xffu << SPI_RDR_RD1_Pos) /**< \brief (SPI_RDR) Receive Data */
+#define SPI_RDR_RD2_Pos 16
+#define SPI_RDR_RD2_Msk (0xffu << SPI_RDR_RD2_Pos) /**< \brief (SPI_RDR) Receive Data */
+#define SPI_RDR_RD3_Pos 24
+#define SPI_RDR_RD3_Msk (0xffu << SPI_RDR_RD3_Pos) /**< \brief (SPI_RDR) Receive Data */
+#define SPI_RDR_RD0_FIFO_MULTI_DATA_16_Pos 0
+#define SPI_RDR_RD0_FIFO_MULTI_DATA_16_Msk (0xffffu << SPI_RDR_RD0_FIFO_MULTI_DATA_16_Pos) /**< \brief (SPI_RDR) Receive Data */
+#define SPI_RDR_RD1_FIFO_MULTI_DATA_16_Pos 16
+#define SPI_RDR_RD1_FIFO_MULTI_DATA_16_Msk (0xffffu << SPI_RDR_RD1_FIFO_MULTI_DATA_16_Pos) /**< \brief (SPI_RDR) Receive Data */
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
+#define SPI_TDR_TD_Pos 0
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
+#define SPI_TDR_PCS_Pos 16
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
+#define SPI_TDR_TD0_Pos 0
+#define SPI_TDR_TD0_Msk (0xffffu << SPI_TDR_TD0_Pos) /**< \brief (SPI_TDR) Transmit Data */
+#define SPI_TDR_TD0(value) ((SPI_TDR_TD0_Msk & ((value) << SPI_TDR_TD0_Pos)))
+#define SPI_TDR_TD1_Pos 16
+#define SPI_TDR_TD1_Msk (0xffffu << SPI_TDR_TD1_Pos) /**< \brief (SPI_TDR) Transmit Data */
+#define SPI_TDR_TD1(value) ((SPI_TDR_TD1_Msk & ((value) << SPI_TDR_TD1_Pos)))
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) */
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) */
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error (cleared on read) */
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status (cleared on read) */
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising (cleared on read) */
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) */
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) */
+#define SPI_SR_CMP (0x1u << 11) /**< \brief (SPI_SR) Comparison Status (cleared on read) */
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
+#define SPI_SR_TXFEF (0x1u << 24) /**< \brief (SPI_SR) Transmit FIFO Empty Flag (cleared on read) */
+#define SPI_SR_TXFFF (0x1u << 25) /**< \brief (SPI_SR) Transmit FIFO Full Flag (cleared on read) */
+#define SPI_SR_TXFTHF (0x1u << 26) /**< \brief (SPI_SR) Transmit FIFO Threshold Flag (cleared on read) */
+#define SPI_SR_RXFEF (0x1u << 27) /**< \brief (SPI_SR) Receive FIFO Empty Flag */
+#define SPI_SR_RXFFF (0x1u << 28) /**< \brief (SPI_SR) Receive FIFO Full Flag */
+#define SPI_SR_RXFTHF (0x1u << 29) /**< \brief (SPI_SR) Receive FIFO Threshold Flag */
+#define SPI_SR_TXFPTEF (0x1u << 30) /**< \brief (SPI_SR) Transmit FIFO Pointer Error Flag */
+#define SPI_SR_RXFPTEF (0x1u << 31) /**< \brief (SPI_SR) Receive FIFO Pointer Error Flag */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
+#define SPI_IER_CMP (0x1u << 11) /**< \brief (SPI_IER) Comparison Interrupt Enable */
+#define SPI_IER_TXFEF (0x1u << 24) /**< \brief (SPI_IER) TXFEF Interrupt Enable */
+#define SPI_IER_TXFFF (0x1u << 25) /**< \brief (SPI_IER) TXFFF Interrupt Enable */
+#define SPI_IER_TXFTHF (0x1u << 26) /**< \brief (SPI_IER) TXFTHF Interrupt Enable */
+#define SPI_IER_RXFEF (0x1u << 27) /**< \brief (SPI_IER) RXFEF Interrupt Enable */
+#define SPI_IER_RXFFF (0x1u << 28) /**< \brief (SPI_IER) RXFFF Interrupt Enable */
+#define SPI_IER_RXFTHF (0x1u << 29) /**< \brief (SPI_IER) RXFTHF Interrupt Enable */
+#define SPI_IER_TXFPTEF (0x1u << 30) /**< \brief (SPI_IER) TXFPTEF Interrupt Enable */
+#define SPI_IER_RXFPTEF (0x1u << 31) /**< \brief (SPI_IER) RXFPTEF Interrupt Enable */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
+#define SPI_IDR_CMP (0x1u << 11) /**< \brief (SPI_IDR) Comparison Interrupt Disable */
+#define SPI_IDR_TXFEF (0x1u << 24) /**< \brief (SPI_IDR) TXFEF Interrupt Disable */
+#define SPI_IDR_TXFFF (0x1u << 25) /**< \brief (SPI_IDR) TXFFF Interrupt Disable */
+#define SPI_IDR_TXFTHF (0x1u << 26) /**< \brief (SPI_IDR) TXFTHF Interrupt Disable */
+#define SPI_IDR_RXFEF (0x1u << 27) /**< \brief (SPI_IDR) RXFEF Interrupt Disable */
+#define SPI_IDR_RXFFF (0x1u << 28) /**< \brief (SPI_IDR) RXFFF Interrupt Disable */
+#define SPI_IDR_RXFTHF (0x1u << 29) /**< \brief (SPI_IDR) RXFTHF Interrupt Disable */
+#define SPI_IDR_TXFPTEF (0x1u << 30) /**< \brief (SPI_IDR) TXFPTEF Interrupt Disable */
+#define SPI_IDR_RXFPTEF (0x1u << 31) /**< \brief (SPI_IDR) RXFPTEF Interrupt Disable */
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
+#define SPI_IMR_CMP (0x1u << 11) /**< \brief (SPI_IMR) Comparison Interrupt Mask */
+#define SPI_IMR_TXFEF (0x1u << 24) /**< \brief (SPI_IMR) TXFEF Interrupt Mask */
+#define SPI_IMR_TXFFF (0x1u << 25) /**< \brief (SPI_IMR) TXFFF Interrupt Mask */
+#define SPI_IMR_TXFTHF (0x1u << 26) /**< \brief (SPI_IMR) TXFTHF Interrupt Mask */
+#define SPI_IMR_RXFEF (0x1u << 27) /**< \brief (SPI_IMR) RXFEF Interrupt Mask */
+#define SPI_IMR_RXFFF (0x1u << 28) /**< \brief (SPI_IMR) RXFFF Interrupt Mask */
+#define SPI_IMR_RXFTHF (0x1u << 29) /**< \brief (SPI_IMR) RXFTHF Interrupt Mask */
+#define SPI_IMR_TXFPTEF (0x1u << 30) /**< \brief (SPI_IMR) TXFPTEF Interrupt Mask */
+#define SPI_IMR_RXFPTEF (0x1u << 31) /**< \brief (SPI_IMR) RXFPTEF Interrupt Mask */
+/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Active After Transfer */
+#define SPI_CSR_BITS_Pos 4
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
+#define SPI_CSR_BITS(value) ((SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos)))
+#define   SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
+#define   SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
+#define   SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
+#define   SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
+#define   SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
+#define   SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
+#define   SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
+#define   SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
+#define   SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
+#define SPI_CSR_SCBR_Pos 8
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Bit Rate */
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
+#define SPI_CSR_DLYBS_Pos 16
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
+#define SPI_CSR_DLYBCT_Pos 24
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
+/* -------- SPI_FMR : (SPI Offset: 0x40) FIFO Mode Register -------- */
+#define SPI_FMR_TXRDYM_Pos 0
+#define SPI_FMR_TXRDYM_Msk (0x3u << SPI_FMR_TXRDYM_Pos) /**< \brief (SPI_FMR) Transmitter Data Register Empty Mode */
+#define SPI_FMR_TXRDYM(value) ((SPI_FMR_TXRDYM_Msk & ((value) << SPI_FMR_TXRDYM_Pos)))
+#define   SPI_FMR_TXRDYM_ONE_DATA (0x0u << 0) /**< \brief (SPI_FMR) TDRE will be at level '1' when at least one data can be written in the Transmit FIFO. */
+#define   SPI_FMR_TXRDYM_TWO_DATA (0x1u << 0) /**< \brief (SPI_FMR) TDRE will be at level '1' when at least two data can be written in the Transmit FIFO. */
+#define   SPI_FMR_TXRDYM_FOUR_DATA (0x2u << 0) /**< \brief (SPI_FMR) TDRE will be at level '1' when at least four data can be written in the Transmit FIFO. */
+#define SPI_FMR_RXRDYM_Pos 4
+#define SPI_FMR_RXRDYM_Msk (0x3u << SPI_FMR_RXRDYM_Pos) /**< \brief (SPI_FMR) Receiver Data Register Full Mode */
+#define SPI_FMR_RXRDYM(value) ((SPI_FMR_RXRDYM_Msk & ((value) << SPI_FMR_RXRDYM_Pos)))
+#define   SPI_FMR_RXRDYM_ONE_DATA (0x0u << 4) /**< \brief (SPI_FMR) RDRF will be at level '1' when at least one unread data is in the Receive FIFO. */
+#define   SPI_FMR_RXRDYM_TWO_DATA (0x1u << 4) /**< \brief (SPI_FMR) RDRF will be at level '1' when at least two unread data are in the Receive FIFO. */
+#define   SPI_FMR_RXRDYM_FOUR_DATA (0x2u << 4) /**< \brief (SPI_FMR) RDRF will be at level '1' when at least four unread data are in the Receive FIFO. */
+#define SPI_FMR_TXFTHRES_Pos 16
+#define SPI_FMR_TXFTHRES_Msk (0x3fu << SPI_FMR_TXFTHRES_Pos) /**< \brief (SPI_FMR) Transmit FIFO Threshold */
+#define SPI_FMR_TXFTHRES(value) ((SPI_FMR_TXFTHRES_Msk & ((value) << SPI_FMR_TXFTHRES_Pos)))
+#define SPI_FMR_RXFTHRES_Pos 24
+#define SPI_FMR_RXFTHRES_Msk (0x3fu << SPI_FMR_RXFTHRES_Pos) /**< \brief (SPI_FMR) Receive FIFO Threshold */
+#define SPI_FMR_RXFTHRES(value) ((SPI_FMR_RXFTHRES_Msk & ((value) << SPI_FMR_RXFTHRES_Pos)))
+/* -------- SPI_FLR : (SPI Offset: 0x44) FIFO Level Register -------- */
+#define SPI_FLR_TXFL_Pos 0
+#define SPI_FLR_TXFL_Msk (0x3fu << SPI_FLR_TXFL_Pos) /**< \brief (SPI_FLR) Transmit FIFO Level */
+#define SPI_FLR_RXFL_Pos 16
+#define SPI_FLR_RXFL_Msk (0x3fu << SPI_FLR_RXFL_Pos) /**< \brief (SPI_FLR) Receive FIFO Level */
+/* -------- SPI_CMPR : (SPI Offset: 0x48) Comparison Register -------- */
+#define SPI_CMPR_VAL1_Pos 0
+#define SPI_CMPR_VAL1_Msk (0xffffu << SPI_CMPR_VAL1_Pos) /**< \brief (SPI_CMPR) First Comparison Value for Received Character */
+#define SPI_CMPR_VAL1(value) ((SPI_CMPR_VAL1_Msk & ((value) << SPI_CMPR_VAL1_Pos)))
+#define SPI_CMPR_VAL2_Pos 16
+#define SPI_CMPR_VAL2_Msk (0xffffu << SPI_CMPR_VAL2_Pos) /**< \brief (SPI_CMPR) Second Comparison Value for Received Character */
+#define SPI_CMPR_VAL2(value) ((SPI_CMPR_VAL2_Msk & ((value) << SPI_CMPR_VAL2_Pos)))
+/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Mode Register -------- */
+#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */
+#define SPI_WPMR_WPKEY_Pos 8
+#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key */
+#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))
+#define   SPI_WPMR_WPKEY_PASSWD (0x535049u << 8) /**< \brief (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
+#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */
+#define SPI_WPSR_WPVSRC_Pos 8
+#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_SPI_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_ssc.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_ssc.h
new file mode 100644
index 000000000..0dcafb947
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_ssc.h
@@ -0,0 +1,287 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_SSC_COMPONENT_
+#define _SAMA5D2_SSC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_SSC Synchronous Serial Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Ssc hardware registers */
+typedef struct {
+  __O  uint32_t SSC_CR;        /**< \brief (Ssc Offset: 0x0) Control Register */
+  __IO uint32_t SSC_CMR;       /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
+  __I  uint32_t Reserved1[2];
+  __IO uint32_t SSC_RCMR;      /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
+  __IO uint32_t SSC_RFMR;      /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
+  __IO uint32_t SSC_TCMR;      /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
+  __IO uint32_t SSC_TFMR;      /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
+  __I  uint32_t SSC_RHR;       /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
+  __O  uint32_t SSC_THR;       /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
+  __I  uint32_t Reserved2[2];
+  __I  uint32_t SSC_RSHR;      /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
+  __IO uint32_t SSC_TSHR;      /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
+  __IO uint32_t SSC_RC0R;      /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
+  __IO uint32_t SSC_RC1R;      /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
+  __I  uint32_t SSC_SR;        /**< \brief (Ssc Offset: 0x40) Status Register */
+  __O  uint32_t SSC_IER;       /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
+  __O  uint32_t SSC_IDR;       /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
+  __I  uint32_t SSC_IMR;       /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
+  __I  uint32_t Reserved3[37];
+  __IO uint32_t SSC_WPMR;      /**< \brief (Ssc Offset: 0xE4) Write Protection Mode Register */
+  __I  uint32_t SSC_WPSR;      /**< \brief (Ssc Offset: 0xE8) Write Protection Status Register */
+  __I  uint32_t Reserved4[4];
+  __I  uint32_t SSC_VERSION;   /**< \brief (Ssc Offset: 0xFC) Version Register */
+} Ssc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
+#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */
+#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */
+#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */
+#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */
+#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */
+/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
+#define SSC_CMR_DIV_Pos 0
+#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */
+#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
+/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
+#define SSC_RCMR_CKS_Pos 0
+#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */
+#define SSC_RCMR_CKS(value) ((SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos)))
+#define   SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */
+#define   SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */
+#define   SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */
+#define SSC_RCMR_CKO_Pos 2
+#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
+#define SSC_RCMR_CKO(value) ((SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos)))
+#define   SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None, RK pin is an input */
+#define   SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock, RK pin is an output */
+#define   SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */
+#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
+#define SSC_RCMR_CKG_Pos 6
+#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
+#define SSC_RCMR_CKG(value) ((SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos)))
+#define   SSC_RCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_RCMR) None */
+#define   SSC_RCMR_CKG_EN_RF_LOW (0x1u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */
+#define   SSC_RCMR_CKG_EN_RF_HIGH (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */
+#define SSC_RCMR_START_Pos 8
+#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */
+#define SSC_RCMR_START(value) ((SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos)))
+#define   SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
+#define   SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */
+#define   SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */
+#define   SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */
+#define   SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */
+#define   SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */
+#define   SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */
+#define   SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */
+#define   SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */
+#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
+#define SSC_RCMR_STTDLY_Pos 16
+#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */
+#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
+#define SSC_RCMR_PERIOD_Pos 24
+#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
+#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
+/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
+#define SSC_RFMR_DATLEN_Pos 0
+#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */
+#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
+#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */
+#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
+#define SSC_RFMR_DATNB_Pos 8
+#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */
+#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
+#define SSC_RFMR_FSLEN_Pos 16
+#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
+#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
+#define SSC_RFMR_FSOS_Pos 20
+#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
+#define SSC_RFMR_FSOS(value) ((SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos)))
+#define   SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None, RF pin is an input */
+#define   SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse, RF pin is an output */
+#define   SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse, RF pin is an output */
+#define   SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer, RF pin is an output */
+#define   SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer, RF pin is an output */
+#define   SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */
+#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
+#define   SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */
+#define   SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */
+#define SSC_RFMR_FSLEN_EXT_Pos 28
+#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */
+#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
+#define SSC_TCMR_CKS_Pos 0
+#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */
+#define SSC_TCMR_CKS(value) ((SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos)))
+#define   SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */
+#define   SSC_TCMR_CKS_RK (0x1u << 0) /**< \brief (SSC_TCMR) RK Clock signal */
+#define   SSC_TCMR_CKS_TK (0x2u << 0) /**< \brief (SSC_TCMR) TK pin */
+#define SSC_TCMR_CKO_Pos 2
+#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
+#define SSC_TCMR_CKO(value) ((SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos)))
+#define   SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None, TK pin is an input */
+#define   SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */
+#define   SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */
+#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
+#define SSC_TCMR_CKG_Pos 6
+#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
+#define SSC_TCMR_CKG(value) ((SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos)))
+#define   SSC_TCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_TCMR) None */
+#define   SSC_TCMR_CKG_EN_TF_LOW (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */
+#define   SSC_TCMR_CKG_EN_TF_HIGH (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */
+#define SSC_TCMR_START_Pos 8
+#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */
+#define SSC_TCMR_START(value) ((SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos)))
+#define   SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data */
+#define   SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */
+#define   SSC_TCMR_START_TF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */
+#define   SSC_TCMR_START_TF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */
+#define   SSC_TCMR_START_TF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */
+#define   SSC_TCMR_START_TF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */
+#define   SSC_TCMR_START_TF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */
+#define   SSC_TCMR_START_TF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */
+#define SSC_TCMR_STTDLY_Pos 16
+#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */
+#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
+#define SSC_TCMR_PERIOD_Pos 24
+#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
+#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
+/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
+#define SSC_TFMR_DATLEN_Pos 0
+#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */
+#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
+#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */
+#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
+#define SSC_TFMR_DATNB_Pos 8
+#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per Frame */
+#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
+#define SSC_TFMR_FSLEN_Pos 16
+#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */
+#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
+#define SSC_TFMR_FSOS_Pos 20
+#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
+#define SSC_TFMR_FSOS(value) ((SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos)))
+#define   SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None, TF pin is an input */
+#define   SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse, TF pin is an output */
+#define   SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse, TF pin is an output */
+#define   SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */
+#define   SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */
+#define   SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */
+#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
+#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
+#define   SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */
+#define   SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */
+#define SSC_TFMR_FSLEN_EXT_Pos 28
+#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */
+#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
+#define SSC_RHR_RDAT_Pos 0
+#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */
+/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
+#define SSC_THR_TDAT_Pos 0
+#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */
+#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
+/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
+#define SSC_RSHR_RSDAT_Pos 0
+#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */
+/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
+#define SSC_TSHR_TSDAT_Pos 0
+#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
+#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
+/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
+#define SSC_RC0R_CP0_Pos 0
+#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
+#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
+/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
+#define SSC_RC1R_CP1_Pos 0
+#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
+#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
+/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
+#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */
+#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */
+#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */
+#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */
+#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */
+#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */
+#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */
+#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */
+#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */
+#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */
+/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
+#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
+#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
+#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
+#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
+#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
+#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
+#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
+#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
+/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
+#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
+#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
+#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
+#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
+#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
+#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
+#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
+#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
+/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
+#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
+#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
+#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
+#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
+#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
+#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
+#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
+#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
+/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protection Mode Register -------- */
+#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protection Enable */
+#define SSC_WPMR_WPKEY_Pos 8
+#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protection Key */
+#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))
+#define   SSC_WPMR_WPKEY_PASSWD (0x535343u << 8) /**< \brief (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
+/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protection Status Register -------- */
+#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protection Violation Status */
+#define SSC_WPSR_WPVSRC_Pos 8
+#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */
+/* -------- SSC_VERSION : (SSC Offset: 0xFC) Version Register -------- */
+#define SSC_VERSION_VERSION_Pos 0
+#define SSC_VERSION_VERSION_Msk (0xffffu << SSC_VERSION_VERSION_Pos) /**< \brief (SSC_VERSION) Version of the Hardware Module */
+#define SSC_VERSION_MFN_Pos 16
+#define SSC_VERSION_MFN_Msk (0x7u << SSC_VERSION_MFN_Pos) /**< \brief (SSC_VERSION) Metal Fix Number */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_SSC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_tc.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_tc.h
new file mode 100644
index 000000000..7e6ba4207
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_tc.h
@@ -0,0 +1,360 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_TC_COMPONENT_
+#define _SAMA5D2_TC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Timer Counter */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_TC Timer Counter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief TcChannel hardware registers */
+typedef struct {
+  __O  uint32_t TC_CCR;       /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
+  __IO uint32_t TC_CMR;       /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
+  __IO uint32_t TC_SMMR;      /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */
+  __I  uint32_t TC_RAB;       /**< \brief (TcChannel Offset: 0xC) Register AB */
+  __I  uint32_t TC_CV;        /**< \brief (TcChannel Offset: 0x10) Counter Value */
+  __IO uint32_t TC_RA;        /**< \brief (TcChannel Offset: 0x14) Register A */
+  __IO uint32_t TC_RB;        /**< \brief (TcChannel Offset: 0x18) Register B */
+  __IO uint32_t TC_RC;        /**< \brief (TcChannel Offset: 0x1C) Register C */
+  __I  uint32_t TC_SR;        /**< \brief (TcChannel Offset: 0x20) Status Register */
+  __O  uint32_t TC_IER;       /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
+  __O  uint32_t TC_IDR;       /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
+  __I  uint32_t TC_IMR;       /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
+  __IO uint32_t TC_EMR;       /**< \brief (TcChannel Offset: 0x30) Extended Mode Register */
+  __I  uint32_t Reserved1[3];
+} TcChannel;
+/** \brief Tc hardware registers */
+#define TCCHANNEL_NUMBER 3
+typedef struct {
+       TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
+  __O  uint32_t  TC_BCR;                       /**< \brief (Tc Offset: 0xC0) Block Control Register */
+  __IO uint32_t  TC_BMR;                       /**< \brief (Tc Offset: 0xC4) Block Mode Register */
+  __O  uint32_t  TC_QIER;                      /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
+  __O  uint32_t  TC_QIDR;                      /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
+  __I  uint32_t  TC_QIMR;                      /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
+  __I  uint32_t  TC_QISR;                      /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
+  __IO uint32_t  TC_FMR;                       /**< \brief (Tc Offset: 0xD8) Fault Mode Register */
+  __I  uint32_t  Reserved1[2];
+  __IO uint32_t  TC_WPMR;                      /**< \brief (Tc Offset: 0xE4) Write Protection Mode Register */
+  __I  uint32_t  Reserved2[5];
+  __I  uint32_t  TC_VER;                       /**< \brief (Tc Offset: 0xFC) Version Register */
+} Tc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
+#define TC_CMR_TCCLKS_Pos 0
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
+#define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos)))
+#define   TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: internal GCLK [TC_ID] clock signal (from PMC) */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: internal div8 clock signal (from PMC) */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: internal div32 clock signal (from PMC) */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: internal div128 clock signal (from PMC) */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: internal slow_clock clock signal (from PMC) */
+#define   TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
+#define   TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
+#define   TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
+#define TC_CMR_BURST_Pos 4
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
+#define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos)))
+#define   TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
+#define TC_CMR_ETRGEDG_Pos 8
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
+#define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos)))
+#define   TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
+#define TC_CMR_LDRA_Pos 16
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
+#define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos)))
+#define   TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_LDRB_Pos 18
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
+#define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos)))
+#define   TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_SBSMPLR_Pos 20
+#define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos) /**< \brief (TC_CMR) Loading Edge Subsampling Ratio */
+#define TC_CMR_SBSMPLR(value) ((TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos)))
+#define   TC_CMR_SBSMPLR_ONE (0x0u << 20) /**< \brief (TC_CMR) Load a Capture Register each selected edge */
+#define   TC_CMR_SBSMPLR_HALF (0x1u << 20) /**< \brief (TC_CMR) Load a Capture Register every 2 selected edges */
+#define   TC_CMR_SBSMPLR_FOURTH (0x2u << 20) /**< \brief (TC_CMR) Load a Capture Register every 4 selected edges */
+#define   TC_CMR_SBSMPLR_EIGHTH (0x3u << 20) /**< \brief (TC_CMR) Load a Capture Register every 8 selected edges */
+#define   TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20) /**< \brief (TC_CMR) Load a Capture Register every 16 selected edges */
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
+#define TC_CMR_EEVTEDG_Pos 8
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
+#define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos)))
+#define   TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
+#define   TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_EEVT_Pos 10
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
+#define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos)))
+#define   TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
+#define   TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
+#define   TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
+#define   TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
+#define TC_CMR_WAVSEL_Pos 13
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
+#define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos)))
+#define   TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
+#define TC_CMR_ACPA_Pos 16
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
+#define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos)))
+#define   TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ACPC_Pos 18
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
+#define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos)))
+#define   TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_AEEVT_Pos 20
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
+#define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos)))
+#define   TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
+#define   TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ASWTRG_Pos 22
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
+#define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos)))
+#define   TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPB_Pos 24
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
+#define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos)))
+#define   TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPC_Pos 26
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
+#define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos)))
+#define   TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BEEVT_Pos 28
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
+#define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos)))
+#define   TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BSWTRG_Pos 30
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
+#define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos)))
+#define   TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
+/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */
+#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */
+#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) Down Count */
+/* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */
+#define TC_RAB_RAB_Pos 0
+#define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
+#define TC_CV_CV_Pos 0
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
+#define TC_RA_RA_Pos 0
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
+#define TC_RB_RB_Pos 0
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
+#define TC_RC_RC_Pos 0
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status (cleared on read) */
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status (cleared on read) */
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status (cleared on read) */
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status (cleared on read) */
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status (cleared on read) */
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status (cleared on read) */
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status (cleared on read) */
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status (cleared on read) */
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
+/* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */
+#define TC_EMR_TRIGSRCA_Pos 0
+#define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos) /**< \brief (TC_EMR) Trigger Source for Input A */
+#define TC_EMR_TRIGSRCA(value) ((TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos)))
+#define   TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */
+#define   TC_EMR_TRIGSRCA_PWMx (0x1u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven internally by PWMx */
+#define TC_EMR_TRIGSRCB_Pos 4
+#define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos) /**< \brief (TC_EMR) Trigger Source for Input B */
+#define TC_EMR_TRIGSRCB(value) ((TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos)))
+#define   TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */
+#define   TC_EMR_TRIGSRCB_PWMx (0x1u << 4) /**< \brief (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). */
+#define TC_EMR_NODIVCLK (0x1u << 8) /**< \brief (TC_EMR) No Divided Clock */
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
+#define TC_BMR_TC0XC0S_Pos 0
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
+#define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos)))
+#define   TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
+#define   TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
+#define   TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
+#define TC_BMR_TC1XC1S_Pos 2
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
+#define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos)))
+#define   TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
+#define   TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
+#define   TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
+#define TC_BMR_TC2XC2S_Pos 4
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
+#define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos)))
+#define   TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
+#define   TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA0 */
+#define   TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
+#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder Enabled */
+#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) Position Enabled */
+#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) Speed Enabled */
+#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding Transparent */
+#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) Edge on PHA Count Mode */
+#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) Inverted PHA */
+#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) Inverted PHB */
+#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) Inverted Index */
+#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) Swap PHA and PHB */
+#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) Index Pin is PHB Pin */
+#define TC_BMR_AUTOC (0x1u << 18) /**< \brief (TC_BMR) Auto-Correction of missing pulses */
+#define   TC_BMR_AUTOC_DISABLED (0x0u << 18) /**< \brief (TC_BMR) The detection and auto-correction function is disabled. */
+#define   TC_BMR_AUTOC_ENABLED (0x1u << 18) /**< \brief (TC_BMR) The detection and auto-correction function is enabled. */
+#define TC_BMR_MAXFILT_Pos 20
+#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) Maximum Filter */
+#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
+#define TC_BMR_MAXCMP_Pos 26
+#define TC_BMR_MAXCMP_Msk (0xfu << TC_BMR_MAXCMP_Pos) /**< \brief (TC_BMR) Maximum Consecutive Missing Pulses */
+#define TC_BMR_MAXCMP(value) ((TC_BMR_MAXCMP_Msk & ((value) << TC_BMR_MAXCMP_Pos)))
+/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
+#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) Index */
+#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) Direction Change */
+#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature Error */
+/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
+#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) Index */
+#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) Direction Change */
+#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature Error */
+/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
+#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) Index */
+#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) Direction Change */
+#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature Error */
+/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
+#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) Index */
+#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) Direction Change */
+#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature Error */
+#define TC_QISR_MPE (0x1u << 3) /**< \brief (TC_QISR) Consecutive Missing Pulse Error */
+#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */
+/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */
+#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) Enable Compare Fault Channel 0 */
+#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) Enable Compare Fault Channel 1 */
+/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */
+#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protection Enable */
+#define TC_WPMR_WPKEY_Pos 8
+#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protection Key */
+#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))
+#define   TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
+/* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */
+#define TC_VER_VERSION_Pos 0
+#define TC_VER_VERSION_Msk (0xfffu << TC_VER_VERSION_Pos) /**< \brief (TC_VER) Version of the Hardware Module */
+#define TC_VER_MFN_Pos 16
+#define TC_VER_MFN_Msk (0x7u << TC_VER_MFN_Pos) /**< \brief (TC_VER) Metal Fix Number */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_TC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_tdes.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_tdes.h
new file mode 100644
index 000000000..5f93c1753
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_tdes.h
@@ -0,0 +1,175 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_TDES_COMPONENT_
+#define _SAMA5D2_TDES_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_TDES Triple Data Encryption Standard */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Tdes hardware registers */
+typedef struct {
+  __O  uint32_t TDES_CR;        /**< \brief (Tdes Offset: 0x00) Control Register */
+  __IO uint32_t TDES_MR;        /**< \brief (Tdes Offset: 0x04) Mode Register */
+  __I  uint32_t Reserved1[2];
+  __O  uint32_t TDES_IER;       /**< \brief (Tdes Offset: 0x10) Interrupt Enable Register */
+  __O  uint32_t TDES_IDR;       /**< \brief (Tdes Offset: 0x14) Interrupt Disable Register */
+  __I  uint32_t TDES_IMR;       /**< \brief (Tdes Offset: 0x18) Interrupt Mask Register */
+  __I  uint32_t TDES_ISR;       /**< \brief (Tdes Offset: 0x1C) Interrupt Status Register */
+  __O  uint32_t TDES_KEY1WR[2]; /**< \brief (Tdes Offset: 0x20) Key 1 Word Register */
+  __O  uint32_t TDES_KEY2WR[2]; /**< \brief (Tdes Offset: 0x28) Key 2 Word Register */
+  __O  uint32_t TDES_KEY3WR[2]; /**< \brief (Tdes Offset: 0x30) Key 3 Word Register */
+  __I  uint32_t Reserved2[2];
+  __O  uint32_t TDES_IDATAR[2]; /**< \brief (Tdes Offset: 0x40) Input Data Register */
+  __I  uint32_t Reserved3[2];
+  __I  uint32_t TDES_ODATAR[2]; /**< \brief (Tdes Offset: 0x50) Output Data Register */
+  __I  uint32_t Reserved4[2];
+  __O  uint32_t TDES_IVR[2];    /**< \brief (Tdes Offset: 0x60) Initialization Vector Register */
+  __I  uint32_t Reserved5[2];
+  __IO uint32_t TDES_XTEA_RNDR; /**< \brief (Tdes Offset: 0x70) XTEA Rounds Register */
+  __I  uint32_t Reserved6[34];
+  __I  uint32_t TDES_VERSION;   /**< \brief (Tdes Offset: 0xFC) Version Register */
+} Tdes;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TDES_CR : (TDES Offset: 0x00) Control Register -------- */
+#define TDES_CR_START (0x1u << 0) /**< \brief (TDES_CR) Start Processing */
+#define TDES_CR_SWRST (0x1u << 8) /**< \brief (TDES_CR) Software Reset */
+#define TDES_CR_LOADSEED (0x1u << 16) /**< \brief (TDES_CR) Load Seed */
+/* -------- TDES_MR : (TDES Offset: 0x04) Mode Register -------- */
+#define TDES_MR_CIPHER (0x1u << 0) /**< \brief (TDES_MR) Processing Mode */
+#define   TDES_MR_CIPHER_DECRYPT (0x0u << 0) /**< \brief (TDES_MR) Decrypts data. */
+#define   TDES_MR_CIPHER_ENCRYPT (0x1u << 0) /**< \brief (TDES_MR) Encrypts data. */
+#define TDES_MR_TDESMOD_Pos 1
+#define TDES_MR_TDESMOD_Msk (0x3u << TDES_MR_TDESMOD_Pos) /**< \brief (TDES_MR) ALGORITHM Mode */
+#define TDES_MR_TDESMOD(value) ((TDES_MR_TDESMOD_Msk & ((value) << TDES_MR_TDESMOD_Pos)))
+#define   TDES_MR_TDESMOD_SINGLE_DES (0x0u << 1) /**< \brief (TDES_MR) Single DES processing using TDES_KEY1WRx registers */
+#define   TDES_MR_TDESMOD_TRIPLE_DES (0x1u << 1) /**< \brief (TDES_MR) Triple DES processing using TDES_KEY1WRx, TDES_KEY2WRx and TDES_KEY3WRx registers */
+#define   TDES_MR_TDESMOD_XTEA (0x2u << 1) /**< \brief (TDES_MR) XTEA processing using TDES_KEY1WRx, TDES_KEY2WRx */
+#define TDES_MR_KEYMOD (0x1u << 4) /**< \brief (TDES_MR) Key Mode */
+#define TDES_MR_SMOD_Pos 8
+#define TDES_MR_SMOD_Msk (0x3u << TDES_MR_SMOD_Pos) /**< \brief (TDES_MR) Start Mode */
+#define TDES_MR_SMOD(value) ((TDES_MR_SMOD_Msk & ((value) << TDES_MR_SMOD_Pos)))
+#define   TDES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (TDES_MR) Manual Mode */
+#define   TDES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (TDES_MR) Auto Mode */
+#define   TDES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (TDES_MR) TDES_IDATAR0 access only Auto Mode */
+#define TDES_MR_OPMOD_Pos 12
+#define TDES_MR_OPMOD_Msk (0x3u << TDES_MR_OPMOD_Pos) /**< \brief (TDES_MR) Operation Mode */
+#define TDES_MR_OPMOD(value) ((TDES_MR_OPMOD_Msk & ((value) << TDES_MR_OPMOD_Pos)))
+#define   TDES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (TDES_MR) Electronic Code Book mode */
+#define   TDES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (TDES_MR) Cipher Block Chaining mode */
+#define   TDES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (TDES_MR) Output Feedback mode */
+#define   TDES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (TDES_MR) Cipher Feedback mode */
+#define TDES_MR_LOD (0x1u << 15) /**< \brief (TDES_MR) Last Output Data Mode */
+#define TDES_MR_CFBS_Pos 16
+#define TDES_MR_CFBS_Msk (0x3u << TDES_MR_CFBS_Pos) /**< \brief (TDES_MR) Cipher Feedback Data Size */
+#define TDES_MR_CFBS(value) ((TDES_MR_CFBS_Msk & ((value) << TDES_MR_CFBS_Pos)))
+#define   TDES_MR_CFBS_SIZE_64BIT (0x0u << 16) /**< \brief (TDES_MR) 64-bit */
+#define   TDES_MR_CFBS_SIZE_32BIT (0x1u << 16) /**< \brief (TDES_MR) 32-bit */
+#define   TDES_MR_CFBS_SIZE_16BIT (0x2u << 16) /**< \brief (TDES_MR) 16-bit */
+#define   TDES_MR_CFBS_SIZE_8BIT (0x3u << 16) /**< \brief (TDES_MR) 8-bit */
+#define TDES_MR_CKEY_Pos 20
+#define TDES_MR_CKEY_Msk (0xfu << TDES_MR_CKEY_Pos) /**< \brief (TDES_MR) Countermeasure Key */
+#define TDES_MR_CKEY(value) ((TDES_MR_CKEY_Msk & ((value) << TDES_MR_CKEY_Pos)))
+#define TDES_MR_CMTYP1 (0x1u << 24) /**< \brief (TDES_MR) Countermeasure Type 1 */
+#define   TDES_MR_CMTYP1_NO_PAUSE (0x0u << 24) /**< \brief (TDES_MR) Countermeasure type 1 is disabled */
+#define   TDES_MR_CMTYP1_PAUSE (0x1u << 24) /**< \brief (TDES_MR) Countermeasure type 1 is enabled */
+#define TDES_MR_CMTYP2 (0x1u << 25) /**< \brief (TDES_MR) Countermeasure Type 2 */
+#define   TDES_MR_CMTYP2_NO_DUMMY (0x0u << 25) /**< \brief (TDES_MR) Countermeasure type 2 is disabled */
+#define   TDES_MR_CMTYP2_DUMMY (0x1u << 25) /**< \brief (TDES_MR) Countermeasure type 2 is enabled */
+#define TDES_MR_CMTYP3 (0x1u << 26) /**< \brief (TDES_MR) Countermeasure Type 3 */
+#define   TDES_MR_CMTYP3_NO_RESTART (0x0u << 26) /**< \brief (TDES_MR) Countermeasure type 3 is disabled */
+#define   TDES_MR_CMTYP3_RESTART (0x1u << 26) /**< \brief (TDES_MR) Countermeasure type 3 is enabled */
+#define TDES_MR_CMTYP4 (0x1u << 27) /**< \brief (TDES_MR) Countermeasure Type 4 */
+#define   TDES_MR_CMTYP4_NO_IDLECURRENT (0x0u << 27) /**< \brief (TDES_MR) Countermeasure type 4 is disabled */
+#define   TDES_MR_CMTYP4_IDLECURRENT (0x1u << 27) /**< \brief (TDES_MR) Countermeasure type 4 is enabled */
+#define TDES_MR_CMTYP5 (0x1u << 28) /**< \brief (TDES_MR) Countermeasure Type 5 */
+#define   TDES_MR_CMTYP5_NO_ADDACCESS (0x0u << 28) /**< \brief (TDES_MR) Countermeasure type 5 is disabled */
+#define   TDES_MR_CMTYP5_ADDACCESS (0x1u << 28) /**< \brief (TDES_MR) Countermeasure type 5 is enabled */
+#define TDES_MR_CMTYP6 (0x1u << 29) /**< \brief (TDES_MR) Countermeasure Type 6 */
+#define   TDES_MR_CMTYP6_NO_UNIFORM (0x0u << 29) /**< \brief (TDES_MR) Countermeasure type 6 is disabled */
+#define   TDES_MR_CMTYP6_UNIFORM (0x1u << 29) /**< \brief (TDES_MR) Countermeasure type 6 is enabled */
+/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */
+#define TDES_IER_DATRDY (0x1u << 0) /**< \brief (TDES_IER) Data Ready Interrupt Enable */
+#define TDES_IER_URAD (0x1u << 8) /**< \brief (TDES_IER) Unspecified Register Access Detection Interrupt Enable */
+/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */
+#define TDES_IDR_DATRDY (0x1u << 0) /**< \brief (TDES_IDR) Data Ready Interrupt Disable */
+#define TDES_IDR_URAD (0x1u << 8) /**< \brief (TDES_IDR) Unspecified Register Access Detection Interrupt Disable */
+/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */
+#define TDES_IMR_DATRDY (0x1u << 0) /**< \brief (TDES_IMR) Data Ready Interrupt Mask */
+#define TDES_IMR_URAD (0x1u << 8) /**< \brief (TDES_IMR) Unspecified Register Access Detection Interrupt Mask */
+/* -------- TDES_ISR : (TDES Offset: 0x1C) Interrupt Status Register -------- */
+#define TDES_ISR_DATRDY (0x1u << 0) /**< \brief (TDES_ISR) Data Ready (cleared by setting bit START or bit SWRST in TDES_CR or by reading TDES_ODATARx) */
+#define TDES_ISR_URAD (0x1u << 8) /**< \brief (TDES_ISR) Unspecified Register Access Detection Status (cleared by setting bit TDES_CR.SWRST) */
+#define TDES_ISR_URAT_Pos 12
+#define TDES_ISR_URAT_Msk (0x3u << TDES_ISR_URAT_Pos) /**< \brief (TDES_ISR) Unspecified Register Access (cleared by setting bit TDES_CR.SWRST) */
+#define   TDES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (TDES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */
+#define   TDES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (TDES_ISR) Output Data Register read during the data processing. */
+#define   TDES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (TDES_ISR) Mode Register written during the data processing. */
+#define   TDES_ISR_URAT_WOR_RD_ACCESS (0x3u << 12) /**< \brief (TDES_ISR) Write-only register read access. */
+/* -------- TDES_KEY1WR[2] : (TDES Offset: 0x20) Key 1 Word Register -------- */
+#define TDES_KEY1WR_KEY1W_Pos 0
+#define TDES_KEY1WR_KEY1W_Msk (0xffffffffu << TDES_KEY1WR_KEY1W_Pos) /**< \brief (TDES_KEY1WR[2]) Key 1 Word */
+#define TDES_KEY1WR_KEY1W(value) ((TDES_KEY1WR_KEY1W_Msk & ((value) << TDES_KEY1WR_KEY1W_Pos)))
+/* -------- TDES_KEY2WR[2] : (TDES Offset: 0x28) Key 2 Word Register -------- */
+#define TDES_KEY2WR_KEY2W_Pos 0
+#define TDES_KEY2WR_KEY2W_Msk (0xffffffffu << TDES_KEY2WR_KEY2W_Pos) /**< \brief (TDES_KEY2WR[2]) Key 2 Word */
+#define TDES_KEY2WR_KEY2W(value) ((TDES_KEY2WR_KEY2W_Msk & ((value) << TDES_KEY2WR_KEY2W_Pos)))
+/* -------- TDES_KEY3WR[2] : (TDES Offset: 0x30) Key 3 Word Register -------- */
+#define TDES_KEY3WR_KEY3W_Pos 0
+#define TDES_KEY3WR_KEY3W_Msk (0xffffffffu << TDES_KEY3WR_KEY3W_Pos) /**< \brief (TDES_KEY3WR[2]) Key 3 Word */
+#define TDES_KEY3WR_KEY3W(value) ((TDES_KEY3WR_KEY3W_Msk & ((value) << TDES_KEY3WR_KEY3W_Pos)))
+/* -------- TDES_IDATAR[2] : (TDES Offset: 0x40) Input Data Register -------- */
+#define TDES_IDATAR_IDATA_Pos 0
+#define TDES_IDATAR_IDATA_Msk (0xffffffffu << TDES_IDATAR_IDATA_Pos) /**< \brief (TDES_IDATAR[2]) Input Data */
+#define TDES_IDATAR_IDATA(value) ((TDES_IDATAR_IDATA_Msk & ((value) << TDES_IDATAR_IDATA_Pos)))
+/* -------- TDES_ODATAR[2] : (TDES Offset: 0x50) Output Data Register -------- */
+#define TDES_ODATAR_ODATA_Pos 0
+#define TDES_ODATAR_ODATA_Msk (0xffffffffu << TDES_ODATAR_ODATA_Pos) /**< \brief (TDES_ODATAR[2]) Output Data */
+/* -------- TDES_IVR[2] : (TDES Offset: 0x60) Initialization Vector Register -------- */
+#define TDES_IVR_IV_Pos 0
+#define TDES_IVR_IV_Msk (0xffffffffu << TDES_IVR_IV_Pos) /**< \brief (TDES_IVR[2]) Initialization Vector */
+#define TDES_IVR_IV(value) ((TDES_IVR_IV_Msk & ((value) << TDES_IVR_IV_Pos)))
+/* -------- TDES_XTEA_RNDR : (TDES Offset: 0x70) XTEA Rounds Register -------- */
+#define TDES_XTEA_RNDR_XTEA_RNDS_Pos 0
+#define TDES_XTEA_RNDR_XTEA_RNDS_Msk (0x3fu << TDES_XTEA_RNDR_XTEA_RNDS_Pos) /**< \brief (TDES_XTEA_RNDR) Number of Rounds */
+#define TDES_XTEA_RNDR_XTEA_RNDS(value) ((TDES_XTEA_RNDR_XTEA_RNDS_Msk & ((value) << TDES_XTEA_RNDR_XTEA_RNDS_Pos)))
+/* -------- TDES_VERSION : (TDES Offset: 0xFC) Version Register -------- */
+#define TDES_VERSION_VERSION_Pos 0
+#define TDES_VERSION_VERSION_Msk (0xfffu << TDES_VERSION_VERSION_Pos) /**< \brief (TDES_VERSION) Version of the Hardware Module */
+#define TDES_VERSION_MFN_Pos 16
+#define TDES_VERSION_MFN_Msk (0x7u << TDES_VERSION_MFN_Pos) /**< \brief (TDES_VERSION) Metal Fix Number */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_TDES_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_trng.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_trng.h
new file mode 100644
index 000000000..527a91c67
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_trng.h
@@ -0,0 +1,80 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_TRNG_COMPONENT_
+#define _SAMA5D2_TRNG_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR True Random Number Generator */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_TRNG True Random Number Generator */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Trng hardware registers */
+typedef struct {
+  __O uint32_t TRNG_CR;       /**< \brief (Trng Offset: 0x00) Control Register */
+  __I uint32_t Reserved1[3];
+  __O uint32_t TRNG_IER;      /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */
+  __O uint32_t TRNG_IDR;      /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */
+  __I uint32_t TRNG_IMR;      /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */
+  __I uint32_t TRNG_ISR;      /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */
+  __I uint32_t Reserved2[12];
+  __I uint32_t TRNG_ODATA;    /**< \brief (Trng Offset: 0x50) Output Data Register */
+  __I uint32_t Reserved3[42];
+  __I uint32_t TRNG_VERSION;  /**< \brief (Trng Offset: 0xFC) Version Register */
+} Trng;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */
+#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to Provide Random Values */
+#define TRNG_CR_KEY_Pos 8
+#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key */
+#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos)))
+#define   TRNG_CR_KEY_PASSWD (0x524E47u << 8) /**< \brief (TRNG_CR) Writing any other value in this field aborts the write operation. */
+/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */
+#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */
+/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */
+#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */
+/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */
+#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */
+/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */
+#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */
+/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */
+#define TRNG_ODATA_ODATA_Pos 0
+#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */
+/* -------- TRNG_VERSION : (TRNG Offset: 0xFC) Version Register -------- */
+#define TRNG_VERSION_VERSION_Pos 0
+#define TRNG_VERSION_VERSION_Msk (0xfffu << TRNG_VERSION_VERSION_Pos) /**< \brief (TRNG_VERSION) Version of the Hardware Module */
+#define TRNG_VERSION_MFN_Pos 16
+#define TRNG_VERSION_MFN_Msk (0x7u << TRNG_VERSION_MFN_Pos) /**< \brief (TRNG_VERSION) Metal Fix Number */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_TRNG_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_twi.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_twi.h
new file mode 100644
index 000000000..bf5e9117c
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_twi.h
@@ -0,0 +1,379 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_TWI_COMPONENT_
+#define _SAMA5D2_TWI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Two-wire Interface High Speed */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_TWI Two-wire Interface High Speed */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Twi hardware registers */
+typedef struct {
+  __O  uint32_t TWI_CR;      /**< \brief (Twi Offset: 0x00) Control Register */
+  __IO uint32_t TWI_MMR;     /**< \brief (Twi Offset: 0x04) Master Mode Register */
+  __IO uint32_t TWI_SMR;     /**< \brief (Twi Offset: 0x08) Slave Mode Register */
+  __IO uint32_t TWI_IADR;    /**< \brief (Twi Offset: 0x0C) Internal Address Register */
+  __IO uint32_t TWI_CWGR;    /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
+  __I  uint32_t Reserved1[3];
+  __I  uint32_t TWI_SR;      /**< \brief (Twi Offset: 0x20) Status Register */
+  __O  uint32_t TWI_IER;     /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
+  __O  uint32_t TWI_IDR;     /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
+  __I  uint32_t TWI_IMR;     /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
+  __I  uint32_t TWI_RHR;     /**< \brief (Twi Offset: 0x30) Receive Holding Register */
+  __O  uint32_t TWI_THR;     /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
+  __IO uint32_t TWI_SMBTR;   /**< \brief (Twi Offset: 0x38) SMBus Timing Register */
+  __I  uint32_t Reserved2[1];
+  __IO uint32_t TWI_ACR;     /**< \brief (Twi Offset: 0x40) Alternative Command Register */
+  __IO uint32_t TWI_FILTR;   /**< \brief (Twi Offset: 0x44) Filter Register */
+  __I  uint32_t Reserved3[1];
+  __IO uint32_t TWI_SWMR;    /**< \brief (Twi Offset: 0x4C) SleepWalking Matching Register */
+  __IO uint32_t TWI_FMR;     /**< \brief (Twi Offset: 0x50) FIFO Mode Register */
+  __I  uint32_t TWI_FLR;     /**< \brief (Twi Offset: 0x54) FIFO Level Register */
+  __I  uint32_t Reserved4[2];
+  __I  uint32_t TWI_FSR;     /**< \brief (Twi Offset: 0x60) FIFO Status Register */
+  __O  uint32_t TWI_FIER;    /**< \brief (Twi Offset: 0x64) FIFO Interrupt Enable Register */
+  __O  uint32_t TWI_FIDR;    /**< \brief (Twi Offset: 0x68) FIFO Interrupt Disable Register */
+  __I  uint32_t TWI_FIMR;    /**< \brief (Twi Offset: 0x6C) FIFO Interrupt Mask Register */
+  __I  uint32_t Reserved5[24];
+  __I  uint32_t TWI_DR;      /**< \brief (Twi Offset: 0xD0) Debug Register */
+  __I  uint32_t Reserved6[4];
+  __IO uint32_t TWI_WPMR;    /**< \brief (Twi Offset: 0xE4) Write Protection Mode Register */
+  __I  uint32_t TWI_WPSR;    /**< \brief (Twi Offset: 0xE8) Write Protection Status Register */
+} Twi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBus Quick Command */
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */
+#define TWI_CR_HSEN (0x1u << 8) /**< \brief (TWI_CR) TWI High-Speed Mode Enabled */
+#define TWI_CR_HSDIS (0x1u << 9) /**< \brief (TWI_CR) TWI High-Speed Mode Disabled */
+#define TWI_CR_SMBEN (0x1u << 10) /**< \brief (TWI_CR) SMBus Mode Enabled */
+#define TWI_CR_SMBDIS (0x1u << 11) /**< \brief (TWI_CR) SMBus Mode Disabled */
+#define TWI_CR_PECEN (0x1u << 12) /**< \brief (TWI_CR) Packet Error Checking Enable */
+#define TWI_CR_PECDIS (0x1u << 13) /**< \brief (TWI_CR) Packet Error Checking Disable */
+#define TWI_CR_PECRQ (0x1u << 14) /**< \brief (TWI_CR) PEC Request */
+#define TWI_CR_CLEAR (0x1u << 15) /**< \brief (TWI_CR) Bus CLEAR Command */
+#define TWI_CR_ACMEN (0x1u << 16) /**< \brief (TWI_CR) Alternative Command Mode Enable */
+#define TWI_CR_ACMDIS (0x1u << 17) /**< \brief (TWI_CR) Alternative Command Mode Disable */
+#define TWI_CR_THRCLR (0x1u << 24) /**< \brief (TWI_CR) Transmit Holding Register Clear */
+#define TWI_CR_LOCKCLR (0x1u << 26) /**< \brief (TWI_CR) Lock Clear */
+#define TWI_CR_FIFOEN (0x1u << 28) /**< \brief (TWI_CR) FIFO Enable */
+#define TWI_CR_FIFODIS (0x1u << 29) /**< \brief (TWI_CR) FIFO Disable */
+/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
+#define TWI_MMR_IADRSZ_Pos 8
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */
+#define TWI_MMR_IADRSZ(value) ((TWI_MMR_IADRSZ_Msk & ((value) << TWI_MMR_IADRSZ_Pos)))
+#define   TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */
+#define   TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */
+#define   TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
+#define   TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */
+#define TWI_MMR_DADR_Pos 16
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
+/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
+#define TWI_SMR_NACKEN (0x1u << 0) /**< \brief (TWI_SMR) Slave Receiver Data Phase NACK enable */
+#define TWI_SMR_SMDA (0x1u << 2) /**< \brief (TWI_SMR) SMBus Default Address */
+#define TWI_SMR_SMHH (0x1u << 3) /**< \brief (TWI_SMR) SMBus Host Header */
+#define TWI_SMR_SCLWSDIS (0x1u << 6) /**< \brief (TWI_SMR) Clock Wait State Disable */
+#define TWI_SMR_MASK_Pos 8
+#define TWI_SMR_MASK_Msk (0x7fu << TWI_SMR_MASK_Pos) /**< \brief (TWI_SMR) Slave Address Mask */
+#define TWI_SMR_MASK(value) ((TWI_SMR_MASK_Msk & ((value) << TWI_SMR_MASK_Pos)))
+#define TWI_SMR_SADR_Pos 16
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
+#define TWI_SMR_SADR1EN (0x1u << 28) /**< \brief (TWI_SMR) Slave Address 1 Enable */
+#define TWI_SMR_SADR2EN (0x1u << 29) /**< \brief (TWI_SMR) Slave Address 2 Enable */
+#define TWI_SMR_SADR3EN (0x1u << 30) /**< \brief (TWI_SMR) Slave Address 3 Enable */
+#define TWI_SMR_DATAMEN (0x1u << 31) /**< \brief (TWI_SMR) Data Matching Enable */
+/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
+#define TWI_IADR_IADR_Pos 0
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
+/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
+#define TWI_CWGR_CLDIV_Pos 0
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
+#define TWI_CWGR_CHDIV_Pos 8
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
+#define TWI_CWGR_CKDIV_Pos 16
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
+#define TWI_CWGR_CKSRC (0x1u << 20) /**< \brief (TWI_CWGR) Transfer Rate Clock Source */
+#define   TWI_CWGR_CKSRC_PERIPH_CK (0x0u << 20) /**< \brief (TWI_CWGR) Peripheral clock is used to generate the TWI baud rate. */
+#define   TWI_CWGR_CKSRC_PMC_PCK (0x1u << 20) /**< \brief (TWI_CWGR) PMC PCKx is used to generate the TWI baud rate. */
+#define TWI_CWGR_HOLD_Pos 24
+#define TWI_CWGR_HOLD_Msk (0x1fu << TWI_CWGR_HOLD_Pos) /**< \brief (TWI_CWGR) TWD Hold Time Versus TWCK Falling */
+#define TWI_CWGR_HOLD(value) ((TWI_CWGR_HOLD_Msk & ((value) << TWI_CWGR_HOLD_Pos)))
+/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (cleared by writing TWI_THR) */
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (cleared by reading TWI_RHR) */
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (cleared by writing TWI_THR) */
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read */
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access */
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (cleared on read) */
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (cleared on read) */
+#define TWI_SR_UNRE (0x1u << 7) /**< \brief (TWI_SR) Underrun Error (cleared on read) */
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (cleared on read) */
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (cleared on read) */
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State */
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (cleared on read) */
+#define TWI_SR_MCACK (0x1u << 16) /**< \brief (TWI_SR) Master Code Acknowledge (cleared on read) */
+#define TWI_SR_TOUT (0x1u << 18) /**< \brief (TWI_SR) Timeout Error (cleared on read) */
+#define TWI_SR_PECERR (0x1u << 19) /**< \brief (TWI_SR) PEC Error (cleared on read) */
+#define TWI_SR_SMBDAM (0x1u << 20) /**< \brief (TWI_SR) SMBus Default Address Match (cleared on read) */
+#define TWI_SR_SMBHHM (0x1u << 21) /**< \brief (TWI_SR) SMBus Host Header Address Match (cleared on read) */
+#define TWI_SR_LOCK (0x1u << 23) /**< \brief (TWI_SR) TWI Lock due to Frame Errors (cleared by writing a one to bit LOCKCLR in TWI_CR) */
+#define TWI_SR_SCL (0x1u << 24) /**< \brief (TWI_SR) SCL Line Value */
+#define TWI_SR_SDA (0x1u << 25) /**< \brief (TWI_SR) SDA Line Value */
+/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
+#define TWI_IER_UNRE (0x1u << 7) /**< \brief (TWI_IER) Underrun Error Interrupt Enable */
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
+#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */
+#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */
+#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */
+#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */
+#define TWI_IER_MCACK (0x1u << 16) /**< \brief (TWI_IER) Master Code Acknowledge Interrupt Enable */
+#define TWI_IER_TOUT (0x1u << 18) /**< \brief (TWI_IER) Timeout Error Interrupt Enable */
+#define TWI_IER_PECERR (0x1u << 19) /**< \brief (TWI_IER) PEC Error Interrupt Enable */
+#define TWI_IER_SMBDAM (0x1u << 20) /**< \brief (TWI_IER) SMBus Default Address Match Interrupt Enable */
+#define TWI_IER_SMBHHM (0x1u << 21) /**< \brief (TWI_IER) SMBus Host Header Address Match Interrupt Enable */
+/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
+#define TWI_IDR_UNRE (0x1u << 7) /**< \brief (TWI_IDR) Underrun Error Interrupt Disable */
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
+#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */
+#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */
+#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */
+#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */
+#define TWI_IDR_MCACK (0x1u << 16) /**< \brief (TWI_IDR) Master Code Acknowledge Interrupt Disable */
+#define TWI_IDR_TOUT (0x1u << 18) /**< \brief (TWI_IDR) Timeout Error Interrupt Disable */
+#define TWI_IDR_PECERR (0x1u << 19) /**< \brief (TWI_IDR) PEC Error Interrupt Disable */
+#define TWI_IDR_SMBDAM (0x1u << 20) /**< \brief (TWI_IDR) SMBus Default Address Match Interrupt Disable */
+#define TWI_IDR_SMBHHM (0x1u << 21) /**< \brief (TWI_IDR) SMBus Host Header Address Match Interrupt Disable */
+/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
+#define TWI_IMR_UNRE (0x1u << 7) /**< \brief (TWI_IMR) Underrun Error Interrupt Mask */
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
+#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */
+#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */
+#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */
+#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */
+#define TWI_IMR_MCACK (0x1u << 16) /**< \brief (TWI_IMR) Master Code Acknowledge Interrupt Mask */
+#define TWI_IMR_TOUT (0x1u << 18) /**< \brief (TWI_IMR) Timeout Error Interrupt Mask */
+#define TWI_IMR_PECERR (0x1u << 19) /**< \brief (TWI_IMR) PEC Error Interrupt Mask */
+#define TWI_IMR_SMBDAM (0x1u << 20) /**< \brief (TWI_IMR) SMBus Default Address Match Interrupt Mask */
+#define TWI_IMR_SMBHHM (0x1u << 21) /**< \brief (TWI_IMR) SMBus Host Header Address Match Interrupt Mask */
+/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
+#define TWI_RHR_RXDATA_Pos 0
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
+#define TWI_RHR_RXDATA0_Pos 0
+#define TWI_RHR_RXDATA0_Msk (0xffu << TWI_RHR_RXDATA0_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data 0 */
+#define TWI_RHR_RXDATA1_Pos 8
+#define TWI_RHR_RXDATA1_Msk (0xffu << TWI_RHR_RXDATA1_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data 1 */
+#define TWI_RHR_RXDATA2_Pos 16
+#define TWI_RHR_RXDATA2_Msk (0xffu << TWI_RHR_RXDATA2_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data 2 */
+#define TWI_RHR_RXDATA3_Pos 24
+#define TWI_RHR_RXDATA3_Msk (0xffu << TWI_RHR_RXDATA3_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data 3 */
+/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
+#define TWI_THR_TXDATA_Pos 0
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
+#define TWI_THR_TXDATA0_Pos 0
+#define TWI_THR_TXDATA0_Msk (0xffu << TWI_THR_TXDATA0_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data 0 */
+#define TWI_THR_TXDATA0(value) ((TWI_THR_TXDATA0_Msk & ((value) << TWI_THR_TXDATA0_Pos)))
+#define TWI_THR_TXDATA1_Pos 8
+#define TWI_THR_TXDATA1_Msk (0xffu << TWI_THR_TXDATA1_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data 1 */
+#define TWI_THR_TXDATA1(value) ((TWI_THR_TXDATA1_Msk & ((value) << TWI_THR_TXDATA1_Pos)))
+#define TWI_THR_TXDATA2_Pos 16
+#define TWI_THR_TXDATA2_Msk (0xffu << TWI_THR_TXDATA2_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data 2 */
+#define TWI_THR_TXDATA2(value) ((TWI_THR_TXDATA2_Msk & ((value) << TWI_THR_TXDATA2_Pos)))
+#define TWI_THR_TXDATA3_Pos 24
+#define TWI_THR_TXDATA3_Msk (0xffu << TWI_THR_TXDATA3_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data 3 */
+#define TWI_THR_TXDATA3(value) ((TWI_THR_TXDATA3_Msk & ((value) << TWI_THR_TXDATA3_Pos)))
+/* -------- TWI_SMBTR : (TWI Offset: 0x38) SMBus Timing Register -------- */
+#define TWI_SMBTR_PRESC_Pos 0
+#define TWI_SMBTR_PRESC_Msk (0xfu << TWI_SMBTR_PRESC_Pos) /**< \brief (TWI_SMBTR) SMBus Clock Prescaler */
+#define TWI_SMBTR_PRESC(value) ((TWI_SMBTR_PRESC_Msk & ((value) << TWI_SMBTR_PRESC_Pos)))
+#define TWI_SMBTR_TLOWS_Pos 8
+#define TWI_SMBTR_TLOWS_Msk (0xffu << TWI_SMBTR_TLOWS_Pos) /**< \brief (TWI_SMBTR) Slave Clock Stretch Maximum Cycles */
+#define TWI_SMBTR_TLOWS(value) ((TWI_SMBTR_TLOWS_Msk & ((value) << TWI_SMBTR_TLOWS_Pos)))
+#define TWI_SMBTR_TLOWM_Pos 16
+#define TWI_SMBTR_TLOWM_Msk (0xffu << TWI_SMBTR_TLOWM_Pos) /**< \brief (TWI_SMBTR) Master Clock Stretch Maximum Cycles */
+#define TWI_SMBTR_TLOWM(value) ((TWI_SMBTR_TLOWM_Msk & ((value) << TWI_SMBTR_TLOWM_Pos)))
+#define TWI_SMBTR_THMAX_Pos 24
+#define TWI_SMBTR_THMAX_Msk (0xffu << TWI_SMBTR_THMAX_Pos) /**< \brief (TWI_SMBTR) Clock High Maximum Cycles */
+#define TWI_SMBTR_THMAX(value) ((TWI_SMBTR_THMAX_Msk & ((value) << TWI_SMBTR_THMAX_Pos)))
+/* -------- TWI_ACR : (TWI Offset: 0x40) Alternative Command Register -------- */
+#define TWI_ACR_DATAL_Pos 0
+#define TWI_ACR_DATAL_Msk (0xffu << TWI_ACR_DATAL_Pos) /**< \brief (TWI_ACR) Data Length */
+#define TWI_ACR_DATAL(value) ((TWI_ACR_DATAL_Msk & ((value) << TWI_ACR_DATAL_Pos)))
+#define TWI_ACR_DIR (0x1u << 8) /**< \brief (TWI_ACR) Transfer Direction */
+#define TWI_ACR_PEC (0x1u << 9) /**< \brief (TWI_ACR) PEC Request (SMBus Mode only) */
+#define TWI_ACR_NDATAL_Pos 16
+#define TWI_ACR_NDATAL_Msk (0xffu << TWI_ACR_NDATAL_Pos) /**< \brief (TWI_ACR) Next Data Length */
+#define TWI_ACR_NDATAL(value) ((TWI_ACR_NDATAL_Msk & ((value) << TWI_ACR_NDATAL_Pos)))
+#define TWI_ACR_NDIR (0x1u << 24) /**< \brief (TWI_ACR) Next Transfer Direction */
+#define TWI_ACR_NPEC (0x1u << 25) /**< \brief (TWI_ACR) Next PEC Request (SMBus Mode only) */
+/* -------- TWI_FILTR : (TWI Offset: 0x44) Filter Register -------- */
+#define TWI_FILTR_FILT (0x1u << 0) /**< \brief (TWI_FILTR) RX Digital Filter */
+#define TWI_FILTR_PADFEN (0x1u << 1) /**< \brief (TWI_FILTR) PAD Filter Enable */
+#define TWI_FILTR_PADFCFG (0x1u << 2) /**< \brief (TWI_FILTR) PAD Filter Config */
+#define TWI_FILTR_THRES_Pos 8
+#define TWI_FILTR_THRES_Msk (0x7u << TWI_FILTR_THRES_Pos) /**< \brief (TWI_FILTR) Digital Filter Threshold */
+#define TWI_FILTR_THRES(value) ((TWI_FILTR_THRES_Msk & ((value) << TWI_FILTR_THRES_Pos)))
+/* -------- TWI_SWMR : (TWI Offset: 0x4C) SleepWalking Matching Register -------- */
+#define TWI_SWMR_SADR1_Pos 0
+#define TWI_SWMR_SADR1_Msk (0x7fu << TWI_SWMR_SADR1_Pos) /**< \brief (TWI_SWMR) Slave Address 1 */
+#define TWI_SWMR_SADR1(value) ((TWI_SWMR_SADR1_Msk & ((value) << TWI_SWMR_SADR1_Pos)))
+#define TWI_SWMR_SADR2_Pos 8
+#define TWI_SWMR_SADR2_Msk (0x7fu << TWI_SWMR_SADR2_Pos) /**< \brief (TWI_SWMR) Slave Address 2 */
+#define TWI_SWMR_SADR2(value) ((TWI_SWMR_SADR2_Msk & ((value) << TWI_SWMR_SADR2_Pos)))
+#define TWI_SWMR_SADR3_Pos 16
+#define TWI_SWMR_SADR3_Msk (0x7fu << TWI_SWMR_SADR3_Pos) /**< \brief (TWI_SWMR) Slave Address 3 */
+#define TWI_SWMR_SADR3(value) ((TWI_SWMR_SADR3_Msk & ((value) << TWI_SWMR_SADR3_Pos)))
+#define TWI_SWMR_DATAM_Pos 24
+#define TWI_SWMR_DATAM_Msk (0xffu << TWI_SWMR_DATAM_Pos) /**< \brief (TWI_SWMR) Data Match */
+#define TWI_SWMR_DATAM(value) ((TWI_SWMR_DATAM_Msk & ((value) << TWI_SWMR_DATAM_Pos)))
+/* -------- TWI_FMR : (TWI Offset: 0x50) FIFO Mode Register -------- */
+#define TWI_FMR_TXRDYM_Pos 0
+#define TWI_FMR_TXRDYM_Msk (0x3u << TWI_FMR_TXRDYM_Pos) /**< \brief (TWI_FMR) Transmitter Ready Mode */
+#define TWI_FMR_TXRDYM(value) ((TWI_FMR_TXRDYM_Msk & ((value) << TWI_FMR_TXRDYM_Pos)))
+#define   TWI_FMR_TXRDYM_ONE_DATA (0x0u << 0) /**< \brief (TWI_FMR) TXRDY will be at level '1' when at least one data can be written in the Transmit FIFO */
+#define   TWI_FMR_TXRDYM_TWO_DATA (0x1u << 0) /**< \brief (TWI_FMR) TXRDY will be at level '1' when at least two data can be written in the Transmit FIFO */
+#define   TWI_FMR_TXRDYM_FOUR_DATA (0x2u << 0) /**< \brief (TWI_FMR) TXRDY will be at level '1' when at least four data can be written in the Transmit FIFO */
+#define TWI_FMR_RXRDYM_Pos 4
+#define TWI_FMR_RXRDYM_Msk (0x3u << TWI_FMR_RXRDYM_Pos) /**< \brief (TWI_FMR) Receiver Ready Mode */
+#define TWI_FMR_RXRDYM(value) ((TWI_FMR_RXRDYM_Msk & ((value) << TWI_FMR_RXRDYM_Pos)))
+#define   TWI_FMR_RXRDYM_ONE_DATA (0x0u << 4) /**< \brief (TWI_FMR) RXRDY will be at level '1' when at least one unread data is in the Receive FIFO */
+#define   TWI_FMR_RXRDYM_TWO_DATA (0x1u << 4) /**< \brief (TWI_FMR) RXRDY will be at level '1' when at least two unread data are in the Receive FIFO */
+#define   TWI_FMR_RXRDYM_FOUR_DATA (0x2u << 4) /**< \brief (TWI_FMR) RXRDY will be at level '1' when at least four unread data are in the Receive FIFO */
+#define TWI_FMR_TXFTHRES_Pos 16
+#define TWI_FMR_TXFTHRES_Msk (0x3fu << TWI_FMR_TXFTHRES_Pos) /**< \brief (TWI_FMR) Transmit FIFO Threshold */
+#define TWI_FMR_TXFTHRES(value) ((TWI_FMR_TXFTHRES_Msk & ((value) << TWI_FMR_TXFTHRES_Pos)))
+#define TWI_FMR_RXFTHRES_Pos 24
+#define TWI_FMR_RXFTHRES_Msk (0x3fu << TWI_FMR_RXFTHRES_Pos) /**< \brief (TWI_FMR) Receive FIFO Threshold */
+#define TWI_FMR_RXFTHRES(value) ((TWI_FMR_RXFTHRES_Msk & ((value) << TWI_FMR_RXFTHRES_Pos)))
+/* -------- TWI_FLR : (TWI Offset: 0x54) FIFO Level Register -------- */
+#define TWI_FLR_TXFL_Pos 0
+#define TWI_FLR_TXFL_Msk (0x3fu << TWI_FLR_TXFL_Pos) /**< \brief (TWI_FLR) Transmit FIFO Level */
+#define TWI_FLR_RXFL_Pos 16
+#define TWI_FLR_RXFL_Msk (0x3fu << TWI_FLR_RXFL_Pos) /**< \brief (TWI_FLR) Receive FIFO Level */
+/* -------- TWI_FSR : (TWI Offset: 0x60) FIFO Status Register -------- */
+#define TWI_FSR_TXFEF (0x1u << 0) /**< \brief (TWI_FSR) Transmit FIFO Empty Flag (cleared on read) */
+#define TWI_FSR_TXFFF (0x1u << 1) /**< \brief (TWI_FSR) Transmit FIFO Full Flag (cleared on read) */
+#define TWI_FSR_TXFTHF (0x1u << 2) /**< \brief (TWI_FSR) Transmit FIFO Threshold Flag (cleared on read) */
+#define TWI_FSR_RXFEF (0x1u << 3) /**< \brief (TWI_FSR) Receive FIFO Empty Flag */
+#define TWI_FSR_RXFFF (0x1u << 4) /**< \brief (TWI_FSR) Receive FIFO Full Flag */
+#define TWI_FSR_RXFTHF (0x1u << 5) /**< \brief (TWI_FSR) Receive FIFO Threshold Flag */
+#define TWI_FSR_TXFPTEF (0x1u << 6) /**< \brief (TWI_FSR) Transmit FIFO Pointer Error Flag */
+#define TWI_FSR_RXFPTEF (0x1u << 7) /**< \brief (TWI_FSR) Receive FIFO Pointer Error Flag */
+/* -------- TWI_FIER : (TWI Offset: 0x64) FIFO Interrupt Enable Register -------- */
+#define TWI_FIER_TXFEF (0x1u << 0) /**< \brief (TWI_FIER) TXFEF Interrupt Enable */
+#define TWI_FIER_TXFFF (0x1u << 1) /**< \brief (TWI_FIER) TXFFF Interrupt Enable */
+#define TWI_FIER_TXFTHF (0x1u << 2) /**< \brief (TWI_FIER) TXFTHF Interrupt Enable */
+#define TWI_FIER_RXFEF (0x1u << 3) /**< \brief (TWI_FIER) RXFEF Interrupt Enable */
+#define TWI_FIER_RXFFF (0x1u << 4) /**< \brief (TWI_FIER) RXFFF Interrupt Enable */
+#define TWI_FIER_RXFTHF (0x1u << 5) /**< \brief (TWI_FIER) RXFTHF Interrupt Enable */
+#define TWI_FIER_TXFPTEF (0x1u << 6) /**< \brief (TWI_FIER) TXFPTEF Interrupt Enable */
+#define TWI_FIER_RXFPTEF (0x1u << 7) /**< \brief (TWI_FIER) RXFPTEF Interrupt Enable */
+/* -------- TWI_FIDR : (TWI Offset: 0x68) FIFO Interrupt Disable Register -------- */
+#define TWI_FIDR_TXFEF (0x1u << 0) /**< \brief (TWI_FIDR) TXFEF Interrupt Disable */
+#define TWI_FIDR_TXFFF (0x1u << 1) /**< \brief (TWI_FIDR) TXFFF Interrupt Disable */
+#define TWI_FIDR_TXFTHF (0x1u << 2) /**< \brief (TWI_FIDR) TXFTHF Interrupt Disable */
+#define TWI_FIDR_RXFEF (0x1u << 3) /**< \brief (TWI_FIDR) RXFEF Interrupt Disable */
+#define TWI_FIDR_RXFFF (0x1u << 4) /**< \brief (TWI_FIDR) RXFFF Interrupt Disable */
+#define TWI_FIDR_RXFTHF (0x1u << 5) /**< \brief (TWI_FIDR) RXFTHF Interrupt Disable */
+#define TWI_FIDR_TXFPTEF (0x1u << 6) /**< \brief (TWI_FIDR) TXFPTEF Interrupt Disable */
+#define TWI_FIDR_RXFPTEF (0x1u << 7) /**< \brief (TWI_FIDR) RXFPTEF Interrupt Disable */
+/* -------- TWI_FIMR : (TWI Offset: 0x6C) FIFO Interrupt Mask Register -------- */
+#define TWI_FIMR_TXFEF (0x1u << 0) /**< \brief (TWI_FIMR) TXFEF Interrupt Mask */
+#define TWI_FIMR_TXFFF (0x1u << 1) /**< \brief (TWI_FIMR) TXFFF Interrupt Mask */
+#define TWI_FIMR_TXFTHF (0x1u << 2) /**< \brief (TWI_FIMR) TXFTHF Interrupt Mask */
+#define TWI_FIMR_RXFEF (0x1u << 3) /**< \brief (TWI_FIMR) RXFEF Interrupt Mask */
+#define TWI_FIMR_RXFFF (0x1u << 4) /**< \brief (TWI_FIMR) RXFFF Interrupt Mask */
+#define TWI_FIMR_RXFTHF (0x1u << 5) /**< \brief (TWI_FIMR) RXFTHF Interrupt Mask */
+#define TWI_FIMR_TXFPTEF (0x1u << 6) /**< \brief (TWI_FIMR) TXFPTEF Interrupt Mask */
+#define TWI_FIMR_RXFPTEF (0x1u << 7) /**< \brief (TWI_FIMR) RXFPTEF Interrupt Mask */
+/* -------- TWI_DR : (TWI Offset: 0xD0) Debug Register -------- */
+#define TWI_DR_SWEN (0x1u << 0) /**< \brief (TWI_DR) SleepWalking Enable */
+#define TWI_DR_CLKRQ (0x1u << 1) /**< \brief (TWI_DR) Clock Request */
+#define TWI_DR_SWMATCH (0x1u << 2) /**< \brief (TWI_DR) SleepWalking Match */
+#define TWI_DR_TRP (0x1u << 3) /**< \brief (TWI_DR) Transfer Pending */
+/* -------- TWI_WPMR : (TWI Offset: 0xE4) Write Protection Mode Register -------- */
+#define TWI_WPMR_WPEN (0x1u << 0) /**< \brief (TWI_WPMR) Write Protection Enable */
+#define TWI_WPMR_WPKEY_Pos 8
+#define TWI_WPMR_WPKEY_Msk (0xffffffu << TWI_WPMR_WPKEY_Pos) /**< \brief (TWI_WPMR) Write Protection Key */
+#define TWI_WPMR_WPKEY(value) ((TWI_WPMR_WPKEY_Msk & ((value) << TWI_WPMR_WPKEY_Pos)))
+#define   TWI_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */
+/* -------- TWI_WPSR : (TWI Offset: 0xE8) Write Protection Status Register -------- */
+#define TWI_WPSR_WPVS (0x1u << 0) /**< \brief (TWI_WPSR) Write Protection Violation Status */
+#define TWI_WPSR_WPVSRC_Pos 8
+#define TWI_WPSR_WPVSRC_Msk (0xffffffu << TWI_WPSR_WPVSRC_Pos) /**< \brief (TWI_WPSR) Write Protection Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_TWI_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_uart.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_uart.h
new file mode 100644
index 000000000..1e4bb40e4
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_uart.h
@@ -0,0 +1,173 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_UART_COMPONENT_
+#define _SAMA5D2_UART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_UART Universal Asynchronous Receiver Transmitter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Uart hardware registers */
+typedef struct {
+  __O  uint32_t UART_CR;       /**< \brief (Uart Offset: 0x0000) Control Register */
+  __IO uint32_t UART_MR;       /**< \brief (Uart Offset: 0x0004) Mode Register */
+  __O  uint32_t UART_IER;      /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
+  __O  uint32_t UART_IDR;      /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
+  __I  uint32_t UART_IMR;      /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
+  __I  uint32_t UART_SR;       /**< \brief (Uart Offset: 0x0014) Status Register */
+  __I  uint32_t UART_RHR;      /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
+  __O  uint32_t UART_THR;      /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
+  __IO uint32_t UART_BRGR;     /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
+  __IO uint32_t UART_CMPR;     /**< \brief (Uart Offset: 0x0024) Comparison Register */
+  __IO uint32_t UART_RTOR;     /**< \brief (Uart Offset: 0x0028) Receiver Time-out Register */
+  __I  uint32_t Reserved1[46];
+  __IO uint32_t UART_WPMR;     /**< \brief (Uart Offset: 0x00E4) Write Protection Mode Register */
+  __I  uint32_t Reserved2[5];
+  __I  uint32_t UART_VERSION;  /**< \brief (Uart Offset: 0x00FC) Version Register */
+} Uart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
+#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
+#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
+#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
+#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
+#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
+#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
+#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status */
+#define UART_CR_RETTO (0x1u << 10) /**< \brief (UART_CR) Rearm Time-out */
+#define UART_CR_STTTO (0x1u << 11) /**< \brief (UART_CR) Start Time-out */
+#define UART_CR_REQCLR (0x1u << 12) /**< \brief (UART_CR) Request Clear */
+#define UART_CR_DBGE (0x1u << 15) /**< \brief (UART_CR) Debug Enable */
+/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
+#define UART_MR_FILTER (0x1u << 4) /**< \brief (UART_MR) Receiver Digital Filter */
+#define   UART_MR_FILTER_DISABLED (0x0u << 4) /**< \brief (UART_MR) UART does not filter the receive line. */
+#define   UART_MR_FILTER_ENABLED (0x1u << 4) /**< \brief (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */
+#define UART_MR_PAR_Pos 9
+#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
+#define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos)))
+#define   UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even Parity */
+#define   UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd Parity */
+#define   UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
+#define   UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
+#define   UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
+#define UART_MR_BRSRCCK (0x1u << 12) /**< \brief (UART_MR) Baud Rate Source Clock */
+#define   UART_MR_BRSRCCK_PERIPH_CLK (0x0u << 12) /**< \brief (UART_MR) The baud rate is driven by the peripheral clock */
+#define   UART_MR_BRSRCCK_PMC_PCK (0x1u << 12) /**< \brief (UART_MR) The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). */
+#define UART_MR_CHMODE_Pos 14
+#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
+#define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos)))
+#define   UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal mode */
+#define   UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic echo */
+#define   UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local loopback */
+#define   UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote loopback */
+/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
+#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
+#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
+#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
+#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
+#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
+#define UART_IER_TIMEOUT (0x1u << 8) /**< \brief (UART_IER) Enable Time-out Interrupt */
+#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
+#define UART_IER_CMP (0x1u << 15) /**< \brief (UART_IER) Enable Comparison Interrupt */
+/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
+#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
+#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
+#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
+#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
+#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
+#define UART_IDR_TIMEOUT (0x1u << 8) /**< \brief (UART_IDR) Disable Time-out Interrupt */
+#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
+#define UART_IDR_CMP (0x1u << 15) /**< \brief (UART_IDR) Disable Comparison Interrupt */
+/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
+#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
+#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
+#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
+#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
+#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
+#define UART_IMR_TIMEOUT (0x1u << 8) /**< \brief (UART_IMR) Mask Time-out Interrupt */
+#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
+#define UART_IMR_CMP (0x1u << 15) /**< \brief (UART_IMR) Mask Comparison Interrupt */
+/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
+#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
+#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
+#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
+#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
+#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
+#define UART_SR_TIMEOUT (0x1u << 8) /**< \brief (UART_SR) Receiver Time-out */
+#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
+#define UART_SR_CMP (0x1u << 15) /**< \brief (UART_SR) Comparison Match */
+#define UART_SR_SWES (0x1u << 21) /**< \brief (UART_SR) SleepWalking Enable Status */
+#define UART_SR_CLKREQ (0x1u << 22) /**< \brief (UART_SR) Clock Request */
+#define UART_SR_WKUPREQ (0x1u << 23) /**< \brief (UART_SR) Wake-Up Request */
+/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
+#define UART_RHR_RXCHR_Pos 0
+#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
+/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
+#define UART_THR_TXCHR_Pos 0
+#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
+#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
+/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define UART_BRGR_CD_Pos 0
+#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
+#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
+/* -------- UART_CMPR : (UART Offset: 0x0024) Comparison Register -------- */
+#define UART_CMPR_VAL1_Pos 0
+#define UART_CMPR_VAL1_Msk (0xffu << UART_CMPR_VAL1_Pos) /**< \brief (UART_CMPR) First Comparison Value for Received Character */
+#define UART_CMPR_VAL1(value) ((UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos)))
+#define UART_CMPR_CMPMODE (0x1u << 12) /**< \brief (UART_CMPR) Comparison Mode */
+#define   UART_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (UART_CMPR) Any character is received and comparison function drives CMP flag. */
+#define   UART_CMPR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (UART_CMPR) Comparison condition must be met to start reception. */
+#define UART_CMPR_CMPPAR (0x1u << 14) /**< \brief (UART_CMPR) Compare Parity */
+#define UART_CMPR_VAL2_Pos 16
+#define UART_CMPR_VAL2_Msk (0xffu << UART_CMPR_VAL2_Pos) /**< \brief (UART_CMPR) Second Comparison Value for Received Character */
+#define UART_CMPR_VAL2(value) ((UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos)))
+/* -------- UART_RTOR : (UART Offset: 0x0028) Receiver Time-out Register -------- */
+#define UART_RTOR_TO_Pos 0
+#define UART_RTOR_TO_Msk (0xffu << UART_RTOR_TO_Pos) /**< \brief (UART_RTOR) Time-out Value */
+#define UART_RTOR_TO(value) ((UART_RTOR_TO_Msk & ((value) << UART_RTOR_TO_Pos)))
+/* -------- UART_WPMR : (UART Offset: 0x00E4) Write Protection Mode Register -------- */
+#define UART_WPMR_WPEN (0x1u << 0) /**< \brief (UART_WPMR) Write Protection Enable */
+#define UART_WPMR_WPKEY_Pos 8
+#define UART_WPMR_WPKEY_Msk (0xffffffu << UART_WPMR_WPKEY_Pos) /**< \brief (UART_WPMR) Write Protection Key */
+#define UART_WPMR_WPKEY(value) ((UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos)))
+#define   UART_WPMR_WPKEY_PASSWD (0x554152u << 8) /**< \brief (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */
+/* -------- UART_VERSION : (UART Offset: 0x00FC) Version Register -------- */
+#define UART_VERSION_VERSION_Pos 0
+#define UART_VERSION_VERSION_Msk (0xfffu << UART_VERSION_VERSION_Pos) /**< \brief (UART_VERSION) Hardware Module Version */
+#define UART_VERSION_MFN_Pos 16
+#define UART_VERSION_MFN_Msk (0x7u << UART_VERSION_MFN_Pos) /**< \brief (UART_VERSION) Metal Fix Number */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_UART_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_udphs.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_udphs.h
new file mode 100644
index 000000000..e68fd0cbd
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_udphs.h
@@ -0,0 +1,399 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_UDPHS_COMPONENT_
+#define _SAMA5D2_UDPHS_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR USB High Speed Device Port */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_UDPHS USB High Speed Device Port */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief UdphsDma hardware registers */
+typedef struct {
+  __IO uint32_t UDPHS_DMANXTDSC;  /**< \brief (UdphsDma Offset: 0x0) UDPHS DMA Next Descriptor Address Register */
+  __IO uint32_t UDPHS_DMAADDRESS; /**< \brief (UdphsDma Offset: 0x4) UDPHS DMA Channel Address Register */
+  __IO uint32_t UDPHS_DMACONTROL; /**< \brief (UdphsDma Offset: 0x8) UDPHS DMA Channel Control Register */
+  __IO uint32_t UDPHS_DMASTATUS;  /**< \brief (UdphsDma Offset: 0xC) UDPHS DMA Channel Status Register */
+} UdphsDma;
+/** \brief UdphsEpt hardware registers */
+typedef struct {
+  __IO uint32_t UDPHS_EPTCFG;    /**< \brief (UdphsEpt Offset: 0x0) UDPHS Endpoint Configuration Register */
+  __O  uint32_t UDPHS_EPTCTLENB; /**< \brief (UdphsEpt Offset: 0x4) UDPHS Endpoint Control Enable Register */
+  __O  uint32_t UDPHS_EPTCTLDIS; /**< \brief (UdphsEpt Offset: 0x8) UDPHS Endpoint Control Disable Register */
+  __I  uint32_t UDPHS_EPTCTL;    /**< \brief (UdphsEpt Offset: 0xC) UDPHS Endpoint Control Register */
+  __I  uint32_t Reserved1[1];
+  __O  uint32_t UDPHS_EPTSETSTA; /**< \brief (UdphsEpt Offset: 0x14) UDPHS Endpoint Set Status Register */
+  __O  uint32_t UDPHS_EPTCLRSTA; /**< \brief (UdphsEpt Offset: 0x18) UDPHS Endpoint Clear Status Register */
+  __I  uint32_t UDPHS_EPTSTA;    /**< \brief (UdphsEpt Offset: 0x1C) UDPHS Endpoint Status Register */
+} UdphsEpt;
+/** \brief Udphs hardware registers */
+#define UDPHSEPT_NUMBER 16
+#define UDPHSDMA_NUMBER 7
+typedef struct {
+  __IO uint32_t UDPHS_CTRL;                 /**< \brief (Udphs Offset: 0x00) UDPHS Control Register */
+  __I  uint32_t UDPHS_FNUM;                 /**< \brief (Udphs Offset: 0x04) UDPHS Frame Number Register */
+  __I  uint32_t Reserved1[2];
+  __IO uint32_t UDPHS_IEN;                  /**< \brief (Udphs Offset: 0x10) UDPHS Interrupt Enable Register */
+  __I  uint32_t UDPHS_INTSTA;               /**< \brief (Udphs Offset: 0x14) UDPHS Interrupt Status Register */
+  __O  uint32_t UDPHS_CLRINT;               /**< \brief (Udphs Offset: 0x18) UDPHS Clear Interrupt Register */
+  __O  uint32_t UDPHS_EPTRST;               /**< \brief (Udphs Offset: 0x1C) UDPHS Endpoints Reset Register */
+  __I  uint32_t Reserved2[44];
+  __IO uint32_t UDPHS_TSTSOFCNT;            /**< \brief (Udphs Offset: 0xD0) UDPHS Test SOF Counter Register */
+  __IO uint32_t UDPHS_TSTCNTA;              /**< \brief (Udphs Offset: 0xD4) UDPHS Test A Counter Register */
+  __IO uint32_t UDPHS_TSTCNTB;              /**< \brief (Udphs Offset: 0xD8) UDPHS Test B Counter Register */
+  __IO uint32_t UDPHS_TSTMODEREG;           /**< \brief (Udphs Offset: 0xDC) UDPHS Test Mode Register */
+  __IO uint32_t UDPHS_TST;                  /**< \brief (Udphs Offset: 0xE0) UDPHS Test Register */
+  __I  uint32_t Reserved3[6];
+  __I  uint32_t UDPHS_VERSION;              /**< \brief (Udphs Offset: 0xFC) UDPHS Version Register */
+       UdphsEpt UDPHS_EPT[UDPHSEPT_NUMBER]; /**< \brief (Udphs Offset: 0x100) endpoint = 0 .. 15 */
+       UdphsDma UDPHS_DMA[UDPHSDMA_NUMBER]; /**< \brief (Udphs Offset: 0x300) channel = 0 .. 6 */
+} Udphs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- UDPHS_CTRL : (UDPHS Offset: 0x00) UDPHS Control Register -------- */
+#define UDPHS_CTRL_DEV_ADDR_Pos 0
+#define UDPHS_CTRL_DEV_ADDR_Msk (0x7fu << UDPHS_CTRL_DEV_ADDR_Pos) /**< \brief (UDPHS_CTRL) UDPHS Address (cleared upon USB reset) */
+#define UDPHS_CTRL_DEV_ADDR(value) ((UDPHS_CTRL_DEV_ADDR_Msk & ((value) << UDPHS_CTRL_DEV_ADDR_Pos)))
+#define UDPHS_CTRL_FADDR_EN (0x1u << 7) /**< \brief (UDPHS_CTRL) Function Address Enable (cleared upon USB reset) */
+#define UDPHS_CTRL_EN_UDPHS (0x1u << 8) /**< \brief (UDPHS_CTRL) UDPHS Enable */
+#define UDPHS_CTRL_DETACH (0x1u << 9) /**< \brief (UDPHS_CTRL) Detach Command */
+#define UDPHS_CTRL_REWAKEUP (0x1u << 10) /**< \brief (UDPHS_CTRL) Send Remote Wake Up (cleared upon USB reset) */
+#define UDPHS_CTRL_PULLD_DIS (0x1u << 11) /**< \brief (UDPHS_CTRL) Pull-Down Disable (cleared upon USB reset) */
+/* -------- UDPHS_FNUM : (UDPHS Offset: 0x04) UDPHS Frame Number Register -------- */
+#define UDPHS_FNUM_MICRO_FRAME_NUM_Pos 0
+#define UDPHS_FNUM_MICRO_FRAME_NUM_Msk (0x7u << UDPHS_FNUM_MICRO_FRAME_NUM_Pos) /**< \brief (UDPHS_FNUM) Microframe Number (cleared upon USB reset) */
+#define UDPHS_FNUM_FRAME_NUMBER_Pos 3
+#define UDPHS_FNUM_FRAME_NUMBER_Msk (0x7ffu << UDPHS_FNUM_FRAME_NUMBER_Pos) /**< \brief (UDPHS_FNUM) Frame Number as defined in the Packet Field Formats (cleared upon USB reset) */
+#define UDPHS_FNUM_FNUM_ERR (0x1u << 31) /**< \brief (UDPHS_FNUM) Frame Number CRC Error (cleared upon USB reset) */
+/* -------- UDPHS_IEN : (UDPHS Offset: 0x10) UDPHS Interrupt Enable Register -------- */
+#define UDPHS_IEN_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_IEN) Suspend Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_IEN) Micro-SOF Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_INT_SOF (0x1u << 3) /**< \brief (UDPHS_IEN) SOF Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_ENDRESET (0x1u << 4) /**< \brief (UDPHS_IEN) End Of Reset Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_IEN) Wake Up CPU Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_IEN) End Of Resume Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_IEN) Upstream Resume Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_EPT_0 (0x1u << 8) /**< \brief (UDPHS_IEN) Endpoint 0 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_EPT_1 (0x1u << 9) /**< \brief (UDPHS_IEN) Endpoint 1 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_EPT_2 (0x1u << 10) /**< \brief (UDPHS_IEN) Endpoint 2 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_EPT_3 (0x1u << 11) /**< \brief (UDPHS_IEN) Endpoint 3 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_EPT_4 (0x1u << 12) /**< \brief (UDPHS_IEN) Endpoint 4 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_EPT_5 (0x1u << 13) /**< \brief (UDPHS_IEN) Endpoint 5 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_EPT_6 (0x1u << 14) /**< \brief (UDPHS_IEN) Endpoint 6 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_EPT_7 (0x1u << 15) /**< \brief (UDPHS_IEN) Endpoint 7 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_EPT_8 (0x1u << 16) /**< \brief (UDPHS_IEN) Endpoint 8 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_EPT_9 (0x1u << 17) /**< \brief (UDPHS_IEN) Endpoint 9 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_EPT_10 (0x1u << 18) /**< \brief (UDPHS_IEN) Endpoint 10 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_EPT_11 (0x1u << 19) /**< \brief (UDPHS_IEN) Endpoint 11 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_EPT_12 (0x1u << 20) /**< \brief (UDPHS_IEN) Endpoint 12 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_EPT_13 (0x1u << 21) /**< \brief (UDPHS_IEN) Endpoint 13 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_EPT_14 (0x1u << 22) /**< \brief (UDPHS_IEN) Endpoint 14 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_EPT_15 (0x1u << 23) /**< \brief (UDPHS_IEN) Endpoint 15 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_DMA_1 (0x1u << 25) /**< \brief (UDPHS_IEN) DMA Channel 1 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_DMA_2 (0x1u << 26) /**< \brief (UDPHS_IEN) DMA Channel 2 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_DMA_3 (0x1u << 27) /**< \brief (UDPHS_IEN) DMA Channel 3 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_DMA_4 (0x1u << 28) /**< \brief (UDPHS_IEN) DMA Channel 4 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_DMA_5 (0x1u << 29) /**< \brief (UDPHS_IEN) DMA Channel 5 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_DMA_6 (0x1u << 30) /**< \brief (UDPHS_IEN) DMA Channel 6 Interrupt Enable (cleared upon USB reset) */
+#define UDPHS_IEN_DMA_7 (0x1u << 31) /**< \brief (UDPHS_IEN) DMA Channel 7 Interrupt Enable (cleared upon USB reset) */
+/* -------- UDPHS_INTSTA : (UDPHS Offset: 0x14) UDPHS Interrupt Status Register -------- */
+#define UDPHS_INTSTA_SPEED (0x1u << 0) /**< \brief (UDPHS_INTSTA) Speed Status */
+#define UDPHS_INTSTA_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_INTSTA) Suspend Interrupt */
+#define UDPHS_INTSTA_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_INTSTA) Micro Start Of Frame Interrupt */
+#define UDPHS_INTSTA_INT_SOF (0x1u << 3) /**< \brief (UDPHS_INTSTA) Start Of Frame Interrupt */
+#define UDPHS_INTSTA_ENDRESET (0x1u << 4) /**< \brief (UDPHS_INTSTA) End Of Reset Interrupt */
+#define UDPHS_INTSTA_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_INTSTA) Wake Up CPU Interrupt */
+#define UDPHS_INTSTA_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_INTSTA) End Of Resume Interrupt */
+#define UDPHS_INTSTA_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_INTSTA) Upstream Resume Interrupt */
+#define UDPHS_INTSTA_EPT_0 (0x1u << 8) /**< \brief (UDPHS_INTSTA) Endpoint 0 Interrupt (cleared upon USB reset) */
+#define UDPHS_INTSTA_EPT_1 (0x1u << 9) /**< \brief (UDPHS_INTSTA) Endpoint 1 Interrupt (cleared upon USB reset) */
+#define UDPHS_INTSTA_EPT_2 (0x1u << 10) /**< \brief (UDPHS_INTSTA) Endpoint 2 Interrupt (cleared upon USB reset) */
+#define UDPHS_INTSTA_EPT_3 (0x1u << 11) /**< \brief (UDPHS_INTSTA) Endpoint 3 Interrupt (cleared upon USB reset) */
+#define UDPHS_INTSTA_EPT_4 (0x1u << 12) /**< \brief (UDPHS_INTSTA) Endpoint 4 Interrupt (cleared upon USB reset) */
+#define UDPHS_INTSTA_EPT_5 (0x1u << 13) /**< \brief (UDPHS_INTSTA) Endpoint 5 Interrupt (cleared upon USB reset) */
+#define UDPHS_INTSTA_EPT_6 (0x1u << 14) /**< \brief (UDPHS_INTSTA) Endpoint 6 Interrupt (cleared upon USB reset) */
+#define UDPHS_INTSTA_EPT_7 (0x1u << 15) /**< \brief (UDPHS_INTSTA) Endpoint 7 Interrupt (cleared upon USB reset) */
+#define UDPHS_INTSTA_EPT_8 (0x1u << 16) /**< \brief (UDPHS_INTSTA) Endpoint 8 Interrupt (cleared upon USB reset) */
+#define UDPHS_INTSTA_EPT_9 (0x1u << 17) /**< \brief (UDPHS_INTSTA) Endpoint 9 Interrupt (cleared upon USB reset) */
+#define UDPHS_INTSTA_EPT_10 (0x1u << 18) /**< \brief (UDPHS_INTSTA) Endpoint 10 Interrupt (cleared upon USB reset) */
+#define UDPHS_INTSTA_EPT_11 (0x1u << 19) /**< \brief (UDPHS_INTSTA) Endpoint 11 Interrupt (cleared upon USB reset) */
+#define UDPHS_INTSTA_EPT_12 (0x1u << 20) /**< \brief (UDPHS_INTSTA) Endpoint 12 Interrupt (cleared upon USB reset) */
+#define UDPHS_INTSTA_EPT_13 (0x1u << 21) /**< \brief (UDPHS_INTSTA) Endpoint 13 Interrupt (cleared upon USB reset) */
+#define UDPHS_INTSTA_EPT_14 (0x1u << 22) /**< \brief (UDPHS_INTSTA) Endpoint 14 Interrupt (cleared upon USB reset) */
+#define UDPHS_INTSTA_EPT_15 (0x1u << 23) /**< \brief (UDPHS_INTSTA) Endpoint 15 Interrupt (cleared upon USB reset) */
+#define UDPHS_INTSTA_DMA_1 (0x1u << 25) /**< \brief (UDPHS_INTSTA) DMA Channel 1 Interrupt */
+#define UDPHS_INTSTA_DMA_2 (0x1u << 26) /**< \brief (UDPHS_INTSTA) DMA Channel 2 Interrupt */
+#define UDPHS_INTSTA_DMA_3 (0x1u << 27) /**< \brief (UDPHS_INTSTA) DMA Channel 3 Interrupt */
+#define UDPHS_INTSTA_DMA_4 (0x1u << 28) /**< \brief (UDPHS_INTSTA) DMA Channel 4 Interrupt */
+#define UDPHS_INTSTA_DMA_5 (0x1u << 29) /**< \brief (UDPHS_INTSTA) DMA Channel 5 Interrupt */
+#define UDPHS_INTSTA_DMA_6 (0x1u << 30) /**< \brief (UDPHS_INTSTA) DMA Channel 6 Interrupt */
+#define UDPHS_INTSTA_DMA_7 (0x1u << 31) /**< \brief (UDPHS_INTSTA) DMA Channel 7 Interrupt */
+/* -------- UDPHS_CLRINT : (UDPHS Offset: 0x18) UDPHS Clear Interrupt Register -------- */
+#define UDPHS_CLRINT_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_CLRINT) Suspend Interrupt Clear */
+#define UDPHS_CLRINT_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_CLRINT) Micro Start Of Frame Interrupt Clear */
+#define UDPHS_CLRINT_INT_SOF (0x1u << 3) /**< \brief (UDPHS_CLRINT) Start Of Frame Interrupt Clear */
+#define UDPHS_CLRINT_ENDRESET (0x1u << 4) /**< \brief (UDPHS_CLRINT) End Of Reset Interrupt Clear */
+#define UDPHS_CLRINT_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_CLRINT) Wake Up CPU Interrupt Clear */
+#define UDPHS_CLRINT_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_CLRINT) End Of Resume Interrupt Clear */
+#define UDPHS_CLRINT_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_CLRINT) Upstream Resume Interrupt Clear */
+/* -------- UDPHS_EPTRST : (UDPHS Offset: 0x1C) UDPHS Endpoints Reset Register -------- */
+#define UDPHS_EPTRST_EPT_0 (0x1u << 0) /**< \brief (UDPHS_EPTRST) Endpoint 0 Reset */
+#define UDPHS_EPTRST_EPT_1 (0x1u << 1) /**< \brief (UDPHS_EPTRST) Endpoint 1 Reset */
+#define UDPHS_EPTRST_EPT_2 (0x1u << 2) /**< \brief (UDPHS_EPTRST) Endpoint 2 Reset */
+#define UDPHS_EPTRST_EPT_3 (0x1u << 3) /**< \brief (UDPHS_EPTRST) Endpoint 3 Reset */
+#define UDPHS_EPTRST_EPT_4 (0x1u << 4) /**< \brief (UDPHS_EPTRST) Endpoint 4 Reset */
+#define UDPHS_EPTRST_EPT_5 (0x1u << 5) /**< \brief (UDPHS_EPTRST) Endpoint 5 Reset */
+#define UDPHS_EPTRST_EPT_6 (0x1u << 6) /**< \brief (UDPHS_EPTRST) Endpoint 6 Reset */
+#define UDPHS_EPTRST_EPT_7 (0x1u << 7) /**< \brief (UDPHS_EPTRST) Endpoint 7 Reset */
+#define UDPHS_EPTRST_EPT_8 (0x1u << 8) /**< \brief (UDPHS_EPTRST) Endpoint 8 Reset */
+#define UDPHS_EPTRST_EPT_9 (0x1u << 9) /**< \brief (UDPHS_EPTRST) Endpoint 9 Reset */
+#define UDPHS_EPTRST_EPT_10 (0x1u << 10) /**< \brief (UDPHS_EPTRST) Endpoint 10 Reset */
+#define UDPHS_EPTRST_EPT_11 (0x1u << 11) /**< \brief (UDPHS_EPTRST) Endpoint 11 Reset */
+#define UDPHS_EPTRST_EPT_12 (0x1u << 12) /**< \brief (UDPHS_EPTRST) Endpoint 12 Reset */
+#define UDPHS_EPTRST_EPT_13 (0x1u << 13) /**< \brief (UDPHS_EPTRST) Endpoint 13 Reset */
+#define UDPHS_EPTRST_EPT_14 (0x1u << 14) /**< \brief (UDPHS_EPTRST) Endpoint 14 Reset */
+#define UDPHS_EPTRST_EPT_15 (0x1u << 15) /**< \brief (UDPHS_EPTRST) Endpoint 15 Reset */
+/* -------- UDPHS_TSTSOFCNT : (UDPHS Offset: 0xD0) UDPHS Test SOF Counter Register -------- */
+#define UDPHS_TSTSOFCNT_SOFCNTMAX_Pos 0
+#define UDPHS_TSTSOFCNT_SOFCNTMAX_Msk (0x7fu << UDPHS_TSTSOFCNT_SOFCNTMAX_Pos) /**< \brief (UDPHS_TSTSOFCNT) SOF Counter Max Value */
+#define UDPHS_TSTSOFCNT_SOFCNTMAX(value) ((UDPHS_TSTSOFCNT_SOFCNTMAX_Msk & ((value) << UDPHS_TSTSOFCNT_SOFCNTMAX_Pos)))
+#define UDPHS_TSTSOFCNT_SOFCTLOAD (0x1u << 7) /**< \brief (UDPHS_TSTSOFCNT) SOF Counter Load */
+/* -------- UDPHS_TSTCNTA : (UDPHS Offset: 0xD4) UDPHS Test A Counter Register -------- */
+#define UDPHS_TSTCNTA_CNTAMAX_Pos 0
+#define UDPHS_TSTCNTA_CNTAMAX_Msk (0x7fffu << UDPHS_TSTCNTA_CNTAMAX_Pos) /**< \brief (UDPHS_TSTCNTA) A Counter Max Value */
+#define UDPHS_TSTCNTA_CNTAMAX(value) ((UDPHS_TSTCNTA_CNTAMAX_Msk & ((value) << UDPHS_TSTCNTA_CNTAMAX_Pos)))
+#define UDPHS_TSTCNTA_CNTALOAD (0x1u << 15) /**< \brief (UDPHS_TSTCNTA) A Counter Load */
+/* -------- UDPHS_TSTCNTB : (UDPHS Offset: 0xD8) UDPHS Test B Counter Register -------- */
+#define UDPHS_TSTCNTB_CNTBMAX_Pos 0
+#define UDPHS_TSTCNTB_CNTBMAX_Msk (0x7fffu << UDPHS_TSTCNTB_CNTBMAX_Pos) /**< \brief (UDPHS_TSTCNTB) B Counter Max Value */
+#define UDPHS_TSTCNTB_CNTBMAX(value) ((UDPHS_TSTCNTB_CNTBMAX_Msk & ((value) << UDPHS_TSTCNTB_CNTBMAX_Pos)))
+#define UDPHS_TSTCNTB_CNTBLOAD (0x1u << 15) /**< \brief (UDPHS_TSTCNTB) B Counter Load */
+/* -------- UDPHS_TSTMODEREG : (UDPHS Offset: 0xDC) UDPHS Test Mode Register -------- */
+#define UDPHS_TSTMODEREG_TSTMODE_Pos 1
+#define UDPHS_TSTMODEREG_TSTMODE_Msk (0x1fu << UDPHS_TSTMODEREG_TSTMODE_Pos) /**< \brief (UDPHS_TSTMODEREG) UDPHS Core TestModeReg */
+#define UDPHS_TSTMODEREG_TSTMODE(value) ((UDPHS_TSTMODEREG_TSTMODE_Msk & ((value) << UDPHS_TSTMODEREG_TSTMODE_Pos)))
+/* -------- UDPHS_TST : (UDPHS Offset: 0xE0) UDPHS Test Register -------- */
+#define UDPHS_TST_SPEED_CFG_Pos 0
+#define UDPHS_TST_SPEED_CFG_Msk (0x3u << UDPHS_TST_SPEED_CFG_Pos) /**< \brief (UDPHS_TST) Speed Configuration */
+#define UDPHS_TST_SPEED_CFG(value) ((UDPHS_TST_SPEED_CFG_Msk & ((value) << UDPHS_TST_SPEED_CFG_Pos)))
+#define   UDPHS_TST_SPEED_CFG_NORMAL (0x0u << 0) /**< \brief (UDPHS_TST) Normal mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode. */
+#define   UDPHS_TST_SPEED_CFG_HIGH_SPEED (0x2u << 0) /**< \brief (UDPHS_TST) Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose. */
+#define   UDPHS_TST_SPEED_CFG_FULL_SPEED (0x3u << 0) /**< \brief (UDPHS_TST) Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake. */
+#define UDPHS_TST_TST_J (0x1u << 2) /**< \brief (UDPHS_TST) Test J Mode */
+#define UDPHS_TST_TST_K (0x1u << 3) /**< \brief (UDPHS_TST) Test K Mode */
+#define UDPHS_TST_TST_PKT (0x1u << 4) /**< \brief (UDPHS_TST) Test Packet Mode */
+#define UDPHS_TST_OPMODE2 (0x1u << 5) /**< \brief (UDPHS_TST) OpMode2 */
+/* -------- UDPHS_VERSION : (UDPHS Offset: 0xFC) UDPHS Version Register -------- */
+#define UDPHS_VERSION_VERSION_Pos 0
+#define UDPHS_VERSION_VERSION_Msk (0xffffu << UDPHS_VERSION_VERSION_Pos) /**< \brief (UDPHS_VERSION) Version of the Hardware Module */
+#define UDPHS_VERSION_MFN_Pos 16
+#define UDPHS_VERSION_MFN_Msk (0x7u << UDPHS_VERSION_MFN_Pos) /**< \brief (UDPHS_VERSION) Metal Fix Number */
+/* -------- UDPHS_EPTCFG : (UDPHS Offset: N/A) UDPHS Endpoint Configuration Register -------- */
+#define UDPHS_EPTCFG_EPT_SIZE_Pos 0
+#define UDPHS_EPTCFG_EPT_SIZE_Msk (0x7u << UDPHS_EPTCFG_EPT_SIZE_Pos) /**< \brief (UDPHS_EPTCFG) Endpoint Size (cleared upon USB reset) */
+#define UDPHS_EPTCFG_EPT_SIZE(value) ((UDPHS_EPTCFG_EPT_SIZE_Msk & ((value) << UDPHS_EPTCFG_EPT_SIZE_Pos)))
+#define   UDPHS_EPTCFG_EPT_SIZE_8 (0x0u << 0) /**< \brief (UDPHS_EPTCFG) 8 bytes */
+#define   UDPHS_EPTCFG_EPT_SIZE_16 (0x1u << 0) /**< \brief (UDPHS_EPTCFG) 16 bytes */
+#define   UDPHS_EPTCFG_EPT_SIZE_32 (0x2u << 0) /**< \brief (UDPHS_EPTCFG) 32 bytes */
+#define   UDPHS_EPTCFG_EPT_SIZE_64 (0x3u << 0) /**< \brief (UDPHS_EPTCFG) 64 bytes */
+#define   UDPHS_EPTCFG_EPT_SIZE_128 (0x4u << 0) /**< \brief (UDPHS_EPTCFG) 128 bytes */
+#define   UDPHS_EPTCFG_EPT_SIZE_256 (0x5u << 0) /**< \brief (UDPHS_EPTCFG) 256 bytes */
+#define   UDPHS_EPTCFG_EPT_SIZE_512 (0x6u << 0) /**< \brief (UDPHS_EPTCFG) 512 bytes */
+#define   UDPHS_EPTCFG_EPT_SIZE_1024 (0x7u << 0) /**< \brief (UDPHS_EPTCFG) 1024 bytes */
+#define UDPHS_EPTCFG_EPT_DIR (0x1u << 3) /**< \brief (UDPHS_EPTCFG) Endpoint Direction (cleared upon USB reset) */
+#define UDPHS_EPTCFG_EPT_TYPE_Pos 4
+#define UDPHS_EPTCFG_EPT_TYPE_Msk (0x3u << UDPHS_EPTCFG_EPT_TYPE_Pos) /**< \brief (UDPHS_EPTCFG) Endpoint Type (cleared upon USB reset) */
+#define UDPHS_EPTCFG_EPT_TYPE(value) ((UDPHS_EPTCFG_EPT_TYPE_Msk & ((value) << UDPHS_EPTCFG_EPT_TYPE_Pos)))
+#define   UDPHS_EPTCFG_EPT_TYPE_CTRL8 (0x0u << 4) /**< \brief (UDPHS_EPTCFG) Control endpoint */
+#define   UDPHS_EPTCFG_EPT_TYPE_ISO (0x1u << 4) /**< \brief (UDPHS_EPTCFG) Isochronous endpoint */
+#define   UDPHS_EPTCFG_EPT_TYPE_BULK (0x2u << 4) /**< \brief (UDPHS_EPTCFG) Bulk endpoint */
+#define   UDPHS_EPTCFG_EPT_TYPE_INT (0x3u << 4) /**< \brief (UDPHS_EPTCFG) Interrupt endpoint */
+#define UDPHS_EPTCFG_BK_NUMBER_Pos 6
+#define UDPHS_EPTCFG_BK_NUMBER_Msk (0x3u << UDPHS_EPTCFG_BK_NUMBER_Pos) /**< \brief (UDPHS_EPTCFG) Number of Banks (cleared upon USB reset) */
+#define UDPHS_EPTCFG_BK_NUMBER(value) ((UDPHS_EPTCFG_BK_NUMBER_Msk & ((value) << UDPHS_EPTCFG_BK_NUMBER_Pos)))
+#define   UDPHS_EPTCFG_BK_NUMBER_0 (0x0u << 6) /**< \brief (UDPHS_EPTCFG) Zero bank, the endpoint is not mapped in memory */
+#define   UDPHS_EPTCFG_BK_NUMBER_1 (0x1u << 6) /**< \brief (UDPHS_EPTCFG) One bank (bank 0) */
+#define   UDPHS_EPTCFG_BK_NUMBER_2 (0x2u << 6) /**< \brief (UDPHS_EPTCFG) Double bank (Ping-Pong: bank0/bank1) */
+#define   UDPHS_EPTCFG_BK_NUMBER_3 (0x3u << 6) /**< \brief (UDPHS_EPTCFG) Triple bank (bank0/bank1/bank2) */
+#define UDPHS_EPTCFG_NB_TRANS_Pos 8
+#define UDPHS_EPTCFG_NB_TRANS_Msk (0x3u << UDPHS_EPTCFG_NB_TRANS_Pos) /**< \brief (UDPHS_EPTCFG) Number Of Transaction per Microframe (cleared upon USB reset) */
+#define UDPHS_EPTCFG_NB_TRANS(value) ((UDPHS_EPTCFG_NB_TRANS_Msk & ((value) << UDPHS_EPTCFG_NB_TRANS_Pos)))
+#define UDPHS_EPTCFG_EPT_MAPD (0x1u << 31) /**< \brief (UDPHS_EPTCFG) Endpoint Mapped (cleared upon USB reset) */
+/* -------- UDPHS_EPTCTLENB : (UDPHS Offset: N/A) UDPHS Endpoint Control Enable Register -------- */
+#define UDPHS_EPTCTLENB_EPT_ENABL (0x1u << 0) /**< \brief (UDPHS_EPTCTLENB) Endpoint Enable */
+#define UDPHS_EPTCTLENB_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTLENB) Packet Auto-Valid Enable */
+#define UDPHS_EPTCTLENB_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTLENB) Interrupts Disable DMA */
+#define UDPHS_EPTCTLENB_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTLENB) NYET Disable (Only for High Speed Bulk OUT endpoints) */
+#define UDPHS_EPTCTLENB_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTLENB) Overflow Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTCTLENB) Received OUT Data Interrupt Enable */
+#define UDPHS_EPTCTLENB_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTLENB) Transmitted IN Data Complete Interrupt Enable */
+#define UDPHS_EPTCTLENB_TXRDY (0x1u << 11) /**< \brief (UDPHS_EPTCTLENB) TX Packet Ready Interrupt Enable */
+#define UDPHS_EPTCTLENB_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTLENB) Received SETUP */
+#define UDPHS_EPTCTLENB_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) Stall Sent Interrupt Enable */
+#define UDPHS_EPTCTLENB_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTLENB) NAKIN Interrupt Enable */
+#define UDPHS_EPTCTLENB_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTLENB) NAKOUT Interrupt Enable */
+#define UDPHS_EPTCTLENB_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTLENB) Busy Bank Interrupt Enable */
+#define UDPHS_EPTCTLENB_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTLENB) Short Packet Send/Short Packet Interrupt Enable */
+#define UDPHS_EPTCTLENB_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTLENB) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTLENB_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTLENB) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTLENB_TXRDY_TRER (0x1u << 11) /**< \brief (UDPHS_EPTCTLENB) TX Packet Ready/Transaction Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTLENB) Error Flow Interrupt Enable */
+#define UDPHS_EPTCTLENB_ERR_CRC_NTR (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) ISO CRC Error/Number of Transaction Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTLENB) Bank Flush Error Interrupt Enable */
+/* -------- UDPHS_EPTCTLDIS : (UDPHS Offset: N/A) UDPHS Endpoint Control Disable Register -------- */
+#define UDPHS_EPTCTLDIS_EPT_DISABL (0x1u << 0) /**< \brief (UDPHS_EPTCTLDIS) Endpoint Disable */
+#define UDPHS_EPTCTLDIS_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTLDIS) Packet Auto-Valid Disable */
+#define UDPHS_EPTCTLDIS_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTLDIS) Interrupts Disable DMA */
+#define UDPHS_EPTCTLDIS_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTLDIS) NYET Enable (Only for High Speed Bulk OUT endpoints) */
+#define UDPHS_EPTCTLDIS_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTLDIS) Overflow Error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTCTLDIS) Received OUT Data Interrupt Disable */
+#define UDPHS_EPTCTLDIS_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTLDIS) Transmitted IN Data Complete Interrupt Disable */
+#define UDPHS_EPTCTLDIS_TXRDY (0x1u << 11) /**< \brief (UDPHS_EPTCTLDIS) TX Packet Ready Interrupt Disable */
+#define UDPHS_EPTCTLDIS_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTLDIS) Received SETUP Interrupt Disable */
+#define UDPHS_EPTCTLDIS_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) Stall Sent Interrupt Disable */
+#define UDPHS_EPTCTLDIS_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTLDIS) NAKIN Interrupt Disable */
+#define UDPHS_EPTCTLDIS_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTLDIS) NAKOUT Interrupt Disable */
+#define UDPHS_EPTCTLDIS_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTLDIS) Busy Bank Interrupt Disable */
+#define UDPHS_EPTCTLDIS_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTLDIS) Short Packet Interrupt Disable */
+#define UDPHS_EPTCTLDIS_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTLDIS) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTLDIS_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTLDIS) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTLDIS_TXRDY_TRER (0x1u << 11) /**< \brief (UDPHS_EPTCTLDIS) TX Packet Ready/Transaction Error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTLDIS) Error Flow Interrupt Disable */
+#define UDPHS_EPTCTLDIS_ERR_CRC_NTR (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) ISO CRC Error/Number of Transaction Error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTLDIS) bank flush error Interrupt Disable */
+/* -------- UDPHS_EPTCTL : (UDPHS Offset: N/A) UDPHS Endpoint Control Register -------- */
+#define UDPHS_EPTCTL_EPT_ENABL (0x1u << 0) /**< \brief (UDPHS_EPTCTL) Endpoint Enable (cleared upon USB reset) */
+#define UDPHS_EPTCTL_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTL) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset) */
+#define UDPHS_EPTCTL_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTL) Interrupt Disables DMA (cleared upon USB reset) */
+#define UDPHS_EPTCTL_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTL) NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset) */
+#define UDPHS_EPTCTL_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTL) Overflow Error Interrupt Enabled (cleared upon USB reset) */
+#define UDPHS_EPTCTL_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTCTL) Received OUT Data Interrupt Enabled (cleared upon USB reset) */
+#define UDPHS_EPTCTL_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTL) Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) */
+#define UDPHS_EPTCTL_TXRDY (0x1u << 11) /**< \brief (UDPHS_EPTCTL) TX Packet Ready Interrupt Enabled (cleared upon USB reset) */
+#define UDPHS_EPTCTL_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTL) Received SETUP Interrupt Enabled (cleared upon USB reset) */
+#define UDPHS_EPTCTL_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTL) Stall Sent Interrupt Enabled (cleared upon USB reset) */
+#define UDPHS_EPTCTL_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTL) NAKIN Interrupt Enabled (cleared upon USB reset) */
+#define UDPHS_EPTCTL_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTL) NAKOUT Interrupt Enabled (cleared upon USB reset) */
+#define UDPHS_EPTCTL_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTL) Busy Bank Interrupt Enabled (cleared upon USB reset) */
+#define UDPHS_EPTCTL_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTL) Short Packet Interrupt Enabled (cleared upon USB reset) */
+#define UDPHS_EPTCTL_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTL) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) */
+#define UDPHS_EPTCTL_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTL) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) */
+#define UDPHS_EPTCTL_TXRDY_TRER (0x1u << 11) /**< \brief (UDPHS_EPTCTL) TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset) */
+#define UDPHS_EPTCTL_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTL) Error Flow Interrupt Enabled (cleared upon USB reset) */
+#define UDPHS_EPTCTL_ERR_CRC_NTR (0x1u << 13) /**< \brief (UDPHS_EPTCTL) ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset) */
+#define UDPHS_EPTCTL_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTL) Bank Flush Error Interrupt Enabled (cleared upon USB reset) */
+/* -------- UDPHS_EPTSETSTA : (UDPHS Offset: N/A) UDPHS Endpoint Set Status Register -------- */
+#define UDPHS_EPTSETSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTSETSTA) Stall Handshake Request Set */
+#define UDPHS_EPTSETSTA_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTSETSTA) KILL Bank Set (for IN Endpoint) */
+#define UDPHS_EPTSETSTA_TXRDY (0x1u << 11) /**< \brief (UDPHS_EPTSETSTA) TX Packet Ready Set */
+#define UDPHS_EPTSETSTA_TXRDY_TRER (0x1u << 11) /**< \brief (UDPHS_EPTSETSTA) TX Packet Ready Set */
+/* -------- UDPHS_EPTCLRSTA : (UDPHS Offset: N/A) UDPHS Endpoint Clear Status Register -------- */
+#define UDPHS_EPTCLRSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTCLRSTA) Stall Handshake Request Clear */
+#define UDPHS_EPTCLRSTA_TOGGLESQ (0x1u << 6) /**< \brief (UDPHS_EPTCLRSTA) Data Toggle Clear */
+#define UDPHS_EPTCLRSTA_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTCLRSTA) Received OUT Data Clear */
+#define UDPHS_EPTCLRSTA_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCLRSTA) Transmitted IN Data Complete Clear */
+#define UDPHS_EPTCLRSTA_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCLRSTA) Received SETUP Clear */
+#define UDPHS_EPTCLRSTA_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCLRSTA) Stall Sent Clear */
+#define UDPHS_EPTCLRSTA_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCLRSTA) NAKIN Clear */
+#define UDPHS_EPTCLRSTA_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCLRSTA) NAKOUT Clear */
+#define UDPHS_EPTCLRSTA_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCLRSTA) Error Flow Clear */
+#define UDPHS_EPTCLRSTA_ERR_CRC_NTR (0x1u << 13) /**< \brief (UDPHS_EPTCLRSTA) Number of Transaction Error Clear */
+#define UDPHS_EPTCLRSTA_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCLRSTA) Bank Flush Error Clear */
+/* -------- UDPHS_EPTSTA : (UDPHS Offset: N/A) UDPHS Endpoint Status Register -------- */
+#define UDPHS_EPTSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTSTA) Stall Handshake Request (cleared upon USB reset) */
+#define UDPHS_EPTSTA_TOGGLESQ_STA_Pos 6
+#define UDPHS_EPTSTA_TOGGLESQ_STA_Msk (0x3u << UDPHS_EPTSTA_TOGGLESQ_STA_Pos) /**< \brief (UDPHS_EPTSTA) Toggle Sequencing (cleared upon USB reset) */
+#define   UDPHS_EPTSTA_TOGGLESQ_STA_DATA0 (0x0u << 6) /**< \brief (UDPHS_EPTSTA) DATA0 */
+#define   UDPHS_EPTSTA_TOGGLESQ_STA_DATA1 (0x1u << 6) /**< \brief (UDPHS_EPTSTA) DATA1 */
+#define   UDPHS_EPTSTA_TOGGLESQ_STA_DATA2 (0x2u << 6) /**< \brief (UDPHS_EPTSTA) Reserved for High Bandwidth Isochronous Endpoint */
+#define   UDPHS_EPTSTA_TOGGLESQ_STA_MDATA (0x3u << 6) /**< \brief (UDPHS_EPTSTA) Reserved for High Bandwidth Isochronous Endpoint */
+#define UDPHS_EPTSTA_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTSTA) Overflow Error (cleared upon USB reset) */
+#define UDPHS_EPTSTA_RXRDY_TXKL (0x1u << 9) /**< \brief (UDPHS_EPTSTA) Received OUT Data/KILL Bank (cleared upon USB reset) */
+#define UDPHS_EPTSTA_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTSTA) Transmitted IN Data Complete (cleared upon USB reset) */
+#define UDPHS_EPTSTA_TXRDY (0x1u << 11) /**< \brief (UDPHS_EPTSTA) TX Packet Ready (cleared upon USB reset) */
+#define UDPHS_EPTSTA_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTSTA) Received SETUP (cleared upon USB reset) */
+#define UDPHS_EPTSTA_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTSTA) Stall Sent (cleared upon USB reset) */
+#define UDPHS_EPTSTA_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTSTA) NAK IN (cleared upon USB reset) */
+#define UDPHS_EPTSTA_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTSTA) NAK OUT (cleared upon USB reset) */
+#define UDPHS_EPTSTA_CURBK_CTLDIR_Pos 16
+#define UDPHS_EPTSTA_CURBK_CTLDIR_Msk (0x3u << UDPHS_EPTSTA_CURBK_CTLDIR_Pos) /**< \brief (UDPHS_EPTSTA) Current Bank/Control Direction (cleared upon USB reset) */
+#define UDPHS_EPTSTA_BUSY_BANK_STA_Pos 18
+#define UDPHS_EPTSTA_BUSY_BANK_STA_Msk (0x3u << UDPHS_EPTSTA_BUSY_BANK_STA_Pos) /**< \brief (UDPHS_EPTSTA) Busy Bank Number (cleared upon USB reset) */
+#define   UDPHS_EPTSTA_BUSY_BANK_STA_0BUSYBANK (0x0u << 18) /**< \brief (UDPHS_EPTSTA) All banks are free */
+#define   UDPHS_EPTSTA_BUSY_BANK_STA_1BUSYBANK (0x1u << 18) /**< \brief (UDPHS_EPTSTA) 1 busy bank */
+#define   UDPHS_EPTSTA_BUSY_BANK_STA_2BUSYBANKS (0x2u << 18) /**< \brief (UDPHS_EPTSTA) 2 busy banks */
+#define   UDPHS_EPTSTA_BUSY_BANK_STA_3BUSYBANKS (0x3u << 18) /**< \brief (UDPHS_EPTSTA) 3 busy banks */
+#define UDPHS_EPTSTA_BYTE_COUNT_Pos 20
+#define UDPHS_EPTSTA_BYTE_COUNT_Msk (0x7ffu << UDPHS_EPTSTA_BYTE_COUNT_Pos) /**< \brief (UDPHS_EPTSTA) UDPHS Byte Count (cleared upon USB reset) */
+#define UDPHS_EPTSTA_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTSTA) Short Packet (cleared upon USB reset) */
+#define UDPHS_EPTSTA_TXRDY_TRER (0x1u << 11) /**< \brief (UDPHS_EPTSTA) TX Packet Ready/Transaction Error (cleared upon USB reset) */
+#define UDPHS_EPTSTA_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTSTA) Error Flow (cleared upon USB reset) */
+#define UDPHS_EPTSTA_ERR_CRC_NTR (0x1u << 13) /**< \brief (UDPHS_EPTSTA) CRC ISO Error/Number of Transaction Error (cleared upon USB reset) */
+#define UDPHS_EPTSTA_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTSTA) Bank Flush Error (cleared upon USB reset) */
+#define UDPHS_EPTSTA_CURBK_Pos 16
+#define UDPHS_EPTSTA_CURBK_Msk (0x3u << UDPHS_EPTSTA_CURBK_Pos) /**< \brief (UDPHS_EPTSTA) Current Bank (cleared upon USB reset) */
+#define   UDPHS_EPTSTA_CURBK_BANK0 (0x0u << 16) /**< \brief (UDPHS_EPTSTA) Bank 0 (or single bank) */
+#define   UDPHS_EPTSTA_CURBK_BANK1 (0x1u << 16) /**< \brief (UDPHS_EPTSTA) Bank 1 */
+#define   UDPHS_EPTSTA_CURBK_BANK2 (0x2u << 16) /**< \brief (UDPHS_EPTSTA) Bank 2 */
+/* -------- UDPHS_DMANXTDSC : (UDPHS Offset: N/A) UDPHS DMA Next Descriptor Address Register -------- */
+#define UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos 0
+#define UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UDPHS_DMANXTDSC) Next Descriptor Address */
+#define UDPHS_DMANXTDSC_NXT_DSC_ADD(value) ((UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos)))
+/* -------- UDPHS_DMAADDRESS : (UDPHS Offset: N/A) UDPHS DMA Channel Address Register -------- */
+#define UDPHS_DMAADDRESS_BUFF_ADD_Pos 0
+#define UDPHS_DMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UDPHS_DMAADDRESS_BUFF_ADD_Pos) /**< \brief (UDPHS_DMAADDRESS) Buffer Address */
+#define UDPHS_DMAADDRESS_BUFF_ADD(value) ((UDPHS_DMAADDRESS_BUFF_ADD_Msk & ((value) << UDPHS_DMAADDRESS_BUFF_ADD_Pos)))
+/* -------- UDPHS_DMACONTROL : (UDPHS Offset: N/A) UDPHS DMA Channel Control Register -------- */
+#define UDPHS_DMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UDPHS_DMACONTROL) (Channel Enable Command) */
+#define UDPHS_DMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UDPHS_DMACONTROL) Load Next Channel Transfer Descriptor Enable (Command) */
+#define UDPHS_DMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UDPHS_DMACONTROL) End of Transfer Enable (Control) */
+#define UDPHS_DMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UDPHS_DMACONTROL) End of Buffer Enable (Control) */
+#define UDPHS_DMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UDPHS_DMACONTROL) End of Transfer Interrupt Enable */
+#define UDPHS_DMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UDPHS_DMACONTROL) End of Buffer Interrupt Enable */
+#define UDPHS_DMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UDPHS_DMACONTROL) Descriptor Loaded Interrupt Enable */
+#define UDPHS_DMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UDPHS_DMACONTROL) Burst Lock Enable */
+#define UDPHS_DMACONTROL_BUFF_LENGTH_Pos 16
+#define UDPHS_DMACONTROL_BUFF_LENGTH_Msk (0xffffu << UDPHS_DMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UDPHS_DMACONTROL) Buffer Byte Length (Write-only) */
+#define UDPHS_DMACONTROL_BUFF_LENGTH(value) ((UDPHS_DMACONTROL_BUFF_LENGTH_Msk & ((value) << UDPHS_DMACONTROL_BUFF_LENGTH_Pos)))
+/* -------- UDPHS_DMASTATUS : (UDPHS Offset: N/A) UDPHS DMA Channel Status Register -------- */
+#define UDPHS_DMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UDPHS_DMASTATUS) Channel Enable Status */
+#define UDPHS_DMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UDPHS_DMASTATUS) Channel Active Status */
+#define UDPHS_DMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UDPHS_DMASTATUS) End of Channel Transfer Status */
+#define UDPHS_DMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UDPHS_DMASTATUS) End of Channel Buffer Status */
+#define UDPHS_DMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UDPHS_DMASTATUS) Descriptor Loaded Status */
+#define UDPHS_DMASTATUS_BUFF_COUNT_Pos 16
+#define UDPHS_DMASTATUS_BUFF_COUNT_Msk (0xffffu << UDPHS_DMASTATUS_BUFF_COUNT_Pos) /**< \brief (UDPHS_DMASTATUS) Buffer Byte Count */
+#define UDPHS_DMASTATUS_BUFF_COUNT(value) ((UDPHS_DMASTATUS_BUFF_COUNT_Msk & ((value) << UDPHS_DMASTATUS_BUFF_COUNT_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_UDPHS_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_usart.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_usart.h
new file mode 100644
index 000000000..60712fd40
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_usart.h
@@ -0,0 +1,468 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_USART_COMPONENT_
+#define _SAMA5D2_USART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_USART Universal Synchronous Asynchronous Receiver Transmitter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+
+/** \brief Usart hardware registers */
+typedef struct {
+	__O  uint32_t US_CR;       /**< \brief (Usart Offset: 0x0000) Control Register */
+	__IO uint32_t US_MR;       /**< \brief (Usart Offset: 0x0004) Mode Register */
+	__O  uint32_t US_IER;      /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
+	__O  uint32_t US_IDR;      /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
+	__I  uint32_t US_IMR;      /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
+	__I  uint32_t US_CSR;      /**< \brief (Usart Offset: 0x0014) Channel Status Register */
+	__I  uint32_t US_RHR;      /**< \brief (Usart Offset: 0x0018) Receive Holding Register */
+	__O  uint32_t US_THR;      /**< \brief (Usart Offset: 0x001C) Transmit Holding Register */
+	__IO uint32_t US_BRGR;     /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
+	__IO uint32_t US_RTOR;     /**< \brief (Usart Offset: 0x0024) Receiver Timeout Register */
+	__IO uint32_t US_TTGR;     /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
+	__I  uint32_t Reserved1[5];
+	__IO uint32_t US_FIDI;     /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
+	__I  uint32_t US_NER;      /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
+	__I  uint32_t Reserved2[1];
+	__IO uint32_t US_IF;       /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
+	__IO uint32_t US_MAN;      /**< \brief (Usart Offset: 0x0050) Manchester Configuration Register */
+	__IO uint32_t US_LINMR;    /**< \brief (Usart Offset: 0x0054) LIN Mode Register */
+	__IO uint32_t US_LINIR;    /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */
+	__I  uint32_t US_LINBRR;   /**< \brief (Usart Offset: 0x005C) LIN Baud Rate Register */
+	__I  uint32_t Reserved3[12];
+	__IO uint32_t US_CMPR;     /**< \brief (Usart Offset: 0x0090) Comparison Register */
+	__I  uint32_t Reserved4[3];
+	__IO uint32_t US_FMR;      /**< \brief (Usart Offset: 0x00A0) FIFO Mode Register */
+	__I  uint32_t US_FLR;      /**< \brief (Usart Offset: 0x00A4) FIFO Level Register */
+	__O  uint32_t US_FIER;     /**< \brief (Usart Offset: 0x00A8) FIFO Interrupt Enable Register */
+	__O  uint32_t US_FIDR;     /**< \brief (Usart Offset: 0x00AC) FIFO Interrupt Disable Register */
+	__I  uint32_t US_FIMR;     /**< \brief (Usart Offset: 0x00B0) FIFO Interrupt Mask Register */
+	__I  uint32_t US_FESR;     /**< \brief (Usart Offset: 0x00B4) FIFO Event Status Register */
+	__I  uint32_t Reserved5[11];
+	__IO uint32_t US_WPMR;     /**< \brief (Usart Offset: 0x00E4) Write Protection Mode Register */
+	__I  uint32_t US_WPSR;     /**< \brief (Usart Offset: 0x00E8) Write Protection Status Register */
+} Usart;
+
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Clear TIMEOUT Flag and Start Time-out After Next Character Received */
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Start Time-out Immediately */
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
+#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */
+#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wake-up Signal */
+#define US_CR_TXFCLR (0x1u << 24) /**< \brief (US_CR) Transmit FIFO Clear */
+#define US_CR_RXFCLR (0x1u << 25) /**< \brief (US_CR) Receive FIFO Clear */
+#define US_CR_TXFLCLR (0x1u << 26) /**< \brief (US_CR) Transmit FIFO Lock CLEAR */
+#define US_CR_REQCLR (0x1u << 28) /**< \brief (US_CR) Request to Clear the Comparison Trigger */
+#define US_CR_FIFOEN (0x1u << 30) /**< \brief (US_CR) FIFO Enable */
+#define US_CR_FIFODIS (0x1u << 31) /**< \brief (US_CR) FIFO Disable */
+/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
+#define US_MR_USART_MODE_Pos 0
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */
+#define US_MR_USART_MODE(value) ((US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos)))
+#define   US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
+#define   US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
+#define   US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
+#define   US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
+#define   US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
+#define   US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */
+#define   US_MR_USART_MODE_LIN_MASTER (0xAu << 0) /**< \brief (US_MR) LIN master */
+#define   US_MR_USART_MODE_LIN_SLAVE (0xBu << 0) /**< \brief (US_MR) LIN Slave */
+#define US_MR_USCLKS_Pos 4
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
+#define US_MR_USCLKS(value) ((US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos)))
+#define   US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Peripheral clock is selected */
+#define   US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Peripheral clock divided (DIV = 8) is selected */
+#define   US_MR_USCLKS_PMC_PCK (0x2u << 4) /**< \brief (US_MR) PMC programmable clock is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. */
+#define   US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) External pin SCK is selected */
+#define US_MR_CHRL_Pos 6
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length */
+#define US_MR_CHRL(value) ((US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos)))
+#define   US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
+#define   US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
+#define   US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
+#define   US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
+#define US_MR_PAR_Pos 9
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
+#define US_MR_PAR(value) ((US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos)))
+#define   US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
+#define   US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
+#define   US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
+#define   US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
+#define   US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
+#define   US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
+#define US_MR_NBSTOP_Pos 12
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
+#define US_MR_NBSTOP(value) ((US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos)))
+#define   US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
+#define   US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
+#define   US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
+#define US_MR_CHMODE_Pos 14
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
+#define US_MR_CHMODE(value) ((US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos)))
+#define   US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal mode */
+#define   US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
+#define   US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
+#define   US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
+#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) Inverted Data */
+#define US_MR_MAX_ITERATION_Pos 24
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Maximum Number of Automatic Iteration */
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Receive Line Filter */
+#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
+#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */
+#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
+/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Timeout Interrupt Enable */
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached Interrupt Enable */
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
+#define US_IER_CMP (0x1u << 22) /**< \brief (US_IER) Comparison Interrupt Enable */
+#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
+#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */
+#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */
+#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */
+#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */
+#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */
+#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */
+#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */
+#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */
+#define US_IER_LINSTE (0x1u << 30) /**< \brief (US_IER) LIN Synch Tolerance Error Interrupt Enable */
+#define US_IER_LINHTE (0x1u << 31) /**< \brief (US_IER) LIN Header Timeout Error Interrupt Enable */
+/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Timeout Interrupt Disable */
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max Number of Repetitions Reached Interrupt Disable */
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
+#define US_IDR_CMP (0x1u << 22) /**< \brief (US_IDR) Comparison Interrupt Disable */
+#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
+#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */
+#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */
+#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */
+#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */
+#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */
+#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */
+#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */
+#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */
+#define US_IDR_LINSTE (0x1u << 30) /**< \brief (US_IDR) LIN Synch Tolerance Error Interrupt Disable */
+#define US_IDR_LINHTE (0x1u << 31) /**< \brief (US_IDR) LIN Header Timeout Error Interrupt Disable */
+/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Timeout Interrupt Mask */
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max Number of Repetitions Reached Interrupt Mask */
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
+#define US_IMR_CMP (0x1u << 22) /**< \brief (US_IMR) Comparison Interrupt Mask */
+#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
+#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */
+#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */
+#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */
+#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */
+#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */
+#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */
+#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */
+#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */
+#define US_IMR_LINSTE (0x1u << 30) /**< \brief (US_IMR) LIN Synch Tolerance Error Interrupt Mask */
+#define US_IMR_LINHTE (0x1u << 31) /**< \brief (US_IMR) LIN Header Timeout Error Interrupt Mask */
+/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready (cleared by reading US_RHR) */
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready (cleared by writing US_THR) */
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Timeout */
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty (cleared by writing US_THR) */
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max Number of Repetitions Reached */
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge Interrupt */
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
+#define US_CSR_CMP (0x1u << 22) /**< \brief (US_CSR) Comparison Status */
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
+#define US_CSR_MANE (0x1u << 24) /**< \brief (US_CSR) Manchester Error */
+#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received */
+#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received */
+#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed */
+#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */
+#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error */
+#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error */
+#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error */
+#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error */
+#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error */
+#define US_CSR_LINSTE (0x1u << 30) /**< \brief (US_CSR) LIN Synch Tolerance Error */
+#define US_CSR_LINHTE (0x1u << 31) /**< \brief (US_CSR) LIN Header Timeout Error */
+/* -------- US_RHR : (USART Offset: 0x0018) Receive Holding Register -------- */
+#define US_RHR_RXCHR_Pos 0
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
+#define US_RHR_RXCHR0_Pos 0
+#define US_RHR_RXCHR0_Msk (0xffu << US_RHR_RXCHR0_Pos) /**< \brief (US_RHR) Received Character */
+#define US_RHR_RXCHR1_Pos 8
+#define US_RHR_RXCHR1_Msk (0xffu << US_RHR_RXCHR1_Pos) /**< \brief (US_RHR) Received Character */
+#define US_RHR_RXCHR2_Pos 16
+#define US_RHR_RXCHR2_Msk (0xffu << US_RHR_RXCHR2_Pos) /**< \brief (US_RHR) Received Character */
+#define US_RHR_RXCHR3_Pos 24
+#define US_RHR_RXCHR3_Msk (0xffu << US_RHR_RXCHR3_Pos) /**< \brief (US_RHR) Received Character */
+/* -------- US_THR : (USART Offset: 0x001C) Transmit Holding Register -------- */
+#define US_THR_TXCHR_Pos 0
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */
+#define US_THR_TXCHR0_Pos 0
+#define US_THR_TXCHR0_Msk (0xffu << US_THR_TXCHR0_Pos) /**< \brief (US_THR) Character to be Transmitted */
+#define US_THR_TXCHR0(value) ((US_THR_TXCHR0_Msk & ((value) << US_THR_TXCHR0_Pos)))
+#define US_THR_TXCHR1_Pos 8
+#define US_THR_TXCHR1_Msk (0xffu << US_THR_TXCHR1_Pos) /**< \brief (US_THR) Character to be Transmitted */
+#define US_THR_TXCHR1(value) ((US_THR_TXCHR1_Msk & ((value) << US_THR_TXCHR1_Pos)))
+#define US_THR_TXCHR2_Pos 16
+#define US_THR_TXCHR2_Msk (0xffu << US_THR_TXCHR2_Pos) /**< \brief (US_THR) Character to be Transmitted */
+#define US_THR_TXCHR2(value) ((US_THR_TXCHR2_Msk & ((value) << US_THR_TXCHR2_Pos)))
+#define US_THR_TXCHR3_Pos 24
+#define US_THR_TXCHR3_Msk (0xffu << US_THR_TXCHR3_Pos) /**< \brief (US_THR) Character to be Transmitted */
+#define US_THR_TXCHR3(value) ((US_THR_TXCHR3_Msk & ((value) << US_THR_TXCHR3_Pos)))
+/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define US_BRGR_CD_Pos 0
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
+#define US_BRGR_FP_Pos 16
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
+/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Timeout Register -------- */
+#define US_RTOR_TO_Pos 0
+#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Timeout Value */
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
+/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
+#define US_TTGR_TG_Pos 0
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
+/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
+#define US_FIDI_FI_DI_RATIO_Pos 0
+#define US_FIDI_FI_DI_RATIO_Msk (0xffffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
+/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
+#define US_NER_NB_ERRORS_Pos 0
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
+/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
+#define US_IF_IRDA_FILTER_Pos 0
+#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */
+#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
+/* -------- US_MAN : (USART Offset: 0x0050) Manchester Configuration Register -------- */
+#define US_MAN_TX_PL_Pos 0
+#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */
+#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
+#define US_MAN_TX_PP_Pos 8
+#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */
+#define US_MAN_TX_PP(value) ((US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos)))
+#define   US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
+#define US_MAN_RX_PL_Pos 16
+#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */
+#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
+#define US_MAN_RX_PP_Pos 24
+#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
+#define US_MAN_RX_PP(value) ((US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos)))
+#define   US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
+#define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */
+#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift Compensation */
+#define US_MAN_RXIDLEV (0x1u << 31) /**< \brief (US_MAN) Receiver Idle Value */
+/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */
+#define US_LINMR_NACT_Pos 0
+#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */
+#define US_LINMR_NACT(value) ((US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos)))
+#define   US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */
+#define   US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */
+#define   US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */
+#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */
+#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */
+#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */
+#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */
+#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */
+#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wake-up Signal Type */
+#define US_LINMR_DLC_Pos 8
+#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */
+#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos)))
+#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) DMAC Mode */
+#define US_LINMR_SYNCDIS (0x1u << 17) /**< \brief (US_LINMR) Synchronization Disable */
+/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */
+#define US_LINIR_IDCHR_Pos 0
+#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */
+#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos)))
+/* -------- US_LINBRR : (USART Offset: 0x005C) LIN Baud Rate Register -------- */
+#define US_LINBRR_LINCD_Pos 0
+#define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos) /**< \brief (US_LINBRR) Clock Divider after Synchronization */
+#define US_LINBRR_LINFP_Pos 16
+#define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos) /**< \brief (US_LINBRR) Fractional Part after Synchronization */
+/* -------- US_CMPR : (USART Offset: 0x0090) Comparison Register -------- */
+#define US_CMPR_VAL1_Pos 0
+#define US_CMPR_VAL1_Msk (0x1ffu << US_CMPR_VAL1_Pos) /**< \brief (US_CMPR) First Comparison Value for Received Character */
+#define US_CMPR_VAL1(value) ((US_CMPR_VAL1_Msk & ((value) << US_CMPR_VAL1_Pos)))
+#define US_CMPR_CMPMODE (0x1u << 12) /**< \brief (US_CMPR) Comparison Mode */
+#define   US_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (US_CMPR) Any character is received and comparison function drives CMP flag. */
+#define   US_CMPR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (US_CMPR) Comparison condition must be met to start reception. */
+#define US_CMPR_CMPPAR (0x1u << 14) /**< \brief (US_CMPR) Compare Parity */
+#define US_CMPR_VAL2_Pos 16
+#define US_CMPR_VAL2_Msk (0x1ffu << US_CMPR_VAL2_Pos) /**< \brief (US_CMPR) Second Comparison Value for Received Character */
+#define US_CMPR_VAL2(value) ((US_CMPR_VAL2_Msk & ((value) << US_CMPR_VAL2_Pos)))
+/* -------- US_FMR : (USART Offset: 0x00A0) FIFO Mode Register -------- */
+#define US_FMR_TXRDYM_Pos 0
+#define US_FMR_TXRDYM_Msk (0x3u << US_FMR_TXRDYM_Pos) /**< \brief (US_FMR) Transmitter Ready Mode */
+#define US_FMR_TXRDYM(value) ((US_FMR_TXRDYM_Msk & ((value) << US_FMR_TXRDYM_Pos)))
+#define   US_FMR_TXRDYM_ONE_DATA (0x0u << 0) /**< \brief (US_FMR) TXRDY will be at level '1' when at least one data can be written in the Transmit FIFO */
+#define   US_FMR_TXRDYM_TWO_DATA (0x1u << 0) /**< \brief (US_FMR) TXRDY will be at level '1' when at least two data can be written in the Transmit FIFO */
+#define   US_FMR_TXRDYM_FOUR_DATA (0x2u << 0) /**< \brief (US_FMR) TXRDY will be at level '1' when at least four data can be written in the Transmit FIFO */
+#define US_FMR_RXRDYM_Pos 4
+#define US_FMR_RXRDYM_Msk (0x3u << US_FMR_RXRDYM_Pos) /**< \brief (US_FMR) Receiver Ready Mode */
+#define US_FMR_RXRDYM(value) ((US_FMR_RXRDYM_Msk & ((value) << US_FMR_RXRDYM_Pos)))
+#define   US_FMR_RXRDYM_ONE_DATA (0x0u << 4) /**< \brief (US_FMR) RXRDY will be at level '1' when at least one unread data is in the Receive FIFO */
+#define   US_FMR_RXRDYM_TWO_DATA (0x1u << 4) /**< \brief (US_FMR) RXRDY will be at level '1' when at least two unread data are in the Receive FIFO */
+#define   US_FMR_RXRDYM_FOUR_DATA (0x2u << 4) /**< \brief (US_FMR) RXRDY will be at level '1' when at least four unread data are in the Receive FIFO */
+#define US_FMR_FRTSC (0x1u << 7) /**< \brief (US_FMR) FIFO RTS pin Control enable (Hardware Handshaking mode only) */
+#define US_FMR_TXFTHRES_Pos 8
+#define US_FMR_TXFTHRES_Msk (0x3fu << US_FMR_TXFTHRES_Pos) /**< \brief (US_FMR) Transmit FIFO Threshold */
+#define US_FMR_TXFTHRES(value) ((US_FMR_TXFTHRES_Msk & ((value) << US_FMR_TXFTHRES_Pos)))
+#define US_FMR_RXFTHRES_Pos 16
+#define US_FMR_RXFTHRES_Msk (0x3fu << US_FMR_RXFTHRES_Pos) /**< \brief (US_FMR) Receive FIFO Threshold */
+#define US_FMR_RXFTHRES(value) ((US_FMR_RXFTHRES_Msk & ((value) << US_FMR_RXFTHRES_Pos)))
+#define US_FMR_RXFTHRES2_Pos 24
+#define US_FMR_RXFTHRES2_Msk (0x3fu << US_FMR_RXFTHRES2_Pos) /**< \brief (US_FMR) Receive FIFO Threshold 2 */
+#define US_FMR_RXFTHRES2(value) ((US_FMR_RXFTHRES2_Msk & ((value) << US_FMR_RXFTHRES2_Pos)))
+/* -------- US_FLR : (USART Offset: 0x00A4) FIFO Level Register -------- */
+#define US_FLR_TXFL_Pos 0
+#define US_FLR_TXFL_Msk (0x3fu << US_FLR_TXFL_Pos) /**< \brief (US_FLR) Transmit FIFO Level */
+#define US_FLR_RXFL_Pos 16
+#define US_FLR_RXFL_Msk (0x3fu << US_FLR_RXFL_Pos) /**< \brief (US_FLR) Receive FIFO Level */
+/* -------- US_FIER : (USART Offset: 0x00A8) FIFO Interrupt Enable Register -------- */
+#define US_FIER_TXFEF (0x1u << 0) /**< \brief (US_FIER) TXFEF Interrupt Enable */
+#define US_FIER_TXFFF (0x1u << 1) /**< \brief (US_FIER) TXFFF Interrupt Enable */
+#define US_FIER_TXFTHF (0x1u << 2) /**< \brief (US_FIER) TXFTHF Interrupt Enable */
+#define US_FIER_RXFEF (0x1u << 3) /**< \brief (US_FIER) RXFEF Interrupt Enable */
+#define US_FIER_RXFFF (0x1u << 4) /**< \brief (US_FIER) RXFFF Interrupt Enable */
+#define US_FIER_RXFTHF (0x1u << 5) /**< \brief (US_FIER) RXFTHF Interrupt Enable */
+#define US_FIER_TXFPTEF (0x1u << 6) /**< \brief (US_FIER) TXFPTEF Interrupt Enable */
+#define US_FIER_RXFPTEF (0x1u << 7) /**< \brief (US_FIER) RXFPTEF Interrupt Enable */
+#define US_FIER_RXFTHF2 (0x1u << 9) /**< \brief (US_FIER) RXFTHF2 Interrupt Enable */
+/* -------- US_FIDR : (USART Offset: 0x00AC) FIFO Interrupt Disable Register -------- */
+#define US_FIDR_TXFEF (0x1u << 0) /**< \brief (US_FIDR) TXFEF Interrupt Disable */
+#define US_FIDR_TXFFF (0x1u << 1) /**< \brief (US_FIDR) TXFFF Interrupt Disable */
+#define US_FIDR_TXFTHF (0x1u << 2) /**< \brief (US_FIDR) TXFTHF Interrupt Disable */
+#define US_FIDR_RXFEF (0x1u << 3) /**< \brief (US_FIDR) RXFEF Interrupt Disable */
+#define US_FIDR_RXFFF (0x1u << 4) /**< \brief (US_FIDR) RXFFF Interrupt Disable */
+#define US_FIDR_RXFTHF (0x1u << 5) /**< \brief (US_FIDR) RXFTHF Interrupt Disable */
+#define US_FIDR_TXFPTEF (0x1u << 6) /**< \brief (US_FIDR) TXFPTEF Interrupt Disable */
+#define US_FIDR_RXFPTEF (0x1u << 7) /**< \brief (US_FIDR) RXFPTEF Interrupt Disable */
+#define US_FIDR_RXFTHF2 (0x1u << 9) /**< \brief (US_FIDR) RXFTHF2 Interrupt Disable */
+/* -------- US_FIMR : (USART Offset: 0x00B0) FIFO Interrupt Mask Register -------- */
+#define US_FIMR_TXFEF (0x1u << 0) /**< \brief (US_FIMR) TXFEF Interrupt Mask */
+#define US_FIMR_TXFFF (0x1u << 1) /**< \brief (US_FIMR) TXFFF Interrupt Mask */
+#define US_FIMR_TXFTHF (0x1u << 2) /**< \brief (US_FIMR) TXFTHF Interrupt Mask */
+#define US_FIMR_RXFEF (0x1u << 3) /**< \brief (US_FIMR) RXFEF Interrupt Mask */
+#define US_FIMR_RXFFF (0x1u << 4) /**< \brief (US_FIMR) RXFFF Interrupt Mask */
+#define US_FIMR_RXFTHF (0x1u << 5) /**< \brief (US_FIMR) RXFTHF Interrupt Mask */
+#define US_FIMR_TXFPTEF (0x1u << 6) /**< \brief (US_FIMR) TXFPTEF Interrupt Mask */
+#define US_FIMR_RXFPTEF (0x1u << 7) /**< \brief (US_FIMR) RXFPTEF Interrupt Mask */
+#define US_FIMR_RXFTHF2 (0x1u << 9) /**< \brief (US_FIMR) RXFTHF2 Interrupt Mask */
+/* -------- US_FESR : (USART Offset: 0x00B4) FIFO Event Status Register -------- */
+#define US_FESR_TXFEF (0x1u << 0) /**< \brief (US_FESR) Transmit FIFO Empty Flag (cleared by writing RSTSTA bit in US_CR) */
+#define US_FESR_TXFFF (0x1u << 1) /**< \brief (US_FESR) Transmit FIFO Full Flag (cleared by writing RSTSTA bit in US_CR) */
+#define US_FESR_TXFTHF (0x1u << 2) /**< \brief (US_FESR) Transmit FIFO Threshold Flag (cleared by writing RSTSTA bit in US_CR) */
+#define US_FESR_RXFEF (0x1u << 3) /**< \brief (US_FESR) Receive FIFO Empty Flag (cleared by writing RSTSTA bit in US_CR) */
+#define US_FESR_RXFFF (0x1u << 4) /**< \brief (US_FESR) Receive FIFO Full Flag (cleared by writing RSTSTA bit in US_CR) */
+#define US_FESR_RXFTHF (0x1u << 5) /**< \brief (US_FESR) Receive FIFO Threshold Flag (cleared by writing RSTSTA bit in US_CR) */
+#define US_FESR_TXFPTEF (0x1u << 6) /**< \brief (US_FESR) Transmit FIFO Pointer Error Flag */
+#define US_FESR_RXFPTEF (0x1u << 7) /**< \brief (US_FESR) Receive FIFO Pointer Error Flag */
+#define US_FESR_TXFLOCK (0x1u << 8) /**< \brief (US_FESR) Transmit FIFO Lock */
+#define US_FESR_RXFTHF2 (0x1u << 9) /**< \brief (US_FESR) Receive FIFO Threshold Flag 2 (cleared by writing RSTSTA bit in US_CR) */
+/* -------- US_WPMR : (USART Offset: 0x00E4) Write Protection Mode Register -------- */
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protection Enable */
+#define US_WPMR_WPKEY_Pos 8
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protection Key */
+#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
+#define   US_WPMR_WPKEY_PASSWD (0x555341u << 8) /**< \brief (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
+/* -------- US_WPSR : (USART Offset: 0x00E8) Write Protection Status Register -------- */
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protection Violation Status */
+#define US_WPSR_WPVSRC_Pos 8
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protection Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_USART_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_wdt.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_wdt.h
new file mode 100644
index 000000000..968302732
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_wdt.h
@@ -0,0 +1,74 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_WDT_COMPONENT_
+#define _SAMA5D2_WDT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Watchdog Timer */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_WDT Watchdog Timer */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Wdt hardware registers */
+typedef struct {
+  __O  uint32_t WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
+  __IO uint32_t WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
+  __I  uint32_t WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
+} Wdt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
+#define WDT_CR_LOCKMR (0x1u << 4) /**< \brief (WDT_CR) Lock Mode Register Write Access */
+#define WDT_CR_KEY_Pos 24
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
+#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
+#define   WDT_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (WDT_CR) Writing any other value in this field aborts the write operation. */
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
+#define WDT_MR_WDV_Pos 0
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
+#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
+#define WDT_MR_WDD_Pos 16
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow (cleared on read) */
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error (cleared on read) */
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_WDT_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_xdmac.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_xdmac.h
new file mode 100644
index 000000000..9629ca389
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/component/component_xdmac.h
@@ -0,0 +1,489 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D2_XDMAC_COMPONENT_
+#define _SAMA5D2_XDMAC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Extensible DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAMA5D2_XDMAC Extensible DMA Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief XdmacChid hardware registers */
+typedef struct {
+  __O  uint32_t XDMAC_CIE;     /**< \brief (XdmacChid Offset: 0x0) Channel Interrupt Enable Register */
+  __O  uint32_t XDMAC_CID;     /**< \brief (XdmacChid Offset: 0x4) Channel Interrupt Disable Register */
+  __O  uint32_t XDMAC_CIM;     /**< \brief (XdmacChid Offset: 0x8) Channel Interrupt Mask Register */
+  __I  uint32_t XDMAC_CIS;     /**< \brief (XdmacChid Offset: 0xC) Channel Interrupt Status Register */
+  __IO uint32_t XDMAC_CSA;     /**< \brief (XdmacChid Offset: 0x10) Channel Source Address Register */
+  __IO uint32_t XDMAC_CDA;     /**< \brief (XdmacChid Offset: 0x14) Channel Destination Address Register */
+  __IO uint32_t XDMAC_CNDA;    /**< \brief (XdmacChid Offset: 0x18) Channel Next Descriptor Address Register */
+  __IO uint32_t XDMAC_CNDC;    /**< \brief (XdmacChid Offset: 0x1C) Channel Next Descriptor Control Register */
+  __IO uint32_t XDMAC_CUBC;    /**< \brief (XdmacChid Offset: 0x20) Channel Microblock Control Register */
+  __IO uint32_t XDMAC_CBC;     /**< \brief (XdmacChid Offset: 0x24) Channel Block Control Register */
+  __IO uint32_t XDMAC_CC;      /**< \brief (XdmacChid Offset: 0x28) Channel Configuration Register */
+  __IO uint32_t XDMAC_CDS_MSP; /**< \brief (XdmacChid Offset: 0x2C) Channel Data Stride Memory Set Pattern */
+  __IO uint32_t XDMAC_CSUS;    /**< \brief (XdmacChid Offset: 0x30) Channel Source Microblock Stride */
+  __IO uint32_t XDMAC_CDUS;    /**< \brief (XdmacChid Offset: 0x34) Channel Destination Microblock Stride */
+  __I  uint32_t Reserved1[2];
+} XdmacChid;
+/** \brief Xdmac hardware registers */
+#define XDMACCHID_NUMBER 16
+typedef struct {
+  __IO uint32_t  XDMAC_GTYPE;                  /**< \brief (Xdmac Offset: 0x00) Global Type Register */
+  __I  uint32_t  XDMAC_GCFG;                   /**< \brief (Xdmac Offset: 0x04) Global Configuration Register */
+  __IO uint32_t  XDMAC_GWAC;                   /**< \brief (Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register */
+  __O  uint32_t  XDMAC_GIE;                    /**< \brief (Xdmac Offset: 0x0C) Global Interrupt Enable Register */
+  __O  uint32_t  XDMAC_GID;                    /**< \brief (Xdmac Offset: 0x10) Global Interrupt Disable Register */
+  __I  uint32_t  XDMAC_GIM;                    /**< \brief (Xdmac Offset: 0x14) Global Interrupt Mask Register */
+  __I  uint32_t  XDMAC_GIS;                    /**< \brief (Xdmac Offset: 0x18) Global Interrupt Status Register */
+  __O  uint32_t  XDMAC_GE;                     /**< \brief (Xdmac Offset: 0x1C) Global Channel Enable Register */
+  __O  uint32_t  XDMAC_GD;                     /**< \brief (Xdmac Offset: 0x20) Global Channel Disable Register */
+  __I  uint32_t  XDMAC_GS;                     /**< \brief (Xdmac Offset: 0x24) Global Channel Status Register */
+  __IO uint32_t  XDMAC_GRS;                    /**< \brief (Xdmac Offset: 0x28) Global Channel Read Suspend Register */
+  __IO uint32_t  XDMAC_GWS;                    /**< \brief (Xdmac Offset: 0x2C) Global Channel Write Suspend Register */
+  __O  uint32_t  XDMAC_GRWS;                   /**< \brief (Xdmac Offset: 0x30) Global Channel Read Write Suspend Register */
+  __O  uint32_t  XDMAC_GRWR;                   /**< \brief (Xdmac Offset: 0x34) Global Channel Read Write Resume Register */
+  __O  uint32_t  XDMAC_GSWR;                   /**< \brief (Xdmac Offset: 0x38) Global Channel Software Request Register */
+  __I  uint32_t  XDMAC_GSWS;                   /**< \brief (Xdmac Offset: 0x3C) Global Channel Software Request Status Register */
+  __O  uint32_t  XDMAC_GSWF;                   /**< \brief (Xdmac Offset: 0x40) Global Channel Software Flush Request Register */
+  __I  uint32_t  Reserved1[3];
+       XdmacChid XDMAC_CHID[XDMACCHID_NUMBER]; /**< \brief (Xdmac Offset: 0x50) chid = 0 .. 15 */
+  __I  uint32_t  Reserved2[747];
+  __IO uint32_t  XDMAC_VERSION;                /**< \brief (Xdmac Offset: 0xFFC) XDMAC Version Register */
+} Xdmac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) Global Type Register -------- */
+#define XDMAC_GTYPE_NB_CH_Pos 0
+#define XDMAC_GTYPE_NB_CH_Msk (0x1fu << XDMAC_GTYPE_NB_CH_Pos) /**< \brief (XDMAC_GTYPE) Number of Channels Minus One */
+#define XDMAC_GTYPE_NB_CH(value) ((XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos)))
+#define XDMAC_GTYPE_FIFO_SZ_Pos 5
+#define XDMAC_GTYPE_FIFO_SZ_Msk (0x7ffu << XDMAC_GTYPE_FIFO_SZ_Pos) /**< \brief (XDMAC_GTYPE) Number of Bytes */
+#define XDMAC_GTYPE_FIFO_SZ(value) ((XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos)))
+#define XDMAC_GTYPE_NB_REQ_Pos 16
+#define XDMAC_GTYPE_NB_REQ_Msk (0x7fu << XDMAC_GTYPE_NB_REQ_Pos) /**< \brief (XDMAC_GTYPE) Number of Peripheral Requests Minus One */
+#define XDMAC_GTYPE_NB_REQ(value) ((XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos)))
+/* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) Global Configuration Register -------- */
+#define XDMAC_GCFG_CGDISREG (0x1u << 0) /**< \brief (XDMAC_GCFG) Configuration Registers Clock Gating Disable */
+#define XDMAC_GCFG_CGDISPIPE (0x1u << 1) /**< \brief (XDMAC_GCFG) Pipeline Clock Gating Disable */
+#define XDMAC_GCFG_CGDISFIFO (0x1u << 2) /**< \brief (XDMAC_GCFG) FIFO Clock Gating Disable */
+#define XDMAC_GCFG_CGDISIF (0x1u << 3) /**< \brief (XDMAC_GCFG) Bus Interface Clock Gating Disable */
+#define XDMAC_GCFG_BXKBEN (0x1u << 8) /**< \brief (XDMAC_GCFG) Boundary X Kilobyte Enable */
+/* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) Global Weighted Arbiter Configuration Register -------- */
+#define XDMAC_GWAC_PW0_Pos 0
+#define XDMAC_GWAC_PW0_Msk (0xfu << XDMAC_GWAC_PW0_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 0 */
+#define XDMAC_GWAC_PW0(value) ((XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos)))
+#define XDMAC_GWAC_PW1_Pos 4
+#define XDMAC_GWAC_PW1_Msk (0xfu << XDMAC_GWAC_PW1_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 1 */
+#define XDMAC_GWAC_PW1(value) ((XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos)))
+#define XDMAC_GWAC_PW2_Pos 8
+#define XDMAC_GWAC_PW2_Msk (0xfu << XDMAC_GWAC_PW2_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 2 */
+#define XDMAC_GWAC_PW2(value) ((XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos)))
+#define XDMAC_GWAC_PW3_Pos 12
+#define XDMAC_GWAC_PW3_Msk (0xfu << XDMAC_GWAC_PW3_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 3 */
+#define XDMAC_GWAC_PW3(value) ((XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos)))
+/* -------- XDMAC_GIE : (XDMAC Offset: 0x0C) Global Interrupt Enable Register -------- */
+#define XDMAC_GIE_IE0 (0x1u << 0) /**< \brief (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit */
+#define XDMAC_GIE_IE1 (0x1u << 1) /**< \brief (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit */
+#define XDMAC_GIE_IE4 (0x1u << 4) /**< \brief (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit */
+#define XDMAC_GIE_IE5 (0x1u << 5) /**< \brief (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit */
+#define XDMAC_GIE_IE6 (0x1u << 6) /**< \brief (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit */
+#define XDMAC_GIE_IE7 (0x1u << 7) /**< \brief (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit */
+#define XDMAC_GIE_IE8 (0x1u << 8) /**< \brief (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit */
+#define XDMAC_GIE_IE9 (0x1u << 9) /**< \brief (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit */
+#define XDMAC_GIE_IE10 (0x1u << 10) /**< \brief (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit */
+#define XDMAC_GIE_IE11 (0x1u << 11) /**< \brief (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit */
+#define XDMAC_GIE_IE12 (0x1u << 12) /**< \brief (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit */
+#define XDMAC_GIE_IE13 (0x1u << 13) /**< \brief (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit */
+#define XDMAC_GIE_IE14 (0x1u << 14) /**< \brief (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit */
+#define XDMAC_GIE_IE15 (0x1u << 15) /**< \brief (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit */
+/* -------- XDMAC_GID : (XDMAC Offset: 0x10) Global Interrupt Disable Register -------- */
+#define XDMAC_GID_ID0 (0x1u << 0) /**< \brief (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit */
+#define XDMAC_GID_ID1 (0x1u << 1) /**< \brief (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit */
+#define XDMAC_GID_ID4 (0x1u << 4) /**< \brief (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit */
+#define XDMAC_GID_ID5 (0x1u << 5) /**< \brief (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit */
+#define XDMAC_GID_ID6 (0x1u << 6) /**< \brief (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit */
+#define XDMAC_GID_ID7 (0x1u << 7) /**< \brief (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit */
+#define XDMAC_GID_ID8 (0x1u << 8) /**< \brief (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit */
+#define XDMAC_GID_ID9 (0x1u << 9) /**< \brief (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit */
+#define XDMAC_GID_ID10 (0x1u << 10) /**< \brief (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit */
+#define XDMAC_GID_ID11 (0x1u << 11) /**< \brief (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit */
+#define XDMAC_GID_ID12 (0x1u << 12) /**< \brief (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit */
+#define XDMAC_GID_ID13 (0x1u << 13) /**< \brief (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit */
+#define XDMAC_GID_ID14 (0x1u << 14) /**< \brief (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit */
+#define XDMAC_GID_ID15 (0x1u << 15) /**< \brief (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit */
+/* -------- XDMAC_GIM : (XDMAC Offset: 0x14) Global Interrupt Mask Register -------- */
+#define XDMAC_GIM_IM0 (0x1u << 0) /**< \brief (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit */
+#define XDMAC_GIM_IM1 (0x1u << 1) /**< \brief (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit */
+#define XDMAC_GIM_IM4 (0x1u << 4) /**< \brief (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit */
+#define XDMAC_GIM_IM5 (0x1u << 5) /**< \brief (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit */
+#define XDMAC_GIM_IM6 (0x1u << 6) /**< \brief (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit */
+#define XDMAC_GIM_IM7 (0x1u << 7) /**< \brief (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit */
+#define XDMAC_GIM_IM8 (0x1u << 8) /**< \brief (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit */
+#define XDMAC_GIM_IM9 (0x1u << 9) /**< \brief (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit */
+#define XDMAC_GIM_IM10 (0x1u << 10) /**< \brief (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit */
+#define XDMAC_GIM_IM11 (0x1u << 11) /**< \brief (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit */
+#define XDMAC_GIM_IM12 (0x1u << 12) /**< \brief (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit */
+#define XDMAC_GIM_IM13 (0x1u << 13) /**< \brief (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit */
+#define XDMAC_GIM_IM14 (0x1u << 14) /**< \brief (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit */
+#define XDMAC_GIM_IM15 (0x1u << 15) /**< \brief (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit */
+/* -------- XDMAC_GIS : (XDMAC Offset: 0x18) Global Interrupt Status Register -------- */
+#define XDMAC_GIS_IS0 (0x1u << 0) /**< \brief (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit */
+#define XDMAC_GIS_IS1 (0x1u << 1) /**< \brief (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit */
+#define XDMAC_GIS_IS4 (0x1u << 4) /**< \brief (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit */
+#define XDMAC_GIS_IS5 (0x1u << 5) /**< \brief (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit */
+#define XDMAC_GIS_IS6 (0x1u << 6) /**< \brief (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit */
+#define XDMAC_GIS_IS7 (0x1u << 7) /**< \brief (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit */
+#define XDMAC_GIS_IS8 (0x1u << 8) /**< \brief (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit */
+#define XDMAC_GIS_IS9 (0x1u << 9) /**< \brief (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit */
+#define XDMAC_GIS_IS10 (0x1u << 10) /**< \brief (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit */
+#define XDMAC_GIS_IS11 (0x1u << 11) /**< \brief (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit */
+#define XDMAC_GIS_IS12 (0x1u << 12) /**< \brief (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit */
+#define XDMAC_GIS_IS13 (0x1u << 13) /**< \brief (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit */
+#define XDMAC_GIS_IS14 (0x1u << 14) /**< \brief (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit */
+#define XDMAC_GIS_IS15 (0x1u << 15) /**< \brief (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit */
+/* -------- XDMAC_GE : (XDMAC Offset: 0x1C) Global Channel Enable Register -------- */
+#define XDMAC_GE_EN0 (0x1u << 0) /**< \brief (XDMAC_GE) XDMAC Channel 0 Enable Bit */
+#define XDMAC_GE_EN1 (0x1u << 1) /**< \brief (XDMAC_GE) XDMAC Channel 1 Enable Bit */
+#define XDMAC_GE_EN4 (0x1u << 4) /**< \brief (XDMAC_GE) XDMAC Channel 4 Enable Bit */
+#define XDMAC_GE_EN5 (0x1u << 5) /**< \brief (XDMAC_GE) XDMAC Channel 5 Enable Bit */
+#define XDMAC_GE_EN6 (0x1u << 6) /**< \brief (XDMAC_GE) XDMAC Channel 6 Enable Bit */
+#define XDMAC_GE_EN7 (0x1u << 7) /**< \brief (XDMAC_GE) XDMAC Channel 7 Enable Bit */
+#define XDMAC_GE_EN8 (0x1u << 8) /**< \brief (XDMAC_GE) XDMAC Channel 8 Enable Bit */
+#define XDMAC_GE_EN9 (0x1u << 9) /**< \brief (XDMAC_GE) XDMAC Channel 9 Enable Bit */
+#define XDMAC_GE_EN10 (0x1u << 10) /**< \brief (XDMAC_GE) XDMAC Channel 10 Enable Bit */
+#define XDMAC_GE_EN11 (0x1u << 11) /**< \brief (XDMAC_GE) XDMAC Channel 11 Enable Bit */
+#define XDMAC_GE_EN12 (0x1u << 12) /**< \brief (XDMAC_GE) XDMAC Channel 12 Enable Bit */
+#define XDMAC_GE_EN13 (0x1u << 13) /**< \brief (XDMAC_GE) XDMAC Channel 13 Enable Bit */
+#define XDMAC_GE_EN14 (0x1u << 14) /**< \brief (XDMAC_GE) XDMAC Channel 14 Enable Bit */
+#define XDMAC_GE_EN15 (0x1u << 15) /**< \brief (XDMAC_GE) XDMAC Channel 15 Enable Bit */
+/* -------- XDMAC_GD : (XDMAC Offset: 0x20) Global Channel Disable Register -------- */
+#define XDMAC_GD_DI0 (0x1u << 0) /**< \brief (XDMAC_GD) XDMAC Channel 0 Disable Bit */
+#define XDMAC_GD_DI1 (0x1u << 1) /**< \brief (XDMAC_GD) XDMAC Channel 1 Disable Bit */
+#define XDMAC_GD_DI4 (0x1u << 4) /**< \brief (XDMAC_GD) XDMAC Channel 4 Disable Bit */
+#define XDMAC_GD_DI5 (0x1u << 5) /**< \brief (XDMAC_GD) XDMAC Channel 5 Disable Bit */
+#define XDMAC_GD_DI6 (0x1u << 6) /**< \brief (XDMAC_GD) XDMAC Channel 6 Disable Bit */
+#define XDMAC_GD_DI7 (0x1u << 7) /**< \brief (XDMAC_GD) XDMAC Channel 7 Disable Bit */
+#define XDMAC_GD_DI8 (0x1u << 8) /**< \brief (XDMAC_GD) XDMAC Channel 8 Disable Bit */
+#define XDMAC_GD_DI9 (0x1u << 9) /**< \brief (XDMAC_GD) XDMAC Channel 9 Disable Bit */
+#define XDMAC_GD_DI10 (0x1u << 10) /**< \brief (XDMAC_GD) XDMAC Channel 10 Disable Bit */
+#define XDMAC_GD_DI11 (0x1u << 11) /**< \brief (XDMAC_GD) XDMAC Channel 11 Disable Bit */
+#define XDMAC_GD_DI12 (0x1u << 12) /**< \brief (XDMAC_GD) XDMAC Channel 12 Disable Bit */
+#define XDMAC_GD_DI13 (0x1u << 13) /**< \brief (XDMAC_GD) XDMAC Channel 13 Disable Bit */
+#define XDMAC_GD_DI14 (0x1u << 14) /**< \brief (XDMAC_GD) XDMAC Channel 14 Disable Bit */
+#define XDMAC_GD_DI15 (0x1u << 15) /**< \brief (XDMAC_GD) XDMAC Channel 15 Disable Bit */
+/* -------- XDMAC_GS : (XDMAC Offset: 0x24) Global Channel Status Register -------- */
+#define XDMAC_GS_ST0 (0x1u << 0) /**< \brief (XDMAC_GS) XDMAC Channel 0 Status Bit */
+#define XDMAC_GS_ST1 (0x1u << 1) /**< \brief (XDMAC_GS) XDMAC Channel 1 Status Bit */
+#define XDMAC_GS_ST4 (0x1u << 4) /**< \brief (XDMAC_GS) XDMAC Channel 4 Status Bit */
+#define XDMAC_GS_ST5 (0x1u << 5) /**< \brief (XDMAC_GS) XDMAC Channel 5 Status Bit */
+#define XDMAC_GS_ST6 (0x1u << 6) /**< \brief (XDMAC_GS) XDMAC Channel 6 Status Bit */
+#define XDMAC_GS_ST7 (0x1u << 7) /**< \brief (XDMAC_GS) XDMAC Channel 7 Status Bit */
+#define XDMAC_GS_ST8 (0x1u << 8) /**< \brief (XDMAC_GS) XDMAC Channel 8 Status Bit */
+#define XDMAC_GS_ST9 (0x1u << 9) /**< \brief (XDMAC_GS) XDMAC Channel 9 Status Bit */
+#define XDMAC_GS_ST10 (0x1u << 10) /**< \brief (XDMAC_GS) XDMAC Channel 10 Status Bit */
+#define XDMAC_GS_ST11 (0x1u << 11) /**< \brief (XDMAC_GS) XDMAC Channel 11 Status Bit */
+#define XDMAC_GS_ST12 (0x1u << 12) /**< \brief (XDMAC_GS) XDMAC Channel 12 Status Bit */
+#define XDMAC_GS_ST13 (0x1u << 13) /**< \brief (XDMAC_GS) XDMAC Channel 13 Status Bit */
+#define XDMAC_GS_ST14 (0x1u << 14) /**< \brief (XDMAC_GS) XDMAC Channel 14 Status Bit */
+#define XDMAC_GS_ST15 (0x1u << 15) /**< \brief (XDMAC_GS) XDMAC Channel 15 Status Bit */
+/* -------- XDMAC_GRS : (XDMAC Offset: 0x28) Global Channel Read Suspend Register -------- */
+#define XDMAC_GRS_RS0 (0x1u << 0) /**< \brief (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit */
+#define XDMAC_GRS_RS1 (0x1u << 1) /**< \brief (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit */
+#define XDMAC_GRS_RS4 (0x1u << 4) /**< \brief (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit */
+#define XDMAC_GRS_RS5 (0x1u << 5) /**< \brief (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit */
+#define XDMAC_GRS_RS6 (0x1u << 6) /**< \brief (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit */
+#define XDMAC_GRS_RS7 (0x1u << 7) /**< \brief (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit */
+#define XDMAC_GRS_RS8 (0x1u << 8) /**< \brief (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit */
+#define XDMAC_GRS_RS9 (0x1u << 9) /**< \brief (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit */
+#define XDMAC_GRS_RS10 (0x1u << 10) /**< \brief (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit */
+#define XDMAC_GRS_RS11 (0x1u << 11) /**< \brief (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit */
+#define XDMAC_GRS_RS12 (0x1u << 12) /**< \brief (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit */
+#define XDMAC_GRS_RS13 (0x1u << 13) /**< \brief (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit */
+#define XDMAC_GRS_RS14 (0x1u << 14) /**< \brief (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit */
+#define XDMAC_GRS_RS15 (0x1u << 15) /**< \brief (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit */
+/* -------- XDMAC_GWS : (XDMAC Offset: 0x2C) Global Channel Write Suspend Register -------- */
+#define XDMAC_GWS_WS0 (0x1u << 0) /**< \brief (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit */
+#define XDMAC_GWS_WS1 (0x1u << 1) /**< \brief (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit */
+#define XDMAC_GWS_WS4 (0x1u << 4) /**< \brief (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit */
+#define XDMAC_GWS_WS5 (0x1u << 5) /**< \brief (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit */
+#define XDMAC_GWS_WS6 (0x1u << 6) /**< \brief (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit */
+#define XDMAC_GWS_WS7 (0x1u << 7) /**< \brief (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit */
+#define XDMAC_GWS_WS8 (0x1u << 8) /**< \brief (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit */
+#define XDMAC_GWS_WS9 (0x1u << 9) /**< \brief (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit */
+#define XDMAC_GWS_WS10 (0x1u << 10) /**< \brief (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit */
+#define XDMAC_GWS_WS11 (0x1u << 11) /**< \brief (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit */
+#define XDMAC_GWS_WS12 (0x1u << 12) /**< \brief (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit */
+#define XDMAC_GWS_WS13 (0x1u << 13) /**< \brief (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit */
+#define XDMAC_GWS_WS14 (0x1u << 14) /**< \brief (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit */
+#define XDMAC_GWS_WS15 (0x1u << 15) /**< \brief (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit */
+/* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) Global Channel Read Write Suspend Register -------- */
+#define XDMAC_GRWS_RWS0 (0x1u << 0) /**< \brief (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit */
+#define XDMAC_GRWS_RWS1 (0x1u << 1) /**< \brief (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit */
+#define XDMAC_GRWS_RWS4 (0x1u << 4) /**< \brief (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit */
+#define XDMAC_GRWS_RWS5 (0x1u << 5) /**< \brief (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit */
+#define XDMAC_GRWS_RWS6 (0x1u << 6) /**< \brief (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit */
+#define XDMAC_GRWS_RWS7 (0x1u << 7) /**< \brief (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit */
+#define XDMAC_GRWS_RWS8 (0x1u << 8) /**< \brief (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit */
+#define XDMAC_GRWS_RWS9 (0x1u << 9) /**< \brief (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit */
+#define XDMAC_GRWS_RWS10 (0x1u << 10) /**< \brief (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit */
+#define XDMAC_GRWS_RWS11 (0x1u << 11) /**< \brief (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit */
+#define XDMAC_GRWS_RWS12 (0x1u << 12) /**< \brief (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit */
+#define XDMAC_GRWS_RWS13 (0x1u << 13) /**< \brief (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit */
+#define XDMAC_GRWS_RWS14 (0x1u << 14) /**< \brief (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit */
+#define XDMAC_GRWS_RWS15 (0x1u << 15) /**< \brief (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit */
+/* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) Global Channel Read Write Resume Register -------- */
+#define XDMAC_GRWR_RWR0 (0x1u << 0) /**< \brief (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit */
+#define XDMAC_GRWR_RWR1 (0x1u << 1) /**< \brief (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit */
+#define XDMAC_GRWR_RWR4 (0x1u << 4) /**< \brief (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit */
+#define XDMAC_GRWR_RWR5 (0x1u << 5) /**< \brief (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit */
+#define XDMAC_GRWR_RWR6 (0x1u << 6) /**< \brief (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit */
+#define XDMAC_GRWR_RWR7 (0x1u << 7) /**< \brief (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit */
+#define XDMAC_GRWR_RWR8 (0x1u << 8) /**< \brief (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit */
+#define XDMAC_GRWR_RWR9 (0x1u << 9) /**< \brief (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit */
+#define XDMAC_GRWR_RWR10 (0x1u << 10) /**< \brief (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit */
+#define XDMAC_GRWR_RWR11 (0x1u << 11) /**< \brief (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit */
+#define XDMAC_GRWR_RWR12 (0x1u << 12) /**< \brief (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit */
+#define XDMAC_GRWR_RWR13 (0x1u << 13) /**< \brief (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit */
+#define XDMAC_GRWR_RWR14 (0x1u << 14) /**< \brief (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit */
+#define XDMAC_GRWR_RWR15 (0x1u << 15) /**< \brief (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit */
+/* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) Global Channel Software Request Register -------- */
+#define XDMAC_GSWR_SWREQ0 (0x1u << 0) /**< \brief (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit */
+#define XDMAC_GSWR_SWREQ1 (0x1u << 1) /**< \brief (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit */
+#define XDMAC_GSWR_SWREQ4 (0x1u << 4) /**< \brief (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit */
+#define XDMAC_GSWR_SWREQ5 (0x1u << 5) /**< \brief (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit */
+#define XDMAC_GSWR_SWREQ6 (0x1u << 6) /**< \brief (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit */
+#define XDMAC_GSWR_SWREQ7 (0x1u << 7) /**< \brief (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit */
+#define XDMAC_GSWR_SWREQ8 (0x1u << 8) /**< \brief (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit */
+#define XDMAC_GSWR_SWREQ9 (0x1u << 9) /**< \brief (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit */
+#define XDMAC_GSWR_SWREQ10 (0x1u << 10) /**< \brief (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit */
+#define XDMAC_GSWR_SWREQ11 (0x1u << 11) /**< \brief (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit */
+#define XDMAC_GSWR_SWREQ12 (0x1u << 12) /**< \brief (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit */
+#define XDMAC_GSWR_SWREQ13 (0x1u << 13) /**< \brief (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit */
+#define XDMAC_GSWR_SWREQ14 (0x1u << 14) /**< \brief (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit */
+#define XDMAC_GSWR_SWREQ15 (0x1u << 15) /**< \brief (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit */
+/* -------- XDMAC_GSWS : (XDMAC Offset: 0x3C) Global Channel Software Request Status Register -------- */
+#define XDMAC_GSWS_SWRS0 (0x1u << 0) /**< \brief (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit */
+#define XDMAC_GSWS_SWRS1 (0x1u << 1) /**< \brief (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit */
+#define XDMAC_GSWS_SWRS4 (0x1u << 4) /**< \brief (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit */
+#define XDMAC_GSWS_SWRS5 (0x1u << 5) /**< \brief (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit */
+#define XDMAC_GSWS_SWRS6 (0x1u << 6) /**< \brief (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit */
+#define XDMAC_GSWS_SWRS7 (0x1u << 7) /**< \brief (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit */
+#define XDMAC_GSWS_SWRS8 (0x1u << 8) /**< \brief (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit */
+#define XDMAC_GSWS_SWRS9 (0x1u << 9) /**< \brief (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit */
+#define XDMAC_GSWS_SWRS10 (0x1u << 10) /**< \brief (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit */
+#define XDMAC_GSWS_SWRS11 (0x1u << 11) /**< \brief (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit */
+#define XDMAC_GSWS_SWRS12 (0x1u << 12) /**< \brief (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit */
+#define XDMAC_GSWS_SWRS13 (0x1u << 13) /**< \brief (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit */
+#define XDMAC_GSWS_SWRS14 (0x1u << 14) /**< \brief (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit */
+#define XDMAC_GSWS_SWRS15 (0x1u << 15) /**< \brief (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit */
+/* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) Global Channel Software Flush Request Register -------- */
+#define XDMAC_GSWF_SWF0 (0x1u << 0) /**< \brief (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit */
+#define XDMAC_GSWF_SWF1 (0x1u << 1) /**< \brief (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit */
+#define XDMAC_GSWF_SWF4 (0x1u << 4) /**< \brief (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit */
+#define XDMAC_GSWF_SWF5 (0x1u << 5) /**< \brief (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit */
+#define XDMAC_GSWF_SWF6 (0x1u << 6) /**< \brief (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit */
+#define XDMAC_GSWF_SWF7 (0x1u << 7) /**< \brief (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit */
+#define XDMAC_GSWF_SWF8 (0x1u << 8) /**< \brief (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit */
+#define XDMAC_GSWF_SWF9 (0x1u << 9) /**< \brief (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit */
+#define XDMAC_GSWF_SWF10 (0x1u << 10) /**< \brief (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit */
+#define XDMAC_GSWF_SWF11 (0x1u << 11) /**< \brief (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit */
+#define XDMAC_GSWF_SWF12 (0x1u << 12) /**< \brief (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit */
+#define XDMAC_GSWF_SWF13 (0x1u << 13) /**< \brief (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit */
+#define XDMAC_GSWF_SWF14 (0x1u << 14) /**< \brief (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit */
+#define XDMAC_GSWF_SWF15 (0x1u << 15) /**< \brief (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit */
+/* -------- XDMAC_CIE : (XDMAC Offset: N/A) Channel Interrupt Enable Register -------- */
+#define XDMAC_CIE_BIE (0x1u << 0) /**< \brief (XDMAC_CIE) End of Block Interrupt Enable Bit */
+#define XDMAC_CIE_LIE (0x1u << 1) /**< \brief (XDMAC_CIE) End of Linked List Interrupt Enable Bit */
+#define XDMAC_CIE_DIE (0x1u << 2) /**< \brief (XDMAC_CIE) End of Disable Interrupt Enable Bit */
+#define XDMAC_CIE_FIE (0x1u << 3) /**< \brief (XDMAC_CIE) End of Flush Interrupt Enable Bit */
+#define XDMAC_CIE_RBIE (0x1u << 4) /**< \brief (XDMAC_CIE) Read Bus Error Interrupt Enable Bit */
+#define XDMAC_CIE_WBIE (0x1u << 5) /**< \brief (XDMAC_CIE) Write Bus Error Interrupt Enable Bit */
+#define XDMAC_CIE_ROIE (0x1u << 6) /**< \brief (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit */
+/* -------- XDMAC_CID : (XDMAC Offset: N/A) Channel Interrupt Disable Register -------- */
+#define XDMAC_CID_BID (0x1u << 0) /**< \brief (XDMAC_CID) End of Block Interrupt Disable Bit */
+#define XDMAC_CID_LID (0x1u << 1) /**< \brief (XDMAC_CID) End of Linked List Interrupt Disable Bit */
+#define XDMAC_CID_DID (0x1u << 2) /**< \brief (XDMAC_CID) End of Disable Interrupt Disable Bit */
+#define XDMAC_CID_FID (0x1u << 3) /**< \brief (XDMAC_CID) End of Flush Interrupt Disable Bit */
+#define XDMAC_CID_RBEID (0x1u << 4) /**< \brief (XDMAC_CID) Read Bus Error Interrupt Disable Bit */
+#define XDMAC_CID_WBEID (0x1u << 5) /**< \brief (XDMAC_CID) Write Bus Error Interrupt Disable Bit */
+#define XDMAC_CID_ROID (0x1u << 6) /**< \brief (XDMAC_CID) Request Overflow Error Interrupt Disable Bit */
+/* -------- XDMAC_CIM : (XDMAC Offset: N/A) Channel Interrupt Mask Register -------- */
+#define XDMAC_CIM_BIM (0x1u << 0) /**< \brief (XDMAC_CIM) End of Block Interrupt Mask Bit */
+#define XDMAC_CIM_LIM (0x1u << 1) /**< \brief (XDMAC_CIM) End of Linked List Interrupt Mask Bit */
+#define XDMAC_CIM_DIM (0x1u << 2) /**< \brief (XDMAC_CIM) End of Disable Interrupt Mask Bit */
+#define XDMAC_CIM_FIM (0x1u << 3) /**< \brief (XDMAC_CIM) End of Flush Interrupt Mask Bit */
+#define XDMAC_CIM_RBEIM (0x1u << 4) /**< \brief (XDMAC_CIM) Read Bus Error Interrupt Mask Bit */
+#define XDMAC_CIM_WBEIM (0x1u << 5) /**< \brief (XDMAC_CIM) Write Bus Error Interrupt Mask Bit */
+#define XDMAC_CIM_ROIM (0x1u << 6) /**< \brief (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit */
+/* -------- XDMAC_CIS : (XDMAC Offset: N/A) Channel Interrupt Status Register -------- */
+#define XDMAC_CIS_BIS (0x1u << 0) /**< \brief (XDMAC_CIS) End of Block Interrupt Status Bit */
+#define XDMAC_CIS_LIS (0x1u << 1) /**< \brief (XDMAC_CIS) End of Linked List Interrupt Status Bit */
+#define XDMAC_CIS_DIS (0x1u << 2) /**< \brief (XDMAC_CIS) End of Disable Interrupt Status Bit */
+#define XDMAC_CIS_FIS (0x1u << 3) /**< \brief (XDMAC_CIS) End of Flush Interrupt Status Bit */
+#define XDMAC_CIS_RBEIS (0x1u << 4) /**< \brief (XDMAC_CIS) Read Bus Error Interrupt Status Bit */
+#define XDMAC_CIS_WBEIS (0x1u << 5) /**< \brief (XDMAC_CIS) Write Bus Error Interrupt Status Bit */
+#define XDMAC_CIS_ROIS (0x1u << 6) /**< \brief (XDMAC_CIS) Request Overflow Error Interrupt Status Bit */
+/* -------- XDMAC_CSA : (XDMAC Offset: N/A) Channel Source Address Register -------- */
+#define XDMAC_CSA_SA_Pos 0
+#define XDMAC_CSA_SA_Msk (0xffffffffu << XDMAC_CSA_SA_Pos) /**< \brief (XDMAC_CSA) Channel x Source Address */
+#define XDMAC_CSA_SA(value) ((XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos)))
+/* -------- XDMAC_CDA : (XDMAC Offset: N/A) Channel Destination Address Register -------- */
+#define XDMAC_CDA_DA_Pos 0
+#define XDMAC_CDA_DA_Msk (0xffffffffu << XDMAC_CDA_DA_Pos) /**< \brief (XDMAC_CDA) Channel x Destination Address */
+#define XDMAC_CDA_DA(value) ((XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos)))
+/* -------- XDMAC_CNDA : (XDMAC Offset: N/A) Channel Next Descriptor Address Register -------- */
+#define XDMAC_CNDA_NDAIF (0x1u << 0) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Interface */
+#define XDMAC_CNDA_NDA_Pos 2
+#define XDMAC_CNDA_NDA_Msk (0x3fffffffu << XDMAC_CNDA_NDA_Pos) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Address */
+#define XDMAC_CNDA_NDA(value) ((XDMAC_CNDA_NDA_Msk & ((value) << XDMAC_CNDA_NDA_Pos)))
+/* -------- XDMAC_CNDC : (XDMAC Offset: N/A) Channel Next Descriptor Control Register -------- */
+#define XDMAC_CNDC_NDE (0x1u << 0) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Enable */
+#define   XDMAC_CNDC_NDE_DSCR_FETCH_DIS (0x0u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is disabled. */
+#define   XDMAC_CNDC_NDE_DSCR_FETCH_EN (0x1u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is enabled. */
+#define XDMAC_CNDC_NDSUP (0x1u << 1) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Source Update */
+#define   XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (0x0u << 1) /**< \brief (XDMAC_CNDC) Source parameters remain unchanged. */
+#define   XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (0x1u << 1) /**< \brief (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. */
+#define XDMAC_CNDC_NDDUP (0x1u << 2) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Destination Update */
+#define   XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (0x0u << 2) /**< \brief (XDMAC_CNDC) Destination parameters remain unchanged. */
+#define   XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (0x1u << 2) /**< \brief (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. */
+#define XDMAC_CNDC_NDVIEW_Pos 3
+#define XDMAC_CNDC_NDVIEW_Msk (0x3u << XDMAC_CNDC_NDVIEW_Pos) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor View */
+#define XDMAC_CNDC_NDVIEW(value) ((XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos)))
+#define   XDMAC_CNDC_NDVIEW_NDV0 (0x0u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 0 */
+#define   XDMAC_CNDC_NDVIEW_NDV1 (0x1u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 1 */
+#define   XDMAC_CNDC_NDVIEW_NDV2 (0x2u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 2 */
+#define   XDMAC_CNDC_NDVIEW_NDV3 (0x3u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 3 */
+/* -------- XDMAC_CUBC : (XDMAC Offset: N/A) Channel Microblock Control Register -------- */
+#define XDMAC_CUBC_UBLEN_Pos 0
+#define XDMAC_CUBC_UBLEN_Msk (0xffffffu << XDMAC_CUBC_UBLEN_Pos) /**< \brief (XDMAC_CUBC) Channel x Microblock Length */
+#define XDMAC_CUBC_UBLEN(value) ((XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos)))
+/* -------- XDMAC_CBC : (XDMAC Offset: N/A) Channel Block Control Register -------- */
+#define XDMAC_CBC_BLEN_Pos 0
+#define XDMAC_CBC_BLEN_Msk (0xfffu << XDMAC_CBC_BLEN_Pos) /**< \brief (XDMAC_CBC) Channel x Block Length */
+#define XDMAC_CBC_BLEN(value) ((XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos)))
+/* -------- XDMAC_CC : (XDMAC Offset: N/A) Channel Configuration Register -------- */
+#define XDMAC_CC_TYPE (0x1u << 0) /**< \brief (XDMAC_CC) Channel x Transfer Type */
+#define   XDMAC_CC_TYPE_MEM_TRAN (0x0u << 0) /**< \brief (XDMAC_CC) Self triggered mode (Memory to Memory Transfer). */
+#define   XDMAC_CC_TYPE_PER_TRAN (0x1u << 0) /**< \brief (XDMAC_CC) Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). */
+#define XDMAC_CC_MBSIZE_Pos 1
+#define XDMAC_CC_MBSIZE_Msk (0x3u << XDMAC_CC_MBSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Memory Burst Size */
+#define XDMAC_CC_MBSIZE(value) ((XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos)))
+#define   XDMAC_CC_MBSIZE_SINGLE (0x0u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to one. */
+#define   XDMAC_CC_MBSIZE_FOUR (0x1u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to four. */
+#define   XDMAC_CC_MBSIZE_EIGHT (0x2u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to eight. */
+#define   XDMAC_CC_MBSIZE_SIXTEEN (0x3u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to sixteen. */
+#define XDMAC_CC_DSYNC (0x1u << 4) /**< \brief (XDMAC_CC) Channel x Synchronization */
+#define   XDMAC_CC_DSYNC_PER2MEM (0x0u << 4) /**< \brief (XDMAC_CC) Peripheral to Memory transfer. */
+#define   XDMAC_CC_DSYNC_MEM2PER (0x1u << 4) /**< \brief (XDMAC_CC) Memory to Peripheral transfer. */
+#define XDMAC_CC_PROT (0x1u << 5) /**< \brief (XDMAC_CC) Channel x Protection */
+#define   XDMAC_CC_PROT_SEC (0x0u << 5) /**< \brief (XDMAC_CC) Channel is secured. */
+#define   XDMAC_CC_PROT_UNSEC (0x1u << 5) /**< \brief (XDMAC_CC) Channel is unsecured. */
+#define XDMAC_CC_SWREQ (0x1u << 6) /**< \brief (XDMAC_CC) Channel x Software Request Trigger */
+#define   XDMAC_CC_SWREQ_HWR_CONNECTED (0x0u << 6) /**< \brief (XDMAC_CC) Hardware request line is connected to the peripheral request line. */
+#define   XDMAC_CC_SWREQ_SWR_CONNECTED (0x1u << 6) /**< \brief (XDMAC_CC) Software request is connected to the peripheral request line. */
+#define XDMAC_CC_MEMSET (0x1u << 7) /**< \brief (XDMAC_CC) Channel x Fill Block of memory */
+#define   XDMAC_CC_MEMSET_NORMAL_MODE (0x0u << 7) /**< \brief (XDMAC_CC) Memset is not activated. */
+#define   XDMAC_CC_MEMSET_HW_MODE (0x1u << 7) /**< \brief (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. */
+#define XDMAC_CC_CSIZE_Pos 8
+#define XDMAC_CC_CSIZE_Msk (0x7u << XDMAC_CC_CSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Chunk Size */
+#define XDMAC_CC_CSIZE(value) ((XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos)))
+#define   XDMAC_CC_CSIZE_CHK_1 (0x0u << 8) /**< \brief (XDMAC_CC) 1 data transferred */
+#define   XDMAC_CC_CSIZE_CHK_2 (0x1u << 8) /**< \brief (XDMAC_CC) 2 data transferred */
+#define   XDMAC_CC_CSIZE_CHK_4 (0x2u << 8) /**< \brief (XDMAC_CC) 4 data transferred */
+#define   XDMAC_CC_CSIZE_CHK_8 (0x3u << 8) /**< \brief (XDMAC_CC) 8 data transferred */
+#define   XDMAC_CC_CSIZE_CHK_16 (0x4u << 8) /**< \brief (XDMAC_CC) 16 data transferred */
+#define XDMAC_CC_DWIDTH_Pos 11
+#define XDMAC_CC_DWIDTH_Msk (0x3u << XDMAC_CC_DWIDTH_Pos) /**< \brief (XDMAC_CC) Channel x Data Width */
+#define XDMAC_CC_DWIDTH(value) ((XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos)))
+#define   XDMAC_CC_DWIDTH_BYTE (0x0u << 11) /**< \brief (XDMAC_CC) The data size is set to 8 bits */
+#define   XDMAC_CC_DWIDTH_HALFWORD (0x1u << 11) /**< \brief (XDMAC_CC) The data size is set to 16 bits */
+#define   XDMAC_CC_DWIDTH_WORD (0x2u << 11) /**< \brief (XDMAC_CC) The data size is set to 32 bits */
+#define   XDMAC_CC_DWIDTH_DWORD (0x3u << 11) /**< \brief (XDMAC_CC) The data size is set to 64 bits */
+#define XDMAC_CC_SIF (0x1u << 13) /**< \brief (XDMAC_CC) Channel x Source Interface Identifier */
+#define   XDMAC_CC_SIF_AHB_IF0 (0x0u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 0. */
+#define   XDMAC_CC_SIF_AHB_IF1 (0x1u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 1. */
+#define XDMAC_CC_DIF (0x1u << 14) /**< \brief (XDMAC_CC) Channel x Destination Interface Identifier */
+#define   XDMAC_CC_DIF_AHB_IF0 (0x0u << 14) /**< \brief (XDMAC_CC) The data is written through the system bus interface 0. */
+#define   XDMAC_CC_DIF_AHB_IF1 (0x1u << 14) /**< \brief (XDMAC_CC) The data is written though the system bus interface 1. */
+#define XDMAC_CC_SAM_Pos 16
+#define XDMAC_CC_SAM_Msk (0x3u << XDMAC_CC_SAM_Pos) /**< \brief (XDMAC_CC) Channel x Source Addressing Mode */
+#define XDMAC_CC_SAM(value) ((XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos)))
+#define   XDMAC_CC_SAM_FIXED_AM (0x0u << 16) /**< \brief (XDMAC_CC) The address remains unchanged. */
+#define   XDMAC_CC_SAM_INCREMENTED_AM (0x1u << 16) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */
+#define   XDMAC_CC_SAM_UBS_AM (0x2u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */
+#define   XDMAC_CC_SAM_UBS_DS_AM (0x3u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */
+#define XDMAC_CC_DAM_Pos 18
+#define XDMAC_CC_DAM_Msk (0x3u << XDMAC_CC_DAM_Pos) /**< \brief (XDMAC_CC) Channel x Destination Addressing Mode */
+#define XDMAC_CC_DAM(value) ((XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos)))
+#define   XDMAC_CC_DAM_FIXED_AM (0x0u << 18) /**< \brief (XDMAC_CC) The address remains unchanged. */
+#define   XDMAC_CC_DAM_INCREMENTED_AM (0x1u << 18) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */
+#define   XDMAC_CC_DAM_UBS_AM (0x2u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */
+#define   XDMAC_CC_DAM_UBS_DS_AM (0x3u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */
+#define XDMAC_CC_INITD (0x1u << 21) /**< \brief (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) */
+#define   XDMAC_CC_INITD_TERMINATED (0x0u << 21) /**< \brief (XDMAC_CC) Channel initialization is in progress. */
+#define   XDMAC_CC_INITD_IN_PROGRESS (0x1u << 21) /**< \brief (XDMAC_CC) Channel initialization is completed. */
+#define XDMAC_CC_RDIP (0x1u << 22) /**< \brief (XDMAC_CC) Read in Progress (this bit is read-only) */
+#define   XDMAC_CC_RDIP_DONE (0x0u << 22) /**< \brief (XDMAC_CC) No Active read transaction on the bus. */
+#define   XDMAC_CC_RDIP_IN_PROGRESS (0x1u << 22) /**< \brief (XDMAC_CC) A read transaction is in progress. */
+#define XDMAC_CC_WRIP (0x1u << 23) /**< \brief (XDMAC_CC) Write in Progress (this bit is read-only) */
+#define   XDMAC_CC_WRIP_DONE (0x0u << 23) /**< \brief (XDMAC_CC) No Active write transaction on the bus. */
+#define   XDMAC_CC_WRIP_IN_PROGRESS (0x1u << 23) /**< \brief (XDMAC_CC) A Write transaction is in progress. */
+#define XDMAC_CC_PERID_Pos 24
+#define XDMAC_CC_PERID_Msk (0x7fu << XDMAC_CC_PERID_Pos) /**< \brief (XDMAC_CC) Channel x Peripheral Identifier */
+#define XDMAC_CC_PERID(value) ((XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos)))
+/* -------- XDMAC_CDS_MSP : (XDMAC Offset: N/A) Channel Data Stride Memory Set Pattern -------- */
+#define XDMAC_CDS_MSP_SDS_MSP_Pos 0
+#define XDMAC_CDS_MSP_SDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_SDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern */
+#define XDMAC_CDS_MSP_SDS_MSP(value) ((XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos)))
+#define XDMAC_CDS_MSP_DDS_MSP_Pos 16
+#define XDMAC_CDS_MSP_DDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_DDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern */
+#define XDMAC_CDS_MSP_DDS_MSP(value) ((XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos)))
+/* -------- XDMAC_CSUS : (XDMAC Offset: N/A) Channel Source Microblock Stride -------- */
+#define XDMAC_CSUS_SUBS_Pos 0
+#define XDMAC_CSUS_SUBS_Msk (0xffffffu << XDMAC_CSUS_SUBS_Pos) /**< \brief (XDMAC_CSUS) Channel x Source Microblock Stride */
+#define XDMAC_CSUS_SUBS(value) ((XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos)))
+/* -------- XDMAC_CDUS : (XDMAC Offset: N/A) Channel Destination Microblock Stride -------- */
+#define XDMAC_CDUS_DUBS_Pos 0
+#define XDMAC_CDUS_DUBS_Msk (0xffffffu << XDMAC_CDUS_DUBS_Pos) /**< \brief (XDMAC_CDUS) Channel x Destination Microblock Stride */
+#define XDMAC_CDUS_DUBS(value) ((XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos)))
+/* -------- XDMAC_VERSION : (XDMAC Offset: 0xFFC) XDMAC Version Register -------- */
+#define XDMAC_VERSION_VERSION_Pos 0
+#define XDMAC_VERSION_VERSION_Msk (0xfffu << XDMAC_VERSION_VERSION_Pos) /**< \brief (XDMAC_VERSION) Version of the Hardware Module */
+#define XDMAC_VERSION_VERSION(value) ((XDMAC_VERSION_VERSION_Msk & ((value) << XDMAC_VERSION_VERSION_Pos)))
+#define XDMAC_VERSION_MFN_Pos 16
+#define XDMAC_VERSION_MFN_Msk (0x7u << XDMAC_VERSION_MFN_Pos) /**< \brief (XDMAC_VERSION) Metal Fix Number */
+#define XDMAC_VERSION_MFN(value) ((XDMAC_VERSION_MFN_Msk & ((value) << XDMAC_VERSION_MFN_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAMA5D2_XDMAC_COMPONENT_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d21.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d21.h
new file mode 100644
index 000000000..f4961852a
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d21.h
@@ -0,0 +1,238 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D21_
+#define _SAMA5D21_
+
+/** \addtogroup SAMA5D21_definitions SAMA5D21 definitions
+  This file defines all structures and symbols for SAMA5D21:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include <stdint.h>
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMA5D21 */
+/* ************************************************************************** */
+
+/** \addtogroup SAMA5D21_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_aesb.h"
+#include "component/component_aes.h"
+#include "component/component_aic.h"
+#include "component/component_aximx.h"
+#include "component/component_bsc.h"
+#include "component/component_chipid.h"
+#include "component/component_classd.h"
+#include "component/component_flexcom.h"
+#include "component/component_gmac.h"
+#include "component/component_i2sc.h"
+#include "component/component_icm.h"
+#include "component/component_isc.h"
+#include "component/component_l2cc.h"
+#include "component/component_lcdc.h"
+#include "component/component_matrix.h"
+#include "component/component_mpddrc.h"
+#include "component/component_pdmic.h"
+#include "component/component_pio.h"
+#include "component/component_pit.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_qspi.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rxlp.h"
+#include "component/component_sckc.h"
+#include "component/component_sdmmc.h"
+#include "component/component_secumod.h"
+#include "component/component_sfc.h"
+#include "component/component_sfr.h"
+#include "component/component_sfrbu.h"
+#include "component/component_sha.h"
+#include "component/component_shdwc.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_tc.h"
+#include "component/component_tdes.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_udphs.h"
+#include "component/component_wdt.h"
+#include "component/component_xdmac.h"
+
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAMA5D21 */
+/* ************************************************************************** */
+
+/** \addtogroup SAMA5D21_base Peripheral Base Address Definitions */
+/*@{*/
+
+#define AXIMX    ((Aximx    *)0x00600000U) /**< \brief (AXIMX   ) Base Address */
+#define L2CC     ((L2cc     *)0x00A00000U) /**< \brief (L2CC    ) Base Address */
+#define SDMMC1   ((Sdmmc    *)0xB0000000U) /**< \brief (SDMMC1  ) Base Address */
+#define LCDC     ((Lcdc     *)0xF0000000U) /**< \brief (LCDC    ) Base Address */
+#define XDMAC1   ((Xdmac    *)0xF0004000U) /**< \brief (XDMAC1  ) Base Address */
+#define ISC      ((Isc      *)0xF0008000U) /**< \brief (ISC     ) Base Address */
+#define MPDDRC   ((Mpddrc   *)0xF000C000U) /**< \brief (MPDDRC  ) Base Address */
+#define XDMAC0   ((Xdmac    *)0xF0010000U) /**< \brief (XDMAC0  ) Base Address */
+#define PMC      ((Pmc      *)0xF0014000U) /**< \brief (PMC     ) Base Address */
+#define MATRIX0  ((Matrix   *)0xF0018000U) /**< \brief (MATRIX0 ) Base Address */
+#define AESB     ((Aesb     *)0xF001C000U) /**< \brief (AESB    ) Base Address */
+#define QSPI0    ((Qspi     *)0xF0020000U) /**< \brief (QSPI0   ) Base Address */
+#define QSPI1    ((Qspi     *)0xF0024000U) /**< \brief (QSPI1   ) Base Address */
+#define SHA      ((Sha      *)0xF0028000U) /**< \brief (SHA     ) Base Address */
+#define AES      ((Aes      *)0xF002C000U) /**< \brief (AES     ) Base Address */
+#define SPI0     ((Spi      *)0xF8000000U) /**< \brief (SPI0    ) Base Address */
+#define SSC0     ((Ssc      *)0xF8004000U) /**< \brief (SSC0    ) Base Address */
+#define GMAC0    ((Gmac     *)0xF8008000U) /**< \brief (GMAC0   ) Base Address */
+#define TC0      ((Tc       *)0xF800C000U) /**< \brief (TC0     ) Base Address */
+#define TC1      ((Tc       *)0xF8010000U) /**< \brief (TC1     ) Base Address */
+#define HSMC     ((Smc      *)0xF8014000U) /**< \brief (HSMC    ) Base Address */
+#define PDMIC    ((Pdmic    *)0xF8018000U) /**< \brief (PDMIC   ) Base Address */
+#define UART0    ((Uart     *)0xF801C000U) /**< \brief (UART0   ) Base Address */
+#define UART1    ((Uart     *)0xF8020000U) /**< \brief (UART1   ) Base Address */
+#define UART2    ((Uart     *)0xF8024000U) /**< \brief (UART2   ) Base Address */
+#define TWIHS0   ((Twi      *)0xF8028000U) /**< \brief (TWIHS0  ) Base Address */
+#define PWM      ((Pwm      *)0xF802C000U) /**< \brief (PWM     ) Base Address */
+#define SFR      ((Sfr      *)0xF8030000U) /**< \brief (SFR     ) Base Address */
+#define FLEXCOM0 ((Flexcom  *)0xF8034000U) /**< \brief (FLEXCOM0) Base Address */
+#define USART0   ((Usart    *)0xF8034200U) /**< \brief (FLEXCOM0_USART) Base Address */
+#define FCOMSPI0 ((Spi      *)0xF8034400U) /**< \brief (FLEXCOM0_SPI) Base Address */
+#define TWI0     ((Twi      *)0xF8034600U) /**< \brief (FLEXCOM0_TWI) Base Address */
+#define FLEXCOM1 ((Flexcom  *)0xF8038000U) /**< \brief (FLEXCOM1) Base Address */
+#define USART1   ((Usart    *)0xF8038200U) /**< \brief (FLEXCOM1_USART) Base Address */
+#define FCOMSPI1 ((Spi      *)0xF8038400U) /**< \brief (FLEXCOM1_SPI) Base Address */
+#define TWI1     ((Twi      *)0xF8038600U) /**< \brief (FLEXCOM1_TWI) Base Address */
+#define SAIC     ((Aic      *)0xF803C000U) /**< \brief (SAIC    ) Base Address */
+#define ICM      ((Icm      *)0xF8040000U) /**< \brief (ICM     ) Base Address */
+#define SECURAM  ((Securam  *)0xF8044000U) /**< \brief (SECURAM ) Base Address */
+#define RSTC     ((Rstc     *)0xF8048000U) /**< \brief (RSTC    ) Base Address */
+#define SHDWC    ((Shdwc    *)0xF8048010U) /**< \brief (SHDWC   ) Base Address */
+#define PIT      ((Pit      *)0xF8048030U) /**< \brief (PIT     ) Base Address */
+#define WDT      ((Wdt      *)0xF8048040U) /**< \brief (WDT     ) Base Address */
+#define SCKC     ((Sckc     *)0xF8048050U) /**< \brief (SCKC    ) Base Address */
+#define BSC      ((Bsc      *)0xF8048054U) /**< \brief (BSC     ) Base Address */
+#define RTC      ((Rtc      *)0xF80480B0U) /**< \brief (RTC     ) Base Address */
+#define RXLP     ((Rxlp     *)0xF8049000U) /**< \brief (RXLP    ) Base Address */
+#define ACC      ((Acc      *)0xF804A000U) /**< \brief (ACC     ) Base Address */
+#define SFC      ((Sfc      *)0xF804C000U) /**< \brief (SFC     ) Base Address */
+#define I2SC0    ((I2sc     *)0xF8050000U) /**< \brief (I2SC0   ) Base Address */
+#define SPI1     ((Spi      *)0xFC000000U) /**< \brief (SPI1    ) Base Address */
+#define SSC1     ((Ssc      *)0xFC004000U) /**< \brief (SSC1    ) Base Address */
+#define UART3    ((Uart     *)0xFC008000U) /**< \brief (UART3   ) Base Address */
+#define UART4    ((Uart     *)0xFC00C000U) /**< \brief (UART4   ) Base Address */
+#define FLEXCOM3 ((Flexcom  *)0xFC014000U) /**< \brief (FLEXCOM3) Base Address */
+#define USART3   ((Usart    *)0xFC014200U) /**< \brief (FLEXCOM3_USART) Base Address */
+#define FCOMSPI3 ((Spi      *)0xFC014400U) /**< \brief (FLEXCOM3_SPI) Base Address */
+#define TWI3     ((Twi      *)0xFC014600U) /**< \brief (FLEXCOM3_TWI) Base Address */
+#define FLEXCOM4 ((Flexcom  *)0xFC018000U) /**< \brief (FLEXCOM4) Base Address */
+#define USART4   ((Usart    *)0xFC018200U) /**< \brief (FLEXCOM4_USART) Base Address */
+#define FCOMSPI4 ((Spi      *)0xFC018400U) /**< \brief (FLEXCOM4_SPI) Base Address */
+#define TWI4     ((Twi      *)0xFC018600U) /**< \brief (FLEXCOM4_TWI) Base Address */
+#define TRNG     ((Trng     *)0xFC01C000U) /**< \brief (TRNG    ) Base Address */
+#define AIC      ((Aic      *)0xFC020000U) /**< \brief (AIC     ) Base Address */
+#define TWIHS1   ((Twi      *)0xFC028000U) /**< \brief (TWIHS1  ) Base Address */
+#define UDPHS    ((Udphs    *)0xFC02C000U) /**< \brief (UDPHS   ) Base Address */
+#define ADC      ((Adc      *)0xFC030000U) /**< \brief (ADC     ) Base Address */
+#define PIOA     ((Pio      *)0xFC038000U) /**< \brief (PIOA    ) Base Address */
+#define MATRIX1  ((Matrix   *)0xFC03C000U) /**< \brief (MATRIX1 ) Base Address */
+#define SECUMOD  ((Secumod  *)0xFC040000U) /**< \brief (SECUMOD ) Base Address */
+#define TDES     ((Tdes     *)0xFC044000U) /**< \brief (TDES    ) Base Address */
+#define CLASSD   ((Classd   *)0xFC048000U) /**< \brief (CLASSD  ) Base Address */
+#define I2SC1    ((I2sc     *)0xFC04C000U) /**< \brief (I2SC1   ) Base Address */
+#define SFRBU    ((Sfrbu    *)0xFC05C000U) /**< \brief (SFRBU   ) Base Address */
+#define CHIPID   ((Chipid   *)0xFC069000U) /**< \brief (CHIPID  ) Base Address */
+
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAMA5D21 */
+/* ************************************************************************** */
+
+/** \addtogroup SAMA5D21_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sama5d21.h"
+
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAMA5D21 */
+/* ************************************************************************** */
+
+#define IRAM_SIZE (0x20000u)
+
+#define EBI_CS0_ADDR    (0x10000000u) /**< EBI Chip Select 0 base address */
+#define DDR_CS_ADDR     (0x20000000u) /**< DDR Chip Select base address */
+#define DDR_AES_CS_ADDR (0x40000000u) /**< DDR with AES Chip Select base address */
+#define EBI_CS1_ADDR    (0x60000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x70000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x80000000u) /**< EBI Chip Select 3 base address */
+#define QSPI_AES0_ADDR  (0x90000000u) /**< QPSI Memory crypted with AES 0 base address */
+#define QSPI_AES1_ADDR  (0x98000000u) /**< QPSI Memory crypted with AES 1 base address */
+#define SDMMC1_ADDR     (0xB0000000u) /**< SDMMC 1 base address */
+#define NFC_ADDR        (0xC0000000u) /**< NAND Flash Controller Command base address */
+#define QSPIMEM0_ADDR   (0xD0000000u) /**< QSPI Memory 0 base address */
+#define QSPIMEM1_ADDR   (0xD8000000u) /**< QSPI Memory 1 base address */
+#define IROM_ADDR       (0x00000000u) /**< Internal ROM base address */
+#define ECC_ROM_ADDR    (0x00040000u) /**< ECC ROM base address */
+#define NFC_RAM_ADDR    (0x00100000u) /**< NAND Flash Controller RAM base address */
+#define IRAM0_ADDR      (0x00200000u) /**< Internal RAM 0 base address */
+#define IRAM_ADDR       IRAM0_ADDR
+#define IRAM1_ADDR      (0x00220000u) /**< Internal RAM 1 base address */
+#define UDPHS_RAM_ADDR  (0x00300000u) /**< USB High Speed Device Port RAM base address */
+#define UHPHS_OHCI_ADDR (0x00400000u) /**< USB High Speed Device Port RAM base address */
+#define UHPHS_EHCI_ADDR (0x00500000u) /**< USB High Speed Device Port RAM base address */
+#define AXIMX_ADDR      (0x00600000u) /**< AXI Bus Matrix base address */
+#define DAP_ADDR        (0x00700000u) /**< Debug Access Port base address */
+#define PTCMEM_ADDR     (0x00800000u) /**< PTC Memory base address */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAMA5D21_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d22.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d22.h
new file mode 100644
index 000000000..fc2bf3a8d
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d22.h
@@ -0,0 +1,240 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D22_
+#define _SAMA5D22_
+
+/** \addtogroup SAMA5D22_definitions SAMA5D22 definitions
+  This file defines all structures and symbols for SAMA5D22:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include <stdint.h>
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMA5D22 */
+/* ************************************************************************** */
+
+/** \addtogroup SAMA5D22_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_aesb.h"
+#include "component/component_aes.h"
+#include "component/component_aic.h"
+#include "component/component_aximx.h"
+#include "component/component_bsc.h"
+#include "component/component_chipid.h"
+#include "component/component_classd.h"
+#include "component/component_flexcom.h"
+#include "component/component_gmac.h"
+#include "component/component_i2sc.h"
+#include "component/component_icm.h"
+#include "component/component_isc.h"
+#include "component/component_l2cc.h"
+#include "component/component_lcdc.h"
+#include "component/component_matrix.h"
+#include "component/component_mcan.h"
+#include "component/component_mpddrc.h"
+#include "component/component_pdmic.h"
+#include "component/component_pio.h"
+#include "component/component_pit.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_qspi.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rxlp.h"
+#include "component/component_sckc.h"
+#include "component/component_sdmmc.h"
+#include "component/component_secumod.h"
+#include "component/component_sfc.h"
+#include "component/component_sfr.h"
+#include "component/component_sfrbu.h"
+#include "component/component_sha.h"
+#include "component/component_shdwc.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_tc.h"
+#include "component/component_tdes.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_udphs.h"
+#include "component/component_wdt.h"
+#include "component/component_xdmac.h"
+
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAMA5D22 */
+/* ************************************************************************** */
+
+/** \addtogroup SAMA5D22_base Peripheral Base Address Definitions */
+/*@{*/
+
+#define AXIMX    ((Aximx    *)0x00600000U) /**< \brief (AXIMX   ) Base Address */
+#define L2CC     ((L2cc     *)0x00A00000U) /**< \brief (L2CC    ) Base Address */
+#define SDMMC1   ((Sdmmc    *)0xB0000000U) /**< \brief (SDMMC1  ) Base Address */
+#define LCDC     ((Lcdc     *)0xF0000000U) /**< \brief (LCDC    ) Base Address */
+#define XDMAC1   ((Xdmac    *)0xF0004000U) /**< \brief (XDMAC1  ) Base Address */
+#define ISC      ((Isc      *)0xF0008000U) /**< \brief (ISC     ) Base Address */
+#define MPDDRC   ((Mpddrc   *)0xF000C000U) /**< \brief (MPDDRC  ) Base Address */
+#define XDMAC0   ((Xdmac    *)0xF0010000U) /**< \brief (XDMAC0  ) Base Address */
+#define PMC      ((Pmc      *)0xF0014000U) /**< \brief (PMC     ) Base Address */
+#define MATRIX0  ((Matrix   *)0xF0018000U) /**< \brief (MATRIX0 ) Base Address */
+#define AESB     ((Aesb     *)0xF001C000U) /**< \brief (AESB    ) Base Address */
+#define QSPI0    ((Qspi     *)0xF0020000U) /**< \brief (QSPI0   ) Base Address */
+#define QSPI1    ((Qspi     *)0xF0024000U) /**< \brief (QSPI1   ) Base Address */
+#define SHA      ((Sha      *)0xF0028000U) /**< \brief (SHA     ) Base Address */
+#define AES      ((Aes      *)0xF002C000U) /**< \brief (AES     ) Base Address */
+#define SPI0     ((Spi      *)0xF8000000U) /**< \brief (SPI0    ) Base Address */
+#define SSC0     ((Ssc      *)0xF8004000U) /**< \brief (SSC0    ) Base Address */
+#define GMAC0    ((Gmac     *)0xF8008000U) /**< \brief (GMAC0   ) Base Address */
+#define TC0      ((Tc       *)0xF800C000U) /**< \brief (TC0     ) Base Address */
+#define TC1      ((Tc       *)0xF8010000U) /**< \brief (TC1     ) Base Address */
+#define HSMC     ((Smc      *)0xF8014000U) /**< \brief (HSMC    ) Base Address */
+#define PDMIC    ((Pdmic    *)0xF8018000U) /**< \brief (PDMIC   ) Base Address */
+#define UART0    ((Uart     *)0xF801C000U) /**< \brief (UART0   ) Base Address */
+#define UART1    ((Uart     *)0xF8020000U) /**< \brief (UART1   ) Base Address */
+#define UART2    ((Uart     *)0xF8024000U) /**< \brief (UART2   ) Base Address */
+#define TWIHS0   ((Twi      *)0xF8028000U) /**< \brief (TWIHS0  ) Base Address */
+#define PWM      ((Pwm      *)0xF802C000U) /**< \brief (PWM     ) Base Address */
+#define SFR      ((Sfr      *)0xF8030000U) /**< \brief (SFR     ) Base Address */
+#define FLEXCOM0 ((Flexcom  *)0xF8034000U) /**< \brief (FLEXCOM0) Base Address */
+#define USART0   ((Usart    *)0xF8034200U) /**< \brief (FLEXCOM0_USART) Base Address */
+#define FCOMSPI0 ((Spi      *)0xF8034400U) /**< \brief (FLEXCOM0_SPI) Base Address */
+#define TWI0     ((Twi      *)0xF8034600U) /**< \brief (FLEXCOM0_TWI) Base Address */
+#define FLEXCOM1 ((Flexcom  *)0xF8038000U) /**< \brief (FLEXCOM1) Base Address */
+#define USART1   ((Usart    *)0xF8038200U) /**< \brief (FLEXCOM1_USART) Base Address */
+#define FCOMSPI1 ((Spi      *)0xF8038400U) /**< \brief (FLEXCOM1_SPI) Base Address */
+#define TWI1     ((Twi      *)0xF8038600U) /**< \brief (FLEXCOM1_TWI) Base Address */
+#define SAIC     ((Aic      *)0xF803C000U) /**< \brief (SAIC    ) Base Address */
+#define ICM      ((Icm      *)0xF8040000U) /**< \brief (ICM     ) Base Address */
+#define SECURAM  ((Securam  *)0xF8044000U) /**< \brief (SECURAM ) Base Address */
+#define RSTC     ((Rstc     *)0xF8048000U) /**< \brief (RSTC    ) Base Address */
+#define SHDWC    ((Shdwc    *)0xF8048010U) /**< \brief (SHDWC   ) Base Address */
+#define PIT      ((Pit      *)0xF8048030U) /**< \brief (PIT     ) Base Address */
+#define WDT      ((Wdt      *)0xF8048040U) /**< \brief (WDT     ) Base Address */
+#define SCKC     ((Sckc     *)0xF8048050U) /**< \brief (SCKC    ) Base Address */
+#define BSC      ((Bsc      *)0xF8048054U) /**< \brief (BSC     ) Base Address */
+#define RTC      ((Rtc      *)0xF80480B0U) /**< \brief (RTC     ) Base Address */
+#define RXLP     ((Rxlp     *)0xF8049000U) /**< \brief (RXLP    ) Base Address */
+#define ACC      ((Acc      *)0xF804A000U) /**< \brief (ACC     ) Base Address */
+#define SFC      ((Sfc      *)0xF804C000U) /**< \brief (SFC     ) Base Address */
+#define I2SC0    ((I2sc     *)0xF8050000U) /**< \brief (I2SC0   ) Base Address */
+#define MCAN0    ((Mcan     *)0xF8054000U) /**< \brief (MCAN0   ) Base Address */
+#define SPI1     ((Spi      *)0xFC000000U) /**< \brief (SPI1    ) Base Address */
+#define SSC1     ((Ssc      *)0xFC004000U) /**< \brief (SSC1    ) Base Address */
+#define UART3    ((Uart     *)0xFC008000U) /**< \brief (UART3   ) Base Address */
+#define UART4    ((Uart     *)0xFC00C000U) /**< \brief (UART4   ) Base Address */
+#define FLEXCOM3 ((Flexcom  *)0xFC014000U) /**< \brief (FLEXCOM3) Base Address */
+#define USART3   ((Usart    *)0xFC014200U) /**< \brief (FLEXCOM3_USART) Base Address */
+#define FCOMSPI3 ((Spi      *)0xFC014400U) /**< \brief (FLEXCOM3_SPI) Base Address */
+#define TWI3     ((Twi      *)0xFC014600U) /**< \brief (FLEXCOM3_TWI) Base Address */
+#define FLEXCOM4 ((Flexcom  *)0xFC018000U) /**< \brief (FLEXCOM4) Base Address */
+#define USART4   ((Usart    *)0xFC018200U) /**< \brief (FLEXCOM4_USART) Base Address */
+#define FCOMSPI4 ((Spi      *)0xFC018400U) /**< \brief (FLEXCOM4_SPI) Base Address */
+#define TWI4     ((Twi      *)0xFC018600U) /**< \brief (FLEXCOM4_TWI) Base Address */
+#define TRNG     ((Trng     *)0xFC01C000U) /**< \brief (TRNG    ) Base Address */
+#define AIC      ((Aic      *)0xFC020000U) /**< \brief (AIC     ) Base Address */
+#define TWIHS1   ((Twi      *)0xFC028000U) /**< \brief (TWIHS1  ) Base Address */
+#define UDPHS    ((Udphs    *)0xFC02C000U) /**< \brief (UDPHS   ) Base Address */
+#define ADC      ((Adc      *)0xFC030000U) /**< \brief (ADC     ) Base Address */
+#define PIOA     ((Pio      *)0xFC038000U) /**< \brief (PIOA    ) Base Address */
+#define MATRIX1  ((Matrix   *)0xFC03C000U) /**< \brief (MATRIX1 ) Base Address */
+#define SECUMOD  ((Secumod  *)0xFC040000U) /**< \brief (SECUMOD ) Base Address */
+#define TDES     ((Tdes     *)0xFC044000U) /**< \brief (TDES    ) Base Address */
+#define CLASSD   ((Classd   *)0xFC048000U) /**< \brief (CLASSD  ) Base Address */
+#define I2SC1    ((I2sc     *)0xFC04C000U) /**< \brief (I2SC1   ) Base Address */
+#define SFRBU    ((Sfrbu    *)0xFC05C000U) /**< \brief (SFRBU   ) Base Address */
+#define CHIPID   ((Chipid   *)0xFC069000U) /**< \brief (CHIPID  ) Base Address */
+
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAMA5D22 */
+/* ************************************************************************** */
+
+/** \addtogroup SAMA5D22_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sama5d22.h"
+
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAMA5D22 */
+/* ************************************************************************** */
+
+#define IRAM_SIZE (0x20000u)
+
+#define EBI_CS0_ADDR    (0x10000000u) /**< EBI Chip Select 0 base address */
+#define DDR_CS_ADDR     (0x20000000u) /**< DDR Chip Select base address */
+#define DDR_AES_CS_ADDR (0x40000000u) /**< DDR with AES Chip Select base address */
+#define EBI_CS1_ADDR    (0x60000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x70000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x80000000u) /**< EBI Chip Select 3 base address */
+#define QSPI_AES0_ADDR  (0x90000000u) /**< QPSI Memory crypted with AES 0 base address */
+#define QSPI_AES1_ADDR  (0x98000000u) /**< QPSI Memory crypted with AES 1 base address */
+#define SDMMC1_ADDR     (0xB0000000u) /**< SDMMC 1 base address */
+#define NFC_ADDR        (0xC0000000u) /**< NAND Flash Controller Command base address */
+#define QSPIMEM0_ADDR   (0xD0000000u) /**< QSPI Memory 0 base address */
+#define QSPIMEM1_ADDR   (0xD8000000u) /**< QSPI Memory 1 base address */
+#define IROM_ADDR       (0x00000000u) /**< Internal ROM base address */
+#define ECC_ROM_ADDR    (0x00040000u) /**< ECC ROM base address */
+#define NFC_RAM_ADDR    (0x00100000u) /**< NAND Flash Controller RAM base address */
+#define IRAM0_ADDR      (0x00200000u) /**< Internal RAM 0 base address */
+#define IRAM_ADDR       IRAM0_ADDR
+#define IRAM1_ADDR      (0x00220000u) /**< Internal RAM 1 base address */
+#define UDPHS_RAM_ADDR  (0x00300000u) /**< USB High Speed Device Port RAM base address */
+#define UHPHS_OHCI_ADDR (0x00400000u) /**< USB High Speed Device Port RAM base address */
+#define UHPHS_EHCI_ADDR (0x00500000u) /**< USB High Speed Device Port RAM base address */
+#define AXIMX_ADDR      (0x00600000u) /**< AXI Bus Matrix base address */
+#define DAP_ADDR        (0x00700000u) /**< Debug Access Port base address */
+#define PTCMEM_ADDR     (0x00800000u) /**< PTC Memory base address */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAMA5D22_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d23.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d23.h
new file mode 100644
index 000000000..74e5ed572
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d23.h
@@ -0,0 +1,240 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D23_
+#define _SAMA5D23_
+
+/** \addtogroup SAMA5D23_definitions SAMA5D23 definitions
+  This file defines all structures and symbols for SAMA5D23:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include <stdint.h>
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMA5D23 */
+/* ************************************************************************** */
+
+/** \addtogroup SAMA5D23_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_aesb.h"
+#include "component/component_aes.h"
+#include "component/component_aic.h"
+#include "component/component_aximx.h"
+#include "component/component_bsc.h"
+#include "component/component_chipid.h"
+#include "component/component_classd.h"
+#include "component/component_flexcom.h"
+#include "component/component_gmac.h"
+#include "component/component_i2sc.h"
+#include "component/component_icm.h"
+#include "component/component_isc.h"
+#include "component/component_l2cc.h"
+#include "component/component_lcdc.h"
+#include "component/component_matrix.h"
+#include "component/component_mcan.h"
+#include "component/component_mpddrc.h"
+#include "component/component_pdmic.h"
+#include "component/component_pio.h"
+#include "component/component_pit.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_qspi.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rxlp.h"
+#include "component/component_sckc.h"
+#include "component/component_sdmmc.h"
+#include "component/component_secumod.h"
+#include "component/component_sfc.h"
+#include "component/component_sfr.h"
+#include "component/component_sfrbu.h"
+#include "component/component_sha.h"
+#include "component/component_shdwc.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_tc.h"
+#include "component/component_tdes.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_udphs.h"
+#include "component/component_wdt.h"
+#include "component/component_xdmac.h"
+
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAMA5D23 */
+/* ************************************************************************** */
+
+/** \addtogroup SAMA5D23_base Peripheral Base Address Definitions */
+/*@{*/
+
+#define AXIMX    ((Aximx    *)0x00600000U) /**< \brief (AXIMX   ) Base Address */
+#define L2CC     ((L2cc     *)0x00A00000U) /**< \brief (L2CC    ) Base Address */
+#define SDMMC1   ((Sdmmc    *)0xB0000000U) /**< \brief (SDMMC1  ) Base Address */
+#define LCDC     ((Lcdc     *)0xF0000000U) /**< \brief (LCDC    ) Base Address */
+#define XDMAC1   ((Xdmac    *)0xF0004000U) /**< \brief (XDMAC1  ) Base Address */
+#define ISC      ((Isc      *)0xF0008000U) /**< \brief (ISC     ) Base Address */
+#define MPDDRC   ((Mpddrc   *)0xF000C000U) /**< \brief (MPDDRC  ) Base Address */
+#define XDMAC0   ((Xdmac    *)0xF0010000U) /**< \brief (XDMAC0  ) Base Address */
+#define PMC      ((Pmc      *)0xF0014000U) /**< \brief (PMC     ) Base Address */
+#define MATRIX0  ((Matrix   *)0xF0018000U) /**< \brief (MATRIX0 ) Base Address */
+#define AESB     ((Aesb     *)0xF001C000U) /**< \brief (AESB    ) Base Address */
+#define QSPI0    ((Qspi     *)0xF0020000U) /**< \brief (QSPI0   ) Base Address */
+#define QSPI1    ((Qspi     *)0xF0024000U) /**< \brief (QSPI1   ) Base Address */
+#define SHA      ((Sha      *)0xF0028000U) /**< \brief (SHA     ) Base Address */
+#define AES      ((Aes      *)0xF002C000U) /**< \brief (AES     ) Base Address */
+#define SPI0     ((Spi      *)0xF8000000U) /**< \brief (SPI0    ) Base Address */
+#define SSC0     ((Ssc      *)0xF8004000U) /**< \brief (SSC0    ) Base Address */
+#define GMAC0    ((Gmac     *)0xF8008000U) /**< \brief (GMAC0   ) Base Address */
+#define TC0      ((Tc       *)0xF800C000U) /**< \brief (TC0     ) Base Address */
+#define TC1      ((Tc       *)0xF8010000U) /**< \brief (TC1     ) Base Address */
+#define HSMC     ((Smc      *)0xF8014000U) /**< \brief (HSMC    ) Base Address */
+#define PDMIC    ((Pdmic    *)0xF8018000U) /**< \brief (PDMIC   ) Base Address */
+#define UART0    ((Uart     *)0xF801C000U) /**< \brief (UART0   ) Base Address */
+#define UART1    ((Uart     *)0xF8020000U) /**< \brief (UART1   ) Base Address */
+#define UART2    ((Uart     *)0xF8024000U) /**< \brief (UART2   ) Base Address */
+#define TWIHS0   ((Twi      *)0xF8028000U) /**< \brief (TWIHS0  ) Base Address */
+#define PWM      ((Pwm      *)0xF802C000U) /**< \brief (PWM     ) Base Address */
+#define SFR      ((Sfr      *)0xF8030000U) /**< \brief (SFR     ) Base Address */
+#define FLEXCOM0 ((Flexcom  *)0xF8034000U) /**< \brief (FLEXCOM0) Base Address */
+#define USART0   ((Usart    *)0xF8034200U) /**< \brief (FLEXCOM0_USART) Base Address */
+#define FCOMSPI0 ((Spi      *)0xF8034400U) /**< \brief (FLEXCOM0_SPI) Base Address */
+#define TWI0     ((Twi      *)0xF8034600U) /**< \brief (FLEXCOM0_TWI) Base Address */
+#define FLEXCOM1 ((Flexcom  *)0xF8038000U) /**< \brief (FLEXCOM1) Base Address */
+#define USART1   ((Usart    *)0xF8038200U) /**< \brief (FLEXCOM1_USART) Base Address */
+#define FCOMSPI1 ((Spi      *)0xF8038400U) /**< \brief (FLEXCOM1_SPI) Base Address */
+#define TWI1     ((Twi      *)0xF8038600U) /**< \brief (FLEXCOM1_TWI) Base Address */
+#define SAIC     ((Aic      *)0xF803C000U) /**< \brief (SAIC    ) Base Address */
+#define ICM      ((Icm      *)0xF8040000U) /**< \brief (ICM     ) Base Address */
+#define SECURAM  ((Securam  *)0xF8044000U) /**< \brief (SECURAM ) Base Address */
+#define RSTC     ((Rstc     *)0xF8048000U) /**< \brief (RSTC    ) Base Address */
+#define SHDWC    ((Shdwc    *)0xF8048010U) /**< \brief (SHDWC   ) Base Address */
+#define PIT      ((Pit      *)0xF8048030U) /**< \brief (PIT     ) Base Address */
+#define WDT      ((Wdt      *)0xF8048040U) /**< \brief (WDT     ) Base Address */
+#define SCKC     ((Sckc     *)0xF8048050U) /**< \brief (SCKC    ) Base Address */
+#define BSC      ((Bsc      *)0xF8048054U) /**< \brief (BSC     ) Base Address */
+#define RTC      ((Rtc      *)0xF80480B0U) /**< \brief (RTC     ) Base Address */
+#define RXLP     ((Rxlp     *)0xF8049000U) /**< \brief (RXLP    ) Base Address */
+#define ACC      ((Acc      *)0xF804A000U) /**< \brief (ACC     ) Base Address */
+#define SFC      ((Sfc      *)0xF804C000U) /**< \brief (SFC     ) Base Address */
+#define I2SC0    ((I2sc     *)0xF8050000U) /**< \brief (I2SC0   ) Base Address */
+#define MCAN0    ((Mcan     *)0xF8054000U) /**< \brief (MCAN0   ) Base Address */
+#define SPI1     ((Spi      *)0xFC000000U) /**< \brief (SPI1    ) Base Address */
+#define SSC1     ((Ssc      *)0xFC004000U) /**< \brief (SSC1    ) Base Address */
+#define UART3    ((Uart     *)0xFC008000U) /**< \brief (UART3   ) Base Address */
+#define UART4    ((Uart     *)0xFC00C000U) /**< \brief (UART4   ) Base Address */
+#define FLEXCOM3 ((Flexcom  *)0xFC014000U) /**< \brief (FLEXCOM3) Base Address */
+#define USART3   ((Usart    *)0xFC014200U) /**< \brief (FLEXCOM3_USART) Base Address */
+#define FCOMSPI3 ((Spi      *)0xFC014400U) /**< \brief (FLEXCOM3_SPI) Base Address */
+#define TWI3     ((Twi      *)0xFC014600U) /**< \brief (FLEXCOM3_TWI) Base Address */
+#define FLEXCOM4 ((Flexcom  *)0xFC018000U) /**< \brief (FLEXCOM4) Base Address */
+#define USART4   ((Usart    *)0xFC018200U) /**< \brief (FLEXCOM4_USART) Base Address */
+#define FCOMSPI4 ((Spi      *)0xFC018400U) /**< \brief (FLEXCOM4_SPI) Base Address */
+#define TWI4     ((Twi      *)0xFC018600U) /**< \brief (FLEXCOM4_TWI) Base Address */
+#define TRNG     ((Trng     *)0xFC01C000U) /**< \brief (TRNG    ) Base Address */
+#define AIC      ((Aic      *)0xFC020000U) /**< \brief (AIC     ) Base Address */
+#define TWIHS1   ((Twi      *)0xFC028000U) /**< \brief (TWIHS1  ) Base Address */
+#define UDPHS    ((Udphs    *)0xFC02C000U) /**< \brief (UDPHS   ) Base Address */
+#define ADC      ((Adc      *)0xFC030000U) /**< \brief (ADC     ) Base Address */
+#define PIOA     ((Pio      *)0xFC038000U) /**< \brief (PIOA    ) Base Address */
+#define MATRIX1  ((Matrix   *)0xFC03C000U) /**< \brief (MATRIX1 ) Base Address */
+#define SECUMOD  ((Secumod  *)0xFC040000U) /**< \brief (SECUMOD ) Base Address */
+#define TDES     ((Tdes     *)0xFC044000U) /**< \brief (TDES    ) Base Address */
+#define CLASSD   ((Classd   *)0xFC048000U) /**< \brief (CLASSD  ) Base Address */
+#define I2SC1    ((I2sc     *)0xFC04C000U) /**< \brief (I2SC1   ) Base Address */
+#define SFRBU    ((Sfrbu    *)0xFC05C000U) /**< \brief (SFRBU   ) Base Address */
+#define CHIPID   ((Chipid   *)0xFC069000U) /**< \brief (CHIPID  ) Base Address */
+
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAMA5D23 */
+/* ************************************************************************** */
+
+/** \addtogroup SAMA5D23_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sama5d23.h"
+
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAMA5D23 */
+/* ************************************************************************** */
+
+#define IRAM_SIZE (0x20000u)
+
+#define EBI_CS0_ADDR    (0x10000000u) /**< EBI Chip Select 0 base address */
+#define DDR_CS_ADDR     (0x20000000u) /**< DDR Chip Select base address */
+#define DDR_AES_CS_ADDR (0x40000000u) /**< DDR with AES Chip Select base address */
+#define EBI_CS1_ADDR    (0x60000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x70000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x80000000u) /**< EBI Chip Select 3 base address */
+#define QSPI_AES0_ADDR  (0x90000000u) /**< QPSI Memory crypted with AES 0 base address */
+#define QSPI_AES1_ADDR  (0x98000000u) /**< QPSI Memory crypted with AES 1 base address */
+#define SDMMC1_ADDR     (0xB0000000u) /**< SDMMC 1 base address */
+#define NFC_ADDR        (0xC0000000u) /**< NAND Flash Controller Command base address */
+#define QSPIMEM0_ADDR   (0xD0000000u) /**< QSPI Memory 0 base address */
+#define QSPIMEM1_ADDR   (0xD8000000u) /**< QSPI Memory 1 base address */
+#define IROM_ADDR       (0x00000000u) /**< Internal ROM base address */
+#define ECC_ROM_ADDR    (0x00040000u) /**< ECC ROM base address */
+#define NFC_RAM_ADDR    (0x00100000u) /**< NAND Flash Controller RAM base address */
+#define IRAM0_ADDR      (0x00200000u) /**< Internal RAM 0 base address */
+#define IRAM_ADDR       IRAM0_ADDR
+#define IRAM1_ADDR      (0x00220000u) /**< Internal RAM 1 base address */
+#define UDPHS_RAM_ADDR  (0x00300000u) /**< USB High Speed Device Port RAM base address */
+#define UHPHS_OHCI_ADDR (0x00400000u) /**< USB High Speed Device Port RAM base address */
+#define UHPHS_EHCI_ADDR (0x00500000u) /**< USB High Speed Device Port RAM base address */
+#define AXIMX_ADDR      (0x00600000u) /**< AXI Bus Matrix base address */
+#define DAP_ADDR        (0x00700000u) /**< Debug Access Port base address */
+#define PTCMEM_ADDR     (0x00800000u) /**< PTC Memory base address */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAMA5D23_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d24.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d24.h
new file mode 100644
index 000000000..99264583c
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d24.h
@@ -0,0 +1,244 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D24_
+#define _SAMA5D24_
+
+/** \addtogroup SAMA5D24_definitions SAMA5D24 definitions
+  This file defines all structures and symbols for SAMA5D24:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include <stdint.h>
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMA5D24 */
+/* ************************************************************************** */
+
+/** \addtogroup SAMA5D24_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_aesb.h"
+#include "component/component_aes.h"
+#include "component/component_aic.h"
+#include "component/component_aximx.h"
+#include "component/component_bsc.h"
+#include "component/component_chipid.h"
+#include "component/component_classd.h"
+#include "component/component_flexcom.h"
+#include "component/component_gmac.h"
+#include "component/component_i2sc.h"
+#include "component/component_icm.h"
+#include "component/component_isc.h"
+#include "component/component_l2cc.h"
+#include "component/component_lcdc.h"
+#include "component/component_matrix.h"
+#include "component/component_mpddrc.h"
+#include "component/component_pdmic.h"
+#include "component/component_pio.h"
+#include "component/component_pit.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_qspi.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rxlp.h"
+#include "component/component_sckc.h"
+#include "component/component_sdmmc.h"
+#include "component/component_secumod.h"
+#include "component/component_sfc.h"
+#include "component/component_sfr.h"
+#include "component/component_sfrbu.h"
+#include "component/component_sha.h"
+#include "component/component_shdwc.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_tc.h"
+#include "component/component_tdes.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_udphs.h"
+#include "component/component_wdt.h"
+#include "component/component_xdmac.h"
+
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAMA5D24 */
+/* ************************************************************************** */
+
+/** \addtogroup SAMA5D24_base Peripheral Base Address Definitions */
+/*@{*/
+
+#define AXIMX    ((Aximx    *)0x00600000U) /**< \brief (AXIMX   ) Base Address */
+#define L2CC     ((L2cc     *)0x00A00000U) /**< \brief (L2CC    ) Base Address */
+#define SDMMC0   ((Sdmmc    *)0xA0000000U) /**< \brief (SDMMC0  ) Base Address */
+#define SDMMC1   ((Sdmmc    *)0xB0000000U) /**< \brief (SDMMC1  ) Base Address */
+#define LCDC     ((Lcdc     *)0xF0000000U) /**< \brief (LCDC    ) Base Address */
+#define XDMAC1   ((Xdmac    *)0xF0004000U) /**< \brief (XDMAC1  ) Base Address */
+#define ISC      ((Isc      *)0xF0008000U) /**< \brief (ISC     ) Base Address */
+#define MPDDRC   ((Mpddrc   *)0xF000C000U) /**< \brief (MPDDRC  ) Base Address */
+#define XDMAC0   ((Xdmac    *)0xF0010000U) /**< \brief (XDMAC0  ) Base Address */
+#define PMC      ((Pmc      *)0xF0014000U) /**< \brief (PMC     ) Base Address */
+#define MATRIX0  ((Matrix   *)0xF0018000U) /**< \brief (MATRIX0 ) Base Address */
+#define AESB     ((Aesb     *)0xF001C000U) /**< \brief (AESB    ) Base Address */
+#define QSPI0    ((Qspi     *)0xF0020000U) /**< \brief (QSPI0   ) Base Address */
+#define QSPI1    ((Qspi     *)0xF0024000U) /**< \brief (QSPI1   ) Base Address */
+#define SHA      ((Sha      *)0xF0028000U) /**< \brief (SHA     ) Base Address */
+#define AES      ((Aes      *)0xF002C000U) /**< \brief (AES     ) Base Address */
+#define SPI0     ((Spi      *)0xF8000000U) /**< \brief (SPI0    ) Base Address */
+#define SSC0     ((Ssc      *)0xF8004000U) /**< \brief (SSC0    ) Base Address */
+#define GMAC0    ((Gmac     *)0xF8008000U) /**< \brief (GMAC0   ) Base Address */
+#define TC0      ((Tc       *)0xF800C000U) /**< \brief (TC0     ) Base Address */
+#define TC1      ((Tc       *)0xF8010000U) /**< \brief (TC1     ) Base Address */
+#define HSMC     ((Smc      *)0xF8014000U) /**< \brief (HSMC    ) Base Address */
+#define PDMIC    ((Pdmic    *)0xF8018000U) /**< \brief (PDMIC   ) Base Address */
+#define UART0    ((Uart     *)0xF801C000U) /**< \brief (UART0   ) Base Address */
+#define UART1    ((Uart     *)0xF8020000U) /**< \brief (UART1   ) Base Address */
+#define UART2    ((Uart     *)0xF8024000U) /**< \brief (UART2   ) Base Address */
+#define TWIHS0   ((Twi      *)0xF8028000U) /**< \brief (TWIHS0  ) Base Address */
+#define PWM      ((Pwm      *)0xF802C000U) /**< \brief (PWM     ) Base Address */
+#define SFR      ((Sfr      *)0xF8030000U) /**< \brief (SFR     ) Base Address */
+#define FLEXCOM0 ((Flexcom  *)0xF8034000U) /**< \brief (FLEXCOM0) Base Address */
+#define USART0   ((Usart    *)0xF8034200U) /**< \brief (FLEXCOM0_USART) Base Address */
+#define FCOMSPI0 ((Spi      *)0xF8034400U) /**< \brief (FLEXCOM0_SPI) Base Address */
+#define TWI0     ((Twi      *)0xF8034600U) /**< \brief (FLEXCOM0_TWI) Base Address */
+#define FLEXCOM1 ((Flexcom  *)0xF8038000U) /**< \brief (FLEXCOM1) Base Address */
+#define USART1   ((Usart    *)0xF8038200U) /**< \brief (FLEXCOM1_USART) Base Address */
+#define FCOMSPI1 ((Spi      *)0xF8038400U) /**< \brief (FLEXCOM1_SPI) Base Address */
+#define TWI1     ((Twi      *)0xF8038600U) /**< \brief (FLEXCOM1_TWI) Base Address */
+#define SAIC     ((Aic      *)0xF803C000U) /**< \brief (SAIC    ) Base Address */
+#define ICM      ((Icm      *)0xF8040000U) /**< \brief (ICM     ) Base Address */
+#define SECURAM  ((Securam  *)0xF8044000U) /**< \brief (SECURAM ) Base Address */
+#define RSTC     ((Rstc     *)0xF8048000U) /**< \brief (RSTC    ) Base Address */
+#define SHDWC    ((Shdwc    *)0xF8048010U) /**< \brief (SHDWC   ) Base Address */
+#define PIT      ((Pit      *)0xF8048030U) /**< \brief (PIT     ) Base Address */
+#define WDT      ((Wdt      *)0xF8048040U) /**< \brief (WDT     ) Base Address */
+#define SCKC     ((Sckc     *)0xF8048050U) /**< \brief (SCKC    ) Base Address */
+#define BSC      ((Bsc      *)0xF8048054U) /**< \brief (BSC     ) Base Address */
+#define RTC      ((Rtc      *)0xF80480B0U) /**< \brief (RTC     ) Base Address */
+#define RXLP     ((Rxlp     *)0xF8049000U) /**< \brief (RXLP    ) Base Address */
+#define ACC      ((Acc      *)0xF804A000U) /**< \brief (ACC     ) Base Address */
+#define SFC      ((Sfc      *)0xF804C000U) /**< \brief (SFC     ) Base Address */
+#define I2SC0    ((I2sc     *)0xF8050000U) /**< \brief (I2SC0   ) Base Address */
+#define SPI1     ((Spi      *)0xFC000000U) /**< \brief (SPI1    ) Base Address */
+#define SSC1     ((Ssc      *)0xFC004000U) /**< \brief (SSC1    ) Base Address */
+#define UART3    ((Uart     *)0xFC008000U) /**< \brief (UART3   ) Base Address */
+#define UART4    ((Uart     *)0xFC00C000U) /**< \brief (UART4   ) Base Address */
+#define FLEXCOM2 ((Flexcom  *)0xFC010000U) /**< \brief (FLEXCOM2) Base Address */
+#define USART2   ((Usart    *)0xFC010200U) /**< \brief (FLEXCOM2_USART) Base Address */
+#define FCOMSPI2 ((Spi      *)0xFC010400U) /**< \brief (FLEXCOM2_SPI) Base Address */
+#define TWI2     ((Twi      *)0xFC010600U) /**< \brief (FLEXCOM2_TWI) Base Address */
+#define FLEXCOM3 ((Flexcom  *)0xFC014000U) /**< \brief (FLEXCOM3) Base Address */
+#define USART3   ((Usart    *)0xFC014200U) /**< \brief (FLEXCOM3_USART) Base Address */
+#define FCOMSPI3 ((Spi      *)0xFC014400U) /**< \brief (FLEXCOM3_SPI) Base Address */
+#define TWI3     ((Twi      *)0xFC014600U) /**< \brief (FLEXCOM3_TWI) Base Address */
+#define FLEXCOM4 ((Flexcom  *)0xFC018000U) /**< \brief (FLEXCOM4) Base Address */
+#define USART4   ((Usart    *)0xFC018200U) /**< \brief (FLEXCOM4_USART) Base Address */
+#define FCOMSPI4 ((Spi      *)0xFC018400U) /**< \brief (FLEXCOM4_SPI) Base Address */
+#define TWI4     ((Twi      *)0xFC018600U) /**< \brief (FLEXCOM4_TWI) Base Address */
+#define TRNG     ((Trng     *)0xFC01C000U) /**< \brief (TRNG    ) Base Address */
+#define AIC      ((Aic      *)0xFC020000U) /**< \brief (AIC     ) Base Address */
+#define TWIHS1   ((Twi      *)0xFC028000U) /**< \brief (TWIHS1  ) Base Address */
+#define UDPHS    ((Udphs    *)0xFC02C000U) /**< \brief (UDPHS   ) Base Address */
+#define ADC      ((Adc      *)0xFC030000U) /**< \brief (ADC     ) Base Address */
+#define PIOA     ((Pio      *)0xFC038000U) /**< \brief (PIOA    ) Base Address */
+#define MATRIX1  ((Matrix   *)0xFC03C000U) /**< \brief (MATRIX1 ) Base Address */
+#define SECUMOD  ((Secumod  *)0xFC040000U) /**< \brief (SECUMOD ) Base Address */
+#define TDES     ((Tdes     *)0xFC044000U) /**< \brief (TDES    ) Base Address */
+#define CLASSD   ((Classd   *)0xFC048000U) /**< \brief (CLASSD  ) Base Address */
+#define I2SC1    ((I2sc     *)0xFC04C000U) /**< \brief (I2SC1   ) Base Address */
+#define SFRBU    ((Sfrbu    *)0xFC05C000U) /**< \brief (SFRBU   ) Base Address */
+#define CHIPID   ((Chipid   *)0xFC069000U) /**< \brief (CHIPID  ) Base Address */
+
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAMA5D24 */
+/* ************************************************************************** */
+
+/** \addtogroup SAMA5D24_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sama5d24.h"
+
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAMA5D24 */
+/* ************************************************************************** */
+
+#define IRAM_SIZE (0x20000u)
+
+#define EBI_CS0_ADDR    (0x10000000u) /**< EBI Chip Select 0 base address */
+#define DDR_CS_ADDR     (0x20000000u) /**< DDR Chip Select base address */
+#define DDR_AES_CS_ADDR (0x40000000u) /**< DDR with AES Chip Select base address */
+#define EBI_CS1_ADDR    (0x60000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x70000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x80000000u) /**< EBI Chip Select 3 base address */
+#define QSPI_AES0_ADDR  (0x90000000u) /**< QPSI Memory crypted with AES 0 base address */
+#define QSPI_AES1_ADDR  (0x98000000u) /**< QPSI Memory crypted with AES 1 base address */
+#define SDMMC0_ADDR     (0xA0000000u) /**< SDMMC 0 base address */
+#define SDMMC1_ADDR     (0xB0000000u) /**< SDMMC 1 base address */
+#define NFC_ADDR        (0xC0000000u) /**< NAND Flash Controller Command base address */
+#define QSPIMEM0_ADDR   (0xD0000000u) /**< QSPI Memory 0 base address */
+#define QSPIMEM1_ADDR   (0xD8000000u) /**< QSPI Memory 1 base address */
+#define IROM_ADDR       (0x00000000u) /**< Internal ROM base address */
+#define ECC_ROM_ADDR    (0x00040000u) /**< ECC ROM base address */
+#define NFC_RAM_ADDR    (0x00100000u) /**< NAND Flash Controller RAM base address */
+#define IRAM0_ADDR      (0x00200000u) /**< Internal RAM 0 base address */
+#define IRAM_ADDR       IRAM0_ADDR
+#define IRAM1_ADDR      (0x00220000u) /**< Internal RAM 1 base address */
+#define UDPHS_RAM_ADDR  (0x00300000u) /**< USB High Speed Device Port RAM base address */
+#define UHPHS_OHCI_ADDR (0x00400000u) /**< USB High Speed Device Port RAM base address */
+#define UHPHS_EHCI_ADDR (0x00500000u) /**< USB High Speed Device Port RAM base address */
+#define AXIMX_ADDR      (0x00600000u) /**< AXI Bus Matrix base address */
+#define DAP_ADDR        (0x00700000u) /**< Debug Access Port base address */
+#define PTCMEM_ADDR     (0x00800000u) /**< PTC Memory base address */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAMA5D24_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d26.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d26.h
new file mode 100644
index 000000000..6592ee9f9
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d26.h
@@ -0,0 +1,244 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D26_
+#define _SAMA5D26_
+
+/** \addtogroup SAMA5D26_definitions SAMA5D26 definitions
+  This file defines all structures and symbols for SAMA5D26:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include <stdint.h>
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMA5D26 */
+/* ************************************************************************** */
+
+/** \addtogroup SAMA5D26_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_aesb.h"
+#include "component/component_aes.h"
+#include "component/component_aic.h"
+#include "component/component_aximx.h"
+#include "component/component_bsc.h"
+#include "component/component_chipid.h"
+#include "component/component_classd.h"
+#include "component/component_flexcom.h"
+#include "component/component_gmac.h"
+#include "component/component_i2sc.h"
+#include "component/component_icm.h"
+#include "component/component_isc.h"
+#include "component/component_l2cc.h"
+#include "component/component_lcdc.h"
+#include "component/component_matrix.h"
+#include "component/component_mpddrc.h"
+#include "component/component_pdmic.h"
+#include "component/component_pio.h"
+#include "component/component_pit.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_qspi.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rxlp.h"
+#include "component/component_sckc.h"
+#include "component/component_sdmmc.h"
+#include "component/component_secumod.h"
+#include "component/component_sfc.h"
+#include "component/component_sfr.h"
+#include "component/component_sfrbu.h"
+#include "component/component_sha.h"
+#include "component/component_shdwc.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_tc.h"
+#include "component/component_tdes.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_udphs.h"
+#include "component/component_wdt.h"
+#include "component/component_xdmac.h"
+
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAMA5D26 */
+/* ************************************************************************** */
+
+/** \addtogroup SAMA5D26_base Peripheral Base Address Definitions */
+/*@{*/
+
+#define AXIMX    ((Aximx    *)0x00600000U) /**< \brief (AXIMX   ) Base Address */
+#define L2CC     ((L2cc     *)0x00A00000U) /**< \brief (L2CC    ) Base Address */
+#define SDMMC0   ((Sdmmc    *)0xA0000000U) /**< \brief (SDMMC0  ) Base Address */
+#define SDMMC1   ((Sdmmc    *)0xB0000000U) /**< \brief (SDMMC1  ) Base Address */
+#define LCDC     ((Lcdc     *)0xF0000000U) /**< \brief (LCDC    ) Base Address */
+#define XDMAC1   ((Xdmac    *)0xF0004000U) /**< \brief (XDMAC1  ) Base Address */
+#define ISC      ((Isc      *)0xF0008000U) /**< \brief (ISC     ) Base Address */
+#define MPDDRC   ((Mpddrc   *)0xF000C000U) /**< \brief (MPDDRC  ) Base Address */
+#define XDMAC0   ((Xdmac    *)0xF0010000U) /**< \brief (XDMAC0  ) Base Address */
+#define PMC      ((Pmc      *)0xF0014000U) /**< \brief (PMC     ) Base Address */
+#define MATRIX0  ((Matrix   *)0xF0018000U) /**< \brief (MATRIX0 ) Base Address */
+#define AESB     ((Aesb     *)0xF001C000U) /**< \brief (AESB    ) Base Address */
+#define QSPI0    ((Qspi     *)0xF0020000U) /**< \brief (QSPI0   ) Base Address */
+#define QSPI1    ((Qspi     *)0xF0024000U) /**< \brief (QSPI1   ) Base Address */
+#define SHA      ((Sha      *)0xF0028000U) /**< \brief (SHA     ) Base Address */
+#define AES      ((Aes      *)0xF002C000U) /**< \brief (AES     ) Base Address */
+#define SPI0     ((Spi      *)0xF8000000U) /**< \brief (SPI0    ) Base Address */
+#define SSC0     ((Ssc      *)0xF8004000U) /**< \brief (SSC0    ) Base Address */
+#define GMAC0    ((Gmac     *)0xF8008000U) /**< \brief (GMAC0   ) Base Address */
+#define TC0      ((Tc       *)0xF800C000U) /**< \brief (TC0     ) Base Address */
+#define TC1      ((Tc       *)0xF8010000U) /**< \brief (TC1     ) Base Address */
+#define HSMC     ((Smc      *)0xF8014000U) /**< \brief (HSMC    ) Base Address */
+#define PDMIC    ((Pdmic    *)0xF8018000U) /**< \brief (PDMIC   ) Base Address */
+#define UART0    ((Uart     *)0xF801C000U) /**< \brief (UART0   ) Base Address */
+#define UART1    ((Uart     *)0xF8020000U) /**< \brief (UART1   ) Base Address */
+#define UART2    ((Uart     *)0xF8024000U) /**< \brief (UART2   ) Base Address */
+#define TWIHS0   ((Twi      *)0xF8028000U) /**< \brief (TWIHS0  ) Base Address */
+#define PWM      ((Pwm      *)0xF802C000U) /**< \brief (PWM     ) Base Address */
+#define SFR      ((Sfr      *)0xF8030000U) /**< \brief (SFR     ) Base Address */
+#define FLEXCOM0 ((Flexcom  *)0xF8034000U) /**< \brief (FLEXCOM0) Base Address */
+#define USART0   ((Usart    *)0xF8034200U) /**< \brief (FLEXCOM0_USART) Base Address */
+#define FCOMSPI0 ((Spi      *)0xF8034400U) /**< \brief (FLEXCOM0_SPI) Base Address */
+#define TWI0     ((Twi      *)0xF8034600U) /**< \brief (FLEXCOM0_TWI) Base Address */
+#define FLEXCOM1 ((Flexcom  *)0xF8038000U) /**< \brief (FLEXCOM1) Base Address */
+#define USART1   ((Usart    *)0xF8038200U) /**< \brief (FLEXCOM1_USART) Base Address */
+#define FCOMSPI1 ((Spi      *)0xF8038400U) /**< \brief (FLEXCOM1_SPI) Base Address */
+#define TWI1     ((Twi      *)0xF8038600U) /**< \brief (FLEXCOM1_TWI) Base Address */
+#define SAIC     ((Aic      *)0xF803C000U) /**< \brief (SAIC    ) Base Address */
+#define ICM      ((Icm      *)0xF8040000U) /**< \brief (ICM     ) Base Address */
+#define SECURAM  ((Securam  *)0xF8044000U) /**< \brief (SECURAM ) Base Address */
+#define RSTC     ((Rstc     *)0xF8048000U) /**< \brief (RSTC    ) Base Address */
+#define SHDWC    ((Shdwc    *)0xF8048010U) /**< \brief (SHDWC   ) Base Address */
+#define PIT      ((Pit      *)0xF8048030U) /**< \brief (PIT     ) Base Address */
+#define WDT      ((Wdt      *)0xF8048040U) /**< \brief (WDT     ) Base Address */
+#define SCKC     ((Sckc     *)0xF8048050U) /**< \brief (SCKC    ) Base Address */
+#define BSC      ((Bsc      *)0xF8048054U) /**< \brief (BSC     ) Base Address */
+#define RTC      ((Rtc      *)0xF80480B0U) /**< \brief (RTC     ) Base Address */
+#define RXLP     ((Rxlp     *)0xF8049000U) /**< \brief (RXLP    ) Base Address */
+#define ACC      ((Acc      *)0xF804A000U) /**< \brief (ACC     ) Base Address */
+#define SFC      ((Sfc      *)0xF804C000U) /**< \brief (SFC     ) Base Address */
+#define I2SC0    ((I2sc     *)0xF8050000U) /**< \brief (I2SC0   ) Base Address */
+#define SPI1     ((Spi      *)0xFC000000U) /**< \brief (SPI1    ) Base Address */
+#define SSC1     ((Ssc      *)0xFC004000U) /**< \brief (SSC1    ) Base Address */
+#define UART3    ((Uart     *)0xFC008000U) /**< \brief (UART3   ) Base Address */
+#define UART4    ((Uart     *)0xFC00C000U) /**< \brief (UART4   ) Base Address */
+#define FLEXCOM2 ((Flexcom  *)0xFC010000U) /**< \brief (FLEXCOM2) Base Address */
+#define USART2   ((Usart    *)0xFC010200U) /**< \brief (FLEXCOM2_USART) Base Address */
+#define FCOMSPI2 ((Spi      *)0xFC010400U) /**< \brief (FLEXCOM2_SPI) Base Address */
+#define TWI2     ((Twi      *)0xFC010600U) /**< \brief (FLEXCOM2_TWI) Base Address */
+#define FLEXCOM3 ((Flexcom  *)0xFC014000U) /**< \brief (FLEXCOM3) Base Address */
+#define USART3   ((Usart    *)0xFC014200U) /**< \brief (FLEXCOM3_USART) Base Address */
+#define FCOMSPI3 ((Spi      *)0xFC014400U) /**< \brief (FLEXCOM3_SPI) Base Address */
+#define TWI3     ((Twi      *)0xFC014600U) /**< \brief (FLEXCOM3_TWI) Base Address */
+#define FLEXCOM4 ((Flexcom  *)0xFC018000U) /**< \brief (FLEXCOM4) Base Address */
+#define USART4   ((Usart    *)0xFC018200U) /**< \brief (FLEXCOM4_USART) Base Address */
+#define FCOMSPI4 ((Spi      *)0xFC018400U) /**< \brief (FLEXCOM4_SPI) Base Address */
+#define TWI4     ((Twi      *)0xFC018600U) /**< \brief (FLEXCOM4_TWI) Base Address */
+#define TRNG     ((Trng     *)0xFC01C000U) /**< \brief (TRNG    ) Base Address */
+#define AIC      ((Aic      *)0xFC020000U) /**< \brief (AIC     ) Base Address */
+#define TWIHS1   ((Twi      *)0xFC028000U) /**< \brief (TWIHS1  ) Base Address */
+#define UDPHS    ((Udphs    *)0xFC02C000U) /**< \brief (UDPHS   ) Base Address */
+#define ADC      ((Adc      *)0xFC030000U) /**< \brief (ADC     ) Base Address */
+#define PIOA     ((Pio      *)0xFC038000U) /**< \brief (PIOA    ) Base Address */
+#define MATRIX1  ((Matrix   *)0xFC03C000U) /**< \brief (MATRIX1 ) Base Address */
+#define SECUMOD  ((Secumod  *)0xFC040000U) /**< \brief (SECUMOD ) Base Address */
+#define TDES     ((Tdes     *)0xFC044000U) /**< \brief (TDES    ) Base Address */
+#define CLASSD   ((Classd   *)0xFC048000U) /**< \brief (CLASSD  ) Base Address */
+#define I2SC1    ((I2sc     *)0xFC04C000U) /**< \brief (I2SC1   ) Base Address */
+#define SFRBU    ((Sfrbu    *)0xFC05C000U) /**< \brief (SFRBU   ) Base Address */
+#define CHIPID   ((Chipid   *)0xFC069000U) /**< \brief (CHIPID  ) Base Address */
+
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAMA5D26 */
+/* ************************************************************************** */
+
+/** \addtogroup SAMA5D26_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sama5d26.h"
+
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAMA5D26 */
+/* ************************************************************************** */
+
+#define IRAM_SIZE (0x20000u)
+
+#define EBI_CS0_ADDR    (0x10000000u) /**< EBI Chip Select 0 base address */
+#define DDR_CS_ADDR     (0x20000000u) /**< DDR Chip Select base address */
+#define DDR_AES_CS_ADDR (0x40000000u) /**< DDR with AES Chip Select base address */
+#define EBI_CS1_ADDR    (0x60000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x70000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x80000000u) /**< EBI Chip Select 3 base address */
+#define QSPI_AES0_ADDR  (0x90000000u) /**< QPSI Memory crypted with AES 0 base address */
+#define QSPI_AES1_ADDR  (0x98000000u) /**< QPSI Memory crypted with AES 1 base address */
+#define SDMMC0_ADDR     (0xA0000000u) /**< SDMMC 0 base address */
+#define SDMMC1_ADDR     (0xB0000000u) /**< SDMMC 1 base address */
+#define NFC_ADDR        (0xC0000000u) /**< NAND Flash Controller Command base address */
+#define QSPIMEM0_ADDR   (0xD0000000u) /**< QSPI Memory 0 base address */
+#define QSPIMEM1_ADDR   (0xD8000000u) /**< QSPI Memory 1 base address */
+#define IROM_ADDR       (0x00000000u) /**< Internal ROM base address */
+#define ECC_ROM_ADDR    (0x00040000u) /**< ECC ROM base address */
+#define NFC_RAM_ADDR    (0x00100000u) /**< NAND Flash Controller RAM base address */
+#define IRAM0_ADDR      (0x00200000u) /**< Internal RAM 0 base address */
+#define IRAM_ADDR       IRAM0_ADDR
+#define IRAM1_ADDR      (0x00220000u) /**< Internal RAM 1 base address */
+#define UDPHS_RAM_ADDR  (0x00300000u) /**< USB High Speed Device Port RAM base address */
+#define UHPHS_OHCI_ADDR (0x00400000u) /**< USB High Speed Device Port RAM base address */
+#define UHPHS_EHCI_ADDR (0x00500000u) /**< USB High Speed Device Port RAM base address */
+#define AXIMX_ADDR      (0x00600000u) /**< AXI Bus Matrix base address */
+#define DAP_ADDR        (0x00700000u) /**< Debug Access Port base address */
+#define PTCMEM_ADDR     (0x00800000u) /**< PTC Memory base address */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAMA5D26_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d27.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d27.h
new file mode 100644
index 000000000..70ffabf7c
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d27.h
@@ -0,0 +1,246 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D27_
+#define _SAMA5D27_
+
+/** \addtogroup SAMA5D27_definitions SAMA5D27 definitions
+  This file defines all structures and symbols for SAMA5D27:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include <stdint.h>
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMA5D27 */
+/* ************************************************************************** */
+
+/** \addtogroup SAMA5D27_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_aesb.h"
+#include "component/component_aes.h"
+#include "component/component_aic.h"
+#include "component/component_aximx.h"
+#include "component/component_bsc.h"
+#include "component/component_chipid.h"
+#include "component/component_classd.h"
+#include "component/component_flexcom.h"
+#include "component/component_gmac.h"
+#include "component/component_i2sc.h"
+#include "component/component_icm.h"
+#include "component/component_isc.h"
+#include "component/component_l2cc.h"
+#include "component/component_lcdc.h"
+#include "component/component_matrix.h"
+#include "component/component_mcan.h"
+#include "component/component_mpddrc.h"
+#include "component/component_pdmic.h"
+#include "component/component_pio.h"
+#include "component/component_pit.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_qspi.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rxlp.h"
+#include "component/component_sckc.h"
+#include "component/component_sdmmc.h"
+#include "component/component_secumod.h"
+#include "component/component_sfc.h"
+#include "component/component_sfr.h"
+#include "component/component_sfrbu.h"
+#include "component/component_sha.h"
+#include "component/component_shdwc.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_tc.h"
+#include "component/component_tdes.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_udphs.h"
+#include "component/component_wdt.h"
+#include "component/component_xdmac.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAMA5D27 */
+/* ************************************************************************** */
+
+/** \addtogroup SAMA5D27_base Peripheral Base Address Definitions */
+/*@{*/
+
+#define AXIMX    ((Aximx    *)0x00600000U) /**< \brief (AXIMX   ) Base Address */
+#define L2CC     ((L2cc     *)0x00A00000U) /**< \brief (L2CC    ) Base Address */
+#define SDMMC0   ((Sdmmc    *)0xA0000000U) /**< \brief (SDMMC0  ) Base Address */
+#define SDMMC1   ((Sdmmc    *)0xB0000000U) /**< \brief (SDMMC1  ) Base Address */
+#define LCDC     ((Lcdc     *)0xF0000000U) /**< \brief (LCDC    ) Base Address */
+#define XDMAC1   ((Xdmac    *)0xF0004000U) /**< \brief (XDMAC1  ) Base Address */
+#define ISC      ((Isc      *)0xF0008000U) /**< \brief (ISC     ) Base Address */
+#define MPDDRC   ((Mpddrc   *)0xF000C000U) /**< \brief (MPDDRC  ) Base Address */
+#define XDMAC0   ((Xdmac    *)0xF0010000U) /**< \brief (XDMAC0  ) Base Address */
+#define PMC      ((Pmc      *)0xF0014000U) /**< \brief (PMC     ) Base Address */
+#define MATRIX0  ((Matrix   *)0xF0018000U) /**< \brief (MATRIX0 ) Base Address */
+#define AESB     ((Aesb     *)0xF001C000U) /**< \brief (AESB    ) Base Address */
+#define QSPI0    ((Qspi     *)0xF0020000U) /**< \brief (QSPI0   ) Base Address */
+#define QSPI1    ((Qspi     *)0xF0024000U) /**< \brief (QSPI1   ) Base Address */
+#define SHA      ((Sha      *)0xF0028000U) /**< \brief (SHA     ) Base Address */
+#define AES      ((Aes      *)0xF002C000U) /**< \brief (AES     ) Base Address */
+#define SPI0     ((Spi      *)0xF8000000U) /**< \brief (SPI0    ) Base Address */
+#define SSC0     ((Ssc      *)0xF8004000U) /**< \brief (SSC0    ) Base Address */
+#define GMAC0    ((Gmac     *)0xF8008000U) /**< \brief (GMAC0   ) Base Address */
+#define TC0      ((Tc       *)0xF800C000U) /**< \brief (TC0     ) Base Address */
+#define TC1      ((Tc       *)0xF8010000U) /**< \brief (TC1     ) Base Address */
+#define HSMC     ((Smc      *)0xF8014000U) /**< \brief (HSMC    ) Base Address */
+#define PDMIC    ((Pdmic    *)0xF8018000U) /**< \brief (PDMIC   ) Base Address */
+#define UART0    ((Uart     *)0xF801C000U) /**< \brief (UART0   ) Base Address */
+#define UART1    ((Uart     *)0xF8020000U) /**< \brief (UART1   ) Base Address */
+#define UART2    ((Uart     *)0xF8024000U) /**< \brief (UART2   ) Base Address */
+#define TWIHS0   ((Twi      *)0xF8028000U) /**< \brief (TWIHS0  ) Base Address */
+#define PWM      ((Pwm      *)0xF802C000U) /**< \brief (PWM     ) Base Address */
+#define SFR      ((Sfr      *)0xF8030000U) /**< \brief (SFR     ) Base Address */
+#define FLEXCOM0 ((Flexcom  *)0xF8034000U) /**< \brief (FLEXCOM0) Base Address */
+#define USART0   ((Usart    *)0xF8034200U) /**< \brief (FLEXCOM0_USART) Base Address */
+#define FCOMSPI0 ((Spi      *)0xF8034400U) /**< \brief (FLEXCOM0_SPI) Base Address */
+#define TWI0     ((Twi      *)0xF8034600U) /**< \brief (FLEXCOM0_TWI) Base Address */
+#define FLEXCOM1 ((Flexcom  *)0xF8038000U) /**< \brief (FLEXCOM1) Base Address */
+#define USART1   ((Usart    *)0xF8038200U) /**< \brief (FLEXCOM1_USART) Base Address */
+#define FCOMSPI1 ((Spi      *)0xF8038400U) /**< \brief (FLEXCOM1_SPI) Base Address */
+#define TWI1     ((Twi      *)0xF8038600U) /**< \brief (FLEXCOM1_TWI) Base Address */
+#define SAIC     ((Aic      *)0xF803C000U) /**< \brief (SAIC    ) Base Address */
+#define ICM      ((Icm      *)0xF8040000U) /**< \brief (ICM     ) Base Address */
+#define SECURAM  ((Securam  *)0xF8044000U) /**< \brief (SECURAM ) Base Address */
+#define RSTC     ((Rstc     *)0xF8048000U) /**< \brief (RSTC    ) Base Address */
+#define SHDWC    ((Shdwc    *)0xF8048010U) /**< \brief (SHDWC   ) Base Address */
+#define PIT      ((Pit      *)0xF8048030U) /**< \brief (PIT     ) Base Address */
+#define WDT      ((Wdt      *)0xF8048040U) /**< \brief (WDT     ) Base Address */
+#define SCKC     ((Sckc     *)0xF8048050U) /**< \brief (SCKC    ) Base Address */
+#define BSC      ((Bsc      *)0xF8048054U) /**< \brief (BSC     ) Base Address */
+#define RTC      ((Rtc      *)0xF80480B0U) /**< \brief (RTC     ) Base Address */
+#define RXLP     ((Rxlp     *)0xF8049000U) /**< \brief (RXLP    ) Base Address */
+#define ACC      ((Acc      *)0xF804A000U) /**< \brief (ACC     ) Base Address */
+#define SFC      ((Sfc      *)0xF804C000U) /**< \brief (SFC     ) Base Address */
+#define I2SC0    ((I2sc     *)0xF8050000U) /**< \brief (I2SC0   ) Base Address */
+#define MCAN0    ((Mcan     *)0xF8054000U) /**< \brief (MCAN0   ) Base Address */
+#define SPI1     ((Spi      *)0xFC000000U) /**< \brief (SPI1    ) Base Address */
+#define SSC1     ((Ssc      *)0xFC004000U) /**< \brief (SSC1    ) Base Address */
+#define UART3    ((Uart     *)0xFC008000U) /**< \brief (UART3   ) Base Address */
+#define UART4    ((Uart     *)0xFC00C000U) /**< \brief (UART4   ) Base Address */
+#define FLEXCOM2 ((Flexcom  *)0xFC010000U) /**< \brief (FLEXCOM2) Base Address */
+#define USART2   ((Usart    *)0xFC010200U) /**< \brief (FLEXCOM2_USART) Base Address */
+#define FCOMSPI2 ((Spi      *)0xFC010400U) /**< \brief (FLEXCOM2_SPI) Base Address */
+#define TWI2     ((Twi      *)0xFC010600U) /**< \brief (FLEXCOM2_TWI) Base Address */
+#define FLEXCOM3 ((Flexcom  *)0xFC014000U) /**< \brief (FLEXCOM3) Base Address */
+#define USART3   ((Usart    *)0xFC014200U) /**< \brief (FLEXCOM3_USART) Base Address */
+#define FCOMSPI3 ((Spi      *)0xFC014400U) /**< \brief (FLEXCOM3_SPI) Base Address */
+#define TWI3     ((Twi      *)0xFC014600U) /**< \brief (FLEXCOM3_TWI) Base Address */
+#define FLEXCOM4 ((Flexcom  *)0xFC018000U) /**< \brief (FLEXCOM4) Base Address */
+#define USART4   ((Usart    *)0xFC018200U) /**< \brief (FLEXCOM4_USART) Base Address */
+#define FCOMSPI4 ((Spi      *)0xFC018400U) /**< \brief (FLEXCOM4_SPI) Base Address */
+#define TWI4     ((Twi      *)0xFC018600U) /**< \brief (FLEXCOM4_TWI) Base Address */
+#define TRNG     ((Trng     *)0xFC01C000U) /**< \brief (TRNG    ) Base Address */
+#define AIC      ((Aic      *)0xFC020000U) /**< \brief (AIC     ) Base Address */
+#define TWIHS1   ((Twi      *)0xFC028000U) /**< \brief (TWIHS1  ) Base Address */
+#define UDPHS    ((Udphs    *)0xFC02C000U) /**< \brief (UDPHS   ) Base Address */
+#define ADC      ((Adc      *)0xFC030000U) /**< \brief (ADC     ) Base Address */
+#define PIOA     ((Pio      *)0xFC038000U) /**< \brief (PIOA    ) Base Address */
+#define MATRIX1  ((Matrix   *)0xFC03C000U) /**< \brief (MATRIX1 ) Base Address */
+#define SECUMOD  ((Secumod  *)0xFC040000U) /**< \brief (SECUMOD ) Base Address */
+#define TDES     ((Tdes     *)0xFC044000U) /**< \brief (TDES    ) Base Address */
+#define CLASSD   ((Classd   *)0xFC048000U) /**< \brief (CLASSD  ) Base Address */
+#define I2SC1    ((I2sc     *)0xFC04C000U) /**< \brief (I2SC1   ) Base Address */
+#define MCAN1    ((Mcan     *)0xFC050000U) /**< \brief (MCAN1   ) Base Address */
+#define SFRBU    ((Sfrbu    *)0xFC05C000U) /**< \brief (SFRBU   ) Base Address */
+#define CHIPID   ((Chipid   *)0xFC069000U) /**< \brief (CHIPID  ) Base Address */
+
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAMA5D27 */
+/* ************************************************************************** */
+
+/** \addtogroup SAMA5D27_pio Peripheral Pio Definitions */
+/*@{*/
+
+// #include "pio/pio_sama5d27.h"
+
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAMA5D27 */
+/* ************************************************************************** */
+
+#define IRAM_SIZE (0x20000u)
+
+#define EBI_CS0_ADDR    (0x10000000u) /**< EBI Chip Select 0 base address */
+#define DDR_CS_ADDR     (0x20000000u) /**< DDR Chip Select base address */
+#define DDR_AES_CS_ADDR (0x40000000u) /**< DDR with AES Chip Select base address */
+#define EBI_CS1_ADDR    (0x60000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x70000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x80000000u) /**< EBI Chip Select 3 base address */
+#define QSPI_AES0_ADDR  (0x90000000u) /**< QPSI Memory crypted with AES 0 base address */
+#define QSPI_AES1_ADDR  (0x98000000u) /**< QPSI Memory crypted with AES 1 base address */
+#define SDMMC0_ADDR     (0xA0000000u) /**< SDMMC 0 base address */
+#define SDMMC1_ADDR     (0xB0000000u) /**< SDMMC 1 base address */
+#define NFC_ADDR        (0xC0000000u) /**< NAND Flash Controller Command base address */
+#define QSPIMEM0_ADDR   (0xD0000000u) /**< QSPI Memory 0 base address */
+#define QSPIMEM1_ADDR   (0xD8000000u) /**< QSPI Memory 1 base address */
+#define IROM_ADDR       (0x00000000u) /**< Internal ROM base address */
+#define ECC_ROM_ADDR    (0x00040000u) /**< ECC ROM base address */
+#define NFC_RAM_ADDR    (0x00100000u) /**< NAND Flash Controller RAM base address */
+#define IRAM0_ADDR      (0x00200000u) /**< Internal RAM 0 base address */
+#define IRAM_ADDR       IRAM0_ADDR
+#define IRAM1_ADDR      (0x00220000u) /**< Internal RAM 1 base address */
+#define UDPHS_RAM_ADDR  (0x00300000u) /**< USB High Speed Device Port RAM base address */
+#define UHPHS_OHCI_ADDR (0x00400000u) /**< USB High Speed Device Port RAM base address */
+#define UHPHS_EHCI_ADDR (0x00500000u) /**< USB High Speed Device Port RAM base address */
+#define AXIMX_ADDR      (0x00600000u) /**< AXI Bus Matrix base address */
+#define DAP_ADDR        (0x00700000u) /**< Debug Access Port base address */
+#define PTCMEM_ADDR     (0x00800000u) /**< PTC Memory base address */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAMA5D27_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d28.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d28.h
new file mode 100644
index 000000000..5dc0a073b
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d28.h
@@ -0,0 +1,247 @@
+/* ---------------------------------------------------------------------------- */
+/*                  Atmel Microcontroller Software Support                      */
+/*                       SAM Software Package License                           */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation                                        */
+/*                                                                              */
+/* All rights reserved.                                                         */
+/*                                                                              */
+/* Redistribution and use in source and binary forms, with or without           */
+/* modification, are permitted provided that the following condition is met:    */
+/*                                                                              */
+/* - Redistributions of source code must retain the above copyright notice,     */
+/* this list of conditions and the disclaimer below.                            */
+/*                                                                              */
+/* Atmel's name may not be used to endorse or promote products derived from     */
+/* this software without specific prior written permission.                     */
+/*                                                                              */
+/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/* ---------------------------------------------------------------------------- */
+
+#ifndef _SAMA5D28_
+#define _SAMA5D28_
+
+/** \addtogroup SAMA5D28_definitions SAMA5D28 definitions
+  This file defines all structures and symbols for SAMA5D28:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include <stdint.h>
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMA5D28 */
+/* ************************************************************************** */
+
+/** \addtogroup SAMA5D28_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_aesb.h"
+#include "component/component_aes.h"
+#include "component/component_aic.h"
+#include "component/component_aximx.h"
+#include "component/component_bsc.h"
+#include "component/component_chipid.h"
+#include "component/component_classd.h"
+#include "component/component_flexcom.h"
+#include "component/component_gmac.h"
+#include "component/component_i2sc.h"
+#include "component/component_icm.h"
+#include "component/component_isc.h"
+#include "component/component_l2cc.h"
+#include "component/component_lcdc.h"
+#include "component/component_matrix.h"
+#include "component/component_mcan.h"
+#include "component/component_mpddrc.h"
+#include "component/component_pdmic.h"
+#include "component/component_pio.h"
+#include "component/component_pit.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_qspi.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rxlp.h"
+#include "component/component_sckc.h"
+#include "component/component_sdmmc.h"
+#include "component/component_secumod.h"
+#include "component/component_sfc.h"
+#include "component/component_sfr.h"
+#include "component/component_sfrbu.h"
+#include "component/component_sha.h"
+#include "component/component_shdwc.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_tc.h"
+#include "component/component_tdes.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_udphs.h"
+#include "component/component_wdt.h"
+#include "component/component_xdmac.h"
+
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAMA5D28 */
+/* ************************************************************************** */
+
+/** \addtogroup SAMA5D28_base Peripheral Base Address Definitions */
+/*@{*/
+
+#define AXIMX    ((Aximx    *)0x00600000U) /**< \brief (AXIMX   ) Base Address */
+#define L2CC     ((L2cc     *)0x00A00000U) /**< \brief (L2CC    ) Base Address */
+#define SDMMC0   ((Sdmmc    *)0xA0000000U) /**< \brief (SDMMC0  ) Base Address */
+#define SDMMC1   ((Sdmmc    *)0xB0000000U) /**< \brief (SDMMC1  ) Base Address */
+#define LCDC     ((Lcdc     *)0xF0000000U) /**< \brief (LCDC    ) Base Address */
+#define XDMAC1   ((Xdmac    *)0xF0004000U) /**< \brief (XDMAC1  ) Base Address */
+#define ISC      ((Isc      *)0xF0008000U) /**< \brief (ISC     ) Base Address */
+#define MPDDRC   ((Mpddrc   *)0xF000C000U) /**< \brief (MPDDRC  ) Base Address */
+#define XDMAC0   ((Xdmac    *)0xF0010000U) /**< \brief (XDMAC0  ) Base Address */
+#define PMC      ((Pmc      *)0xF0014000U) /**< \brief (PMC     ) Base Address */
+#define MATRIX0  ((Matrix   *)0xF0018000U) /**< \brief (MATRIX0 ) Base Address */
+#define AESB     ((Aesb     *)0xF001C000U) /**< \brief (AESB    ) Base Address */
+#define QSPI0    ((Qspi     *)0xF0020000U) /**< \brief (QSPI0   ) Base Address */
+#define QSPI1    ((Qspi     *)0xF0024000U) /**< \brief (QSPI1   ) Base Address */
+#define SHA      ((Sha      *)0xF0028000U) /**< \brief (SHA     ) Base Address */
+#define AES      ((Aes      *)0xF002C000U) /**< \brief (AES     ) Base Address */
+#define SPI0     ((Spi      *)0xF8000000U) /**< \brief (SPI0    ) Base Address */
+#define SSC0     ((Ssc      *)0xF8004000U) /**< \brief (SSC0    ) Base Address */
+#define GMAC0    ((Gmac     *)0xF8008000U) /**< \brief (GMAC0   ) Base Address */
+#define TC0      ((Tc       *)0xF800C000U) /**< \brief (TC0     ) Base Address */
+#define TC1      ((Tc       *)0xF8010000U) /**< \brief (TC1     ) Base Address */
+#define HSMC     ((Smc      *)0xF8014000U) /**< \brief (HSMC    ) Base Address */
+#define PDMIC    ((Pdmic    *)0xF8018000U) /**< \brief (PDMIC   ) Base Address */
+#define UART0    ((Uart     *)0xF801C000U) /**< \brief (UART0   ) Base Address */
+#define UART1    ((Uart     *)0xF8020000U) /**< \brief (UART1   ) Base Address */
+#define UART2    ((Uart     *)0xF8024000U) /**< \brief (UART2   ) Base Address */
+#define TWIHS0   ((Twi      *)0xF8028000U) /**< \brief (TWIHS0  ) Base Address */
+#define PWM      ((Pwm      *)0xF802C000U) /**< \brief (PWM     ) Base Address */
+#define SFR      ((Sfr      *)0xF8030000U) /**< \brief (SFR     ) Base Address */
+#define FLEXCOM0 ((Flexcom  *)0xF8034000U) /**< \brief (FLEXCOM0) Base Address */
+#define USART0   ((Usart    *)0xF8034200U) /**< \brief (FLEXCOM0_USART) Base Address */
+#define FCOMSPI0 ((Spi      *)0xF8034400U) /**< \brief (FLEXCOM0_SPI) Base Address */
+#define TWI0     ((Twi      *)0xF8034600U) /**< \brief (FLEXCOM0_TWI) Base Address */
+#define FLEXCOM1 ((Flexcom  *)0xF8038000U) /**< \brief (FLEXCOM1) Base Address */
+#define USART1   ((Usart    *)0xF8038200U) /**< \brief (FLEXCOM1_USART) Base Address */
+#define FCOMSPI1 ((Spi      *)0xF8038400U) /**< \brief (FLEXCOM1_SPI) Base Address */
+#define TWI1     ((Twi      *)0xF8038600U) /**< \brief (FLEXCOM1_TWI) Base Address */
+#define SAIC     ((Aic      *)0xF803C000U) /**< \brief (SAIC    ) Base Address */
+#define ICM      ((Icm      *)0xF8040000U) /**< \brief (ICM     ) Base Address */
+#define SECURAM  ((Securam  *)0xF8044000U) /**< \brief (SECURAM ) Base Address */
+#define RSTC     ((Rstc     *)0xF8048000U) /**< \brief (RSTC    ) Base Address */
+#define SHDWC    ((Shdwc    *)0xF8048010U) /**< \brief (SHDWC   ) Base Address */
+#define PIT      ((Pit      *)0xF8048030U) /**< \brief (PIT     ) Base Address */
+#define WDT      ((Wdt      *)0xF8048040U) /**< \brief (WDT     ) Base Address */
+#define SCKC     ((Sckc     *)0xF8048050U) /**< \brief (SCKC    ) Base Address */
+#define BSC      ((Bsc      *)0xF8048054U) /**< \brief (BSC     ) Base Address */
+#define RTC      ((Rtc      *)0xF80480B0U) /**< \brief (RTC     ) Base Address */
+#define RXLP     ((Rxlp     *)0xF8049000U) /**< \brief (RXLP    ) Base Address */
+#define ACC      ((Acc      *)0xF804A000U) /**< \brief (ACC     ) Base Address */
+#define SFC      ((Sfc      *)0xF804C000U) /**< \brief (SFC     ) Base Address */
+#define I2SC0    ((I2sc     *)0xF8050000U) /**< \brief (I2SC0   ) Base Address */
+#define MCAN0    ((Mcan     *)0xF8054000U) /**< \brief (MCAN0   ) Base Address */
+#define SPI1     ((Spi      *)0xFC000000U) /**< \brief (SPI1    ) Base Address */
+#define SSC1     ((Ssc      *)0xFC004000U) /**< \brief (SSC1    ) Base Address */
+#define UART3    ((Uart     *)0xFC008000U) /**< \brief (UART3   ) Base Address */
+#define UART4    ((Uart     *)0xFC00C000U) /**< \brief (UART4   ) Base Address */
+#define FLEXCOM2 ((Flexcom  *)0xFC010000U) /**< \brief (FLEXCOM2) Base Address */
+#define USART2   ((Usart    *)0xFC010200U) /**< \brief (FLEXCOM2_USART) Base Address */
+#define FCOMSPI2 ((Spi      *)0xFC010400U) /**< \brief (FLEXCOM2_SPI) Base Address */
+#define TWI2     ((Twi      *)0xFC010600U) /**< \brief (FLEXCOM2_TWI) Base Address */
+#define FLEXCOM3 ((Flexcom  *)0xFC014000U) /**< \brief (FLEXCOM3) Base Address */
+#define USART3   ((Usart    *)0xFC014200U) /**< \brief (FLEXCOM3_USART) Base Address */
+#define FCOMSPI3 ((Spi      *)0xFC014400U) /**< \brief (FLEXCOM3_SPI) Base Address */
+#define TWI3     ((Twi      *)0xFC014600U) /**< \brief (FLEXCOM3_TWI) Base Address */
+#define FLEXCOM4 ((Flexcom  *)0xFC018000U) /**< \brief (FLEXCOM4) Base Address */
+#define USART4   ((Usart    *)0xFC018200U) /**< \brief (FLEXCOM4_USART) Base Address */
+#define FCOMSPI4 ((Spi      *)0xFC018400U) /**< \brief (FLEXCOM4_SPI) Base Address */
+#define TWI4     ((Twi      *)0xFC018600U) /**< \brief (FLEXCOM4_TWI) Base Address */
+#define TRNG     ((Trng     *)0xFC01C000U) /**< \brief (TRNG    ) Base Address */
+#define AIC      ((Aic      *)0xFC020000U) /**< \brief (AIC     ) Base Address */
+#define TWIHS1   ((Twi      *)0xFC028000U) /**< \brief (TWIHS1  ) Base Address */
+#define UDPHS    ((Udphs    *)0xFC02C000U) /**< \brief (UDPHS   ) Base Address */
+#define ADC      ((Adc      *)0xFC030000U) /**< \brief (ADC     ) Base Address */
+#define PIOA     ((Pio      *)0xFC038000U) /**< \brief (PIOA    ) Base Address */
+#define MATRIX1  ((Matrix   *)0xFC03C000U) /**< \brief (MATRIX1 ) Base Address */
+#define SECUMOD  ((Secumod  *)0xFC040000U) /**< \brief (SECUMOD ) Base Address */
+#define TDES     ((Tdes     *)0xFC044000U) /**< \brief (TDES    ) Base Address */
+#define CLASSD   ((Classd   *)0xFC048000U) /**< \brief (CLASSD  ) Base Address */
+#define I2SC1    ((I2sc     *)0xFC04C000U) /**< \brief (I2SC1   ) Base Address */
+#define MCAN1    ((Mcan     *)0xFC050000U) /**< \brief (MCAN1   ) Base Address */
+#define SFRBU    ((Sfrbu    *)0xFC05C000U) /**< \brief (SFRBU   ) Base Address */
+#define CHIPID   ((Chipid   *)0xFC069000U) /**< \brief (CHIPID  ) Base Address */
+
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAMA5D28 */
+/* ************************************************************************** */
+
+/** \addtogroup SAMA5D28_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sama5d28.h"
+
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAMA5D28 */
+/* ************************************************************************** */
+
+#define IRAM_SIZE (0x20000u)
+
+#define EBI_CS0_ADDR    (0x10000000u) /**< EBI Chip Select 0 base address */
+#define DDR_CS_ADDR     (0x20000000u) /**< DDR Chip Select base address */
+#define DDR_AES_CS_ADDR (0x40000000u) /**< DDR with AES Chip Select base address */
+#define EBI_CS1_ADDR    (0x60000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x70000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x80000000u) /**< EBI Chip Select 3 base address */
+#define QSPI_AES0_ADDR  (0x90000000u) /**< QPSI Memory crypted with AES 0 base address */
+#define QSPI_AES1_ADDR  (0x98000000u) /**< QPSI Memory crypted with AES 1 base address */
+#define SDMMC0_ADDR     (0xA0000000u) /**< SDMMC 0 base address */
+#define SDMMC1_ADDR     (0xB0000000u) /**< SDMMC 1 base address */
+#define NFC_ADDR        (0xC0000000u) /**< NAND Flash Controller Command base address */
+#define QSPIMEM0_ADDR   (0xD0000000u) /**< QSPI Memory 0 base address */
+#define QSPIMEM1_ADDR   (0xD8000000u) /**< QSPI Memory 1 base address */
+#define IROM_ADDR       (0x00000000u) /**< Internal ROM base address */
+#define ECC_ROM_ADDR    (0x00040000u) /**< ECC ROM base address */
+#define NFC_RAM_ADDR    (0x00100000u) /**< NAND Flash Controller RAM base address */
+#define IRAM0_ADDR      (0x00200000u) /**< Internal RAM 0 base address */
+#define IRAM_ADDR       IRAM0_ADDR
+#define IRAM1_ADDR      (0x00220000u) /**< Internal RAM 1 base address */
+#define UDPHS_RAM_ADDR  (0x00300000u) /**< USB High Speed Device Port RAM base address */
+#define UHPHS_OHCI_ADDR (0x00400000u) /**< USB High Speed Device Port RAM base address */
+#define UHPHS_EHCI_ADDR (0x00500000u) /**< USB High Speed Device Port RAM base address */
+#define AXIMX_ADDR      (0x00600000u) /**< AXI Bus Matrix base address */
+#define DAP_ADDR        (0x00700000u) /**< Debug Access Port base address */
+#define PTCMEM_ADDR     (0x00800000u) /**< PTC Memory base address */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAMA5D28_ */
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d2x.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d2x.h
new file mode 100644
index 000000000..86123a031
--- /dev/null
+++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d2x.h
@@ -0,0 +1,368 @@
+/*
+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    SAM/sama5d2x.h
+ * @brief   SAM A5 D2x inclusion header.
+ *
+ * @addtogroup SAMA5D2
+ * @{
+ */
+    
+#ifndef _SAMA5D2X_H_
+#define _SAMA5D2X_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "ARMCA5.h"
+/**
+  * @brief SAMA5D2 Family
+  */
+#if !defined  (SAMA5D2)
+#define SAMA5D2
+#endif /* SAMA5D2 */
+
+/** 
+  * @addtogroup Device_Included
+  * @{
+  */
+#if defined(SAMA5D21)
+  #include "sama5d21.h"
+#elif defined(SAMA5D22)
+  #include "sama5d22.h"
+#elif defined(SAMA5D23)
+  #include "sama5d23.h"
+#elif defined(SAMA5D24)
+  #include "sama5d24.h"
+#elif defined(SAMA5D26)
+  #include "sama5d26.h"
+#elif defined(SAMA5D27)
+  #include "sama5d27.h" 
+#elif defined(SAMA5D28)
+  #include "sama5d28.h"  
+#else
+ #error "Please select first the target SAMA5D2x device used in your application (in sama5d2x.h file)"
+#endif
+
+/**@} */
+
+/**
+  * @brief SAMA5D2 Family
+  * @{
+  */
+#define ID_SAIC_FIQ     ( 0) /**< \brief FIQ Interrupt ID (SAIC_FIQ) */
+#define ID_ARM_PMU      ( 2) /**< \brief Performance Monitor Unit (PMU) (ARM_PMU) */
+#define ID_PIT          ( 3) /**< \brief Periodic Interval Timer Interrupt (PIT) */
+#define ID_WDT          ( 4) /**< \brief Watchdog timer Interrupt (WDT) */
+#define ID_GMAC0        ( 5) /**< \brief Ethernet MAC (GMAC0) */
+#define ID_XDMAC0       ( 6) /**< \brief DMA Controller 0 (XDMAC0) */
+#define ID_XDMAC1       ( 7) /**< \brief DMA Controller 1 (XDMAC1) */
+#define ID_ICM          ( 8) /**< \brief Integritry Check Monitor (ICM) */
+#define ID_AES          ( 9) /**< \brief Advanced Enion Standard (AES) */
+#define ID_AESB         (10) /**< \brief AES bridge (AESB) */
+#define ID_TDES         (11) /**< \brief Triple Data Enion Standard (TDES) */
+#define ID_SHA          (12) /**< \brief SHA Signature (SHA) */
+#define ID_MPDDRC       (13) /**< \brief MPDDR controller (MPDDRC) */
+#define ID_MATRIX1      (14) /**< \brief H32MX, 32-bit AHB Matrix (MATRIX1) */
+#define ID_MATRIX0      (15) /**< \brief H64MX, 64-bit AHB Matrix (MATRIX0) */
+#define ID_SECUMOD      (16) /**< \brief Secure Module (SECUMOD) */
+#define ID_HSMC         (17) /**< \brief Multi-bit ECC Interrupt (HSMC) */
+#define ID_PIOA         (18) /**< \brief Parallel I/O Controller (PIOA) */
+#define ID_FLEXCOM0     (19) /**< \brief FLEXCOM 0 (FLEXCOM0) */
+#define ID_USART0       (19) /**< \brief USART (USART0) from FLEXCOM0 */
+#define ID_FCOMSPI0     (19) /**< \brief Serial Peripheral Interface (SPI0) from FLEXCOM0 */
+#define ID_TWI0         (19) /**< \brief Two-Wire Interface (TWI0) from FLEXCOM0 */
+#define ID_FLEXCOM1     (20) /**< \brief FLEXCOM 1 (FLEXCOM1) */
+#define ID_USART1       (20) /**< \brief USART (USART1) from FLEXCOM1 */
+#define ID_FCOMSPI1     (20) /**< \brief Serial Peripheral Interface (SPI1) from FLEXCOM1 */
+#define ID_TWI1         (20) /**< \brief Two-Wire Interface (TWI1) from FLEXCOM1 */
+#define ID_FLEXCOM2     (21) /**< \brief FLEXCOM 1 (FLEXCOM1) */
+#define ID_USART2       (21) /**< \brief USART (USART1) from FLEXCOM1 */
+#define ID_FCOMSPI2     (21) /**< \brief Serial Peripheral Interface (SPI1) from FLEXCOM1 */
+#define ID_TWI2         (21) /**< \brief Two-Wire Interface (TWI1) from FLEXCOM1 */
+#define ID_FLEXCOM3     (22) /**< \brief FLEXCOM 3 (FLEXCOM3) */
+#define ID_USART3       (22) /**< \brief USART (USART3) from FLEXCOM3 */
+#define ID_FCOMSPI3     (22) /**< \brief Serial Peripheral Interface (SPI3) from FLEXCOM3 */
+#define ID_TWI3         (22) /**< \brief Two-Wire Interface (TWI3) from FLEXCOM3 */
+#define ID_FLEXCOM4     (23) /**< \brief FLEXCOM 4 (FLEXCOM4) */
+#define ID_USART4       (23) /**< \brief USART (USART4) from FLEXCOM4 */
+#define ID_FCOMSPI4     (23) /**< \brief Serial Peripheral Interface (SPI4) from FLEXCOM4 */
+#define ID_TWI4         (23) /**< \brief Two-Wire Interface (TWI4) from FLEXCOM4 */
+#define ID_UART0        (24) /**< \brief UART 0 (UART0) */
+#define ID_UART1        (25) /**< \brief UART 1 (UART1) */
+#define ID_UART2        (26) /**< \brief UART 2 (UART2) */
+#define ID_UART3        (27) /**< \brief UART 3 (UART3) */
+#define ID_UART4        (28) /**< \brief UART 4 (UART4) */
+#define ID_TWIHS0       (29) /**< \brief Two-Wire Interface 0 (TWIHS0) */
+#define ID_TWIHS1       (30) /**< \brief Two-Wire Interface 1 (TWIHS1) */
+#define ID_SDMMC0       (31) /**< \brief Secure Digital Multimedia Card Controller 0 (SDMMC0) */
+#define ID_SDMMC1       (32) /**< \brief Secure Digital Multimedia Card Controller 1 (SDMMC1) */
+#define ID_SPI0         (33) /**< \brief Serial Peripheral Interface 0 (SPI0) */
+#define ID_SPI1         (34) /**< \brief Serial Peripheral Interface 1 (SPI1) */
+#define ID_TC0          (35) /**< \brief Timer Counter 0 (ch. 0, 1, 2) (TC0) */
+#define ID_TC1          (36) /**< \brief Timer Counter 1 (ch. 3, 4, 5) (TC1) */
+#define ID_PWM          (38) /**< \brief Pulse Width Modulation Controller0 (ch. 0, 1, 2, 3) (PWM) */
+#define ID_ADC          (40) /**< \brief Touch Screen ADC Controller (ADC) */
+#define ID_UHPHS        (41) /**< \brief USB Host High Speed (UHPHS) */
+#define ID_UDPHS        (42) /**< \brief USB Device High Speed (UDPHS) */
+#define ID_SSC0         (43) /**< \brief Synchronous Serial Controller 0 (SSC0) */
+#define ID_SSC1         (44) /**< \brief Synchronous Serial Controller 1 (SSC1) */
+#define ID_LCDC         (45) /**< \brief LCD Controller (LCDC) */
+#define ID_ISC          (46) /**< \brief Camera Interface (ISC) */
+#define ID_TRNG         (47) /**< \brief True Random Number Generator (TRNG) */
+#define ID_PDMIC        (48) /**< \brief Pulse Density Modulation Interface Controller (PDMIC) */
+#define ID_AIC_IRQ      (49) /**< \brief IRQ Interrupt ID (AIC_IRQ) */
+#define ID_SFC          (50) /**< \brief Fuse Controller (SFC) */
+#define ID_SECURAM      (51) /**< \brief Secured RAM (SECURAM) */
+#define ID_QSPI0        (52) /**< \brief QSPI 0 (QSPI0) */
+#define ID_QSPI1        (53) /**< \brief QSPI 1 (QSPI1) */
+#define ID_I2SC0        (54) /**< \brief Inter-IC Sound Controller 0 (I2SC0) */
+#define ID_I2SC1        (55) /**< \brief Inter-IC Sound Controller 1 (I2SC1) */
+#define ID_CAN0_INT0    (56) /**< \brief MCAN 0 Interrupt0 (CAN0_INT0) */
+#define ID_CAN1_INT0    (57) /**< \brief MCAN 1 Interrupt0 (CAN1_INT0) */
+#define ID_CLASSD       (59) /**< \brief Audio Class D amplifier (CLASSD) */
+#define ID_SFR          (60) /**< \brief Special Function Register  (SFR) */
+#define ID_SAIC         (61) /**< \brief Secured Advanced Interrupt Controller  (SAIC) */
+#define ID_AIC          (62) /**< \brief Advanced Interrupt Controller  (AIC) */
+#define ID_L2CC         (63) /**< \brief L2 Cache Controller (L2CC) */
+#define ID_CAN0_INT1    (64) /**< \brief MCAN 0 Interrupt1 (CAN0_INT1) */
+#define ID_CAN1_INT1    (65) /**< \brief MCAN 1 Interrupt1 (CAN1_INT1) */
+#define ID_GMAC0_Q1     (66) /**< \brief GMAC Queue 1 Interrupt (GMAC0_Q1) */
+#define ID_GMAC0_Q2     (67) /**< \brief GMAC Queue 2 Interrupt (GMAC0_Q2) */
+#define ID_PIOB         (68) /**< \brief  (PIOB) */
+#define ID_PIOC         (69) /**< \brief  (PIOC) */
+#define ID_PIOD         (70) /**< \brief  (PIOD) */
+#define ID_SDMMC0_TIMER (71) /**< \brief  (SDMMC0_TIMER) */
+#define ID_SDMMC1_TIMER (72) /**< \brief  (SDMMC1_TIMER) */
+#define ID_SYSC         (74) /**< \brief System Controller Interrupt, RTC, RSTC, PMC (SYSC) */
+#define ID_ACC          (75) /**< \brief Analog Comparator (ACC) */
+#define ID_RXLP         (76) /**< \brief Uart Low Power (RXLP) */
+#define ID_CHIPID       (78) /**< \brief Chip ID (CHIPID) */
+
+#define ID_PERIPH_COUNT (79) /**< \brief Number of peripheral IDs */
+
+/* XDMA Peripheral Interface Number */
+
+#define PERID_TWIHS0_TX    0
+#define PERID_TWIHS0_RX    1
+#define PERID_TWIHS1_TX    2
+#define PERID_TWIHS1_RX    3
+#define PERID_QSPI0_TX     4
+#define PERID_QSPI0_RX     5
+#define PERID_SPI0_TX      6
+#define PERID_SPI0_RX      7
+#define PERID_SPI1_TX      8
+#define PERID_SPI1_RX      9
+#define PERID_PWM_TX       10
+#define PERID_PWM_RX       0XFF
+#define PERID_FLEXCOM0_TX  11
+#define PERID_FLEXCOM0_RX  12
+#define PERID_FLEXCOM1_TX  13
+#define PERID_FLEXCOM1_RX  14
+#define PERID_FLEXCOM2_TX  15
+#define PERID_FLEXCOM2_RX  16
+#define PERID_FLEXCOM3_TX  17
+#define PERID_FLEXCOM3_RX  18
+#define PERID_FLEXCOM4_TX  19
+#define PERID_FLEXCOM4_RX  20
+#define PERID_SSC0_TX      21
+#define PERID_SSC0_RX      22
+#define PERID_SSC1_TX      23
+#define PERID_SSC1_RX      24
+#define PERID_ADC_TX       0XFF
+#define PERID_ADC_RX       25
+#define PERID_AES_TX       26
+#define PERID_AES_RX       27
+#define PERID_TDES_TX      28
+#define PERID_TDES_RX      29
+#define PERID_SHA_TX       30
+#define PERID_SHA_RX       0XFF
+#define PERID_I2SC0_TX     31
+#define PERID_I2SC0_RX     32
+#define PERID_I2SC1_TX     33
+#define PERID_I2SC1_RX     34
+#define PERID_UART0_TX     35
+#define PERID_UART0_RX     36
+#define PERID_UART1_TX     37
+#define PERID_UART1_RX     38
+#define PERID_UART2_TX     39
+#define PERID_UART2_RX     40
+#define PERID_UART3_TX     41
+#define PERID_UART3_RX     42
+#define PERID_UART4_TX     43
+#define PERID_UART4_RX     44
+#define PERID_TC0_TX       0XFF
+#define PERID_TC0_RX       45
+#define PERID_TC1_TX       0XFF
+#define PERID_TC1_RX       46
+#define PERID_CLASSD_TX    47
+#define PERID_CLASSD_RX    0XFF
+#define PERID_QSPI1_TX     48
+#define PERID_QSPI1_RX     49
+#define PERID_PDMIC_TX     0XFF
+#define PERID_PDMIC_RX     50
+
+#define ID_SAIC_FIQ_MSK       (1 << (ID_SAIC_FIQ & 0x1F))
+#define ID_ARM_PMU_MSK        (1 << (ID_ARM_PMU & 0x1F))
+#define ID_PIT_MSK            (1 << (ID_PIT & 0x1F))
+#define ID_WDT_MSK            (1 << (ID_WDT & 0x1F))
+#define ID_GMAC0_MSK          (1 << (ID_GMAC0 & 0x1F))
+#define ID_XDMAC0_MSK         (1 << (ID_XDMAC0 & 0x1F))
+#define ID_XDMAC1_MSK         (1 << (ID_XDMAC1 & 0x1F))
+#define ID_ICM_MSK            (1 << (ID_ICM & 0x1F))
+#define ID_AES_MSK            (1 << (ID_AES & 0x1F))
+#define ID_AESB_MSK           (1 << (ID_AESB & 0x1F))
+#define ID_TDES_MSK           (1 << (ID_TDES & 0x1F))
+#define ID_SHA_MSK            (1 << (ID_SHA & 0x1F))
+#define ID_MPDDRC_MSK         (1 << (ID_MPDDRC & 0x1F))
+#define ID_MATRIX1_MSK        (1 << (ID_MATRIX1 & 0x1F))
+#define ID_MATRIX0_MSK        (1 << (ID_MATRIX0 & 0x1F))
+#define ID_SECUMOD_MSK        (1 << (ID_SECUMOD & 0x1F))
+#define ID_HSMC_MSK           (1 << (ID_HSMC & 0x1F))
+#define ID_PIOA_MSK           (1 << (ID_PIOA & 0x1F))
+#define ID_FLEXCOM0_MSK       (1 << (ID_FLEXCOM0 & 0x1F))
+#define ID_USART0_MSK         (1 << (ID_USART0 & 0x1F))
+#define ID_FCOMSPI0_MSK       (1 << (ID_FCOMSPI0 & 0x1F))
+#define ID_TWI0_MSK           (1 << (ID_TWI0 & 0x1F))
+#define ID_FLEXCOM1_MSK       (1 << (ID_FLEXCOM1 & 0x1F))
+#define ID_USART1_MSK         (1 << (ID_USART1 & 0x1F))
+#define ID_FCOMSPI1_MSK       (1 << (ID_FCOMSPI1 & 0x1F))
+#define ID_TWI1_MSK           (1 << (ID_TWI1 & 0x1F))
+#define ID_FLEXCOM2_MSK       (1 << (ID_FLEXCOM2 & 0x1F))
+#define ID_USART2_MSK         (1 << (ID_USART2 & 0x1F))
+#define ID_FCOMSPI2_MSK       (1 << (ID_FCOMSPI2 & 0x1F))
+#define ID_TWI2_MSK           (1 << (ID_TWI2 & 0x1F))
+#define ID_FLEXCOM3_MSK       (1 << (ID_FLEXCOM3 & 0x1F))
+#define ID_USART3_MSK         (1 << (ID_USART3 & 0x1F))
+#define ID_FCOMSPI3_MSK       (1 << (ID_FCOMSPI3 & 0x1F))
+#define ID_TWI3_MSK           (1 << (ID_TWI3 & 0x1F))
+#define ID_FLEXCOM4_MSK       (1 << (ID_FLEXCOM4 & 0x1F))
+#define ID_USART4_MSK         (1 << (ID_USART4 & 0x1F))
+#define ID_FCOMSPI4_MSK       (1 << (ID_FCOMSPI4 & 0x1F))
+#define ID_TWI4_MSK           (1 << (ID_TWI4 & 0x1F))
+#define ID_UART0_MSK          (1 << (ID_UART0 & 0x1F))
+#define ID_UART1_MSK          (1 << (ID_UART1 & 0x1F))
+#define ID_UART2_MSK          (1 << (ID_UART2 & 0x1F))
+#define ID_UART3_MSK          (1 << (ID_UART3 & 0x1F))
+#define ID_UART4_MSK          (1 << (ID_UART4 & 0x1F))
+#define ID_TWIHS0_MSK         (1 << (ID_TWIHS0 & 0x1F))
+#define ID_TWIHS1_MSK         (1 << (ID_TWIHS1 & 0x1F))
+#define ID_SDMMC0_MSK         (1 << (ID_SDMMC0 & 0x1F))
+#define ID_SDMMC1_MSK         (1 << (ID_SDMMC1 & 0x1F))
+#define ID_SPI0_MSK           (1 << (ID_SPI0 & 0x1F))
+#define ID_SPI1_MSK           (1 << (ID_SPI1 & 0x1F))
+#define ID_TC0_MSK            (1 << (ID_TC0 & 0x1F))
+#define ID_TC1_MSK            (1 << (ID_TC1 & 0x1F))
+#define ID_PWM_MSK            (1 << (ID_PWM & 0x1F))
+#define ID_ADC_MSK            (1 << (ID_ADC & 0x1F))
+#define ID_UHPHS_MSK          (1 << (ID_UHPHS & 0x1F))
+#define ID_UDPHS_MSK          (1 << (ID_UDPHS & 0x1F))
+#define ID_SSC0_MSK           (1 << (ID_SSC0 & 0x1F))
+#define ID_SSC1_MSK           (1 << (ID_SSC1 & 0x1F))
+#define ID_LCDC_MSK           (1 << (ID_LCDC & 0x1F))
+#define ID_ISC_MSK            (1 << (ID_ISC & 0x1F))
+#define ID_TRNG_MSK           (1 << (ID_TRNG & 0x1F))
+#define ID_PDMIC_MSK          (1 << (ID_PDMIC & 0x1F))
+#define ID_AIC_IRQ_MSK        (1 << (ID_AIC_IRQ & 0x1F))
+#define ID_SFC_MSK            (1 << (ID_SFC & 0x1F))
+#define ID_SECURAM_MSK        (1 << (ID_SECURAM & 0x1F))
+#define ID_QSPI0_MSK          (1 << (ID_QSPI0 & 0x1F))
+#define ID_QSPI1_MSK          (1 << (ID_QSPI1 & 0x1F))
+#define ID_I2SC0_MSK          (1 << (ID_I2SC0 & 0x1F))
+#define ID_I2SC1_MSK          (1 << (ID_I2SC1 & 0x1F))
+#define ID_CAN0_INT0_MSK      (1 << (ID_CAN0_INT0 & 0x1F))
+#define ID_CAN1_INT0_MSK      (1 << (ID_CAN1_INT0 & 0x1F))
+#define ID_CLASSD_MSK         (1 << (ID_CLASSD & 0x1F))
+#define ID_SFR_MSK            (1 << (ID_SFR & 0x1F))
+#define ID_SAIC_MSK           (1 << (ID_SAIC & 0x1F))
+#define ID_AIC_MSK            (1 << (ID_AIC & 0x1F))
+#define ID_L2CC_MSK           (1 << (ID_L2CC & 0x1F))
+#define ID_CAN0_INT1_MSK      (1 << (ID_CAN0_INT1 & 0x1F))
+#define ID_CAN1_INT1_MSK      (1 << (ID_CAN1_INT1 & 0x1F))
+#define ID_GMAC0_Q1_MSK       (1 << (ID_GMAC0_Q1 & 0x1F))
+#define ID_GMAC0_Q2_MSK       (1 << (ID_GMAC0_Q2 & 0x1F))
+#define ID_PIOB_MSK           (1 << (ID_PIOB & 0x1F))
+#define ID_PIOC_MSK           (1 << (ID_PIOC & 0x1F))
+#define ID_PIOD_MSK           (1 << (ID_PIOD & 0x1F))
+#define ID_SDMMC0_TIMER_MSK   (1 << (ID_SDMMC0_TIMER & 0x1F))
+#define ID_SDMMC1_TIMER_MSK   (1 << (ID_SDMMC1_TIMER & 0x1F))
+#define ID_SYSC_MSK           (1 << (ID_SYSC & 0x1F))
+#define ID_ACC_MSK            (1 << (ID_ACC & 0x1F))
+#define ID_RXLP_MSK           (1 << (ID_RXLP & 0x1F))
+#define ID_CHIPID_MSK         (1 << (ID_CHIPID & 0x1F))
+
+/* MASTER MATRIX ID DEFINITION FOR SAMA5D2x */
+
+#define H64MX_MASTER_BRIDGE_FROM_AXI  0
+#define H64MX_MASTER_XDMAC0_0         1
+#define H64MX_MASTER_XDMAC0_1         2
+#define H64MX_MASTER_XDMAC1_0         3
+#define H64MX_MASTER_XDMAC1_1         4
+#define H64MX_MASTER_LCDC_DMA_0       5
+#define H64MX_MASTER_LCDC_DMA_1       6
+#define H64MX_MASTER_SDMMC0           7
+#define H64MX_MASTER_SDMMC1           8
+#define H64MX_MASTER_ISC_DMA          9
+#define H64MX_MASTER_AESB            10
+#define H64MX_MASTER_BRIDGE_H64MX    11
+
+#define H32MX_MASTER_BRIDGE_H32MX     0
+#define H32MX_MASTER_ICM              1
+#define H32MX_MASTER_UHPHS_EHCI_DMA   2
+#define H32MX_MASTER_UHPHS_OHCI_DMA   3
+#define H32MX_MASTER_UDPHS_DMA        4
+#define H32MX_MASTER_GMAC_DMA         5
+#define H32MX_MASTER_CAN0_DMA         6
+#define H32MX_MASTER_CAN1_DMA         7
+
+ /* SLAVE MATRIX ID DEFINITIONS FOR SAMA5D2x */
+
+ #define H64MX_SLAVE_BRIDGE_H32MX     0
+ #define H64MX_SLAVE_APB              1
+ #define H64MX_SLAVE_SDMMC            1
+ #define H64MX_SLAVE_DDR_PORT0        2
+ #define H64MX_SLAVE_DDR_PORT1        3
+ #define H64MX_SLAVE_DDR_PORT2        4
+ #define H64MX_SLAVE_DDR_PORT3        5
+ #define H64MX_SLAVE_DDR_PORT4        6
+ #define H64MX_SLAVE_DDR_PORT5        7
+ #define H64MX_SLAVE_DDR_PORT6        8
+ #define H64MX_SLAVE_DDR_PORT7        9
+ #define H64MX_SLAVE_SRAM            10
+ #define H64MX_SLAVE_L2C_SRAM        11
+ #define H64MX_SLAVE_QSPI0           12
+ #define H64MX_SLAVE_QSPI1           13
+ #define H64MX_SLAVE_AESB            14
+
+ #define H32MX_SLAVE_BRIDGE_H64MX     0
+ #define H32MX_SLAVE_APB0             1
+ #define H32MX_SLAVE_APB1             2
+ #define H32MX_SLAVE_EBI              3
+ #define H32MX_SLAVE_NFC_CMD          3
+ #define H32MX_SLAVE_NFC_SRAM         4
+ #define H32MX_SLAVE_USB              5
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+/**@} */
+#endif /* __SAMA5D2X_H */
+
author	isiora <none@example.com>	2017-11-14 22:43:14 +0000
committer	isiora <none@example.com>	2017-11-14 22:43:14 +0000
commit	2e7c937f0b2d2505f707970d0f8f1c3086cae279 (patch)
tree	adedd6e99948a7b23a485c8047c6c165f7ae7c51 /os/common/startup
parent	7b3fe37b28fd37d80de146de6f34665168323c83 (diff)
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