diff options
| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2016-02-16 09:53:03 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2016-02-16 09:53:03 +0000 |
| commit | 566bc155acac0ef8f2826920244713f10044f951 (patch) | |
| tree | b01a82d1de1b8dc5bcc625c6f77e5bd25cbcb395 /os/common/startup/e200/devices | |
| parent | b1b94e5bdf4eb998bbfe907e1de1d4e1c965b503 (diff) | |
| download | ChibiOS-566bc155acac0ef8f2826920244713f10044f951.tar.gz ChibiOS-566bc155acac0ef8f2826920244713f10044f951.tar.bz2 ChibiOS-566bc155acac0ef8f2826920244713f10044f951.zip | |
Start of tree reorganization.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8897 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/common/startup/e200/devices')
38 files changed, 6125 insertions, 0 deletions
diff --git a/os/common/startup/e200/devices/SPC560BCxx/boot.h b/os/common/startup/e200/devices/SPC560BCxx/boot.h new file mode 100644 index 000000000..7af28f997 --- /dev/null +++ b/os/common/startup/e200/devices/SPC560BCxx/boot.h @@ -0,0 +1,117 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC560BCxx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_ME 0x00001000
+#define MSR_DE 0x00000200
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC560BCxx/boot.s b/os/common/startup/e200/devices/SPC560BCxx/boot.s new file mode 100644 index 000000000..089095be2 --- /dev/null +++ b/os/common/startup/e200/devices/SPC560BCxx/boot.s @@ -0,0 +1,217 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC560BCxx/boot.s
+ * @brief SPC560BCxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+ .long 0x015A0000
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ bl _coreinit
+#endif
+ bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ lis %r4, __ram_reloc_start__@h
+ ori %r4, %r4, __ram_reloc_start__@l
+ lis %r5, __ram_reloc_dest__@h
+ ori %r5, %r5, __ram_reloc_dest__@l
+ lis %r6, __ram_reloc_end__@h
+ ori %r6, %r6, __ram_reloc_end__@l
+.relloop:
+ cmpl cr0, %r4, %r6
+ bge cr0, .relend
+ lwz %r7, 0(%r4)
+ addi %r4, %r4, 4
+ stw %r7, 0(%r5)
+ addi %r5, %r5, 4
+ b .relloop
+.relend:
+ lis %r3, _boot_address@h
+ ori %r3, %r3, _boot_address@l
+ mtctr %r3
+ bctrl
+#else
+ b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_coreinit:
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor %r0, %r0, %r0
+ xor %r1, %r1, %r1
+ xor %r2, %r2, %r2
+ xor %r3, %r3, %r3
+ xor %r4, %r4, %r4
+ xor %r5, %r5, %r5
+ xor %r6, %r6, %r6
+ xor %r7, %r7, %r7
+ xor %r8, %r8, %r8
+ xor %r9, %r9, %r9
+ xor %r10, %r10, %r10
+ xor %r11, %r11, %r11
+ xor %r12, %r12, %r12
+ xor %r13, %r13, %r13
+ xor %r14, %r14, %r14
+ xor %r15, %r15, %r15
+ xor %r16, %r16, %r16
+ xor %r17, %r17, %r17
+ xor %r18, %r18, %r18
+ xor %r19, %r19, %r19
+ xor %r20, %r20, %r20
+ xor %r21, %r21, %r21
+ xor %r22, %r22, %r22
+ xor %r23, %r23, %r23
+ xor %r24, %r24, %r24
+ xor %r25, %r25, %r25
+ xor %r26, %r26, %r26
+ xor %r27, %r27, %r27
+ xor %r28, %r28, %r28
+ xor %r29, %r29, %r29
+ xor %r30, %r30, %r30
+ xor %r31, %r31, %r31
+ lis %r4, __ram_start__@h
+ ori %r4, %r4, __ram_start__@l
+ lis %r5, __ram_end__@h
+ ori %r5, %r5, __ram_end__@l
+.cleareccloop:
+ cmpl %cr0, %r4, %r5
+ bge %cr0, .cleareccend
+ stmw %r16, 0(%r4)
+ addi %r4, %r4, 64
+ b .cleareccloop
+.cleareccend:
+
+ /*
+ * Branch prediction enabled.
+ */
+ li %r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, %r3 /* BUCSR */
+
+ blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ lis %r3, BOOT_MSR_DEFAULT@h
+ ori %r3, %r3, BOOT_MSR_DEFAULT@l
+ mtMSR %r3
+
+ /* IVPR initialization.*/
+ lis %r3, __ivpr_base__@h
+ ori %r3, %r3, __ivpr_base__@l
+ mtIVPR %r3
+
+ blr
+
+ .section .ivors, "ax"
+
+ .globl IVORS
+IVORS:
+ b _IVOR0
+ .align 4
+ b _IVOR1
+ .align 4
+ b _IVOR2
+ .align 4
+ b _IVOR3
+ .align 4
+ b _IVOR4
+ .align 4
+ b _IVOR5
+ .align 4
+ b _IVOR6
+ .align 4
+ b _IVOR7
+ .align 4
+ b _IVOR8
+ .align 4
+ b _IVOR9
+ .align 4
+ b _IVOR10
+ .align 4
+ b _IVOR11
+ .align 4
+ b _IVOR12
+ .align 4
+ b _IVOR13
+ .align 4
+ b _IVOR14
+ .align 4
+ b _IVOR15
+
+ .section .handlers, "ax"
+
+ /*
+ * Default IVOR handlers.
+ */
+ .align 2
+ .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
+ .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
+ .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
+_IVOR0:
+_IVOR1:
+_IVOR2:
+_IVOR3:
+_IVOR5:
+_IVOR6:
+_IVOR7:
+_IVOR8:
+_IVOR9:
+_IVOR11:
+_IVOR12:
+_IVOR13:
+_IVOR14:
+_IVOR15:
+ .global _unhandled_exception
+_unhandled_exception:
+ b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC560BCxx/intc.h b/os/common/startup/e200/devices/SPC560BCxx/intc.h new file mode 100644 index 000000000..668eac387 --- /dev/null +++ b/os/common/startup/e200/devices/SPC560BCxx/intc.h @@ -0,0 +1,96 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC560BCxx/intc.h
+ * @brief SPC560BCxx INTC module header.
+ *
+ * @addtogroup INTC
+ * @{
+ */
+
+#ifndef _INTC_H_
+#define _INTC_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name INTC addresses
+ * @{
+ */
+#define INTC_BASE 0xFFF48000
+#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
+#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
+/** @} */
+
+/**
+ * @brief INTC priority levels.
+ */
+#define INTC_PRIORITY_LEVELS 16U
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name INTC-related macros
+ * @{
+ */
+#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
+#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
+#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
+#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
+#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
+/** @} */
+
+/**
+ * @brief Core selection macros for PSR register.
+ */
+#define INTC_PSR_CORE0 0x00
+
+/**
+ * @brief PSR register content helper
+ */
+#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _INTC_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC560BCxx/ppcparams.h b/os/common/startup/e200/devices/SPC560BCxx/ppcparams.h new file mode 100644 index 000000000..2e89aa8fb --- /dev/null +++ b/os/common/startup/e200/devices/SPC560BCxx/ppcparams.h @@ -0,0 +1,86 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC560BCxx/ppcparams.h
+ * @brief PowerPC parameters for the SPC560BCxx.
+ *
+ * @defgroup PPC_SPC560BCxx SPC560BCxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC560BCxx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief Family identification macro.
+ */
+#define PPC_SPC560BCxx
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z0
+
+/**
+ * @brief Number of cores.
+ */
+#define PPC_CORE_NUMBER 1
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 20
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS FALSE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE FALSE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER FALSE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 217
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC560Bxx/boot.h b/os/common/startup/e200/devices/SPC560Bxx/boot.h new file mode 100644 index 000000000..f6482d0af --- /dev/null +++ b/os/common/startup/e200/devices/SPC560Bxx/boot.h @@ -0,0 +1,117 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC560Bxx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_ME 0x00001000
+#define MSR_DE 0x00000200
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC560Bxx/boot.s b/os/common/startup/e200/devices/SPC560Bxx/boot.s new file mode 100644 index 000000000..7cf3349e5 --- /dev/null +++ b/os/common/startup/e200/devices/SPC560Bxx/boot.s @@ -0,0 +1,217 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC560Bxx/boot.s
+ * @brief SPC560Bxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+ .long 0x015A0000
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ bl _coreinit
+#endif
+ bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ lis %r4, __ram_reloc_start__@h
+ ori %r4, %r4, __ram_reloc_start__@l
+ lis %r5, __ram_reloc_dest__@h
+ ori %r5, %r5, __ram_reloc_dest__@l
+ lis %r6, __ram_reloc_end__@h
+ ori %r6, %r6, __ram_reloc_end__@l
+.relloop:
+ cmpl cr0, %r4, %r6
+ bge cr0, .relend
+ lwz %r7, 0(%r4)
+ addi %r4, %r4, 4
+ stw %r7, 0(%r5)
+ addi %r5, %r5, 4
+ b .relloop
+.relend:
+ lis %r3, _boot_address@h
+ ori %r3, %r3, _boot_address@l
+ mtctr %r3
+ bctrl
+#else
+ b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_coreinit:
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor %r0, %r0, %r0
+ xor %r1, %r1, %r1
+ xor %r2, %r2, %r2
+ xor %r3, %r3, %r3
+ xor %r4, %r4, %r4
+ xor %r5, %r5, %r5
+ xor %r6, %r6, %r6
+ xor %r7, %r7, %r7
+ xor %r8, %r8, %r8
+ xor %r9, %r9, %r9
+ xor %r10, %r10, %r10
+ xor %r11, %r11, %r11
+ xor %r12, %r12, %r12
+ xor %r13, %r13, %r13
+ xor %r14, %r14, %r14
+ xor %r15, %r15, %r15
+ xor %r16, %r16, %r16
+ xor %r17, %r17, %r17
+ xor %r18, %r18, %r18
+ xor %r19, %r19, %r19
+ xor %r20, %r20, %r20
+ xor %r21, %r21, %r21
+ xor %r22, %r22, %r22
+ xor %r23, %r23, %r23
+ xor %r24, %r24, %r24
+ xor %r25, %r25, %r25
+ xor %r26, %r26, %r26
+ xor %r27, %r27, %r27
+ xor %r28, %r28, %r28
+ xor %r29, %r29, %r29
+ xor %r30, %r30, %r30
+ xor %r31, %r31, %r31
+ lis %r4, __ram_start__@h
+ ori %r4, %r4, __ram_start__@l
+ lis %r5, __ram_end__@h
+ ori %r5, %r5, __ram_end__@l
+.cleareccloop:
+ cmpl %cr0, %r4, %r5
+ bge %cr0, .cleareccend
+ stmw %r16, 0(%r4)
+ addi %r4, %r4, 64
+ b .cleareccloop
+.cleareccend:
+
+ /*
+ * Branch prediction enabled.
+ */
+ li %r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, %r3 /* BUCSR */
+
+ blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ lis %r3, BOOT_MSR_DEFAULT@h
+ ori %r3, %r3, BOOT_MSR_DEFAULT@l
+ mtMSR %r3
+
+ /* IVPR initialization.*/
+ lis %r3, __ivpr_base__@h
+ ori %r3, %r3, __ivpr_base__@l
+ mtIVPR %r3
+
+ blr
+
+ .section .ivors, "ax"
+
+ .globl IVORS
+IVORS:
+ b _IVOR0
+ .align 4
+ b _IVOR1
+ .align 4
+ b _IVOR2
+ .align 4
+ b _IVOR3
+ .align 4
+ b _IVOR4
+ .align 4
+ b _IVOR5
+ .align 4
+ b _IVOR6
+ .align 4
+ b _IVOR7
+ .align 4
+ b _IVOR8
+ .align 4
+ b _IVOR9
+ .align 4
+ b _IVOR10
+ .align 4
+ b _IVOR11
+ .align 4
+ b _IVOR12
+ .align 4
+ b _IVOR13
+ .align 4
+ b _IVOR14
+ .align 4
+ b _IVOR15
+
+ .section .handlers, "ax"
+
+ /*
+ * Default IVOR handlers.
+ */
+ .align 2
+ .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
+ .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
+ .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
+_IVOR0:
+_IVOR1:
+_IVOR2:
+_IVOR3:
+_IVOR5:
+_IVOR6:
+_IVOR7:
+_IVOR8:
+_IVOR9:
+_IVOR11:
+_IVOR12:
+_IVOR13:
+_IVOR14:
+_IVOR15:
+ .global _unhandled_exception
+_unhandled_exception:
+ b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC560Bxx/intc.h b/os/common/startup/e200/devices/SPC560Bxx/intc.h new file mode 100644 index 000000000..bde2c94aa --- /dev/null +++ b/os/common/startup/e200/devices/SPC560Bxx/intc.h @@ -0,0 +1,96 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC560Bxx/intc.h
+ * @brief SPC560Bxx INTC module header.
+ *
+ * @addtogroup INTC
+ * @{
+ */
+
+#ifndef _INTC_H_
+#define _INTC_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name INTC addresses
+ * @{
+ */
+#define INTC_BASE 0xFFF48000
+#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
+#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
+/** @} */
+
+/**
+ * @brief INTC priority levels.
+ */
+#define INTC_PRIORITY_LEVELS 16U
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name INTC-related macros
+ * @{
+ */
+#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
+#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
+#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
+#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
+#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
+/** @} */
+
+/**
+ * @brief Core selection macros for PSR register.
+ */
+#define INTC_PSR_CORE0 0x00
+
+/**
+ * @brief PSR register content helper
+ */
+#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _INTC_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC560Bxx/ppcparams.h b/os/common/startup/e200/devices/SPC560Bxx/ppcparams.h new file mode 100644 index 000000000..6a1761421 --- /dev/null +++ b/os/common/startup/e200/devices/SPC560Bxx/ppcparams.h @@ -0,0 +1,86 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC560Bxx/ppcparams.h
+ * @brief PowerPC parameters for the SPC560Bxx.
+ *
+ * @defgroup PPC_SPC560Bxx SPC560Bxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC560Bxx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief Family identification macro.
+ */
+#define PPC_SPC560Bxx
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z0
+
+/**
+ * @brief Number of cores.
+ */
+#define PPC_CORE_NUMBER 1
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 20
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS FALSE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE FALSE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER FALSE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 234
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC560Dxx/boot.h b/os/common/startup/e200/devices/SPC560Dxx/boot.h new file mode 100644 index 000000000..9650c7a10 --- /dev/null +++ b/os/common/startup/e200/devices/SPC560Dxx/boot.h @@ -0,0 +1,117 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC560Dxx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_ME 0x00001000
+#define MSR_DE 0x00000200
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC560Dxx/boot.s b/os/common/startup/e200/devices/SPC560Dxx/boot.s new file mode 100644 index 000000000..601f14f20 --- /dev/null +++ b/os/common/startup/e200/devices/SPC560Dxx/boot.s @@ -0,0 +1,217 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC560Dxx/boot.s
+ * @brief SPC560Dxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+ .long 0x015A0000
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ bl _coreinit
+#endif
+ bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ lis r4, __ram_reloc_start__@h
+ ori r4, r4, __ram_reloc_start__@l
+ lis r5, __ram_reloc_dest__@h
+ ori r5, r5, __ram_reloc_dest__@l
+ lis r6, __ram_reloc_end__@h
+ ori r6, r6, __ram_reloc_end__@l
+.relloop:
+ cmpl cr0, r4, r6
+ bge cr0, .relend
+ lwz r7, 0(r4)
+ addi r4, r4, 4
+ stw r7, 0(r5)
+ addi r5, r5, 4
+ b .relloop
+.relend:
+ lis r3, _boot_address@h
+ ori r3, r3, _boot_address@l
+ mtctr r3
+ bctrl
+#else
+ b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_coreinit:
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor r0, r0, r0
+ xor r1, r1, r1
+ xor r2, r2, r2
+ xor r3, r3, r3
+ xor r4, r4, r4
+ xor r5, r5, r5
+ xor r6, r6, r6
+ xor r7, r7, r7
+ xor r8, r8, r8
+ xor r9, r9, r9
+ xor r10, r10, r10
+ xor r11, r11, r11
+ xor r12, r12, r12
+ xor r13, r13, r13
+ xor r14, r14, r14
+ xor r15, r15, r15
+ xor r16, r16, r16
+ xor r17, r17, r17
+ xor r18, r18, r18
+ xor r19, r19, r19
+ xor r20, r20, r20
+ xor r21, r21, r21
+ xor r22, r22, r22
+ xor r23, r23, r23
+ xor r24, r24, r24
+ xor r25, r25, r25
+ xor r26, r26, r26
+ xor r27, r27, r27
+ xor r28, r28, r28
+ xor r29, r29, r29
+ xor r30, r30, r30
+ xor r31, r31, r31
+ lis r4, __ram_start__@h
+ ori r4, r4, __ram_start__@l
+ lis r5, __ram_end__@h
+ ori r5, r5, __ram_end__@l
+.cleareccloop:
+ cmpl cr0, r4, r5
+ bge cr0, .cleareccend
+ stmw r16, 0(r4)
+ addi r4, r4, 64
+ b .cleareccloop
+.cleareccend:
+
+ /*
+ * Branch prediction enabled.
+ */
+ li r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, r3 /* BUCSR */
+
+ blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ lis r3, BOOT_MSR_DEFAULT@h
+ ori r3, r3, BOOT_MSR_DEFAULT@l
+ mtMSR r3
+
+ /* IVPR initialization.*/
+ lis r3, __ivpr_base__@h
+ ori r3, r3, __ivpr_base__@l
+ mtIVPR r3
+
+ blr
+
+ .section .ivors, "ax"
+
+ .globl IVORS
+IVORS:
+ b _IVOR0
+ .align 4
+ b _IVOR1
+ .align 4
+ b _IVOR2
+ .align 4
+ b _IVOR3
+ .align 4
+ b _IVOR4
+ .align 4
+ b _IVOR5
+ .align 4
+ b _IVOR6
+ .align 4
+ b _IVOR7
+ .align 4
+ b _IVOR8
+ .align 4
+ b _IVOR9
+ .align 4
+ b _IVOR10
+ .align 4
+ b _IVOR11
+ .align 4
+ b _IVOR12
+ .align 4
+ b _IVOR13
+ .align 4
+ b _IVOR14
+ .align 4
+ b _IVOR15
+
+ .section .handlers, "ax"
+
+ /*
+ * Default IVOR handlers.
+ */
+ .align 2
+ .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
+ .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
+ .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
+_IVOR0:
+_IVOR1:
+_IVOR2:
+_IVOR3:
+_IVOR5:
+_IVOR6:
+_IVOR7:
+_IVOR8:
+_IVOR9:
+_IVOR11:
+_IVOR12:
+_IVOR13:
+_IVOR14:
+_IVOR15:
+ .global _unhandled_exception
+_unhandled_exception:
+ b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC560Dxx/boot_cw.s b/os/common/startup/e200/devices/SPC560Dxx/boot_cw.s new file mode 100644 index 000000000..a2b268a17 --- /dev/null +++ b/os/common/startup/e200/devices/SPC560Dxx/boot_cw.s @@ -0,0 +1,203 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC560Dxx/boot.s
+ * @brief SPC560Dxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ .extern _boot_address
+ .extern __ram_start__
+ .extern __ram_end__
+ .extern __ivpr_base__
+
+ .extern _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
+ .extern _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
+ .extern _IVOR12, _IVOR13, _IVOR14, _IVOR15
+
+ /* BAM record.*/
+ .section .boot, 16
+
+ .long 0x015A0000
+ .long _reset_address
+
+ .align 4
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ se_bl _coreinit
+#endif
+ se_bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ e_lis r4, __ram_reloc_start__@h
+ e_or2i r4, r4, __ram_reloc_start__@l
+ e_lis r5, __ram_reloc_dest__@h
+ e_or2i r5, r5, __ram_reloc_dest__@l
+ e_lis r6, __ram_reloc_end__@h
+ e_or2i r6, r6, __ram_reloc_end__@l
+.relloop:
+ se_cmpl r4, r6
+ se_bge .relend
+ se_lwz r7, 0(r4)
+ se_addi r4, 4
+ se_stw r7, 0(r5)
+ se_addi r5, 4
+ se_b .relloop
+.relend:
+ e_lis r3, _boot_address@h
+ e_or2i r3, _boot_address@l
+ mtctr r3
+ se_bctrl
+#else
+ e_b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 4
+_coreinit:
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor r0, r0, r0
+ xor r1, r1, r1
+ xor r2, r2, r2
+ xor r3, r3, r3
+ xor r4, r4, r4
+ xor r5, r5, r5
+ xor r6, r6, r6
+ xor r7, r7, r7
+ xor r8, r8, r8
+ xor r9, r9, r9
+ xor r10, r10, r10
+ xor r11, r11, r11
+ xor r12, r12, r12
+ xor r13, r13, r13
+ xor r14, r14, r14
+ xor r15, r15, r15
+ xor r16, r16, r16
+ xor r17, r17, r17
+ xor r18, r18, r18
+ xor r19, r19, r19
+ xor r20, r20, r20
+ xor r21, r21, r21
+ xor r22, r22, r22
+ xor r23, r23, r23
+ xor r24, r24, r24
+ xor r25, r25, r25
+ xor r26, r26, r26
+ xor r27, r27, r27
+ xor r28, r28, r28
+ xor r29, r29, r29
+ xor r30, r30, r30
+ xor r31, r31, r31
+ e_lis r4, __ram_start__@h
+ e_or2i r4, __ram_start__@l
+ e_lis r5, __ram_end__@h
+ e_or2i r5, __ram_end__@l
+.cleareccloop:
+ se_cmpl r4, r5
+ se_bge .cleareccend
+ e_stmw r16, 0(r4)
+ e_addi r4, r4, 64
+ se_b .cleareccloop
+.cleareccend:
+
+ /*
+ * Branch prediction enabled.
+ */
+ e_li r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, r3 /* BUCSR */
+
+ se_blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 4
+_ivinit:
+ /* MSR initialization.*/
+ e_lis r3, BOOT_MSR_DEFAULT@h
+ e_ori r3, r3, BOOT_MSR_DEFAULT@l
+ mtMSR r3
+
+ /* IVPR initialization.*/
+ e_lis r3, __ivpr_base__@h
+ e_or2i r3, __ivpr_base__@l
+ mtIVPR r3
+
+ se_blr
+
+ .section .ivors, text_vle
+ .align 16
+ .globl IVORS
+IVORS:
+ e_b _IVOR0
+ .align 16
+ e_b _IVOR1
+ .align 16
+ e_b _IVOR2
+ .align 16
+ e_b _IVOR3
+ .align 16
+ e_b _IVOR4
+ .align 16
+ e_b _IVOR5
+ .align 16
+ e_b _IVOR6
+ .align 16
+ e_b _IVOR7
+ .align 16
+ e_b _IVOR8
+ .align 16
+ e_b _IVOR9
+ .align 16
+ e_b _IVOR10
+ .align 16
+ e_b _IVOR11
+ .align 16
+ e_b _IVOR12
+ .align 16
+ e_b _IVOR13
+ .align 16
+ e_b _IVOR14
+ .align 16
+ e_b _IVOR15
+
+ .section .handlers, text_vle
+ .align 16
+
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC560Dxx/intc.h b/os/common/startup/e200/devices/SPC560Dxx/intc.h new file mode 100644 index 000000000..6c3bbec60 --- /dev/null +++ b/os/common/startup/e200/devices/SPC560Dxx/intc.h @@ -0,0 +1,96 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC560Dxx/intc.h
+ * @brief SPC560Dxx INTC module header.
+ *
+ * @addtogroup INTC
+ * @{
+ */
+
+#ifndef _INTC_H_
+#define _INTC_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name INTC addresses
+ * @{
+ */
+#define INTC_BASE 0xFFF48000
+#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
+#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
+/** @} */
+
+/**
+ * @brief INTC priority levels.
+ */
+#define INTC_PRIORITY_LEVELS 16U
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name INTC-related macros
+ * @{
+ */
+#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
+#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
+#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
+#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
+#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
+/** @} */
+
+/**
+ * @brief Core selection macros for PSR register.
+ */
+#define INTC_PSR_CORE0 0x00
+
+/**
+ * @brief PSR register content helper
+ */
+#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _INTC_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC560Dxx/ppcparams.h b/os/common/startup/e200/devices/SPC560Dxx/ppcparams.h new file mode 100644 index 000000000..4a62a0772 --- /dev/null +++ b/os/common/startup/e200/devices/SPC560Dxx/ppcparams.h @@ -0,0 +1,86 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC560Dxx/ppcparams.h
+ * @brief PowerPC parameters for the SPC560Dxx.
+ *
+ * @defgroup PPC_SPC560Dxx SPC560Dxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC560Dxx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief Family identification macro.
+ */
+#define PPC_SPC560Dxx
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z0
+
+/**
+ * @brief Number of cores.
+ */
+#define PPC_CORE_NUMBER 1
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 20
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS FALSE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE FALSE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER FALSE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 155
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC560Pxx/boot.h b/os/common/startup/e200/devices/SPC560Pxx/boot.h new file mode 100644 index 000000000..2c104d402 --- /dev/null +++ b/os/common/startup/e200/devices/SPC560Pxx/boot.h @@ -0,0 +1,117 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC560Pxx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_ME 0x00001000
+#define MSR_DE 0x00000200
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC560Pxx/boot.s b/os/common/startup/e200/devices/SPC560Pxx/boot.s new file mode 100644 index 000000000..cdbecf616 --- /dev/null +++ b/os/common/startup/e200/devices/SPC560Pxx/boot.s @@ -0,0 +1,217 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC560Pxx/boot.s
+ * @brief SPC560Pxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+ .long 0x015A0000
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ bl _coreinit
+#endif
+ bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ lis %r4, __ram_reloc_start__@h
+ ori %r4, %r4, __ram_reloc_start__@l
+ lis %r5, __ram_reloc_dest__@h
+ ori %r5, %r5, __ram_reloc_dest__@l
+ lis %r6, __ram_reloc_end__@h
+ ori %r6, %r6, __ram_reloc_end__@l
+.relloop:
+ cmpl cr0, %r4, %r6
+ bge cr0, .relend
+ lwz %r7, 0(%r4)
+ addi %r4, %r4, 4
+ stw %r7, 0(%r5)
+ addi %r5, %r5, 4
+ b .relloop
+.relend:
+ lis %r3, _boot_address@h
+ ori %r3, %r3, _boot_address@l
+ mtctr %r3
+ bctrl
+#else
+ b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_coreinit:
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor %r0, %r0, %r0
+ xor %r1, %r1, %r1
+ xor %r2, %r2, %r2
+ xor %r3, %r3, %r3
+ xor %r4, %r4, %r4
+ xor %r5, %r5, %r5
+ xor %r6, %r6, %r6
+ xor %r7, %r7, %r7
+ xor %r8, %r8, %r8
+ xor %r9, %r9, %r9
+ xor %r10, %r10, %r10
+ xor %r11, %r11, %r11
+ xor %r12, %r12, %r12
+ xor %r13, %r13, %r13
+ xor %r14, %r14, %r14
+ xor %r15, %r15, %r15
+ xor %r16, %r16, %r16
+ xor %r17, %r17, %r17
+ xor %r18, %r18, %r18
+ xor %r19, %r19, %r19
+ xor %r20, %r20, %r20
+ xor %r21, %r21, %r21
+ xor %r22, %r22, %r22
+ xor %r23, %r23, %r23
+ xor %r24, %r24, %r24
+ xor %r25, %r25, %r25
+ xor %r26, %r26, %r26
+ xor %r27, %r27, %r27
+ xor %r28, %r28, %r28
+ xor %r29, %r29, %r29
+ xor %r30, %r30, %r30
+ xor %r31, %r31, %r31
+ lis %r4, __ram_start__@h
+ ori %r4, %r4, __ram_start__@l
+ lis %r5, __ram_end__@h
+ ori %r5, %r5, __ram_end__@l
+.cleareccloop:
+ cmpl %cr0, %r4, %r5
+ bge %cr0, .cleareccend
+ stmw %r16, 0(%r4)
+ addi %r4, %r4, 64
+ b .cleareccloop
+.cleareccend:
+
+ /*
+ * Branch prediction enabled.
+ */
+ li %r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, %r3 /* BUCSR */
+
+ blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ lis %r3, BOOT_MSR_DEFAULT@h
+ ori %r3, %r3, BOOT_MSR_DEFAULT@l
+ mtMSR %r3
+
+ /* IVPR initialization.*/
+ lis %r3, __ivpr_base__@h
+ ori %r3, %r3, __ivpr_base__@l
+ mtIVPR %r3
+
+ blr
+
+ .section .ivors, "ax"
+
+ .globl IVORS
+IVORS:
+ b _IVOR0
+ .align 4
+ b _IVOR1
+ .align 4
+ b _IVOR2
+ .align 4
+ b _IVOR3
+ .align 4
+ b _IVOR4
+ .align 4
+ b _IVOR5
+ .align 4
+ b _IVOR6
+ .align 4
+ b _IVOR7
+ .align 4
+ b _IVOR8
+ .align 4
+ b _IVOR9
+ .align 4
+ b _IVOR10
+ .align 4
+ b _IVOR11
+ .align 4
+ b _IVOR12
+ .align 4
+ b _IVOR13
+ .align 4
+ b _IVOR14
+ .align 4
+ b _IVOR15
+
+ .section .handlers, "ax"
+
+ /*
+ * Default IVOR handlers.
+ */
+ .align 2
+ .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
+ .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
+ .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
+_IVOR0:
+_IVOR1:
+_IVOR2:
+_IVOR3:
+_IVOR5:
+_IVOR6:
+_IVOR7:
+_IVOR8:
+_IVOR9:
+_IVOR11:
+_IVOR12:
+_IVOR13:
+_IVOR14:
+_IVOR15:
+ .global _unhandled_exception
+_unhandled_exception:
+ b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC560Pxx/intc.h b/os/common/startup/e200/devices/SPC560Pxx/intc.h new file mode 100644 index 000000000..75440fb75 --- /dev/null +++ b/os/common/startup/e200/devices/SPC560Pxx/intc.h @@ -0,0 +1,96 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC560Pxx/intc.h
+ * @brief SPC560Pxx INTC module header.
+ *
+ * @addtogroup INTC
+ * @{
+ */
+
+#ifndef _INTC_H_
+#define _INTC_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name INTC addresses
+ * @{
+ */
+#define INTC_BASE 0xFFF48000
+#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
+#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
+/** @} */
+
+/**
+ * @brief INTC priority levels.
+ */
+#define INTC_PRIORITY_LEVELS 16U
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name INTC-related macros
+ * @{
+ */
+#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
+#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
+#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
+#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
+#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
+/** @} */
+
+/**
+ * @brief Core selection macros for PSR register.
+ */
+#define INTC_PSR_CORE0 0x00
+
+/**
+ * @brief PSR register content helper
+ */
+#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _INTC_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC560Pxx/ppcparams.h b/os/common/startup/e200/devices/SPC560Pxx/ppcparams.h new file mode 100644 index 000000000..9bd1c565a --- /dev/null +++ b/os/common/startup/e200/devices/SPC560Pxx/ppcparams.h @@ -0,0 +1,86 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC560Pxx/ppcparams.h
+ * @brief PowerPC parameters for the SPC560Pxx.
+ *
+ * @defgroup PPC_SPC560Pxx SPC560Pxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC560Pxx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief Family identification macro.
+ */
+#define PPC_SPC560Pxx
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z0
+
+/**
+ * @brief Number of cores.
+ */
+#define PPC_CORE_NUMBER 1
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 20
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS FALSE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE FALSE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER FALSE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 261
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC563Mxx/boot.h b/os/common/startup/e200/devices/SPC563Mxx/boot.h new file mode 100644 index 000000000..a5fd71c62 --- /dev/null +++ b/os/common/startup/e200/devices/SPC563Mxx/boot.h @@ -0,0 +1,122 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC563Mxx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_UCLE 0x04000000
+#define MSR_SPE 0x02000000
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_FP 0x00002000
+#define MSR_ME 0x00001000
+#define MSR_FE0 0x00000800
+#define MSR_DE 0x00000200
+#define MSR_FE1 0x00000100
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC563Mxx/boot.s b/os/common/startup/e200/devices/SPC563Mxx/boot.s new file mode 100644 index 000000000..d9627dd39 --- /dev/null +++ b/os/common/startup/e200/devices/SPC563Mxx/boot.s @@ -0,0 +1,191 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC563Mxx/boot.s
+ * @brief SPC563Mxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+#if BOOT_USE_VLE
+ .long 0x015A0000
+#else
+ .long 0x005A0000
+#endif
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ bl _coreinit
+#endif
+ bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ lis %r4, __ram_reloc_start__@h
+ ori %r4, %r4, __ram_reloc_start__@l
+ lis %r5, __ram_reloc_dest__@h
+ ori %r5, %r5, __ram_reloc_dest__@l
+ lis %r6, __ram_reloc_end__@h
+ ori %r6, %r6, __ram_reloc_end__@l
+.relloop:
+ cmpl cr0, %r4, %r6
+ bge cr0, .relend
+ lwz %r7, 0(%r4)
+ addi %r4, %r4, 4
+ stw %r7, 0(%r5)
+ addi %r5, %r5, 4
+ b .relloop
+.relend:
+ lis %r3, _boot_address@h
+ ori %r3, %r3, _boot_address@l
+ mtctr %r3
+ bctrl
+#else
+ b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_coreinit:
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor %r0, %r0, %r0
+ xor %r1, %r1, %r1
+ xor %r2, %r2, %r2
+ xor %r3, %r3, %r3
+ xor %r4, %r4, %r4
+ xor %r5, %r5, %r5
+ xor %r6, %r6, %r6
+ xor %r7, %r7, %r7
+ xor %r8, %r8, %r8
+ xor %r9, %r9, %r9
+ xor %r10, %r10, %r10
+ xor %r11, %r11, %r11
+ xor %r12, %r12, %r12
+ xor %r13, %r13, %r13
+ xor %r14, %r14, %r14
+ xor %r15, %r15, %r15
+ xor %r16, %r16, %r16
+ xor %r17, %r17, %r17
+ xor %r18, %r18, %r18
+ xor %r19, %r19, %r19
+ xor %r20, %r20, %r20
+ xor %r21, %r21, %r21
+ xor %r22, %r22, %r22
+ xor %r23, %r23, %r23
+ xor %r24, %r24, %r24
+ xor %r25, %r25, %r25
+ xor %r26, %r26, %r26
+ xor %r27, %r27, %r27
+ xor %r28, %r28, %r28
+ xor %r29, %r29, %r29
+ xor %r30, %r30, %r30
+ xor %r31, %r31, %r31
+ lis %r4, __ram_start__@h
+ ori %r4, %r4, __ram_start__@l
+ lis %r5, __ram_end__@h
+ ori %r5, %r5, __ram_end__@l
+.cleareccloop:
+ cmpl %cr0, %r4, %r5
+ bge %cr0, .cleareccend
+ stmw %r16, 0(%r4)
+ addi %r4, %r4, 64
+ b .cleareccloop
+.cleareccend:
+
+ /*
+ * Branch prediction enabled.
+ */
+ li %r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, %r3 /* BUCSR */
+
+ blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+_ivinit:
+ /* MSR initialization.*/
+ lis %r3, BOOT_MSR_DEFAULT@h
+ ori %r3, %r3, BOOT_MSR_DEFAULT@l
+ mtMSR %r3
+
+ /* IVPR initialization.*/
+ lis %r3, __ivpr_base__@h
+ ori %r3, %r3, __ivpr_base__@l
+ mtIVPR %r3
+
+ /* IVORs initialization.*/
+ lis %r3, _unhandled_exception@h
+ ori %r3, %r3, _unhandled_exception@l
+
+ mtspr 400, %r3 /* IVOR0-15 */
+ mtspr 401, %r3
+ mtspr 402, %r3
+ mtspr 403, %r3
+ mtspr 404, %r3
+ mtspr 405, %r3
+ mtspr 406, %r3
+ mtspr 407, %r3
+ mtspr 408, %r3
+ mtspr 409, %r3
+ mtspr 410, %r3
+ mtspr 411, %r3
+ mtspr 412, %r3
+ mtspr 413, %r3
+ mtspr 414, %r3
+ mtspr 415, %r3
+ mtspr 528, %r3 /* IVOR32-34 */
+ mtspr 529, %r3
+ mtspr 530, %r3
+
+ blr
+
+ .section .handlers, "ax"
+
+ /*
+ * Unhandled exceptions handler.
+ */
+ .weak _unhandled_exception
+ .type _unhandled_exception, @function
+_unhandled_exception:
+ b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC563Mxx/intc.h b/os/common/startup/e200/devices/SPC563Mxx/intc.h new file mode 100644 index 000000000..b7a5d920a --- /dev/null +++ b/os/common/startup/e200/devices/SPC563Mxx/intc.h @@ -0,0 +1,96 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC563Mxx/intc.h
+ * @brief SPC563Mxx INTC module header.
+ *
+ * @addtogroup INTC
+ * @{
+ */
+
+#ifndef _INTC_H_
+#define _INTC_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name INTC addresses
+ * @{
+ */
+#define INTC_BASE 0xFFF48000
+#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
+#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
+/** @} */
+
+/**
+ * @brief INTC priority levels.
+ */
+#define INTC_PRIORITY_LEVELS 16U
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name INTC-related macros
+ * @{
+ */
+#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
+#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
+#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
+#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
+#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
+/** @} */
+
+/**
+ * @brief Core selection macros for PSR register.
+ */
+#define INTC_PSR_CORE0 0x00
+
+/**
+ * @brief PSR register content helper
+ */
+#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _INTC_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC563Mxx/ppcparams.h b/os/common/startup/e200/devices/SPC563Mxx/ppcparams.h new file mode 100644 index 000000000..315e53f0b --- /dev/null +++ b/os/common/startup/e200/devices/SPC563Mxx/ppcparams.h @@ -0,0 +1,86 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC563Mxx/ppcparams.h
+ * @brief PowerPC parameters for the SPC563Mxx.
+ *
+ * @defgroup PPC_SPC563Mxx SPC563Mxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC563Mxx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief Family identification macro.
+ */
+#define PPC_SPC563Mxx
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z3
+
+/**
+ * @brief Number of cores.
+ */
+#define PPC_CORE_NUMBER 1
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 16
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS TRUE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE TRUE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER TRUE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 360
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC564Axx/boot.h b/os/common/startup/e200/devices/SPC564Axx/boot.h new file mode 100644 index 000000000..14a13840b --- /dev/null +++ b/os/common/startup/e200/devices/SPC564Axx/boot.h @@ -0,0 +1,245 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC564Axx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name MASx registers definitions
+ * @{
+ */
+#define MAS0_TBLMAS_TBL 0x10000000
+#define MAS0_ESEL_MASK 0x000F0000
+#define MAS0_ESEL(n) ((n) << 16)
+
+#define MAS1_VALID 0x80000000
+#define MAS1_IPROT 0x40000000
+#define MAS1_TID_MASK 0x00FF0000
+#define MAS1_TS 0x00001000
+#define MAS1_TSISE_MASK 0x00000F80
+#define MAS1_TSISE_1K 0x00000000
+#define MAS1_TSISE_2K 0x00000080
+#define MAS1_TSISE_4K 0x00000100
+#define MAS1_TSISE_8K 0x00000180
+#define MAS1_TSISE_16K 0x00000200
+#define MAS1_TSISE_32K 0x00000280
+#define MAS1_TSISE_64K 0x00000300
+#define MAS1_TSISE_128K 0x00000380
+#define MAS1_TSISE_256K 0x00000400
+#define MAS1_TSISE_512K 0x00000480
+#define MAS1_TSISE_1M 0x00000500
+#define MAS1_TSISE_2M 0x00000580
+#define MAS1_TSISE_4M 0x00000600
+#define MAS1_TSISE_8M 0x00000680
+#define MAS1_TSISE_16M 0x00000700
+#define MAS1_TSISE_32M 0x00000780
+#define MAS1_TSISE_64M 0x00000800
+#define MAS1_TSISE_128M 0x00000880
+#define MAS1_TSISE_256M 0x00000900
+#define MAS1_TSISE_512M 0x00000980
+#define MAS1_TSISE_1G 0x00000A00
+#define MAS1_TSISE_2G 0x00000A80
+#define MAS1_TSISE_4G 0x00000B00
+
+#define MAS2_EPN_MASK 0xFFFFFC00
+#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK)
+#define MAS2_EBOOK 0x00000000
+#define MAS2_VLE 0x00000020
+#define MAS2_W 0x00000010
+#define MAS2_I 0x00000008
+#define MAS2_M 0x00000004
+#define MAS2_G 0x00000002
+#define MAS2_E 0x00000001
+
+#define MAS3_RPN_MASK 0xFFFFFC00
+#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK)
+#define MAS3_U0 0x00000200
+#define MAS3_U1 0x00000100
+#define MAS3_U2 0x00000080
+#define MAS3_U3 0x00000040
+#define MAS3_UX 0x00000020
+#define MAS3_SX 0x00000010
+#define MAS3_UW 0x00000008
+#define MAS3_SW 0x00000004
+#define MAS3_UR 0x00000002
+#define MAS3_SR 0x00000001
+/** @} */
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BPRED_MASK 0x00000006
+#define BUCSR_BPRED_0 0x00000000
+#define BUCSR_BPRED_1 0x00000002
+#define BUCSR_BPRED_2 0x00000004
+#define BUCSR_BPRED_3 0x00000006
+#define BUCSR_BALLOC_MASK 0x00000030
+#define BUCSR_BALLOC_0 0x00000000
+#define BUCSR_BALLOC_1 0x00000010
+#define BUCSR_BALLOC_2 0x00000020
+#define BUCSR_BALLOC_3 0x00000030
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name LICSR1 registers definitions
+ * @{
+ */
+#define LICSR1_ICE 0x00000001
+#define LICSR1_ICINV 0x00000002
+#define LICSR1_ICORG 0x00000010
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_UCLE 0x04000000
+#define MSR_SPE 0x02000000
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_FP 0x00002000
+#define MSR_ME 0x00001000
+#define MSR_FE0 0x00000800
+#define MSR_DE 0x00000200
+#define MSR_FE1 0x00000100
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * TLB default settings.
+ */
+#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
+#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
+#define TLB0_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE)
+#define TLB0_MAS3 (MAS3_RPN(0x40000000) | \
+ MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
+ MAS3_UR | MAS3_SR)
+
+#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
+#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_4M)
+#define TLB1_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE)
+#define TLB1_MAS3 (MAS3_RPN(0x00000000) | \
+ MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
+ MAS3_UR | MAS3_SR)
+
+#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
+#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I)
+#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
+#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I)
+#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
+#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB4_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I)
+#define TLB4_MAS3 (MAS3_RPN(0xFFF00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \
+ BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * LICSR1 default settings.
+ */
+#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC564Axx/boot.s b/os/common/startup/e200/devices/SPC564Axx/boot.s new file mode 100644 index 000000000..549f926ec --- /dev/null +++ b/os/common/startup/e200/devices/SPC564Axx/boot.s @@ -0,0 +1,356 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC564Axx/boot.s
+ * @brief SPC564Axx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+#if BOOT_USE_VLE
+ .long 0x015A0000
+#else
+ .long 0x005A0000
+#endif
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ bl _coreinit
+#endif
+ bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ lis %r4, __ram_reloc_start__@h
+ ori %r4, %r4, __ram_reloc_start__@l
+ lis %r5, __ram_reloc_dest__@h
+ ori %r5, %r5, __ram_reloc_dest__@l
+ lis %r6, __ram_reloc_end__@h
+ ori %r6, %r6, __ram_reloc_end__@l
+.relloop:
+ cmpl cr0, %r4, %r6
+ bge cr0, .relend
+ lwz %r7, 0(%r4)
+ addi %r4, %r4, 4
+ stw %r7, 0(%r5)
+ addi %r5, %r5, 4
+ b .relloop
+.relend:
+ lis %r3, _boot_address@h
+ ori %r3, %r3, _boot_address@l
+ mtctr %r3
+ bctrl
+#else
+ b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_ramcode:
+ tlbwe
+ isync
+ blr
+
+ .align 2
+_coreinit:
+ /*
+ * Invalidating all TLBs except TLB1.
+ */
+ lis %r3, 0
+ mtspr 625, %r3 /* MAS1 */
+ mtspr 626, %r3 /* MAS2 */
+ mtspr 627, %r3 /* MAS3 */
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(0))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+
+ /*
+ * TLB0 allocated to internal RAM.
+ */
+ lis %r3, TLB0_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB0_MAS1@h
+ ori %r3, %r3, TLB0_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB0_MAS2@h
+ ori %r3, %r3, TLB0_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB0_MAS3@h
+ ori %r3, %r3, TLB0_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB2 allocated to internal Peripherals Bridge A.
+ */
+ lis %r3, TLB2_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB2_MAS1@h
+ ori %r3, %r3, TLB2_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB2_MAS2@h
+ ori %r3, %r3, TLB2_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB2_MAS3@h
+ ori %r3, %r3, TLB2_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB3 allocated to internal Peripherals Bridge B.
+ */
+ lis %r3, TLB3_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB3_MAS1@h
+ ori %r3, %r3, TLB3_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB3_MAS2@h
+ ori %r3, %r3, TLB3_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB3_MAS3@h
+ ori %r3, %r3, TLB3_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB4 allocated to on-platform peripherals.
+ */
+ lis %r3, TLB4_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB4_MAS1@h
+ ori %r3, %r3, TLB4_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB4_MAS2@h
+ ori %r3, %r3, TLB4_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB4_MAS3@h
+ ori %r3, %r3, TLB4_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor %r0, %r0, %r0
+ xor %r1, %r1, %r1
+ xor %r2, %r2, %r2
+ xor %r3, %r3, %r3
+ xor %r4, %r4, %r4
+ xor %r5, %r5, %r5
+ xor %r6, %r6, %r6
+ xor %r7, %r7, %r7
+ xor %r8, %r8, %r8
+ xor %r9, %r9, %r9
+ xor %r10, %r10, %r10
+ xor %r11, %r11, %r11
+ xor %r12, %r12, %r12
+ xor %r13, %r13, %r13
+ xor %r14, %r14, %r14
+ xor %r15, %r15, %r15
+ xor %r16, %r16, %r16
+ xor %r17, %r17, %r17
+ xor %r18, %r18, %r18
+ xor %r19, %r19, %r19
+ xor %r20, %r20, %r20
+ xor %r21, %r21, %r21
+ xor %r22, %r22, %r22
+ xor %r23, %r23, %r23
+ xor %r24, %r24, %r24
+ xor %r25, %r25, %r25
+ xor %r26, %r26, %r26
+ xor %r27, %r27, %r27
+ xor %r28, %r28, %r28
+ xor %r29, %r29, %r29
+ xor %r30, %r30, %r30
+ xor %r31, %r31, %r31
+ lis %r4, __ram_start__@h
+ ori %r4, %r4, __ram_start__@l
+ lis %r5, __ram_end__@h
+ ori %r5, %r5, __ram_end__@l
+.cleareccloop:
+ cmpl %cr0, %r4, %r5
+ bge %cr0, .cleareccend
+ stmw %r16, 0(%r4)
+ addi %r4, %r4, 64
+ b .cleareccloop
+.cleareccend:
+
+ /*
+ * *Finally* the TLB1 is re-allocated to flash, note, the final phase
+ * is executed from RAM.
+ */
+ lis %r3, TLB1_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB1_MAS1@h
+ ori %r3, %r3, TLB1_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB1_MAS2@h
+ ori %r3, %r3, TLB1_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB1_MAS3@h
+ ori %r3, %r3, TLB1_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ mflr %r4
+ lis %r6, _ramcode@h
+ ori %r6, %r6, _ramcode@l
+ lis %r7, 0x40010000@h
+ mtctr %r7
+ lwz %r3, 0(%r6)
+ stw %r3, 0(%r7)
+ lwz %r3, 4(%r6)
+ stw %r3, 4(%r7)
+ lwz %r3, 8(%r6)
+ stw %r3, 8(%r7)
+ bctrl
+ mtlr %r4
+
+ /*
+ * Branch prediction enabled.
+ */
+ li %r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, %r3 /* BUCSR */
+
+ /*
+ * Cache invalidated and then enabled.
+ */
+ li %r3, LICSR1_ICINV
+ mtspr 1011, %r3 /* LICSR1 */
+.inv: mfspr %r3, 1011 /* LICSR1 */
+ andi. %r3, %r3, LICSR1_ICINV
+ bne .inv
+ lis %r3, BOOT_LICSR1_DEFAULT@h
+ ori %r3, %r3, BOOT_LICSR1_DEFAULT@l
+ mtspr 1011, %r3 /* LICSR1 */
+
+ blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ lis %r3, BOOT_MSR_DEFAULT@h
+ ori %r3, %r3, BOOT_MSR_DEFAULT@l
+ mtMSR %r3
+
+ /* IVPR initialization.*/
+ lis %r3, __ivpr_base__@h
+ ori %r3, %r3, __ivpr_base__@l
+ mtIVPR %r3
+
+ /* IVORs initialization.*/
+ lis %r3, _unhandled_exception@h
+ ori %r3, %r3, _unhandled_exception@l
+
+ mtspr 400, %r3 /* IVOR0-15 */
+ mtspr 401, %r3
+ mtspr 402, %r3
+ mtspr 403, %r3
+ mtspr 404, %r3
+ mtspr 405, %r3
+ mtspr 406, %r3
+ mtspr 407, %r3
+ mtspr 408, %r3
+ mtspr 409, %r3
+ mtspr 410, %r3
+ mtspr 411, %r3
+ mtspr 412, %r3
+ mtspr 413, %r3
+ mtspr 414, %r3
+ mtspr 415, %r3
+ mtspr 528, %r3 /* IVOR32-34 */
+ mtspr 529, %r3
+ mtspr 530, %r3
+
+ blr
+
+ .section .handlers, "ax"
+
+ /*
+ * Unhandled exceptions handler.
+ */
+ .weak _unhandled_exception
+ .type _unhandled_exception, @function
+_unhandled_exception:
+ b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC564Axx/intc.h b/os/common/startup/e200/devices/SPC564Axx/intc.h new file mode 100644 index 000000000..7f34613d9 --- /dev/null +++ b/os/common/startup/e200/devices/SPC564Axx/intc.h @@ -0,0 +1,96 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC564Axx/intc.h
+ * @brief SPC564Axx INTC module header.
+ *
+ * @addtogroup INTC
+ * @{
+ */
+
+#ifndef _INTC_H_
+#define _INTC_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name INTC addresses
+ * @{
+ */
+#define INTC_BASE 0xFFF48000
+#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
+#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
+/** @} */
+
+/**
+ * @brief INTC priority levels.
+ */
+#define INTC_PRIORITY_LEVELS 16U
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name INTC-related macros
+ * @{
+ */
+#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
+#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
+#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
+#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
+#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
+/** @} */
+
+/**
+ * @brief Core selection macros for PSR register.
+ */
+#define INTC_PSR_CORE0 0x00
+
+/**
+ * @brief PSR register content helper
+ */
+#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _INTC_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC564Axx/ppcparams.h b/os/common/startup/e200/devices/SPC564Axx/ppcparams.h new file mode 100644 index 000000000..ed4716b99 --- /dev/null +++ b/os/common/startup/e200/devices/SPC564Axx/ppcparams.h @@ -0,0 +1,86 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC564Axx/ppcparams.h
+ * @brief PowerPC parameters for the SPC564Axx.
+ *
+ * @defgroup PPC_SPC564Axx SPC564Axx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC564Axx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief Family identification macro.
+ */
+#define PPC_SPC564Axx
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z4
+
+/**
+ * @brief Number of cores.
+ */
+#define PPC_CORE_NUMBER 1
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 16
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS TRUE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE TRUE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER TRUE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 486
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC56ECxx/boot.h b/os/common/startup/e200/devices/SPC56ECxx/boot.h new file mode 100644 index 000000000..4c50922b8 --- /dev/null +++ b/os/common/startup/e200/devices/SPC56ECxx/boot.h @@ -0,0 +1,251 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC56ECxx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name MASx registers definitions
+ * @{
+ */
+#define MAS0_TBLMAS_TBL 0x10000000
+#define MAS0_ESEL_MASK 0x000F0000
+#define MAS0_ESEL(n) ((n) << 16)
+
+#define MAS1_VALID 0x80000000
+#define MAS1_IPROT 0x40000000
+#define MAS1_TID_MASK 0x00FF0000
+#define MAS1_TS 0x00001000
+#define MAS1_TSISE_MASK 0x00000F80
+#define MAS1_TSISE_1K 0x00000000
+#define MAS1_TSISE_2K 0x00000080
+#define MAS1_TSISE_4K 0x00000100
+#define MAS1_TSISE_8K 0x00000180
+#define MAS1_TSISE_16K 0x00000200
+#define MAS1_TSISE_32K 0x00000280
+#define MAS1_TSISE_64K 0x00000300
+#define MAS1_TSISE_128K 0x00000380
+#define MAS1_TSISE_256K 0x00000400
+#define MAS1_TSISE_512K 0x00000480
+#define MAS1_TSISE_1M 0x00000500
+#define MAS1_TSISE_2M 0x00000580
+#define MAS1_TSISE_4M 0x00000600
+#define MAS1_TSISE_8M 0x00000680
+#define MAS1_TSISE_16M 0x00000700
+#define MAS1_TSISE_32M 0x00000780
+#define MAS1_TSISE_64M 0x00000800
+#define MAS1_TSISE_128M 0x00000880
+#define MAS1_TSISE_256M 0x00000900
+#define MAS1_TSISE_512M 0x00000980
+#define MAS1_TSISE_1G 0x00000A00
+#define MAS1_TSISE_2G 0x00000A80
+#define MAS1_TSISE_4G 0x00000B00
+
+#define MAS2_EPN_MASK 0xFFFFFC00
+#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK)
+#define MAS2_EBOOK 0x00000000
+#define MAS2_VLE 0x00000020
+#define MAS2_W 0x00000010
+#define MAS2_I 0x00000008
+#define MAS2_M 0x00000004
+#define MAS2_G 0x00000002
+#define MAS2_E 0x00000001
+
+#define MAS3_RPN_MASK 0xFFFFFC00
+#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK)
+#define MAS3_U0 0x00000200
+#define MAS3_U1 0x00000100
+#define MAS3_U2 0x00000080
+#define MAS3_U3 0x00000040
+#define MAS3_UX 0x00000020
+#define MAS3_SX 0x00000010
+#define MAS3_UW 0x00000008
+#define MAS3_SW 0x00000004
+#define MAS3_UR 0x00000002
+#define MAS3_SR 0x00000001
+/** @} */
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BPRED_MASK 0x00000006
+#define BUCSR_BPRED_0 0x00000000
+#define BUCSR_BPRED_1 0x00000002
+#define BUCSR_BPRED_2 0x00000004
+#define BUCSR_BPRED_3 0x00000006
+#define BUCSR_BALLOC_MASK 0x00000030
+#define BUCSR_BALLOC_0 0x00000000
+#define BUCSR_BALLOC_1 0x00000010
+#define BUCSR_BALLOC_2 0x00000020
+#define BUCSR_BALLOC_3 0x00000030
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name LICSR1 registers definitions
+ * @{
+ */
+#define LICSR1_ICE 0x00000001
+#define LICSR1_ICINV 0x00000002
+#define LICSR1_ICORG 0x00000010
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_UCLE 0x04000000
+#define MSR_SPE 0x02000000
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_FP 0x00002000
+#define MSR_ME 0x00001000
+#define MSR_FE0 0x00000800
+#define MSR_DE 0x00000200
+#define MSR_FE1 0x00000100
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * TLB default settings.
+ */
+#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
+#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_4M)
+#define TLB0_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE)
+#define TLB0_MAS3 (MAS3_RPN(0x00000000) | \
+ MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
+ MAS3_UR | MAS3_SR)
+
+#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
+#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
+#define TLB1_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE)
+#define TLB1_MAS3 (MAS3_RPN(0x40000000) | \
+ MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
+ MAS3_UR | MAS3_SR)
+
+#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
+#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I)
+#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
+#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I)
+#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
+#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB4_MAS2 (MAS2_EPN(0x8FF00000) | MAS2_I)
+#define TLB4_MAS3 (MAS3_RPN(0x8FF00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB5_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(5))
+#define TLB5_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB5_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I)
+#define TLB5_MAS3 (MAS3_RPN(0xFFF00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \
+ BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * LICSR1 default settings.
+ */
+#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC56ECxx/boot.s b/os/common/startup/e200/devices/SPC56ECxx/boot.s new file mode 100644 index 000000000..26cfcaaec --- /dev/null +++ b/os/common/startup/e200/devices/SPC56ECxx/boot.s @@ -0,0 +1,406 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC56ECxx/boot.s
+ * @brief SPC56ECxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+#if BOOT_USE_VLE
+ .long 0x015A0000
+#else
+ .long 0x005A0000
+#endif
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ bl _coreinit
+#endif
+ bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ lis %r4, __ram_reloc_start__@h
+ ori %r4, %r4, __ram_reloc_start__@l
+ lis %r5, __ram_reloc_dest__@h
+ ori %r5, %r5, __ram_reloc_dest__@l
+ lis %r6, __ram_reloc_end__@h
+ ori %r6, %r6, __ram_reloc_end__@l
+.relloop:
+ cmpl cr0, %r4, %r6
+ bge cr0, .relend
+ lwz %r7, 0(%r4)
+ addi %r4, %r4, 4
+ stw %r7, 0(%r5)
+ addi %r5, %r5, 4
+ b .relloop
+.relend:
+ lis %r3, _boot_address@h
+ ori %r3, %r3, _boot_address@l
+ mtctr %r3
+ bctrl
+#else
+ b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_ramcode:
+ tlbwe
+ isync
+ blr
+
+ .align 2
+_coreinit:
+ /*
+ * Invalidating all TLBs except TLB0.
+ */
+ lis %r3, 0
+ mtspr 625, %r3 /* MAS1 */
+ mtspr 626, %r3 /* MAS2 */
+ mtspr 627, %r3 /* MAS3 */
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+
+ /*
+ * TLB1 allocated to internal RAM.
+ */
+ lis %r3, TLB1_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB1_MAS1@h
+ ori %r3, %r3, TLB1_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB1_MAS2@h
+ ori %r3, %r3, TLB1_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB1_MAS3@h
+ ori %r3, %r3, TLB1_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB2 allocated to internal Peripherals Bridge A.
+ */
+ lis %r3, TLB2_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB2_MAS1@h
+ ori %r3, %r3, TLB2_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB2_MAS2@h
+ ori %r3, %r3, TLB2_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB2_MAS3@h
+ ori %r3, %r3, TLB2_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB3 allocated to internal Peripherals Bridge B.
+ */
+ lis %r3, TLB3_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB3_MAS1@h
+ ori %r3, %r3, TLB3_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB3_MAS2@h
+ ori %r3, %r3, TLB3_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB3_MAS3@h
+ ori %r3, %r3, TLB3_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB4 allocated to on-platform peripherals.
+ */
+ lis %r3, TLB4_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB4_MAS1@h
+ ori %r3, %r3, TLB4_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB4_MAS2@h
+ ori %r3, %r3, TLB4_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB4_MAS3@h
+ ori %r3, %r3, TLB4_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB5 allocated to on-platform peripherals.
+ */
+ lis %r3, TLB5_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB5_MAS1@h
+ ori %r3, %r3, TLB5_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB5_MAS2@h
+ ori %r3, %r3, TLB5_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB5_MAS3@h
+ ori %r3, %r3, TLB5_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor %r0, %r0, %r0
+ xor %r1, %r1, %r1
+ xor %r2, %r2, %r2
+ xor %r3, %r3, %r3
+ xor %r4, %r4, %r4
+ xor %r5, %r5, %r5
+ xor %r6, %r6, %r6
+ xor %r7, %r7, %r7
+ xor %r8, %r8, %r8
+ xor %r9, %r9, %r9
+ xor %r10, %r10, %r10
+ xor %r11, %r11, %r11
+ xor %r12, %r12, %r12
+ xor %r13, %r13, %r13
+ xor %r14, %r14, %r14
+ xor %r15, %r15, %r15
+ xor %r16, %r16, %r16
+ xor %r17, %r17, %r17
+ xor %r18, %r18, %r18
+ xor %r19, %r19, %r19
+ xor %r20, %r20, %r20
+ xor %r21, %r21, %r21
+ xor %r22, %r22, %r22
+ xor %r23, %r23, %r23
+ xor %r24, %r24, %r24
+ xor %r25, %r25, %r25
+ xor %r26, %r26, %r26
+ xor %r27, %r27, %r27
+ xor %r28, %r28, %r28
+ xor %r29, %r29, %r29
+ xor %r30, %r30, %r30
+ xor %r31, %r31, %r31
+ lis %r4, __ram_start__@h
+ ori %r4, %r4, __ram_start__@l
+ lis %r5, __ram_end__@h
+ ori %r5, %r5, __ram_end__@l
+.cleareccloop:
+ cmpl %cr0, %r4, %r5
+ bge %cr0, .cleareccend
+ stmw %r16, 0(%r4)
+ addi %r4, %r4, 64
+ b .cleareccloop
+.cleareccend:
+
+ /*
+ * Special function registers clearing, required in order to avoid
+ * possible problems with lockstep mode.
+ */
+ mtcrf 0xFF, %r31
+ mtspr 9, %r31 /* CTR */
+ mtspr 22, %r31 /* DEC */
+ mtspr 26, %r31 /* SRR0-1 */
+ mtspr 27, %r31
+ mtspr 54, %r31 /* DECAR */
+ mtspr 58, %r31 /* CSRR0-1 */
+ mtspr 59, %r31
+ mtspr 61, %r31 /* DEAR */
+ mtspr 256, %r31 /* USPRG0 */
+ mtspr 272, %r31 /* SPRG1-7 */
+ mtspr 273, %r31
+ mtspr 274, %r31
+ mtspr 275, %r31
+ mtspr 276, %r31
+ mtspr 277, %r31
+ mtspr 278, %r31
+ mtspr 279, %r31
+ mtspr 285, %r31 /* TBU */
+ mtspr 284, %r31 /* TBL */
+#if 0
+ mtspr 318, %r31 /* DVC1-2 */
+ mtspr 319, %r31
+#endif
+ mtspr 562, %r31 /* DBCNT */
+ mtspr 570, %r31 /* MCSRR0 */
+ mtspr 571, %r31 /* MCSRR1 */
+ mtspr 604, %r31 /* SPRG8-9 */
+ mtspr 605, %r31
+
+ /*
+ * *Finally* the TLB0 is re-allocated to flash, note, the final phase
+ * is executed from RAM.
+ */
+ lis %r3, TLB0_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB0_MAS1@h
+ ori %r3, %r3, TLB0_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB0_MAS2@h
+ ori %r3, %r3, TLB0_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB0_MAS3@h
+ ori %r3, %r3, TLB0_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ mflr %r4
+ lis %r6, _ramcode@h
+ ori %r6, %r6, _ramcode@l
+ lis %r7, 0x40010000@h
+ mtctr %r7
+ lwz %r3, 0(%r6)
+ stw %r3, 0(%r7)
+ lwz %r3, 4(%r6)
+ stw %r3, 4(%r7)
+ lwz %r3, 8(%r6)
+ stw %r3, 8(%r7)
+ bctrl
+ mtlr %r4
+
+ /*
+ * Branch prediction enabled.
+ */
+ li %r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, %r3 /* BUCSR */
+
+ /*
+ * Cache invalidated and then enabled.
+ */
+ li %r3, LICSR1_ICINV
+ mtspr 1011, %r3 /* LICSR1 */
+.inv: mfspr %r3, 1011 /* LICSR1 */
+ andi. %r3, %r3, LICSR1_ICINV
+ bne .inv
+ lis %r3, BOOT_LICSR1_DEFAULT@h
+ ori %r3, %r3, BOOT_LICSR1_DEFAULT@l
+ mtspr 1011, %r3 /* LICSR1 */
+
+ blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ lis %r3, BOOT_MSR_DEFAULT@h
+ ori %r3, %r3, BOOT_MSR_DEFAULT@l
+ mtMSR %r3
+
+ /* IVPR initialization.*/
+ lis %r3, __ivpr_base__@h
+ ori %r3, %r3, __ivpr_base__@l
+ mtIVPR %r3
+
+ /* IVORs initialization.*/
+ lis %r3, _unhandled_exception@h
+ ori %r3, %r3, _unhandled_exception@l
+
+ mtspr 400, %r3 /* IVOR0-15 */
+ mtspr 401, %r3
+ mtspr 402, %r3
+ mtspr 403, %r3
+ mtspr 404, %r3
+ mtspr 405, %r3
+ mtspr 406, %r3
+ mtspr 407, %r3
+ mtspr 408, %r3
+ mtspr 409, %r3
+ mtspr 410, %r3
+ mtspr 411, %r3
+ mtspr 412, %r3
+ mtspr 413, %r3
+ mtspr 414, %r3
+ mtspr 415, %r3
+ mtspr 528, %r3 /* IVOR32-34 */
+ mtspr 529, %r3
+ mtspr 530, %r3
+
+ blr
+
+ .section .handlers, "ax"
+
+ /*
+ * Unhandled exceptions handler.
+ */
+ .weak _unhandled_exception
+ .type _unhandled_exception, @function
+_unhandled_exception:
+ b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC56ECxx/boot_cw.s b/os/common/startup/e200/devices/SPC56ECxx/boot_cw.s new file mode 100644 index 000000000..b6698607b --- /dev/null +++ b/os/common/startup/e200/devices/SPC56ECxx/boot_cw.s @@ -0,0 +1,403 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC56ECxx/boot.s
+ * @brief SPC56ECxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ .extern _boot_address
+ .extern __ram_start__
+ .extern __ram_end__
+ .extern __ivpr_base__
+
+ .extern _unhandled_exception
+
+ /* BAM record.*/
+ .section .boot, 16
+
+#if BOOT_USE_VLE
+ .long 0x015A0000
+#else
+ .long 0x005A0000
+#endif
+ .long _reset_address
+
+ .align 4
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ e_bl _coreinit
+#endif
+ e_bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ e_lis r4, __ram_reloc_start__@h
+ e_or2i r4, r4, __ram_reloc_start__@l
+ e_lis r5, __ram_reloc_dest__@h
+ e_or2i r5, r5, __ram_reloc_dest__@l
+ e_lis r6, __ram_reloc_end__@h
+ e_or2i r6, r6, __ram_reloc_end__@l
+.relloop:
+ se_cmpl r4, r6
+ se_bge .relend
+ se_lwz r7, 0(r4)
+ se_addi r4, 4
+ se_stw r7, 0(r5)
+ se_addi r5, 4
+ se_b .relloop
+.relend:
+ e_lis r3, _boot_address@h
+ e_or2i r3, _boot_address@l
+ mtctr r3
+ se_bctrl
+#else
+ e_b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 4
+_ramcode:
+ tlbwe
+ se_isync
+ se_blr
+
+ .align 2
+_coreinit:
+ /*
+ * Invalidating all TLBs except TLB0.
+ */
+ e_lis r3, 0
+ mtspr 625, r3 /* MAS1 */
+ mtspr 626, r3 /* MAS2 */
+ mtspr 627, r3 /* MAS3 */
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+ e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
+ mtspr 624, r3 /* MAS0 */
+ tlbwe
+
+ /*
+ * TLB1 allocated to internal RAM.
+ */
+ e_lis r3, TLB1_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB1_MAS1@h
+ e_or2i r3, TLB1_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB1_MAS2@h
+ e_or2i r3, TLB1_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB1_MAS3@h
+ e_or2i r3, TLB1_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB2 allocated to internal Peripherals Bridge A.
+ */
+ e_lis r3, TLB2_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB2_MAS1@h
+ e_or2i r3, TLB2_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB2_MAS2@h
+ e_or2i r3, TLB2_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB2_MAS3@h
+ e_or2i r3, TLB2_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB3 allocated to internal Peripherals Bridge B.
+ */
+ e_lis r3, TLB3_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB3_MAS1@h
+ e_or2i r3, TLB3_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB3_MAS2@h
+ e_or2i r3, TLB3_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB3_MAS3@h
+ e_or2i r3, TLB3_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB4 allocated to on-platform peripherals.
+ */
+ e_lis r3, TLB4_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB4_MAS1@h
+ e_or2i r3, TLB4_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB4_MAS2@h
+ e_or2i r3, TLB4_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB4_MAS3@h
+ e_or2i r3, TLB4_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB5 allocated to on-platform peripherals.
+ */
+ e_lis r3, TLB5_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB5_MAS1@h
+ e_or2i r3, TLB5_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB5_MAS2@h
+ e_or2i r3, TLB5_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB5_MAS3@h
+ e_or2i r3, TLB5_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor r0, r0, r0
+ xor r1, r1, r1
+ xor r2, r2, r2
+ xor r3, r3, r3
+ xor r4, r4, r4
+ xor r5, r5, r5
+ xor r6, r6, r6
+ xor r7, r7, r7
+ xor r8, r8, r8
+ xor r9, r9, r9
+ xor r10, r10, r10
+ xor r11, r11, r11
+ xor r12, r12, r12
+ xor r13, r13, r13
+ xor r14, r14, r14
+ xor r15, r15, r15
+ xor r16, r16, r16
+ xor r17, r17, r17
+ xor r18, r18, r18
+ xor r19, r19, r19
+ xor r20, r20, r20
+ xor r21, r21, r21
+ xor r22, r22, r22
+ xor r23, r23, r23
+ xor r24, r24, r24
+ xor r25, r25, r25
+ xor r26, r26, r26
+ xor r27, r27, r27
+ xor r28, r28, r28
+ xor r29, r29, r29
+ xor r30, r30, r30
+ xor r31, r31, r31
+ e_lis r4, __ram_start__@h
+ e_or2i r4, __ram_start__@l
+ e_lis r5, __ram_end__@h
+ e_or2i r5, __ram_end__@l
+.cleareccloop:
+ se_cmpl r4, r5
+ se_bge .cleareccend
+ e_stmw r16, 0(r4)
+ e_addi r4, r4, 64
+ se_b .cleareccloop
+.cleareccend:
+
+ /*
+ * Special function registers clearing, required in order to avoid
+ * possible problems with lockstep mode.
+ */
+ mtcrf 0xFF, r31
+ mtspr 9, r31 /* CTR */
+ mtspr 22, r31 /* DEC */
+ mtspr 26, r31 /* SRR0-1 */
+ mtspr 27, r31
+ mtspr 54, r31 /* DECAR */
+ mtspr 58, r31 /* CSRR0-1 */
+ mtspr 59, r31
+ mtspr 61, r31 /* DEAR */
+ mtspr 256, r31 /* USPRG0 */
+ mtspr 272, r31 /* SPRG1-7 */
+ mtspr 273, r31
+ mtspr 274, r31
+ mtspr 275, r31
+ mtspr 276, r31
+ mtspr 277, r31
+ mtspr 278, r31
+ mtspr 279, r31
+ mtspr 285, r31 /* TBU */
+ mtspr 284, r31 /* TBL */
+#if 0
+ mtspr 318, r31 /* DVC1-2 */
+ mtspr 319, r31
+#endif
+ mtspr 562, r31 /* DBCNT */
+ mtspr 570, r31 /* MCSRR0 */
+ mtspr 571, r31 /* MCSRR1 */
+ mtspr 604, r31 /* SPRG8-9 */
+ mtspr 605, r31
+
+ /*
+ * *Finally* the TLB0 is re-allocated to flash, note, the final phase
+ * is executed from RAM.
+ */
+ e_lis r3, TLB0_MAS0@h
+ mtspr 624, r3 /* MAS0 */
+ e_lis r3, TLB0_MAS1@h
+ e_or2i r3, TLB0_MAS1@l
+ mtspr 625, r3 /* MAS1 */
+ e_lis r3, TLB0_MAS2@h
+ e_or2i r3, TLB0_MAS2@l
+ mtspr 626, r3 /* MAS2 */
+ e_lis r3, TLB0_MAS3@h
+ e_or2i r3, TLB0_MAS3@l
+ mtspr 627, r3 /* MAS3 */
+ se_mflr r4
+ e_lis r6, _ramcode@h
+ e_or2i r6, _ramcode@l
+ e_lis r7, 0x40010000@h
+ mtctr r7
+ se_lwz r3, 0(r6)
+ se_stw r3, 0(r7)
+ se_lwz r3, 4(r6)
+ se_stw r3, 4(r7)
+ se_lwz r3, 8(r6)
+ se_stw r3, 8(r7)
+ se_bctrl
+ mtlr r4
+
+ /*
+ * Branch prediction enabled.
+ */
+ e_li r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, r3 /* BUCSR */
+
+ /*
+ * Cache invalidated and then enabled.
+ */
+ se_li r3, LICSR1_ICINV
+ mtspr 1011, r3 /* LICSR1 */
+.inv: mfspr r3, 1011 /* LICSR1 */
+ e_andi. r3, r3, LICSR1_ICINV
+ se_bne .inv
+ e_lis r3, BOOT_LICSR1_DEFAULT@h
+ e_or2i r3, BOOT_LICSR1_DEFAULT@l
+ mtspr 1011, r3 /* LICSR1 */
+
+ se_blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 4
+_ivinit:
+ /* MSR initialization.*/
+ e_lis r3, BOOT_MSR_DEFAULT@h
+ e_ori r3, r3, BOOT_MSR_DEFAULT@l
+ mtMSR r3
+
+ /* IVPR initialization.*/
+ e_lis r3, __ivpr_base__@h
+ e_or2i r3, __ivpr_base__@l
+ mtIVPR r3
+
+ /* IVORs initialization.*/
+ e_lis r3, _unhandled_exception@h
+ e_or2i r3, _unhandled_exception@l
+
+ mtspr 400, r3 /* IVOR0-15 */
+ mtspr 401, r3
+ mtspr 402, r3
+ mtspr 403, r3
+ mtspr 404, r3
+ mtspr 405, r3
+ mtspr 406, r3
+ mtspr 407, r3
+ mtspr 408, r3
+ mtspr 409, r3
+ mtspr 410, r3
+ mtspr 411, r3
+ mtspr 412, r3
+ mtspr 413, r3
+ mtspr 414, r3
+ mtspr 415, r3
+ mtspr 528, r3 /* IVOR32-34 */
+ mtspr 529, r3
+ mtspr 530, r3
+
+ se_blr
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC56ECxx/intc.h b/os/common/startup/e200/devices/SPC56ECxx/intc.h new file mode 100644 index 000000000..bb8b13dbc --- /dev/null +++ b/os/common/startup/e200/devices/SPC56ECxx/intc.h @@ -0,0 +1,98 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC56ECxx/intc.h
+ * @brief SPC56ECxx INTC module header.
+ *
+ * @addtogroup INTC
+ * @{
+ */
+
+#ifndef _INTC_H_
+#define _INTC_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name INTC addresses
+ * @{
+ */
+#define INTC_BASE 0xFFF48000
+#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
+#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
+/** @} */
+
+/**
+ * @brief INTC priority levels.
+ */
+#define INTC_PRIORITY_LEVELS 16U
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name INTC-related macros
+ * @{
+ */
+#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
+#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
+#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
+#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
+#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
+/** @} */
+
+/**
+ * @brief Core selection macros for PSR register.
+ */
+#define INTC_PSR_CORE0 0x00
+#define INTC_PSR_CORE1 0xC0
+#define INTC_PSR_CORES01 0x40
+
+/**
+ * @brief PSR register content helper
+ */
+#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _INTC_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC56ECxx/ppcparams.h b/os/common/startup/e200/devices/SPC56ECxx/ppcparams.h new file mode 100644 index 000000000..90538fecb --- /dev/null +++ b/os/common/startup/e200/devices/SPC56ECxx/ppcparams.h @@ -0,0 +1,86 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC56ECxx/ppcparams.h
+ * @brief PowerPC parameters for the SPC56ECxx.
+ *
+ * @defgroup PPC_SPC56ECxx SPC56ECxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC56ECxx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief Family identification macro.
+ */
+#define PPC_SPC56ECxx
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z4
+
+/**
+ * @brief Number of cores.
+ */
+#define PPC_CORE_NUMBER 1
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 16
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS TRUE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE TRUE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER TRUE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 279
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC56ELxx/boot.h b/os/common/startup/e200/devices/SPC56ELxx/boot.h new file mode 100644 index 000000000..aeb2bc0bc --- /dev/null +++ b/os/common/startup/e200/devices/SPC56ELxx/boot.h @@ -0,0 +1,251 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC56ELxx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name MASx registers definitions
+ * @{
+ */
+#define MAS0_TBLMAS_TBL 0x10000000
+#define MAS0_ESEL_MASK 0x000F0000
+#define MAS0_ESEL(n) ((n) << 16)
+
+#define MAS1_VALID 0x80000000
+#define MAS1_IPROT 0x40000000
+#define MAS1_TID_MASK 0x00FF0000
+#define MAS1_TS 0x00001000
+#define MAS1_TSISE_MASK 0x00000F80
+#define MAS1_TSISE_1K 0x00000000
+#define MAS1_TSISE_2K 0x00000080
+#define MAS1_TSISE_4K 0x00000100
+#define MAS1_TSISE_8K 0x00000180
+#define MAS1_TSISE_16K 0x00000200
+#define MAS1_TSISE_32K 0x00000280
+#define MAS1_TSISE_64K 0x00000300
+#define MAS1_TSISE_128K 0x00000380
+#define MAS1_TSISE_256K 0x00000400
+#define MAS1_TSISE_512K 0x00000480
+#define MAS1_TSISE_1M 0x00000500
+#define MAS1_TSISE_2M 0x00000580
+#define MAS1_TSISE_4M 0x00000600
+#define MAS1_TSISE_8M 0x00000680
+#define MAS1_TSISE_16M 0x00000700
+#define MAS1_TSISE_32M 0x00000780
+#define MAS1_TSISE_64M 0x00000800
+#define MAS1_TSISE_128M 0x00000880
+#define MAS1_TSISE_256M 0x00000900
+#define MAS1_TSISE_512M 0x00000980
+#define MAS1_TSISE_1G 0x00000A00
+#define MAS1_TSISE_2G 0x00000A80
+#define MAS1_TSISE_4G 0x00000B00
+
+#define MAS2_EPN_MASK 0xFFFFFC00
+#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK)
+#define MAS2_EBOOK 0x00000000
+#define MAS2_VLE 0x00000020
+#define MAS2_W 0x00000010
+#define MAS2_I 0x00000008
+#define MAS2_M 0x00000004
+#define MAS2_G 0x00000002
+#define MAS2_E 0x00000001
+
+#define MAS3_RPN_MASK 0xFFFFFC00
+#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK)
+#define MAS3_U0 0x00000200
+#define MAS3_U1 0x00000100
+#define MAS3_U2 0x00000080
+#define MAS3_U3 0x00000040
+#define MAS3_UX 0x00000020
+#define MAS3_SX 0x00000010
+#define MAS3_UW 0x00000008
+#define MAS3_SW 0x00000004
+#define MAS3_UR 0x00000002
+#define MAS3_SR 0x00000001
+/** @} */
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BPRED_MASK 0x00000006
+#define BUCSR_BPRED_0 0x00000000
+#define BUCSR_BPRED_1 0x00000002
+#define BUCSR_BPRED_2 0x00000004
+#define BUCSR_BPRED_3 0x00000006
+#define BUCSR_BALLOC_MASK 0x00000030
+#define BUCSR_BALLOC_0 0x00000000
+#define BUCSR_BALLOC_1 0x00000010
+#define BUCSR_BALLOC_2 0x00000020
+#define BUCSR_BALLOC_3 0x00000030
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name LICSR1 registers definitions
+ * @{
+ */
+#define LICSR1_ICE 0x00000001
+#define LICSR1_ICINV 0x00000002
+#define LICSR1_ICORG 0x00000010
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_UCLE 0x04000000
+#define MSR_SPE 0x02000000
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_FP 0x00002000
+#define MSR_ME 0x00001000
+#define MSR_FE0 0x00000800
+#define MSR_DE 0x00000200
+#define MSR_FE1 0x00000100
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * TLB default settings.
+ */
+#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
+#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_2M)
+#define TLB0_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE)
+#define TLB0_MAS3 (MAS3_RPN(0x00000000) | \
+ MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
+ MAS3_UR | MAS3_SR)
+
+#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
+#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
+#define TLB1_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE)
+#define TLB1_MAS3 (MAS3_RPN(0x40000000) | \
+ MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
+ MAS3_UR | MAS3_SR)
+
+#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
+#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I)
+#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
+#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I)
+#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
+#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB4_MAS2 (MAS2_EPN(0x8FF00000) | MAS2_I)
+#define TLB4_MAS3 (MAS3_RPN(0x8FF00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB5_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(5))
+#define TLB5_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB5_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I)
+#define TLB5_MAS3 (MAS3_RPN(0xFFF00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \
+ BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * LICSR1 default settings.
+ */
+#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC56ELxx/boot.s b/os/common/startup/e200/devices/SPC56ELxx/boot.s new file mode 100644 index 000000000..1508f0c17 --- /dev/null +++ b/os/common/startup/e200/devices/SPC56ELxx/boot.s @@ -0,0 +1,408 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC56ELxx/boot.s
+ * @brief SPC56ELxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+#if BOOT_USE_VLE
+ .long 0x015A0000
+#else
+ .long 0x005A0000
+#endif
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+ bl _coreinit
+ bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ lis %r4, __ram_reloc_start__@h
+ ori %r4, %r4, __ram_reloc_start__@l
+ lis %r5, __ram_reloc_dest__@h
+ ori %r5, %r5, __ram_reloc_dest__@l
+ lis %r6, __ram_reloc_end__@h
+ ori %r6, %r6, __ram_reloc_end__@l
+.relloop:
+ cmpl cr0, %r4, %r6
+ bge cr0, .relend
+ lwz %r7, 0(%r4)
+ addi %r4, %r4, 4
+ stw %r7, 0(%r5)
+ addi %r5, %r5, 4
+ b .relloop
+.relend:
+ lis %r3, _boot_address@h
+ ori %r3, %r3, _boot_address@l
+ mtctr %r3
+ bctrl
+#else
+ b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_ramcode:
+ tlbwe
+ isync
+ blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ .align 2
+_coreinit:
+#if BOOT_PERFORM_CORE_INIT
+ /*
+ * Invalidating all TLBs except TLB0.
+ */
+ lis %r3, 0
+ mtspr 625, %r3 /* MAS1 */
+ mtspr 626, %r3 /* MAS2 */
+ mtspr 627, %r3 /* MAS3 */
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+
+ /*
+ * TLB1 allocated to internal RAM.
+ */
+ lis %r3, TLB1_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB1_MAS1@h
+ ori %r3, %r3, TLB1_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB1_MAS2@h
+ ori %r3, %r3, TLB1_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB1_MAS3@h
+ ori %r3, %r3, TLB1_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB2 allocated to internal Peripherals Bridge A.
+ */
+ lis %r3, TLB2_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB2_MAS1@h
+ ori %r3, %r3, TLB2_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB2_MAS2@h
+ ori %r3, %r3, TLB2_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB2_MAS3@h
+ ori %r3, %r3, TLB2_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB3 allocated to internal Peripherals Bridge B.
+ */
+ lis %r3, TLB3_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB3_MAS1@h
+ ori %r3, %r3, TLB3_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB3_MAS2@h
+ ori %r3, %r3, TLB3_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB3_MAS3@h
+ ori %r3, %r3, TLB3_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB4 allocated to on-platform peripherals.
+ */
+ lis %r3, TLB4_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB4_MAS1@h
+ ori %r3, %r3, TLB4_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB4_MAS2@h
+ ori %r3, %r3, TLB4_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB4_MAS3@h
+ ori %r3, %r3, TLB4_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB5 allocated to on-platform peripherals.
+ */
+ lis %r3, TLB5_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB5_MAS1@h
+ ori %r3, %r3, TLB5_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB5_MAS2@h
+ ori %r3, %r3, TLB5_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB5_MAS3@h
+ ori %r3, %r3, TLB5_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor %r0, %r0, %r0
+ xor %r1, %r1, %r1
+ xor %r2, %r2, %r2
+ xor %r3, %r3, %r3
+ xor %r4, %r4, %r4
+ xor %r5, %r5, %r5
+ xor %r6, %r6, %r6
+ xor %r7, %r7, %r7
+ xor %r8, %r8, %r8
+ xor %r9, %r9, %r9
+ xor %r10, %r10, %r10
+ xor %r11, %r11, %r11
+ xor %r12, %r12, %r12
+ xor %r13, %r13, %r13
+ xor %r14, %r14, %r14
+ xor %r15, %r15, %r15
+ xor %r16, %r16, %r16
+ xor %r17, %r17, %r17
+ xor %r18, %r18, %r18
+ xor %r19, %r19, %r19
+ xor %r20, %r20, %r20
+ xor %r21, %r21, %r21
+ xor %r22, %r22, %r22
+ xor %r23, %r23, %r23
+ xor %r24, %r24, %r24
+ xor %r25, %r25, %r25
+ xor %r26, %r26, %r26
+ xor %r27, %r27, %r27
+ xor %r28, %r28, %r28
+ xor %r29, %r29, %r29
+ xor %r30, %r30, %r30
+ xor %r31, %r31, %r31
+ lis %r4, __ram_start__@h
+ ori %r4, %r4, __ram_start__@l
+ lis %r5, __ram_end__@h
+ ori %r5, %r5, __ram_end__@l
+.cleareccloop:
+ cmpl %cr0, %r4, %r5
+ bge %cr0, .cleareccend
+ stmw %r16, 0(%r4)
+ addi %r4, %r4, 64
+ b .cleareccloop
+.cleareccend:
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Special function registers clearing, required in order to avoid
+ * possible problems with lockstep mode.
+ */
+ mtcrf 0xFF, %r31
+ mtspr 9, %r31 /* CTR */
+ mtspr 22, %r31 /* DEC */
+ mtspr 26, %r31 /* SRR0-1 */
+ mtspr 27, %r31
+ mtspr 54, %r31 /* DECAR */
+ mtspr 58, %r31 /* CSRR0-1 */
+ mtspr 59, %r31
+ mtspr 61, %r31 /* DEAR */
+ mtspr 256, %r31 /* USPRG0 */
+ mtspr 272, %r31 /* SPRG1-7 */
+ mtspr 273, %r31
+ mtspr 274, %r31
+ mtspr 275, %r31
+ mtspr 276, %r31
+ mtspr 277, %r31
+ mtspr 278, %r31
+ mtspr 279, %r31
+ mtspr 285, %r31 /* TBU */
+ mtspr 284, %r31 /* TBL */
+#if 0
+ mtspr 318, %r31 /* DVC1-2 */
+ mtspr 319, %r31
+#endif
+ mtspr 562, %r31 /* DBCNT */
+ mtspr 570, %r31 /* MCSRR0 */
+ mtspr 571, %r31 /* MCSRR1 */
+ mtspr 604, %r31 /* SPRG8-9 */
+ mtspr 605, %r31
+
+#if BOOT_PERFORM_CORE_INIT
+ /*
+ * *Finally* the TLB0 is re-allocated to flash, note, the final phase
+ * is executed from RAM.
+ */
+ lis %r3, TLB0_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB0_MAS1@h
+ ori %r3, %r3, TLB0_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB0_MAS2@h
+ ori %r3, %r3, TLB0_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB0_MAS3@h
+ ori %r3, %r3, TLB0_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ mflr %r4
+ lis %r6, _ramcode@h
+ ori %r6, %r6, _ramcode@l
+ lis %r7, 0x40010000@h
+ mtctr %r7
+ lwz %r3, 0(%r6)
+ stw %r3, 0(%r7)
+ lwz %r3, 4(%r6)
+ stw %r3, 4(%r7)
+ lwz %r3, 8(%r6)
+ stw %r3, 8(%r7)
+ bctrl
+ mtlr %r4
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Branch prediction enabled.
+ */
+ li %r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, %r3 /* BUCSR */
+
+ /*
+ * Cache invalidated and then enabled.
+ */
+ li %r3, LICSR1_ICINV
+ mtspr 1011, %r3 /* LICSR1 */
+.inv: mfspr %r3, 1011 /* LICSR1 */
+ andi. %r3, %r3, LICSR1_ICINV
+ bne .inv
+ lis %r3, BOOT_LICSR1_DEFAULT@h
+ ori %r3, %r3, BOOT_LICSR1_DEFAULT@l
+ mtspr 1011, %r3 /* LICSR1 */
+
+ blr
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ lis %r3, BOOT_MSR_DEFAULT@h
+ ori %r3, %r3, BOOT_MSR_DEFAULT@l
+ mtMSR %r3
+
+ /* IVPR initialization.*/
+ lis %r3, __ivpr_base__@h
+ ori %r3, %r3, __ivpr_base__@l
+ mtIVPR %r3
+
+ /* IVORs initialization.*/
+ lis %r3, _unhandled_exception@h
+ ori %r3, %r3, _unhandled_exception@l
+
+ mtspr 400, %r3 /* IVOR0-15 */
+ mtspr 401, %r3
+ mtspr 402, %r3
+ mtspr 403, %r3
+ mtspr 404, %r3
+ mtspr 405, %r3
+ mtspr 406, %r3
+ mtspr 407, %r3
+ mtspr 408, %r3
+ mtspr 409, %r3
+ mtspr 410, %r3
+ mtspr 411, %r3
+ mtspr 412, %r3
+ mtspr 413, %r3
+ mtspr 414, %r3
+ mtspr 415, %r3
+ mtspr 528, %r3 /* IVOR32-34 */
+ mtspr 529, %r3
+ mtspr 530, %r3
+
+ blr
+
+ .section .handlers, "ax"
+
+ /*
+ * Unhandled exceptions handler.
+ */
+ .weak _unhandled_exception
+ .type _unhandled_exception, @function
+_unhandled_exception:
+ b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC56ELxx/intc.h b/os/common/startup/e200/devices/SPC56ELxx/intc.h new file mode 100644 index 000000000..bb4c98f57 --- /dev/null +++ b/os/common/startup/e200/devices/SPC56ELxx/intc.h @@ -0,0 +1,96 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC56ELxx/intc.h
+ * @brief SPC56ELxx INTC module header.
+ *
+ * @addtogroup INTC
+ * @{
+ */
+
+#ifndef _INTC_H_
+#define _INTC_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name INTC addresses
+ * @{
+ */
+#define INTC_BASE 0xFFF48000
+#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
+#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
+/** @} */
+
+/**
+ * @brief INTC priority levels.
+ */
+#define INTC_PRIORITY_LEVELS 16U
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name INTC-related macros
+ * @{
+ */
+#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
+#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
+#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
+#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
+#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
+/** @} */
+
+/**
+ * @brief Core selection macros for PSR register.
+ */
+#define INTC_PSR_CORE0 0x00
+
+/**
+ * @brief PSR register content helper
+ */
+#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _INTC_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC56ELxx/ppcparams.h b/os/common/startup/e200/devices/SPC56ELxx/ppcparams.h new file mode 100644 index 000000000..c7bceb487 --- /dev/null +++ b/os/common/startup/e200/devices/SPC56ELxx/ppcparams.h @@ -0,0 +1,86 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC56ELxx/ppcparams.h
+ * @brief PowerPC parameters for the SPC56ELxx.
+ *
+ * @defgroup PPC_SPC56ELxx SPC56ELxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC56ELxx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief Family identification macro.
+ */
+#define PPC_SPC56ELxx
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z4
+
+/**
+ * @brief Number of cores.
+ */
+#define PPC_CORE_NUMBER 1
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 16
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS TRUE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE TRUE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER TRUE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 256
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC57EMxx_HSM/boot.h b/os/common/startup/e200/devices/SPC57EMxx_HSM/boot.h new file mode 100644 index 000000000..e00933bbf --- /dev/null +++ b/os/common/startup/e200/devices/SPC57EMxx_HSM/boot.h @@ -0,0 +1,96 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC57EMxx_HSM.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_ME 0x00001000
+#define MSR_DE 0x00000200
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC57EMxx_HSM/boot.s b/os/common/startup/e200/devices/SPC57EMxx_HSM/boot.s new file mode 100644 index 000000000..3aa286d58 --- /dev/null +++ b/os/common/startup/e200/devices/SPC57EMxx_HSM/boot.s @@ -0,0 +1,211 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC57EMxx_HSM/boot.s
+ * @brief SPC57EMxx_HSM boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#define HSBI_CCR 0xA3F14004
+#define HSBI_CCR_CE 0x00000001
+#define HSBI_CCR_INV 0x00000002
+
+#if !defined(__DOXYGEN__)
+
+ /* Boot record.*/
+ .section .boot, "ax"
+
+ .long 0xFFFF0000
+ .long 0xFFFF0000
+ .long 0xFFFFFFFF
+ .long _reset_address
+ .long 0xFFFFFFFF
+ .long 0xFFFFFFFF
+ .long 0xFFFFFFFF
+ .long 0xFFFFFFFF
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+ bl _coreinit
+ bl _ivinit
+ b _boot_address
+
+ .align 2
+_coreinit:
+#if 0
+ /*
+ * Cache invalidate and enable.
+ */
+ lis %r7, HSBI_CCR@h
+ ori %r7, %r7, HSBI_CCR@l
+ li %r0, HSBI_CCR_INV | HSBI_CCR_CE
+ stw %r0, 0(%r7)
+.inv:
+ lwz %r0, 0(%r7)
+ andi. %r0, %r0, HSBI_CCR_INV
+ bne+ %cr0, .inv
+#endif
+
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor %r0, %r0, %r0
+ xor %r1, %r1, %r1
+ xor %r2, %r2, %r2
+ xor %r3, %r3, %r3
+ xor %r4, %r4, %r4
+ xor %r5, %r5, %r5
+ xor %r6, %r6, %r6
+ xor %r7, %r7, %r7
+ xor %r8, %r8, %r8
+ xor %r9, %r9, %r9
+ xor %r10, %r10, %r10
+ xor %r11, %r11, %r11
+ xor %r12, %r12, %r12
+ xor %r13, %r13, %r13
+ xor %r14, %r14, %r14
+ xor %r15, %r15, %r15
+ xor %r16, %r16, %r16
+ xor %r17, %r17, %r17
+ xor %r18, %r18, %r18
+ xor %r19, %r19, %r19
+ xor %r20, %r20, %r20
+ xor %r21, %r21, %r21
+ xor %r22, %r22, %r22
+ xor %r23, %r23, %r23
+ xor %r24, %r24, %r24
+ xor %r25, %r25, %r25
+ xor %r26, %r26, %r26
+ xor %r27, %r27, %r27
+ xor %r28, %r28, %r28
+ xor %r29, %r29, %r29
+ xor %r30, %r30, %r30
+ xor %r31, %r31, %r31
+ lis %r4, __ram_start__@h
+ ori %r4, %r4, __ram_start__@l
+ lis %r5, __ram_end__@h
+ ori %r5, %r5, __ram_end__@l
+.cleareccloop:
+ cmpl %cr0, %r4, %r5
+ bge %cr0, .cleareccend
+ stmw %r16, 0(%r4)
+ addi %r4, %r4, 64
+ b .cleareccloop
+.cleareccend:
+
+ /*
+ * Branch prediction enabled.
+ */
+ li %r3, BUCSR_DEFAULT
+ mtspr 1013, %r3 /* BUCSR */
+
+ blr
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ lis %r3, MSR_DEFAULT@h
+ ori %r3, %r3, MSR_DEFAULT@l
+ mtMSR %r3
+
+ /* IVPR initialization.*/
+ lis %r3, __ivpr_base__@h
+ ori %r3, %r3, __ivpr_base__@l
+ mtIVPR %r3
+
+ blr
+
+ .section .ivors, "ax"
+
+ .globl IVORS
+IVORS:
+IVOR0: b _IVOR0
+ .align 4
+IVOR1: b _IVOR1
+ .align 4
+IVOR2: b _IVOR2
+ .align 4
+IVOR3: b _IVOR3
+ .align 4
+IVOR4: b _IVOR4
+ .align 4
+IVOR5: b _IVOR5
+ .align 4
+IVOR6: b _IVOR6
+ .align 4
+IVOR7: b _IVOR7
+ .align 4
+IVOR8: b _IVOR8
+ .align 4
+IVOR9: b _IVOR9
+ .align 4
+IVOR10: b _IVOR10
+ .align 4
+IVOR11: b _IVOR11
+ .align 4
+IVOR12: b _IVOR12
+ .align 4
+IVOR13: b _IVOR13
+ .align 4
+IVOR14: b _IVOR14
+ .align 4
+IVOR15: b _IVOR15
+
+ .section .handlers, "ax"
+
+ /*
+ * Default IVOR handlers.
+ */
+ .align 2
+ .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
+ .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
+ .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
+_IVOR0:
+_IVOR1:
+_IVOR2:
+_IVOR3:
+_IVOR5:
+_IVOR6:
+_IVOR7:
+_IVOR8:
+_IVOR9:
+_IVOR11:
+_IVOR12:
+_IVOR13:
+_IVOR14:
+_IVOR15:
+ .global _unhandled_exception
+_unhandled_exception:
+ b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC57EMxx_HSM/intc.h b/os/common/startup/e200/devices/SPC57EMxx_HSM/intc.h new file mode 100644 index 000000000..ef660f195 --- /dev/null +++ b/os/common/startup/e200/devices/SPC57EMxx_HSM/intc.h @@ -0,0 +1,97 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC57EMxx_HSM/intc.h
+ * @brief SPC57EMxx_HSM INTC module header.
+ *
+ * @addtogroup INTC
+ * @{
+ */
+
+#ifndef _INTC_H_
+#define _INTC_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name INTC addresses
+ * @{
+ */
+#define INTC_BASE 0xA3F48000
+#define INTC_IACKR_ADDR (INTC_BASE + 0x20)
+#define INTC_EOIR_ADDR (INTC_BASE + 0x30)
+/** @} */
+
+/**
+ * @brief INTC priority levels.
+ */
+#define INTC_PRIORITY_LEVELS 16U
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @name INTC-related macros
+ * @{
+ */
+#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
+#define INTC_MPROT (*((volatile uint32_t *)(INTC_BASE + 4)))
+#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
+#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x20 + ((n) * sizeof (uint32_t)))))
+#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x30 + ((n) * sizeof (uint32_t)))))
+#define INTC_PSR(n) (*((volatile uint16_t *)(INTC_BASE + 0x60 + ((n) * sizeof (uint16_t)))))
+/** @} */
+
+/**
+ * @brief Core selection macros for PSR register.
+ */
+#define INTC_PSR_CORE4 0x8000
+
+/**
+ * @brief PSR register content helper
+ */
+#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _INTC_H_ */
+
+/** @} */
diff --git a/os/common/startup/e200/devices/SPC57EMxx_HSM/ppcparams.h b/os/common/startup/e200/devices/SPC57EMxx_HSM/ppcparams.h new file mode 100644 index 000000000..96ee29e27 --- /dev/null +++ b/os/common/startup/e200/devices/SPC57EMxx_HSM/ppcparams.h @@ -0,0 +1,91 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC57EMxx_HSM/ppcparams.h
+ * @brief PowerPC parameters for the SPC57EMxx_HSM.
+ *
+ * @defgroup PPC_SPC57EMxx_HSM SPC57EMxx_HSM Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC57EMxx_HSM platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief Family identification macro.
+ */
+#define PPC_SPC560Dxx
+
+/**
+ * @brief Alternate identification macro.
+ */
+#define PPC_SPC57EMxx_HSM
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z0
+
+/**
+ * @brief Number of cores.
+ */
+#define PPC_CORE_NUMBER 1
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 20
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS FALSE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE FALSE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER FALSE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 64
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
|