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| author | edolomb <none@example.com> | 2019-01-17 15:19:20 +0000 |
|---|---|---|
| committer | edolomb <none@example.com> | 2019-01-17 15:19:20 +0000 |
| commit | 29309f101a4828842c377ff11a3a59908aab05f2 (patch) | |
| tree | f75aef8484bc3522621b128eb6bfeacd55ad0e47 /os/common/startup/ARM/devices | |
| parent | 696701cd6fe254a4cb2e3f748cacabe853d42a9e (diff) | |
| download | ChibiOS-29309f101a4828842c377ff11a3a59908aab05f2.tar.gz ChibiOS-29309f101a4828842c377ff11a3a59908aab05f2.tar.bz2 ChibiOS-29309f101a4828842c377ff11a3a59908aab05f2.zip | |
Updated SAMA drivers (still incomplete)
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12543 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os/common/startup/ARM/devices')
| -rw-r--r-- | os/common/startup/ARM/devices/SAMA5D2/mmu.c | 27 |
1 files changed, 22 insertions, 5 deletions
diff --git a/os/common/startup/ARM/devices/SAMA5D2/mmu.c b/os/common/startup/ARM/devices/SAMA5D2/mmu.c index a4f3b0ea0..449019526 100644 --- a/os/common/startup/ARM/devices/SAMA5D2/mmu.c +++ b/os/common/startup/ARM/devices/SAMA5D2/mmu.c @@ -48,9 +48,17 @@ #define SAMA_L2CC_ENABLE 0
#endif
+#if (SAMA_L2CC_ASSUME_ENABLED && SAMA_L2CC_ENABLE)
+#error "These macros are mutually exclusive"
+#endif
+
/*===========================================================================*/
/* Module local definitions. */
/*===========================================================================*/
+/*
+ * @brief No cacheable memory start address.
+ */
+#define NO_CACHE_MEMORY_START_ADDR ((uint8_t *) 0x26F00000)
/*===========================================================================*/
/* Module exported variables. */
@@ -77,7 +85,7 @@ * +---------+--+-+--+-+-----+--------+-------+-+------+--+-+-+-+---+
* | section |NS|0|nG|S|AP[2]|TEX[2:0]|AP[1:0]| |domain|XN|C|B|1|PXN|
* +---------+--+-+--+-+-----+--------+-------+-+------+--+-+-+-+---+
- * | |0 |0|0 |1|0 |111 |11 |0|0000 |0 |1|1|1|0 | == normal, cacheable
+ * | |X |0|0 |0|0 |111 |11 |0|0000 |0 |1|1|1|0 | == normal, cacheable, write back, no write allocate
* | |0 |0|0 |1|0 |100 |11 |0|0000 |0 |0|0|1|0 | == normal, no-cacheable
* | |0 |0|0 |1|0 |000 |11 |0|0000 |0 |0|1|1|0 | == device
* | |0 |0|0 |1|0 |000 |11 |0|0000 |0 |0|0|1|0 | == strongly-ordered
@@ -121,8 +129,8 @@ void __core_init(void) { Invalidate a disabled L1 D Cache.*/
pm = __get_SCTLR();
if ((pm & SCTLR_C_Msk)) {
- L1C_CleanInvalidateCache(DCISW_CLEAN);
L1C_DisableCaches();
+ L1C_CleanInvalidateCache(DCISW_CLEAN);
}
/* Disable the MMU and invalidate TLB.*/
@@ -164,7 +172,7 @@ void __core_init(void) { TTE_SECT_MEM_CACHEABLE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x00) |
- TTE_SECT_S | TTE_TYPE_SECT;
+ TTE_TYPE_SECT;
/*
* UDPHS RAM region
*
@@ -264,7 +272,7 @@ void __core_init(void) { TTE_SECT_MEM_CACHEABLE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x00) |
- TTE_SECT_S | TTE_TYPE_SECT;
+ TTE_TYPE_SECT;
/*
* DDR AESB regions
*
@@ -275,7 +283,7 @@ void __core_init(void) { TTE_SECT_MEM_CACHEABLE |
TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x00) |
- TTE_SECT_S | TTE_TYPE_SECT;
+ TTE_TYPE_SECT;
/*
* EBI 1, 2 and 3 regions
*
@@ -360,6 +368,9 @@ void __core_init(void) { TTE_SECT_EXE_NEVER |
TTE_SECT_S | TTE_TYPE_SECT;
+ /* Make a NO CACHE AREA */
+ MMU_MemorySection((mmuTable + ((uint32_t)NO_CACHE_MEMORY_START_ADDR >> 20)), NORMAL, NON_CACHEABLE, NON_CACHEABLE);
+
/* Invalidate TLB and L1 I cache
Enable caches and MMU.*/
MMU_InvalidateTLB();
@@ -395,11 +406,17 @@ void __core_init(void) { /* Invalidate and enable L2 cache.*/
L2C_InvAllByWay();
+ L2C_310->AUX_CNT = L2CC_ACR_DPEN | L2CC_ACR_IPEN;
+
+ /* Prefetch control register. Double linefeed, instr and data enabled.*/
+ *((uint32_t *)((char *)L2C_310+0x0F60)) = 0x75800001;
L2C_Enable();
__DSB();
__ISB();
}
#endif
+
+
#endif
}
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