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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2015-09-04 11:40:50 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2015-09-04 11:40:50 +0000 |
| commit | 8b7eab2521bf632fc45e66001b57a452e63ef0fa (patch) | |
| tree | 29a2b2ed21bd064c9faa850ffb396bbb28197458 /os/common/ports/ARMCMx/compilers | |
| parent | 9ce134193104f8349fcf523cf2c25fce499cc6ef (diff) | |
| download | ChibiOS-8b7eab2521bf632fc45e66001b57a452e63ef0fa.tar.gz ChibiOS-8b7eab2521bf632fc45e66001b57a452e63ef0fa.tar.bz2 ChibiOS-8b7eab2521bf632fc45e66001b57a452e63ef0fa.zip | |
F7 scatter files improvements.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8276 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/common/ports/ARMCMx/compilers')
3 files changed, 26 insertions, 16 deletions
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld index 81fb0fb89..94668b13e 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld @@ -49,10 +49,13 @@ REGION_ALIAS("DATA_RAM", ram0); /* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
-/* RAM region to be used for NOCACHE segment.*/
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* RAM region to be used for nocache segment.*/
REGION_ALIAS("NOCACHE_RAM", ram3);
-/* RAM region to be used for ETH segment.*/
+/* RAM region to be used for eth segment.*/
REGION_ALIAS("ETH_RAM", ram3);
INCLUDE ld/rules_STM32F7xx.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_DMA.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_DMA.ld index a8e0626d2..03d2e1478 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_DMA.ld +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_DMA.ld @@ -48,10 +48,13 @@ REGION_ALIAS("DATA_RAM", ram1); /* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram1);
-/* RAM region to be used for NOCACHE segment.*/
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram1);
+
+/* RAM region to be used for nocache segment.*/
REGION_ALIAS("NOCACHE_RAM", ram3);
-/* RAM region to be used for ETH segment.*/
+/* RAM region to be used for eth segment.*/
REGION_ALIAS("ETH_RAM", ram2);
INCLUDE rules_dma.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld index 39aad4419..ffed12231 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld @@ -112,7 +112,7 @@ SECTIONS /* Special section for non cache-able areas.*/
.nocache (NOLOAD) : ALIGN(4)
{
- __nocache_start__ = .;
+ __nocache_base__ = .;
*(.nocache)
*(.nocache.*)
*(.bss.__nocache_*)
@@ -121,14 +121,14 @@ SECTIONS } > NOCACHE_RAM
/* Special section for Ethernet DMA non cache-able areas.*/
- .ethram (NOLOAD) : ALIGN(4)
+ .eth (NOLOAD) : ALIGN(4)
{
- __ethram_start__ = .;
- *(.ethram)
- *(.ethram.*)
- *(.bss.__ethram_*)
+ __eth_base__ = .;
+ *(.eth)
+ *(.eth.*)
+ *(.bss.__eth_*)
. = ALIGN(4);
- __ethram_end__ = .;
+ __eth_end__ = .;
} > ETH_RAM
.mstack :
@@ -256,9 +256,13 @@ SECTIONS . = ALIGN(4);
__ram7_free__ = .;
} > ram7
-}
-/* Heap default boundaries, it is defaulted to be the non-used part
- of ram0 region.*/
-__heap_base__ = __ram0_free__;
-__heap_end__ = __ram0_end__;
+ /* The default heap uses the (statically) unused part of a RAM section.*/
+ .heap (NOLOAD) :
+ {
+ . = ALIGN(8);
+ __heap_base__ = .;
+ . = ORIGIN(HEAP_RAM) + LENGTH(HEAP_RAM);
+ __heap_end__ = .;
+ } > HEAP_RAM
+}
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