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| author | isiora <none@example.com> | 2017-08-14 09:03:32 +0000 |
|---|---|---|
| committer | isiora <none@example.com> | 2017-08-14 09:03:32 +0000 |
| commit | c06ff694bdfa0e9e4dd26143c351eaf348cbfd0e (patch) | |
| tree | c28f6cfd84d0aaf9661aa2aedcf84e8b6d0fbfb1 /os/common/ports/ARMCAx-TZ | |
| parent | 1320b9c2e29e3c5326d90e22ce84bfca38f2db01 (diff) | |
| download | ChibiOS-c06ff694bdfa0e9e4dd26143c351eaf348cbfd0e.tar.gz ChibiOS-c06ff694bdfa0e9e4dd26143c351eaf348cbfd0e.tar.bz2 ChibiOS-c06ff694bdfa0e9e4dd26143c351eaf348cbfd0e.zip | |
Enabled FIQ in _port_thread_start
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10422 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/common/ports/ARMCAx-TZ')
| -rw-r--r-- | os/common/ports/ARMCAx-TZ/compilers/GCC/chcoreasm.S | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/os/common/ports/ARMCAx-TZ/compilers/GCC/chcoreasm.S b/os/common/ports/ARMCAx-TZ/compilers/GCC/chcoreasm.S index fe5a58b2e..ecb06a8c2 100644 --- a/os/common/ports/ARMCAx-TZ/compilers/GCC/chcoreasm.S +++ b/os/common/ports/ARMCAx-TZ/compilers/GCC/chcoreasm.S @@ -151,7 +151,7 @@ Mon_Irq_Handler: msr CPSR_c, #MODE_SYS | I_BIT | F_BIT
stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ.
- /* bl chSchDoNTReschedule */
+ /* Save the s_ctx e recover the ns_ctx */
// Re-establish the original conditions
ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ.
@@ -171,8 +171,9 @@ Mon_Irq_Handler: *
*/
Mon_Fiq_Handler:
- // Here the fiq is taken from non-secure state
- // current mode is monitor (so current state is secure).
+ // Here the fiq is taken from non-secure state, via the FIQ vector
+ // that is in the mon vector table.
+ // Current mode is monitor (so current state is secure).
// Note also that we never leave secure state while sec FIQ was disabled,
// then it's always safe to process the FIQ here.
stmfd sp!, {lr} // save lr into monitor stack
@@ -278,8 +279,7 @@ _fiq_ret_arm: /*
* Threads trampoline code.
- * NOTE: The threads always start in ARM mode and then switches to the
- * thread-function mode.
+ * NOTE: The threads always start in ARM mode.
*/
.balign 16
.code 32
@@ -288,6 +288,7 @@ _port_thread_start: #if CH_DBG_SYSTEM_STATE_CHECK
bl _dbg_check_unlock
#endif
+ msr CPSR_c, #MODE_SYS | I_BIT
mov r0, r5
mov lr, pc
bx r4
|