diff options
| author | Rocco Marco Guglielmi <roccomarco.guglielmi@live.com> | 2017-07-29 08:34:26 +0000 |
|---|---|---|
| committer | Rocco Marco Guglielmi <roccomarco.guglielmi@live.com> | 2017-07-29 08:34:26 +0000 |
| commit | 3ea96b878c6b959fb8c9c400e3f1404f2ceade85 (patch) | |
| tree | 890a14246f54667278240a2001bd921118f62662 /os/common/ports/ARMCAx-TZ | |
| parent | 4633e54ba996a03d63c3fa3efe7bfb222297a40e (diff) | |
| download | ChibiOS-3ea96b878c6b959fb8c9c400e3f1404f2ceade85.tar.gz ChibiOS-3ea96b878c6b959fb8c9c400e3f1404f2ceade85.tar.bz2 ChibiOS-3ea96b878c6b959fb8c9c400e3f1404f2ceade85.zip | |
Renamed ports/ARMCMAx-TZ as ports/ARMCAx-TZ
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10342 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/common/ports/ARMCAx-TZ')
| -rw-r--r-- | os/common/ports/ARMCAx-TZ/chcore.c | 54 | ||||
| -rw-r--r-- | os/common/ports/ARMCAx-TZ/chcore.h | 522 | ||||
| -rw-r--r-- | os/common/ports/ARMCAx-TZ/chcore_timer.h | 124 | ||||
| -rw-r--r-- | os/common/ports/ARMCAx-TZ/compilers/GCC/chcoreasm.S | 297 | ||||
| -rw-r--r-- | os/common/ports/ARMCAx-TZ/compilers/GCC/chtypes.h | 115 | ||||
| -rw-r--r-- | os/common/ports/ARMCAx-TZ/compilers/GCC/mk/port_generic.mk | 7 |
6 files changed, 1119 insertions, 0 deletions
diff --git a/os/common/ports/ARMCAx-TZ/chcore.c b/os/common/ports/ARMCAx-TZ/chcore.c new file mode 100644 index 000000000..fc283864a --- /dev/null +++ b/os/common/ports/ARMCAx-TZ/chcore.c @@ -0,0 +1,54 @@ +/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file ARMCMAx-TZ/chcore.c
+ * @brief ARMCMAx-TZ port code.
+ *
+ * @addtogroup ARMCMAx-TZ_CORE
+ * @{
+ */
+
+#include "ch.h"
+
+/*===========================================================================*/
+/* Module local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module exported functions. */
+/*===========================================================================*/
+
+/** @} */
diff --git a/os/common/ports/ARMCAx-TZ/chcore.h b/os/common/ports/ARMCAx-TZ/chcore.h new file mode 100644 index 000000000..7be2cdaca --- /dev/null +++ b/os/common/ports/ARMCAx-TZ/chcore.h @@ -0,0 +1,522 @@ +/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file ARMCMAx-TZ/chcore.h
+ * @brief ARMCMAx-TZ architecture port macros and structures.
+ *
+ * @addtogroup ARMCMAx-TZ_CORE
+ * @{
+ */
+
+#ifndef CHCORE_H
+#define CHCORE_H
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name Port Capabilities and Constants
+ * @{
+ */
+/**
+ * @brief This port supports a realtime counter.
+ */
+#define PORT_SUPPORTS_RT FALSE
+
+/**
+ * @brief Natural alignment constant.
+ * @note It is the minimum alignment for pointer-size variables.
+ */
+#define PORT_NATURAL_ALIGN sizeof (void *)
+
+/**
+ * @brief Stack alignment constant.
+ * @note It is the alignement required for the stack pointer.
+ */
+#define PORT_STACK_ALIGN sizeof (stkalign_t)
+
+/**
+ * @brief Working Areas alignment constant.
+ * @note It is the alignment to be enforced for thread working areas.
+ */
+#define PORT_WORKING_AREA_ALIGN sizeof (stkalign_t)
+/** @} */
+
+/**
+ * @name Architecture and Compiler
+ * @{
+ */
+/**
+ * @brief Macro defining a generic ARM architecture.
+ */
+#define PORT_ARCHITECTURE_ARM
+
+/* The following code is not processed when the file is included from an
+ asm module because those intrinsic macros are not necessarily defined
+ by the assembler too.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Compiler name and version.
+ */
+#if defined(__GNUC__) || defined(__DOXYGEN__)
+#define PORT_COMPILER_NAME "GCC " __VERSION__
+
+#else
+#error "unsupported compiler"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+/** @} */
+
+/**
+ * @name ARM variants
+ * @{
+ */
+#define ARM_CORE_CORTEX_A5 105
+#define ARM_CORE_CORTEX_A8 108
+#define ARM_CORE_CORTEX_A9 109
+/** @} */
+
+/* Inclusion of the ARM implementation specific parameters.*/
+#include "armparams.h"
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an alternative timer implementation.
+ * @details Usually the port uses a timer interface defined in the file
+ * @p chcore_timer.h, if this option is enabled then the file
+ * @p chcore_timer_alt.h is included instead.
+ */
+#if !defined(PORT_USE_ALT_TIMER)
+#define PORT_USE_ALT_TIMER FALSE
+#endif
+
+/**
+ * @brief Stack size for the system idle thread.
+ * @details This size depends on the idle thread implementation, usually
+ * the idle thread should take no more space than those reserved
+ * by @p PORT_INT_REQUIRED_STACK.
+ * @note In this port it is set to 32 because the idle thread does have
+ * a stack frame when compiling without optimizations. You may
+ * reduce this value to zero when compiling with optimizations.
+ */
+#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
+#define PORT_IDLE_THREAD_STACK_SIZE 32
+#endif
+
+/**
+ * @brief Per-thread stack overhead for interrupts servicing.
+ * @details This constant is used in the calculation of the correct working
+ * area size.
+ */
+#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__)
+#define PORT_INT_REQUIRED_STACK 32
+#endif
+
+/**
+ * @brief If enabled allows the idle thread to enter a low power mode.
+ */
+#ifndef ARM_ENABLE_WFI_IDLE
+#define ARM_ENABLE_WFI_IDLE FALSE
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* ARM core check.*/
+#if (ARM_CORE == ARM_CORE_CORTEX_A5) || defined(__DOXYGEN__)
+#define PORT_ARCHITECTURE_ARM_ARM7
+#define PORT_ARCHITECTURE_NAME "ARMv7"
+#define PORT_CORE_VARIANT_NAME "ARM Cortex-A5"
+
+#elif ARM_CORE == ARM_CORE_CORTEX_A8
+#define PORT_ARCHITECTURE_ARM_CORTEXA8
+#define PORT_ARCHITECTURE_NAME "ARMv7"
+#define PORT_CORE_VARIANT_NAME "ARM Cortex-A8"
+
+#elif ARM_CORE == ARM_CORE_CORTEX_A9
+#define PORT_ARCHITECTURE_ARM_CORTEXA9
+#define PORT_ARCHITECTURE_NAME "ARMv7"
+#define PORT_CORE_VARIANT_NAME "ARM Cortex-A9"
+
+#else
+#error "unknown or unsupported ARM core"
+#endif
+
+#define PORT_INFO "Pure THUMB mode"
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/**
+ * @brief Type of stack and memory alignment enforcement.
+ * @note In this architecture the stack alignment is enforced to 64 bits.
+ */
+typedef uint64_t stkalign_t;
+
+/**
+ * @brief Generic ARM register.
+ */
+typedef void *regarm_t;
+
+/**
+ * @brief Interrupt saved context.
+ * @details This structure represents the stack frame saved during an
+ * interrupt handler.
+ */
+struct port_extctx {
+ regarm_t spsr_irq;
+ regarm_t lr_irq;
+ regarm_t r0;
+ regarm_t r1;
+ regarm_t r2;
+ regarm_t r3;
+ regarm_t r12;
+ regarm_t lr_usr;
+};
+
+/**
+ * @brief System saved context.
+ * @details This structure represents the inner stack frame during a context
+ * switch.
+ */
+struct port_intctx {
+ regarm_t r4;
+ regarm_t r5;
+ regarm_t r6;
+ regarm_t r7;
+ regarm_t r8;
+ regarm_t r9;
+ regarm_t r10;
+ regarm_t r11;
+ regarm_t lr;
+};
+
+/**
+ * @brief Platform dependent part of the @p thread_t structure.
+ * @details In this port the structure just holds a pointer to the
+ * @p port_intctx structure representing the stack pointer
+ * at context switch time.
+ */
+struct port_context {
+ struct port_intctx *sp;
+};
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Platform dependent part of the @p chThdCreateI() API.
+ * @details This code usually setup the context switching frame represented
+ * by an @p port_intctx structure.
+ */
+#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) { \
+ (tp)->ctx.sp = (struct port_intctx *)((uint8_t *)(wtop) - \
+ sizeof (struct port_intctx)); \
+ (tp)->ctx.sp->r4 = (regarm_t)(pf); \
+ (tp)->ctx.sp->r5 = (regarm_t)(arg); \
+ (tp)->ctx.sp->lr = (regarm_t)(_port_thread_start); \
+}
+
+/**
+ * @brief Computes the thread working area global size.
+ * @note There is no need to perform alignments in this macro.
+ */
+#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) + \
+ sizeof(struct port_extctx) + \
+ ((size_t)(n)) + ((size_t)(PORT_INT_REQUIRED_STACK)))
+
+/**
+ * @brief Static working area allocation.
+ * @details This macro is used to allocate a static thread working area
+ * aligned as both position and size.
+ *
+ * @param[in] s the name to be assigned to the stack array
+ * @param[in] n the stack size to be assigned to the thread
+ */
+#define PORT_WORKING_AREA(s, n) \
+ stkalign_t s[THD_WORKING_AREA_SIZE(n) / sizeof (stkalign_t)]
+
+/**
+ * @brief Priority level verification macro.
+ * @todo Add the required parameters to armparams.h.
+ */
+#define PORT_IRQ_IS_VALID_PRIORITY(n) false
+
+/**
+ * @brief IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers
+ * enabled to invoke system APIs.
+ */
+#define PORT_IRQ_PROLOGUE()
+
+/**
+ * @brief IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers
+ * enabled to invoke system APIs.
+ */
+#define PORT_IRQ_EPILOGUE() return chSchIsPreemptionRequired()
+
+/**
+ * @brief IRQ handler function declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ */
+#define PORT_IRQ_HANDLER(id) \
+ __attribute__((interrupt("FIQ"))) void id(void)
+
+/**
+ * @brief Fast IRQ handler function declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ */
+#define PORT_FAST_IRQ_HANDLER(id) \
+ __attribute__((interrupt("FIQ"))) void id(void)
+
+/**
+ * @brief Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ * is responsible for the context switch between 2 threads.
+ * @note The implementation of this code affects <b>directly</b> the context
+ * switch performance so optimize here as much as you can.
+ * @note Implemented as inlined code for performance reasons.
+ *
+ * @param[in] ntp the thread to be switched in
+ * @param[in] otp the thread to be switched out
+ */
+#if defined(THUMB)
+
+#if CH_DBG_ENABLE_STACK_CHECK == TRUE
+#define port_switch(ntp, otp) { \
+ register struct port_intctx *r13 asm ("r13"); \
+ if ((stkalign_t *)(r13 - 1) < otp->wabase) \
+ chSysHalt("stack overflow"); \
+ _port_switch_thumb(ntp, otp); \
+}
+#else
+#define port_switch(ntp, otp) _port_switch_thumb(ntp, otp)
+#endif
+
+#else /* !defined(THUMB) */
+
+#if CH_DBG_ENABLE_STACK_CHECK == TRUE
+#define port_switch(ntp, otp) { \
+ register struct port_intctx *r13 asm ("r13"); \
+ if ((stkalign_t *)(r13 - 1) < otp->wabase) \
+ chSysHalt("stack overflow"); \
+ _port_switch_arm(ntp, otp); \
+}
+#else
+#define port_switch(ntp, otp) _port_switch_arm(ntp, otp)
+#endif
+
+#endif /* !defined(THUMB) */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#if defined(THUMB_PRESENT)
+ syssts_t _port_get_cpsr(void);
+#endif
+#if defined(THUMB)
+ void _port_switch_thumb(thread_t *ntp, thread_t *otp);
+#else
+ void _port_switch_arm(thread_t *ntp, thread_t *otp);
+#endif
+ void _port_thread_start(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Port-related initialization code.
+ */
+static inline void port_init(void) {
+
+}
+
+/**
+ * @brief Returns a word encoding the current interrupts status.
+ *
+ * @return The interrupts status.
+ */
+static inline syssts_t port_get_irq_status(void) {
+ syssts_t sts;
+
+#if defined(THUMB)
+ sts = _port_get_cpsr();
+#else
+ __asm volatile ("mrs %[p0], CPSR" : [p0] "=r" (sts) :);
+#endif
+ /*lint -save -e530 [9.1] Asm instruction not seen by lint.*/
+ return sts;
+ /*lint -restore*/
+}
+
+/**
+ * @brief Checks the interrupt status.
+ *
+ * @param[in] sts the interrupt status word
+ *
+ * @return The interrupt status.
+ * @retval false the word specified a disabled interrupts status.
+ * @retval true the word specified an enabled interrupts status.
+ */
+static inline bool port_irq_enabled(syssts_t sts) {
+
+ return (sts & (syssts_t)0x40) == (syssts_t)0;
+}
+
+/**
+ * @brief Determines the current execution context.
+ *
+ * @return The execution context.
+ * @retval false not running in ISR mode.
+ * @retval true running in ISR mode.
+ */
+static inline bool port_is_isr_context(void) {
+ syssts_t sts;
+
+#if defined(THUMB)
+ sts = _port_get_cpsr();
+#else
+ __asm volatile ("mrs %[p0], CPSR" : [p0] "=r" (sts) :);
+#endif
+
+ /*lint -save -e530 [9.1] Asm instruction not seen by lint.*/
+ return (sts & (syssts_t)0x1F) == (syssts_t)0x11;
+ /*lint -restore*/
+}
+
+/**
+ * @brief Kernel-lock action.
+ * @details In this port it disables the FIQ sources and keeps IRQ sources
+ * enabled.
+ */
+static inline void port_lock(void) {
+
+ __asm volatile ("msr CPSR_c, #0x5F" : : : "memory");
+}
+
+/**
+ * @brief Kernel-unlock action.
+ * @details In this port it enables both the IRQ and FIQ sources.
+ */
+static inline void port_unlock(void) {
+
+ __asm volatile ("msr CPSR_c, #0x1F" : : : "memory");
+}
+
+/**
+ * @brief Kernel-lock action from an interrupt handler.
+ * @note Empty in this port.
+ */
+static inline void port_lock_from_isr(void) {
+
+}
+
+/**
+ * @brief Kernel-unlock action from an interrupt handler.
+ * @note Empty in this port.
+ */
+static inline void port_unlock_from_isr(void) {
+
+}
+
+/**
+ * @brief Disables all the interrupt sources.
+ * @details In this port it disables FIQ sources.
+ */
+static inline void port_disable(void) {
+
+ __asm volatile ("msr CPSR_c, #0x5F" : : : "memory");
+}
+
+/**
+ * @brief Disables the interrupt sources below kernel-level priority.
+ * @note Interrupt sources above kernel level remains enabled.
+ * @note In this port it disables the FIQ sources.
+ */
+static inline void port_suspend(void) {
+
+ __asm volatile ("msr CPSR_c, #0x5F" : : : "memory");
+}
+
+/**
+ * @brief Enables all the interrupt sources.
+ * @note In this port it enables both the IRQ and FIQ sources.
+ */
+static inline void port_enable(void) {
+
+ __asm volatile ("msr CPSR_c, #0x1F" : : : "memory");
+}
+
+/**
+ * @brief Enters an architecture-dependent IRQ-waiting mode.
+ * @details The function is meant to return when an interrupt becomes pending.
+ * The simplest implementation is an empty function or macro but this
+ * would not take advantage of architecture-specific power saving
+ * modes.
+ * @note Implemented as an inlined @p WFI instruction.
+ */
+static inline void port_wait_for_interrupt(void) {
+
+ asm volatile ("wfi" : : : "memory");
+}
+
+#if CH_CFG_ST_TIMEDELTA > 0
+#if PORT_USE_ALT_TIMER == FALSE
+#include "chcore_timer.h"
+#else /* PORT_USE_ALT_TIMER */
+#include "chcore_timer_alt.h"
+#endif /* PORT_USE_ALT_TIMER */
+#endif /* CH_CFG_ST_TIMEDELTA > 0 */
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* CHCORE_H */
+
+/** @} */
diff --git a/os/common/ports/ARMCAx-TZ/chcore_timer.h b/os/common/ports/ARMCAx-TZ/chcore_timer.h new file mode 100644 index 000000000..c27b0b3c8 --- /dev/null +++ b/os/common/ports/ARMCAx-TZ/chcore_timer.h @@ -0,0 +1,124 @@ +/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file chcore_timer.h
+ * @brief System timer header file.
+ *
+ * @addtogroup ARMCMAx-TZ_TIMER
+ * @{
+ */
+
+#ifndef CHCORE_TIMER_H
+#define CHCORE_TIMER_H
+
+/* This is the only header in the HAL designed to be include-able alone.*/
+#include "hal_st.h"
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Starts the alarm.
+ * @note Makes sure that no spurious alarms are triggered after
+ * this call.
+ *
+ * @param[in] time the time to be set for the first alarm
+ *
+ * @notapi
+ */
+static inline void port_timer_start_alarm(systime_t time) {
+
+ stStartAlarm(time);
+}
+
+/**
+ * @brief Stops the alarm interrupt.
+ *
+ * @notapi
+ */
+static inline void port_timer_stop_alarm(void) {
+
+ stStopAlarm();
+}
+
+/**
+ * @brief Sets the alarm time.
+ *
+ * @param[in] time the time to be set for the next alarm
+ *
+ * @notapi
+ */
+static inline void port_timer_set_alarm(systime_t time) {
+
+ stSetAlarm(time);
+}
+
+/**
+ * @brief Returns the system time.
+ *
+ * @return The system time.
+ *
+ * @notapi
+ */
+static inline systime_t port_timer_get_time(void) {
+
+ return stGetCounter();
+}
+
+/**
+ * @brief Returns the current alarm time.
+ *
+ * @return The currently set alarm time.
+ *
+ * @notapi
+ */
+static inline systime_t port_timer_get_alarm(void) {
+
+ return stGetAlarm();
+}
+
+#endif /* CHCORE_TIMER_H */
+
+/** @} */
diff --git a/os/common/ports/ARMCAx-TZ/compilers/GCC/chcoreasm.S b/os/common/ports/ARMCAx-TZ/compilers/GCC/chcoreasm.S new file mode 100644 index 000000000..90438ea6d --- /dev/null +++ b/os/common/ports/ARMCAx-TZ/compilers/GCC/chcoreasm.S @@ -0,0 +1,297 @@ +/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file ARMCMAx-TZ/compilers/GCC/chcoreasm.S
+ * @brief ARMCMAx-TZ architecture port low level code.
+ *
+ * @addtogroup ARMCMAx-TZ_CORE
+ * @{
+ */
+
+#define _FROM_ASM_
+#include "chlicense.h"
+#include "chconf.h"
+#include "armparams.h"
+
+#define FALSE 0
+#define TRUE 1
+
+#if !defined(__DOXYGEN__)
+
+/*
+ * RTOS-specific context offset.
+ */
+#if defined(_CHIBIOS_RT_CONF_)
+#define CONTEXT_OFFSET 12
+#elif defined(_CHIBIOS_NIL_CONF_)
+#define CONTEXT_OFFSET 0
+#else
+#error "invalid chconf.h"
+#endif
+
+ .set MODE_USR, 0x10
+ .set MODE_FIQ, 0x11
+ .set MODE_IRQ, 0x12
+ .set MODE_SVC, 0x13
+ .set MODE_MON, 0x16
+ .set MODE_ABT, 0x17
+ .set MODE_UND, 0x1B
+ .set MODE_SYS, 0x1F
+
+ .equ I_BIT, 0x80
+ .equ F_BIT, 0x40
+ .equ SCR_NS, 0x01
+ .equ SCR_IRQ, 0x02
+ .equ SCR_FIQ, 0x04
+ .equ SCR_EA, 0x08
+ .equ SCR_FW, 0x10
+ .equ SCR_AW, 0x20
+
+ .equ MON_S_SCR, SCR_IRQ
+ .equ MON_NS_SCR, SCR_FIQ|SCR_NS
+
+ .text
+
+ .balign 16
+
+ .code 32
+ .global _port_switch_arm
+_port_switch_arm:
+ stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+ str sp, [r1, #12]
+ ldr sp, [r0, #12]
+ ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+
+/*
+ * Common IRQ code. It expects a macro ARM_IRQ_VECTOR_REG with the address
+ * of a register holding the address of the ISR to be invoked, the ISR
+ * then returns in the common epilogue code where the context switch will
+ * be performed, if required.
+ * System stack frame structure after a context switch in the
+ * interrupt handler:
+ *
+ * High +------------+
+ * | LR_USR | -+
+ * | r12 | |
+ * | r3 | |
+ * | r2 | | External context: IRQ handler frame
+ * | r1 | |
+ * | r0 | |
+ * | LR_IRQ | | (user code return address)(could be in non-secure space)
+ * | PSR_USR | -+ (user code status)
+ * | .... | <- chSchDoReschedule() stack frame, optimize it for space
+ * | LR | -+ (system code return address)(always in secure space)
+ * | r11 | |
+ * | r10 | |
+ * | r9 | |
+ * | r8 | | Internal context: chSysSwitch() frame
+ * | r7 | |
+ * | r6 | |
+ * | r5 | |
+ * SP-> | r4 | -+
+ * Low +------------+
+ *
+ */
+
+/*
+ * We are facing an architecure with security extension exploited.
+ * The following two monitor execution paths are followed by the execution units
+ * running in secure state when an irq is fired (Mon_Irq_Handler), and in non-secure
+ * state when a fiq interrupt is fired (Mon_Fiq_Handler).
+ * They originate by the monitor irq/fiq vector and run in monitor mode,
+ * ie in secure state.
+ * It assumes the following, set at boot time, or wherever it needs:
+ * SCR.FW == 0 and SCR.FIQ == 1 and SCR.IRQ == 0 in non-secure state,
+ * ie, in non-secure state, FIQs are taken to monitor mode and IRQs locally
+ * SCR.FW == 0 and SCR.FIQ == 0 and SCR.IRQ == 1 in secure state,
+ * ie, in the secure-state, FIQs are taken locally and IRQs to monitor
+ * MVBAR holds the address of the monitor vectors base.
+ * The code and the stacks memory reside both in secure memory.
+ */
+ .balign 16
+ .code 32
+ .global Mon_Fiq_Handler
+ .global Mon_Irq_Handler
+ .global Fiq_Handler
+Mon_Irq_Handler:
+ // here the irq is taken from secure state
+ // current mode is monitor (so current state is secure)
+ //
+ // This procedure is challenging, because the irq must be
+ // executed in the context of the NT thread, it must run
+ // in non-secure state.
+ // So we shall switch to a NT thread(?) and return into non-secure
+ // world where the IRQ will be served.
+
+ // The frame is created in the system stack,
+ // current state is secure.
+ msr CPSR_c, #MODE_SYS | I_BIT | F_BIT
+ stmfd sp!, {r0-r3, r12, lr}
+ msr CPSR_c, #MODE_MON | I_BIT | F_BIT
+ mrs r0, SPSR
+ mov r1, lr
+ msr CPSR_c, #MODE_SYS | I_BIT | F_BIT
+ stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ.
+
+ /* bl chSchDoNTReschedule */
+
+ // Re-establish the original conditions
+ ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ.
+ msr CPSR_c, #MODE_MON | I_BIT | F_BIT
+ msr SPSR_fsxc, r0
+ mov lr, r1
+ msr CPSR_c, #MODE_SYS | I_BIT | F_BIT
+ ldmfd sp!, {r0-r3, r12, lr}
+ msr CPSR_c, #MODE_MON | I_BIT | F_BIT
+ stmfd sp!, {lr} // save lr into monitor stack
+ ldr lr, =MON_NS_SCR // set non-secure SCR before return
+ mrc p15, 0, lr, c1, c1, 0
+ ldmfd sp!, {lr}
+ subs pc, lr, #4 // return into non-secure world
+ // and serve the IRQ
+/*
+ *
+ */
+Mon_Fiq_Handler:
+ // here the fiq is taken from non-secure state
+ // current mode is monitor (so current state is secure)
+ stmfd sp!, {lr} // save lr into monitor stack
+ ldr lr, =MON_S_SCR // set secure SCR before to switch to FIQ mode
+ mrc p15, 0, lr, c1, c1, 0
+ cpsid if, #MODE_FIQ // secure FIQ mode
+ stmfd sp!, {r0-r3, r12} // IRQ frame, save scratch registers
+ ldr r0, =ARM_IRQ_VECTOR_REG
+ ldr r0, [r0]
+ ldr lr, =_mon_fiq_ret_arm // ISR return point.
+ bx r0 // Calling the ISR.
+_mon_fiq_ret_arm:
+ cmp r0, #0
+ ldmfd sp!, {r0-r3, r12}
+ cpsid if, #MODE_MON
+ ldr lr, =MON_NS_SCR // set non-secure SCR before return
+ mrceq p15, 0, lr, c1, c1, 0 // only if it will return
+ ldmfd sp!, {lr}
+ subeqs pc, lr, #4 // No reschedule, returns.
+
+ // Now the frame is created in the system stack, the IRQ
+ // and monitor stacks are empty, the state is secure.
+ msr CPSR_c, #MODE_SYS | I_BIT | F_BIT
+ stmfd sp!, {r0-r3, r12, lr}
+ msr CPSR_c, #MODE_MON | I_BIT | F_BIT
+ mrs r0, SPSR
+ mov r1, lr
+ msr CPSR_c, #MODE_SYS | I_BIT | F_BIT
+ stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ.
+
+ // Context switch.
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_lock
+#endif
+ bl chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_unlock
+#endif
+
+ // Re-establish the IRQ conditions again.
+ ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ.
+ msr CPSR_c, #MODE_MON | I_BIT | F_BIT
+ msr SPSR_fsxc, r0
+ mov lr, r1
+ msr CPSR_c, #MODE_SYS | I_BIT | F_BIT
+ ldmfd sp!, {r0-r3, r12, lr}
+ msr CPSR_c, #MODE_MON | I_BIT | F_BIT
+ stmfd sp!, {lr} // save lr into monitor stack
+ ldr lr, =MON_NS_SCR // set non-secure SCR before return
+ mrc p15, 0, lr, c1, c1, 0
+ ldmfd sp!, {lr}
+ subs pc, lr, #4 // return into non-secure world
+/*
+ *
+ */
+Fiq_Handler:
+ // the fiq is taken locally from secure state
+ // current mode is fiq
+ stmfd sp!, {r0-r3, r12, lr} // save scratch registers and lr
+ ldr r0, =ARM_IRQ_VECTOR_REG
+ ldr r0, [r0]
+ ldr lr, =_fiq_ret_arm // ISR return point.
+ bx r0 // Calling the ISR.
+_fiq_ret_arm:
+ cmp r0, #0
+ ldmfd sp!, {r0-r3, r12, lr}
+ subeqs pc, lr, #4 // No reschedule, returns.
+
+ // Now the frame is created in the system stack, the IRQ
+ // stack is empty.
+ msr CPSR_c, #MODE_SYS | I_BIT | F_BIT
+ stmfd sp!, {r0-r3, r12, lr}
+ msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT
+ mrs r0, SPSR
+ mov r1, lr
+ msr CPSR_c, #MODE_SYS | I_BIT | F_BIT
+ stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ.
+
+ // Context switch.
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_lock
+#endif
+ bl chSchDoReschedule
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_unlock
+#endif
+
+ // Re-establish the IRQ conditions again.
+ ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ.
+ msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT
+ msr SPSR_fsxc, r0
+ mov lr, r1
+ msr CPSR_c, #MODE_SYS | I_BIT | F_BIT
+ ldmfd sp!, {r0-r3, r12, lr}
+ msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT
+ subs pc, lr, #4
+
+/*
+ * Threads trampoline code.
+ * NOTE: The threads always start in ARM mode and then switches to the
+ * thread-function mode.
+ */
+ .balign 16
+ .code 32
+ .globl _port_thread_start
+_port_thread_start:
+#if CH_DBG_SYSTEM_STATE_CHECK
+ bl _dbg_check_unlock
+#endif
+ mov r0, r5
+ mov lr, pc
+ bx r4
+#if defined(_CHIBIOS_RT_CONF_)
+ mov r0, #0 /* MSG_OK */
+ bl chThdExit
+_zombies: b _zombies
+#endif
+#if defined(_CHIBIOS_NIL_CONF_)
+ mov r0, #0
+ bl chSysHalt
+#endif
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/ports/ARMCAx-TZ/compilers/GCC/chtypes.h b/os/common/ports/ARMCAx-TZ/compilers/GCC/chtypes.h new file mode 100644 index 000000000..1bd3b07c5 --- /dev/null +++ b/os/common/ports/ARMCAx-TZ/compilers/GCC/chtypes.h @@ -0,0 +1,115 @@ +/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio.
+
+ This file is part of ChibiOS.
+
+ ChibiOS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file ARMCMAx-TZ/compilers/GCC/chtypes.h
+ * @brief ARMCMAx-TZ port system types.
+ *
+ * @addtogroup ARMCMAx-TZ_GCC_CORE
+ * @{
+ */
+
+#ifndef CHTYPES_H
+#define CHTYPES_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/**
+ * @name Common constants
+ */
+/**
+ * @brief Generic 'false' boolean constant.
+ */
+#if !defined(FALSE) || defined(__DOXYGEN__)
+#define FALSE 0
+#endif
+
+/**
+ * @brief Generic 'true' boolean constant.
+ */
+#if !defined(TRUE) || defined(__DOXYGEN__)
+#define TRUE 1
+#endif
+/** @} */
+
+/**
+ * @name Kernel types
+ * @{
+ */
+typedef uint32_t rtcnt_t; /**< Realtime counter. */
+typedef uint64_t rttime_t; /**< Realtime accumulator. */
+typedef uint32_t syssts_t; /**< System status word. */
+typedef uint8_t tmode_t; /**< Thread flags. */
+typedef uint8_t tstate_t; /**< Thread state. */
+typedef uint8_t trefs_t; /**< Thread references counter. */
+typedef uint8_t tslices_t; /**< Thread time slices counter.*/
+typedef uint32_t tprio_t; /**< Thread priority. */
+typedef int32_t msg_t; /**< Inter-thread message. */
+typedef int32_t eventid_t; /**< Numeric event identifier. */
+typedef uint32_t eventmask_t; /**< Mask of event identifiers. */
+typedef uint32_t eventflags_t; /**< Mask of event flags. */
+typedef int32_t cnt_t; /**< Generic signed counter. */
+typedef uint32_t ucnt_t; /**< Generic unsigned counter. */
+/** @} */
+
+/**
+ * @brief ROM constant modifier.
+ * @note It is set to use the "const" keyword in this port.
+ */
+#define ROMCONST const
+
+/**
+ * @brief Makes functions not inlineable.
+ * @note If the compiler does not support such attribute then some
+ * time-dependent services could be degraded.
+ */
+#define NOINLINE __attribute__((noinline))
+
+/**
+ * @brief Optimized thread function declaration macro.
+ */
+#define PORT_THD_FUNCTION(tname, arg) void tname(void *arg)
+
+/**
+ * @brief Packed variable specifier.
+ */
+#define PACKED_VAR __attribute__((packed))
+
+/**
+ * @brief Memory alignment enforcement for variables.
+ */
+#define ALIGNED_VAR(n) __attribute__((aligned(n)))
+
+/**
+ * @brief Size of a pointer.
+ * @note To be used where the sizeof operator cannot be used, preprocessor
+ * expressions for example.
+ */
+#define SIZEOF_PTR 4
+
+/**
+ * @brief True if alignment is low-high in current architecture.
+ */
+#define REVERSE_ORDER 1
+
+#endif /* CHTYPES_H */
+
+/** @} */
diff --git a/os/common/ports/ARMCAx-TZ/compilers/GCC/mk/port_generic.mk b/os/common/ports/ARMCAx-TZ/compilers/GCC/mk/port_generic.mk new file mode 100644 index 000000000..7b156c938 --- /dev/null +++ b/os/common/ports/ARMCAx-TZ/compilers/GCC/mk/port_generic.mk @@ -0,0 +1,7 @@ +# List of the ChibiOS/RT ARMCAx-TZ generic port files.
+PORTSRC = ${CHIBIOS}/os/common/ports/ARMCAx-TZ/chcore.c
+
+PORTASM = $(CHIBIOS)/os/common/ports/ARMCAx-TZ/compilers/GCC/chcoreasm.S
+
+PORTINC = ${CHIBIOS}/os/common/ports/ARMCAx-TZ \
+ ${CHIBIOS}/os/common/ports/ARMCAx-TZ/compilers/GCC
|