More headers updated.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10825 35acf78f-673a-0410-8e92-d51de3d6d3f4

16 files changed, 306 insertions, 178 deletions

diff --git a/os/common/ext/ST/STM32F3xx/stm32f301x8.h b/os/common/ext/ST/STM32F3xx/stm32f301x8.h
index f226230e3..a20c44ef2 100644
--- a/os/common/ext/ST/STM32F3xx/stm32f301x8.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f301x8.h
@@ -2,8 +2,6 @@
   ******************************************************************************

   * @file    stm32f301x8.h

   * @author  MCD Application Team

-  * @version V2.3.1

-  * @date    16-December-2016

   * @brief   CMSIS STM32F301x8 Devices Peripheral Access Layer Header File.

   *

   *          This file contains:

@@ -3541,9 +3539,19 @@ typedef struct
 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35

 #endif

 

+#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)

 #define EXTI_IMR2_IM_Pos           (0U)                                        

 #define EXTI_IMR2_IM_Msk           (0xFU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000F */

 #define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)

+#define EXTI_IMR2_IM_Pos           (0U)                                        

+#define EXTI_IMR2_IM_Msk           (0xDU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000D */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#else

+#define EXTI_IMR2_IM_Pos           (0U)                                        

+#define EXTI_IMR2_IM_Msk           (0x1U << EXTI_IMR2_IM_Pos)                  /*!< 0x00000001 */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#endif

 

 /*******************  Bit definition for EXTI_EMR2 ****************************/

 #define EXTI_EMR2_MR32_Pos         (0U)                                        

@@ -3562,6 +3570,20 @@ typedef struct
 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35

 #endif

 

+#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0xFU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000F */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0xDU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000D */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#else

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0x1U << EXTI_EMR2_EM_Pos)                  /*!< 0x00000001 */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#endif

+

 /******************  Bit definition for EXTI_RTSR2 register ********************/

 #define EXTI_RTSR2_TR32_Pos        (0U)                                        

 #define EXTI_RTSR2_TR32_Msk        (0x1U << EXTI_RTSR2_TR32_Pos)               /*!< 0x00000001 */

@@ -3811,21 +3833,6 @@ typedef struct
 #define OB_WRP1_nWRP1_Msk    (0xFFU << OB_WRP1_nWRP1_Pos)                      /*!< 0xFF000000 */

 #define OB_WRP1_nWRP1        OB_WRP1_nWRP1_Msk                                 /*!< Flash memory write protection complemented option bytes */

 

-/******************  Bit definition for FLASH_WRP2 register  ******************/

-#define OB_WRP2_WRP2_Pos     (0U)                                              

-#define OB_WRP2_WRP2_Msk     (0xFFU << OB_WRP2_WRP2_Pos)                       /*!< 0x000000FF */

-#define OB_WRP2_WRP2         OB_WRP2_WRP2_Msk                                  /*!< Flash memory write protection option bytes */

-#define OB_WRP2_nWRP2_Pos    (8U)                                              

-#define OB_WRP2_nWRP2_Msk    (0xFFU << OB_WRP2_nWRP2_Pos)                      /*!< 0x0000FF00 */

-#define OB_WRP2_nWRP2        OB_WRP2_nWRP2_Msk                                 /*!< Flash memory write protection complemented option bytes */

-

-/******************  Bit definition for FLASH_WRP3 register  ******************/

-#define OB_WRP3_WRP3_Pos     (16U)                                             

-#define OB_WRP3_WRP3_Msk     (0xFFU << OB_WRP3_WRP3_Pos)                       /*!< 0x00FF0000 */

-#define OB_WRP3_WRP3         OB_WRP3_WRP3_Msk                                  /*!< Flash memory write protection option bytes */

-#define OB_WRP3_nWRP3_Pos    (24U)                                             

-#define OB_WRP3_nWRP3_Msk    (0xFFU << OB_WRP3_nWRP3_Pos)                      /*!< 0xFF000000 */

-#define OB_WRP3_nWRP3        OB_WRP3_nWRP3_Msk                                 /*!< Flash memory write protection complemented option bytes */

 

 /******************************************************************************/

 /*                                                                            */

@@ -5442,9 +5449,9 @@ typedef struct
 #define RTC_CR_COSEL_Pos             (19U)                                     

 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */

 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          

-#define RTC_CR_BCK_Pos               (18U)                                     

-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */

-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            

+#define RTC_CR_BKP_Pos               (18U)                                     

+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */

+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            

 #define RTC_CR_SUB1H_Pos             (17U)                                     

 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */

 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          

@@ -5494,6 +5501,11 @@ typedef struct
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */

 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */

 

+/* Legacy defines */

+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos

+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk

+#define RTC_CR_BCK                   RTC_CR_BKP

+

 /********************  Bits definition for RTC_ISR register  ******************/

 #define RTC_ISR_RECALPF_Pos          (16U)                                     

 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */

diff --git a/os/common/ext/ST/STM32F3xx/stm32f302x8.h b/os/common/ext/ST/STM32F3xx/stm32f302x8.h
index 0d203c7fb..b5753c5b1 100644
--- a/os/common/ext/ST/STM32F3xx/stm32f302x8.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f302x8.h
@@ -2,8 +2,6 @@
   ******************************************************************************

   * @file    stm32f302x8.h

   * @author  MCD Application Team

-  * @version V2.3.1

-  * @date    16-December-2016

   * @brief   CMSIS STM32F302x8 Devices Peripheral Access Layer Header File.

   *

   *          This file contains:

@@ -7137,9 +7135,19 @@ typedef struct
 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35

 #endif

 

+#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)

 #define EXTI_IMR2_IM_Pos           (0U)                                        

 #define EXTI_IMR2_IM_Msk           (0xFU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000F */

 #define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)

+#define EXTI_IMR2_IM_Pos           (0U)                                        

+#define EXTI_IMR2_IM_Msk           (0xDU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000D */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#else

+#define EXTI_IMR2_IM_Pos           (0U)                                        

+#define EXTI_IMR2_IM_Msk           (0x1U << EXTI_IMR2_IM_Pos)                  /*!< 0x00000001 */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#endif

 

 /*******************  Bit definition for EXTI_EMR2 ****************************/

 #define EXTI_EMR2_MR32_Pos         (0U)                                        

@@ -7158,6 +7166,20 @@ typedef struct
 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35

 #endif

 

+#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0xFU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000F */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0xDU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000D */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#else

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0x1U << EXTI_EMR2_EM_Pos)                  /*!< 0x00000001 */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#endif

+

 /******************  Bit definition for EXTI_RTSR2 register ********************/

 #define EXTI_RTSR2_TR32_Pos        (0U)                                        

 #define EXTI_RTSR2_TR32_Msk        (0x1U << EXTI_RTSR2_TR32_Pos)               /*!< 0x00000001 */

@@ -7407,21 +7429,6 @@ typedef struct
 #define OB_WRP1_nWRP1_Msk    (0xFFU << OB_WRP1_nWRP1_Pos)                      /*!< 0xFF000000 */

 #define OB_WRP1_nWRP1        OB_WRP1_nWRP1_Msk                                 /*!< Flash memory write protection complemented option bytes */

 

-/******************  Bit definition for FLASH_WRP2 register  ******************/

-#define OB_WRP2_WRP2_Pos     (0U)                                              

-#define OB_WRP2_WRP2_Msk     (0xFFU << OB_WRP2_WRP2_Pos)                       /*!< 0x000000FF */

-#define OB_WRP2_WRP2         OB_WRP2_WRP2_Msk                                  /*!< Flash memory write protection option bytes */

-#define OB_WRP2_nWRP2_Pos    (8U)                                              

-#define OB_WRP2_nWRP2_Msk    (0xFFU << OB_WRP2_nWRP2_Pos)                      /*!< 0x0000FF00 */

-#define OB_WRP2_nWRP2        OB_WRP2_nWRP2_Msk                                 /*!< Flash memory write protection complemented option bytes */

-

-/******************  Bit definition for FLASH_WRP3 register  ******************/

-#define OB_WRP3_WRP3_Pos     (16U)                                             

-#define OB_WRP3_WRP3_Msk     (0xFFU << OB_WRP3_WRP3_Pos)                       /*!< 0x00FF0000 */

-#define OB_WRP3_WRP3         OB_WRP3_WRP3_Msk                                  /*!< Flash memory write protection option bytes */

-#define OB_WRP3_nWRP3_Pos    (24U)                                             

-#define OB_WRP3_nWRP3_Msk    (0xFFU << OB_WRP3_nWRP3_Pos)                      /*!< 0xFF000000 */

-#define OB_WRP3_nWRP3        OB_WRP3_nWRP3_Msk                                 /*!< Flash memory write protection complemented option bytes */

 

 /******************************************************************************/

 /*                                                                            */

@@ -9058,9 +9065,9 @@ typedef struct
 #define RTC_CR_COSEL_Pos             (19U)                                     

 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */

 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          

-#define RTC_CR_BCK_Pos               (18U)                                     

-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */

-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            

+#define RTC_CR_BKP_Pos               (18U)                                     

+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */

+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            

 #define RTC_CR_SUB1H_Pos             (17U)                                     

 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */

 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          

@@ -9110,6 +9117,11 @@ typedef struct
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */

 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */

 

+/* Legacy defines */

+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos

+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk

+#define RTC_CR_BCK                   RTC_CR_BKP

+

 /********************  Bits definition for RTC_ISR register  ******************/

 #define RTC_ISR_RECALPF_Pos          (16U)                                     

 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */

diff --git a/os/common/ext/ST/STM32F3xx/stm32f302xc.h b/os/common/ext/ST/STM32F3xx/stm32f302xc.h
index 68e6441e4..807124fcc 100644
--- a/os/common/ext/ST/STM32F3xx/stm32f302xc.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f302xc.h
@@ -2,8 +2,6 @@
   ******************************************************************************

   * @file    stm32f302xc.h

   * @author  MCD Application Team

-  * @version V2.3.1

-  * @date    16-December-2016

   * @brief   CMSIS STM32F302xC Devices Peripheral Access Layer Header File.

   *

   *          This file contains:

@@ -7343,9 +7341,15 @@ typedef struct
 #define EXTI_IMR2_IM34 EXTI_IMR2_MR34

 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35

 

+#if defined(EXTI_IMR2_MR33)

 #define EXTI_IMR2_IM_Pos           (0U)                                        

 #define EXTI_IMR2_IM_Msk           (0xFU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000F */

 #define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#else

+#define EXTI_IMR2_IM_Pos           (0U)                                        

+#define EXTI_IMR2_IM_Msk           (0xDU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000D */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#endif

 

 /*******************  Bit definition for EXTI_EMR2 ****************************/

 #define EXTI_EMR2_MR32_Pos         (0U)                                        

@@ -7366,6 +7370,16 @@ typedef struct
 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34

 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35

 

+#if defined(EXTI_EMR2_MR33)

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0xFU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000F */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#else

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0xDU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000D */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#endif

+

 /******************  Bit definition for EXTI_RTSR2 register ********************/

 #define EXTI_RTSR2_TR32_Pos        (0U)                                        

 #define EXTI_RTSR2_TR32_Msk        (0x1U << EXTI_RTSR2_TR32_Pos)               /*!< 0x00000001 */

@@ -9295,9 +9309,9 @@ typedef struct
 #define RTC_CR_COSEL_Pos             (19U)                                     

 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */

 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          

-#define RTC_CR_BCK_Pos               (18U)                                     

-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */

-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            

+#define RTC_CR_BKP_Pos               (18U)                                     

+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */

+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            

 #define RTC_CR_SUB1H_Pos             (17U)                                     

 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */

 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          

@@ -9347,6 +9361,11 @@ typedef struct
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */

 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */

 

+/* Legacy defines */

+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos

+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk

+#define RTC_CR_BCK                   RTC_CR_BKP

+

 /********************  Bits definition for RTC_ISR register  ******************/

 #define RTC_ISR_RECALPF_Pos          (16U)                                     

 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */

diff --git a/os/common/ext/ST/STM32F3xx/stm32f302xe.h b/os/common/ext/ST/STM32F3xx/stm32f302xe.h
index 484c51b43..754bab04e 100644
--- a/os/common/ext/ST/STM32F3xx/stm32f302xe.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f302xe.h
@@ -2,8 +2,6 @@
   ******************************************************************************

   * @file    stm32f302xe.h

   * @author  MCD Application Team

-  * @version V2.3.1

-  * @date    16-December-2016

   * @brief   CMSIS STM32F302xE Devices Peripheral Access Layer Header File.

   *

   *          This file contains:

@@ -7371,9 +7369,15 @@ typedef struct
 #define EXTI_IMR2_IM34 EXTI_IMR2_MR34

 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35

 

+#if defined(EXTI_IMR2_MR33)

 #define EXTI_IMR2_IM_Pos           (0U)                                        

 #define EXTI_IMR2_IM_Msk           (0xFU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000F */

 #define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#else

+#define EXTI_IMR2_IM_Pos           (0U)                                        

+#define EXTI_IMR2_IM_Msk           (0xDU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000D */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#endif

 

 /*******************  Bit definition for EXTI_EMR2 ****************************/

 #define EXTI_EMR2_MR32_Pos         (0U)                                        

@@ -7394,6 +7398,16 @@ typedef struct
 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34

 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35

 

+#if defined(EXTI_EMR2_MR33)

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0xFU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000F */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#else

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0xDU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000D */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#endif

+

 /******************  Bit definition for EXTI_RTSR2 register ********************/

 #define EXTI_RTSR2_TR32_Pos        (0U)                                        

 #define EXTI_RTSR2_TR32_Msk        (0x1U << EXTI_RTSR2_TR32_Pos)               /*!< 0x00000001 */

@@ -10974,9 +10988,9 @@ typedef struct
 #define RTC_CR_COSEL_Pos             (19U)                                     

 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */

 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          

-#define RTC_CR_BCK_Pos               (18U)                                     

-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */

-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            

+#define RTC_CR_BKP_Pos               (18U)                                     

+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */

+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            

 #define RTC_CR_SUB1H_Pos             (17U)                                     

 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */

 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          

@@ -11026,6 +11040,11 @@ typedef struct
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */

 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */

 

+/* Legacy defines */

+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos

+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk

+#define RTC_CR_BCK                   RTC_CR_BKP

+

 /********************  Bits definition for RTC_ISR register  ******************/

 #define RTC_ISR_RECALPF_Pos          (16U)                                     

 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */

diff --git a/os/common/ext/ST/STM32F3xx/stm32f303x8.h b/os/common/ext/ST/STM32F3xx/stm32f303x8.h
index 4f5c2f5a2..2a4b8cc7e 100644
--- a/os/common/ext/ST/STM32F3xx/stm32f303x8.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f303x8.h
@@ -2,8 +2,6 @@
   ******************************************************************************

   * @file    stm32f303x8.h

   * @author  MCD Application Team

-  * @version V2.3.1

-  * @date    16-December-2016

   * @brief   CMSIS STM32F303x8 Devices Peripheral Access Layer Header File.

   *

   *          This file contains:

@@ -7151,9 +7149,19 @@ typedef struct
 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35

 #endif

 

+#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)

 #define EXTI_IMR2_IM_Pos           (0U)                                        

 #define EXTI_IMR2_IM_Msk           (0xFU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000F */

 #define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)

+#define EXTI_IMR2_IM_Pos           (0U)                                        

+#define EXTI_IMR2_IM_Msk           (0xDU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000D */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#else

+#define EXTI_IMR2_IM_Pos           (0U)                                        

+#define EXTI_IMR2_IM_Msk           (0x1U << EXTI_IMR2_IM_Pos)                  /*!< 0x00000001 */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#endif

 

 /*******************  Bit definition for EXTI_EMR2 ****************************/

 #define EXTI_EMR2_MR32_Pos         (0U)                                        

@@ -7172,6 +7180,20 @@ typedef struct
 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35

 #endif

 

+#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0xFU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000F */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0xDU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000D */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#else

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0x1U << EXTI_EMR2_EM_Pos)                  /*!< 0x00000001 */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#endif

+

 /******************  Bit definition for EXTI_RTSR2 register ********************/

 #define EXTI_RTSR2_TR32_Pos        (0U)                                        

 #define EXTI_RTSR2_TR32_Msk        (0x1U << EXTI_RTSR2_TR32_Pos)               /*!< 0x00000001 */

@@ -7421,21 +7443,6 @@ typedef struct
 #define OB_WRP1_nWRP1_Msk    (0xFFU << OB_WRP1_nWRP1_Pos)                      /*!< 0xFF000000 */

 #define OB_WRP1_nWRP1        OB_WRP1_nWRP1_Msk                                 /*!< Flash memory write protection complemented option bytes */

 

-/******************  Bit definition for FLASH_WRP2 register  ******************/

-#define OB_WRP2_WRP2_Pos     (0U)                                              

-#define OB_WRP2_WRP2_Msk     (0xFFU << OB_WRP2_WRP2_Pos)                       /*!< 0x000000FF */

-#define OB_WRP2_WRP2         OB_WRP2_WRP2_Msk                                  /*!< Flash memory write protection option bytes */

-#define OB_WRP2_nWRP2_Pos    (8U)                                              

-#define OB_WRP2_nWRP2_Msk    (0xFFU << OB_WRP2_nWRP2_Pos)                      /*!< 0x0000FF00 */

-#define OB_WRP2_nWRP2        OB_WRP2_nWRP2_Msk                                 /*!< Flash memory write protection complemented option bytes */

-

-/******************  Bit definition for FLASH_WRP3 register  ******************/

-#define OB_WRP3_WRP3_Pos     (16U)                                             

-#define OB_WRP3_WRP3_Msk     (0xFFU << OB_WRP3_WRP3_Pos)                       /*!< 0x00FF0000 */

-#define OB_WRP3_WRP3         OB_WRP3_WRP3_Msk                                  /*!< Flash memory write protection option bytes */

-#define OB_WRP3_nWRP3_Pos    (24U)                                             

-#define OB_WRP3_nWRP3_Msk    (0xFFU << OB_WRP3_nWRP3_Pos)                      /*!< 0xFF000000 */

-#define OB_WRP3_nWRP3        OB_WRP3_nWRP3_Msk                                 /*!< Flash memory write protection complemented option bytes */

 

 /******************************************************************************/

 /*                                                                            */

@@ -9012,9 +9019,9 @@ typedef struct
 #define RTC_CR_COSEL_Pos             (19U)                                     

 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */

 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          

-#define RTC_CR_BCK_Pos               (18U)                                     

-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */

-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            

+#define RTC_CR_BKP_Pos               (18U)                                     

+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */

+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            

 #define RTC_CR_SUB1H_Pos             (17U)                                     

 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */

 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          

@@ -9064,6 +9071,11 @@ typedef struct
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */

 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */

 

+/* Legacy defines */

+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos

+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk

+#define RTC_CR_BCK                   RTC_CR_BKP

+

 /********************  Bits definition for RTC_ISR register  ******************/

 #define RTC_ISR_RECALPF_Pos          (16U)                                     

 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */

@@ -9605,12 +9617,6 @@ typedef struct
 #define SPI_SR_TXE_Pos              (1U)                                       

 #define SPI_SR_TXE_Msk              (0x1U << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */

 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */

-#define SPI_SR_CHSIDE_Pos           (2U)                                       

-#define SPI_SR_CHSIDE_Msk           (0x1U << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */

-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */

-#define SPI_SR_UDR_Pos              (3U)                                       

-#define SPI_SR_UDR_Msk              (0x1U << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */

-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */

 #define SPI_SR_CRCERR_Pos           (4U)                                       

 #define SPI_SR_CRCERR_Msk           (0x1U << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */

 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */

diff --git a/os/common/ext/ST/STM32F3xx/stm32f303xc.h b/os/common/ext/ST/STM32F3xx/stm32f303xc.h
index 35f1d3a2e..ec70ffd22 100644
--- a/os/common/ext/ST/STM32F3xx/stm32f303xc.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f303xc.h
@@ -2,8 +2,6 @@
   ******************************************************************************

   * @file    stm32f303xc.h

   * @author  MCD Application Team

-  * @version V2.3.1

-  * @date    16-December-2016

   * @brief   CMSIS STM32F303xC Devices Peripheral Access Layer Header File.

   *

   *          This file contains:

@@ -7911,6 +7909,10 @@ typedef struct
 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34

 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35

 

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0xFU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000F */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+

 /******************  Bit definition for EXTI_RTSR2 register ********************/

 #define EXTI_RTSR2_TR32_Pos        (0U)                                        

 #define EXTI_RTSR2_TR32_Msk        (0x1U << EXTI_RTSR2_TR32_Pos)               /*!< 0x00000001 */

@@ -9897,9 +9899,9 @@ typedef struct
 #define RTC_CR_COSEL_Pos             (19U)                                     

 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */

 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          

-#define RTC_CR_BCK_Pos               (18U)                                     

-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */

-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            

+#define RTC_CR_BKP_Pos               (18U)                                     

+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */

+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            

 #define RTC_CR_SUB1H_Pos             (17U)                                     

 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */

 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          

@@ -9949,6 +9951,11 @@ typedef struct
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */

 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */

 

+/* Legacy defines */

+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos

+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk

+#define RTC_CR_BCK                   RTC_CR_BKP

+

 /********************  Bits definition for RTC_ISR register  ******************/

 #define RTC_ISR_RECALPF_Pos          (16U)                                     

 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */

diff --git a/os/common/ext/ST/STM32F3xx/stm32f303xe.h b/os/common/ext/ST/STM32F3xx/stm32f303xe.h
index 44520de44..6e1348b11 100644
--- a/os/common/ext/ST/STM32F3xx/stm32f303xe.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f303xe.h
@@ -2,8 +2,6 @@
   ******************************************************************************

   * @file    stm32f303xe.h

   * @author  MCD Application Team

-  * @version V2.3.1

-  * @date    16-December-2016

   * @brief   CMSIS STM32F303xE Devices Peripheral Access Layer Header File.

   *

   *          This file contains:

@@ -7917,6 +7915,10 @@ typedef struct
 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34

 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35

 

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0xFU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000F */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+

 /******************  Bit definition for EXTI_RTSR2 register ********************/

 #define EXTI_RTSR2_TR32_Pos        (0U)                                        

 #define EXTI_RTSR2_TR32_Msk        (0x1U << EXTI_RTSR2_TR32_Pos)               /*!< 0x00000001 */

@@ -11562,9 +11564,9 @@ typedef struct
 #define RTC_CR_COSEL_Pos             (19U)                                     

 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */

 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          

-#define RTC_CR_BCK_Pos               (18U)                                     

-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */

-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            

+#define RTC_CR_BKP_Pos               (18U)                                     

+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */

+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            

 #define RTC_CR_SUB1H_Pos             (17U)                                     

 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */

 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          

@@ -11614,6 +11616,11 @@ typedef struct
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */

 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */

 

+/* Legacy defines */

+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos

+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk

+#define RTC_CR_BCK                   RTC_CR_BKP

+

 /********************  Bits definition for RTC_ISR register  ******************/

 #define RTC_ISR_RECALPF_Pos          (16U)                                     

 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */

diff --git a/os/common/ext/ST/STM32F3xx/stm32f318xx.h b/os/common/ext/ST/STM32F3xx/stm32f318xx.h
index f59f855eb..d732bb6d2 100644
--- a/os/common/ext/ST/STM32F3xx/stm32f318xx.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f318xx.h
@@ -2,8 +2,6 @@
   ******************************************************************************

   * @file    stm32f318xx.h

   * @author  MCD Application Team

-  * @version V2.3.1

-  * @date    16-December-2016

   * @brief   CMSIS STM32F318xx Devices Peripheral Access Layer Header File.

   *

   *          This file contains:

@@ -3540,9 +3538,19 @@ typedef struct
 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35

 #endif

 

+#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)

 #define EXTI_IMR2_IM_Pos           (0U)                                        

 #define EXTI_IMR2_IM_Msk           (0xFU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000F */

 #define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)

+#define EXTI_IMR2_IM_Pos           (0U)                                        

+#define EXTI_IMR2_IM_Msk           (0xDU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000D */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#else

+#define EXTI_IMR2_IM_Pos           (0U)                                        

+#define EXTI_IMR2_IM_Msk           (0x1U << EXTI_IMR2_IM_Pos)                  /*!< 0x00000001 */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#endif

 

 /*******************  Bit definition for EXTI_EMR2 ****************************/

 #define EXTI_EMR2_MR32_Pos         (0U)                                        

@@ -3561,6 +3569,20 @@ typedef struct
 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35

 #endif

 

+#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0xFU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000F */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0xDU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000D */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#else

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0x1U << EXTI_EMR2_EM_Pos)                  /*!< 0x00000001 */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#endif

+

 /******************  Bit definition for EXTI_RTSR2 register ********************/

 #define EXTI_RTSR2_TR32_Pos        (0U)                                        

 #define EXTI_RTSR2_TR32_Msk        (0x1U << EXTI_RTSR2_TR32_Pos)               /*!< 0x00000001 */

@@ -5415,9 +5437,9 @@ typedef struct
 #define RTC_CR_COSEL_Pos             (19U)                                     

 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */

 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          

-#define RTC_CR_BCK_Pos               (18U)                                     

-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */

-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            

+#define RTC_CR_BKP_Pos               (18U)                                     

+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */

+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            

 #define RTC_CR_SUB1H_Pos             (17U)                                     

 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */

 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          

@@ -5467,6 +5489,11 @@ typedef struct
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */

 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */

 

+/* Legacy defines */

+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos

+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk

+#define RTC_CR_BCK                   RTC_CR_BKP

+

 /********************  Bits definition for RTC_ISR register  ******************/

 #define RTC_ISR_RECALPF_Pos          (16U)                                     

 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */

diff --git a/os/common/ext/ST/STM32F3xx/stm32f328xx.h b/os/common/ext/ST/STM32F3xx/stm32f328xx.h
index 768c7fab0..a743cc377 100644
--- a/os/common/ext/ST/STM32F3xx/stm32f328xx.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f328xx.h
@@ -2,8 +2,6 @@
   ******************************************************************************

   * @file    stm32f328xx.h

   * @author  MCD Application Team

-  * @version V2.3.1

-  * @date    16-December-2016

   * @brief   CMSIS STM32F328xx Devices Peripheral Access Layer Header File.

   *

   *          This file contains:

@@ -7150,9 +7148,19 @@ typedef struct
 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35

 #endif

 

+#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)

 #define EXTI_IMR2_IM_Pos           (0U)                                        

 #define EXTI_IMR2_IM_Msk           (0xFU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000F */

 #define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)

+#define EXTI_IMR2_IM_Pos           (0U)                                        

+#define EXTI_IMR2_IM_Msk           (0xDU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000D */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#else

+#define EXTI_IMR2_IM_Pos           (0U)                                        

+#define EXTI_IMR2_IM_Msk           (0x1U << EXTI_IMR2_IM_Pos)                  /*!< 0x00000001 */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#endif

 

 /*******************  Bit definition for EXTI_EMR2 ****************************/

 #define EXTI_EMR2_MR32_Pos         (0U)                                        

@@ -7171,6 +7179,20 @@ typedef struct
 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35

 #endif

 

+#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0xFU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000F */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0xDU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000D */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#else

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0x1U << EXTI_EMR2_EM_Pos)                  /*!< 0x00000001 */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#endif

+

 /******************  Bit definition for EXTI_RTSR2 register ********************/

 #define EXTI_RTSR2_TR32_Pos        (0U)                                        

 #define EXTI_RTSR2_TR32_Msk        (0x1U << EXTI_RTSR2_TR32_Pos)               /*!< 0x00000001 */

@@ -7420,21 +7442,6 @@ typedef struct
 #define OB_WRP1_nWRP1_Msk    (0xFFU << OB_WRP1_nWRP1_Pos)                      /*!< 0xFF000000 */

 #define OB_WRP1_nWRP1        OB_WRP1_nWRP1_Msk                                 /*!< Flash memory write protection complemented option bytes */

 

-/******************  Bit definition for FLASH_WRP2 register  ******************/

-#define OB_WRP2_WRP2_Pos     (0U)                                              

-#define OB_WRP2_WRP2_Msk     (0xFFU << OB_WRP2_WRP2_Pos)                       /*!< 0x000000FF */

-#define OB_WRP2_WRP2         OB_WRP2_WRP2_Msk                                  /*!< Flash memory write protection option bytes */

-#define OB_WRP2_nWRP2_Pos    (8U)                                              

-#define OB_WRP2_nWRP2_Msk    (0xFFU << OB_WRP2_nWRP2_Pos)                      /*!< 0x0000FF00 */

-#define OB_WRP2_nWRP2        OB_WRP2_nWRP2_Msk                                 /*!< Flash memory write protection complemented option bytes */

-

-/******************  Bit definition for FLASH_WRP3 register  ******************/

-#define OB_WRP3_WRP3_Pos     (16U)                                             

-#define OB_WRP3_WRP3_Msk     (0xFFU << OB_WRP3_WRP3_Pos)                       /*!< 0x00FF0000 */

-#define OB_WRP3_WRP3         OB_WRP3_WRP3_Msk                                  /*!< Flash memory write protection option bytes */

-#define OB_WRP3_nWRP3_Pos    (24U)                                             

-#define OB_WRP3_nWRP3_Msk    (0xFFU << OB_WRP3_nWRP3_Pos)                      /*!< 0xFF000000 */

-#define OB_WRP3_nWRP3        OB_WRP3_nWRP3_Msk                                 /*!< Flash memory write protection complemented option bytes */

 

 /******************************************************************************/

 /*                                                                            */

@@ -8985,9 +8992,9 @@ typedef struct
 #define RTC_CR_COSEL_Pos             (19U)                                     

 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */

 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          

-#define RTC_CR_BCK_Pos               (18U)                                     

-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */

-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            

+#define RTC_CR_BKP_Pos               (18U)                                     

+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */

+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            

 #define RTC_CR_SUB1H_Pos             (17U)                                     

 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */

 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          

@@ -9037,6 +9044,11 @@ typedef struct
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */

 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */

 

+/* Legacy defines */

+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos

+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk

+#define RTC_CR_BCK                   RTC_CR_BKP

+

 /********************  Bits definition for RTC_ISR register  ******************/

 #define RTC_ISR_RECALPF_Pos          (16U)                                     

 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */

@@ -9578,12 +9590,6 @@ typedef struct
 #define SPI_SR_TXE_Pos              (1U)                                       

 #define SPI_SR_TXE_Msk              (0x1U << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */

 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */

-#define SPI_SR_CHSIDE_Pos           (2U)                                       

-#define SPI_SR_CHSIDE_Msk           (0x1U << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */

-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */

-#define SPI_SR_UDR_Pos              (3U)                                       

-#define SPI_SR_UDR_Msk              (0x1U << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */

-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */

 #define SPI_SR_CRCERR_Pos           (4U)                                       

 #define SPI_SR_CRCERR_Msk           (0x1U << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */

 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */

@@ -9966,15 +9972,6 @@ typedef struct
 #define SYSCFG_CFGR3_ADC2_DMA_RMP                SYSCFG_CFGR3_ADC2_DMA_RMP_Msk /*!< ADC2 DMA remap */

 #define SYSCFG_CFGR3_ADC2_DMA_RMP_0              (0x1U << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos) /*!< 0x00000100 */

 #define SYSCFG_CFGR3_ADC2_DMA_RMP_1              (0x2U << SYSCFG_CFGR3_ADC2_DMA_RMP_Pos) /*!< 0x00000200 */

-#define SYSCFG_CFGR3_TRIGGER_RMP_Pos             (16U)                         

-#define SYSCFG_CFGR3_TRIGGER_RMP_Msk             (0x3U << SYSCFG_CFGR3_TRIGGER_RMP_Pos) /*!< 0x00030000 */

-#define SYSCFG_CFGR3_TRIGGER_RMP                 SYSCFG_CFGR3_TRIGGER_RMP_Msk  /*!< Trigger remap mask */

-#define SYSCFG_CFGR3_DAC1_TRG3_RMP_Pos           (16U)                         

-#define SYSCFG_CFGR3_DAC1_TRG3_RMP_Msk           (0x1U << SYSCFG_CFGR3_DAC1_TRG3_RMP_Pos) /*!< 0x00010000 */

-#define SYSCFG_CFGR3_DAC1_TRG3_RMP               SYSCFG_CFGR3_DAC1_TRG3_RMP_Msk /*!< DAC1 TRG3 remap */

-#define SYSCFG_CFGR3_DAC1_TRG5_RMP_Pos           (17U)                         

-#define SYSCFG_CFGR3_DAC1_TRG5_RMP_Msk           (0x1U << SYSCFG_CFGR3_DAC1_TRG5_RMP_Pos) /*!< 0x00020000 */

-#define SYSCFG_CFGR3_DAC1_TRG5_RMP               SYSCFG_CFGR3_DAC1_TRG5_RMP_Msk /*!< DAC1 TRG5 remap */

 

 /******************************************************************************/

 /*                                                                            */

diff --git a/os/common/ext/ST/STM32F3xx/stm32f334x8.h b/os/common/ext/ST/STM32F3xx/stm32f334x8.h
index cf075c5c3..4101bac42 100644
--- a/os/common/ext/ST/STM32F3xx/stm32f334x8.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f334x8.h
@@ -2,8 +2,6 @@
   ******************************************************************************

   * @file    stm32f334x8.h

   * @author  MCD Application Team

-  * @version V2.3.1

-  * @date    16-December-2016

   * @brief   CMSIS STM32F334x8 Devices Peripheral Access Layer Header File.

   *

   *          This file contains:

@@ -7339,9 +7337,19 @@ typedef struct
 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35

 #endif

 

+#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)

+#define EXTI_IMR2_IM_Pos           (0U)                                        

+#define EXTI_IMR2_IM_Msk           (0xFU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000F */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)

+#define EXTI_IMR2_IM_Pos           (0U)                                        

+#define EXTI_IMR2_IM_Msk           (0xDU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000D */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#else

 #define EXTI_IMR2_IM_Pos           (0U)                                        

 #define EXTI_IMR2_IM_Msk           (0x1U << EXTI_IMR2_IM_Pos)                  /*!< 0x00000001 */

 #define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            

+#endif

 

 /*******************  Bit definition for EXTI_EMR2 ****************************/

 #define EXTI_EMR2_MR32_Pos         (0U)                                        

@@ -7360,6 +7368,20 @@ typedef struct
 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35

 #endif

 

+#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0xFU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000F */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0xDU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000D */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#else

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0x1U << EXTI_EMR2_EM_Pos)                  /*!< 0x00000001 */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+#endif

+

 /******************  Bit definition for EXTI_RTSR2 register ********************/

 #define EXTI_RTSR2_TR32_Pos        (0U)                                        

 #define EXTI_RTSR2_TR32_Msk        (0x1U << EXTI_RTSR2_TR32_Pos)               /*!< 0x00000001 */

@@ -7609,21 +7631,6 @@ typedef struct
 #define OB_WRP1_nWRP1_Msk    (0xFFU << OB_WRP1_nWRP1_Pos)                      /*!< 0xFF000000 */

 #define OB_WRP1_nWRP1        OB_WRP1_nWRP1_Msk                                 /*!< Flash memory write protection complemented option bytes */

 

-/******************  Bit definition for FLASH_WRP2 register  ******************/

-#define OB_WRP2_WRP2_Pos     (0U)                                              

-#define OB_WRP2_WRP2_Msk     (0xFFU << OB_WRP2_WRP2_Pos)                       /*!< 0x000000FF */

-#define OB_WRP2_WRP2         OB_WRP2_WRP2_Msk                                  /*!< Flash memory write protection option bytes */

-#define OB_WRP2_nWRP2_Pos    (8U)                                              

-#define OB_WRP2_nWRP2_Msk    (0xFFU << OB_WRP2_nWRP2_Pos)                      /*!< 0x0000FF00 */

-#define OB_WRP2_nWRP2        OB_WRP2_nWRP2_Msk                                 /*!< Flash memory write protection complemented option bytes */

-

-/******************  Bit definition for FLASH_WRP3 register  ******************/

-#define OB_WRP3_WRP3_Pos     (16U)                                             

-#define OB_WRP3_WRP3_Msk     (0xFFU << OB_WRP3_WRP3_Pos)                       /*!< 0x00FF0000 */

-#define OB_WRP3_WRP3         OB_WRP3_WRP3_Msk                                  /*!< Flash memory write protection option bytes */

-#define OB_WRP3_nWRP3_Pos    (24U)                                             

-#define OB_WRP3_nWRP3_Msk    (0xFFU << OB_WRP3_nWRP3_Pos)                      /*!< 0xFF000000 */

-#define OB_WRP3_nWRP3        OB_WRP3_nWRP3_Msk                                 /*!< Flash memory write protection complemented option bytes */

 

 /******************************************************************************/

 /*                                                                            */

@@ -11958,9 +11965,9 @@ typedef struct
 #define RTC_CR_COSEL_Pos             (19U)                                     

 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */

 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          

-#define RTC_CR_BCK_Pos               (18U)                                     

-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */

-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            

+#define RTC_CR_BKP_Pos               (18U)                                     

+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */

+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            

 #define RTC_CR_SUB1H_Pos             (17U)                                     

 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */

 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          

@@ -12010,6 +12017,11 @@ typedef struct
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */

 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */

 

+/* Legacy defines */

+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos

+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk

+#define RTC_CR_BCK                   RTC_CR_BKP

+

 /********************  Bits definition for RTC_ISR register  ******************/

 #define RTC_ISR_RECALPF_Pos          (16U)                                     

 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */

@@ -12551,12 +12563,6 @@ typedef struct
 #define SPI_SR_TXE_Pos              (1U)                                       

 #define SPI_SR_TXE_Msk              (0x1U << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */

 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */

-#define SPI_SR_CHSIDE_Pos           (2U)                                       

-#define SPI_SR_CHSIDE_Msk           (0x1U << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */

-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */

-#define SPI_SR_UDR_Pos              (3U)                                       

-#define SPI_SR_UDR_Msk              (0x1U << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */

-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */

 #define SPI_SR_CRCERR_Pos           (4U)                                       

 #define SPI_SR_CRCERR_Msk           (0x1U << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */

 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */

diff --git a/os/common/ext/ST/STM32F3xx/stm32f358xx.h b/os/common/ext/ST/STM32F3xx/stm32f358xx.h
index b33054fd5..b2518d800 100644
--- a/os/common/ext/ST/STM32F3xx/stm32f358xx.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f358xx.h
@@ -2,8 +2,6 @@
   ******************************************************************************

   * @file    stm32f358xx.h

   * @author  MCD Application Team

-  * @version V2.3.1

-  * @date    16-December-2016

   * @brief   CMSIS STM32F358xx Devices Peripheral Access Layer Header File.

   *

   *          This file contains:

@@ -7863,6 +7861,10 @@ typedef struct
 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34

 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35

 

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0xFU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000F */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+

 /******************  Bit definition for EXTI_RTSR2 register ********************/

 #define EXTI_RTSR2_TR32_Pos        (0U)                                        

 #define EXTI_RTSR2_TR32_Msk        (0x1U << EXTI_RTSR2_TR32_Pos)               /*!< 0x00000001 */

@@ -9806,9 +9808,9 @@ typedef struct
 #define RTC_CR_COSEL_Pos             (19U)                                     

 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */

 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          

-#define RTC_CR_BCK_Pos               (18U)                                     

-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */

-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            

+#define RTC_CR_BKP_Pos               (18U)                                     

+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */

+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            

 #define RTC_CR_SUB1H_Pos             (17U)                                     

 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */

 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          

@@ -9858,6 +9860,11 @@ typedef struct
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */

 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */

 

+/* Legacy defines */

+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos

+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk

+#define RTC_CR_BCK                   RTC_CR_BKP

+

 /********************  Bits definition for RTC_ISR register  ******************/

 #define RTC_ISR_RECALPF_Pos          (16U)                                     

 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */

diff --git a/os/common/ext/ST/STM32F3xx/stm32f373xc.h b/os/common/ext/ST/STM32F3xx/stm32f373xc.h
index 4a5545a70..47025d87d 100644
--- a/os/common/ext/ST/STM32F3xx/stm32f373xc.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f373xc.h
@@ -2,8 +2,6 @@
   ******************************************************************************

   * @file    stm32f373xc.h

   * @author  MCD Application Team

-  * @version V2.3.1

-  * @date    16-December-2016

   * @brief   CMSIS STM32F373xC Devices Peripheral Access Layer Header File.

   *

   *          This file contains:

@@ -8374,9 +8372,9 @@ typedef struct
 #define RTC_CR_COSEL_Pos             (19U)                                     

 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */

 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          

-#define RTC_CR_BCK_Pos               (18U)                                     

-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */

-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            

+#define RTC_CR_BKP_Pos               (18U)                                     

+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */

+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            

 #define RTC_CR_SUB1H_Pos             (17U)                                     

 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */

 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          

@@ -8426,6 +8424,11 @@ typedef struct
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */

 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */

 

+/* Legacy defines */

+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos

+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk

+#define RTC_CR_BCK                   RTC_CR_BKP

+

 /********************  Bits definition for RTC_ISR register  ******************/

 #define RTC_ISR_RECALPF_Pos          (16U)                                     

 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */

diff --git a/os/common/ext/ST/STM32F3xx/stm32f378xx.h b/os/common/ext/ST/STM32F3xx/stm32f378xx.h
index 35e2c1ade..fdede2a04 100644
--- a/os/common/ext/ST/STM32F3xx/stm32f378xx.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f378xx.h
@@ -2,8 +2,6 @@
   ******************************************************************************

   * @file    stm32f378xx.h

   * @author  MCD Application Team

-  * @version V2.3.1

-  * @date    16-December-2016

   * @brief   CMSIS STM32F378xx Devices Peripheral Access Layer Header File.

   *

   *          This file contains:

@@ -8287,9 +8285,9 @@ typedef struct
 #define RTC_CR_COSEL_Pos             (19U)                                     

 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */

 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          

-#define RTC_CR_BCK_Pos               (18U)                                     

-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */

-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            

+#define RTC_CR_BKP_Pos               (18U)                                     

+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */

+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            

 #define RTC_CR_SUB1H_Pos             (17U)                                     

 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */

 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          

@@ -8339,6 +8337,11 @@ typedef struct
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */

 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */

 

+/* Legacy defines */

+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos

+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk

+#define RTC_CR_BCK                   RTC_CR_BKP

+

 /********************  Bits definition for RTC_ISR register  ******************/

 #define RTC_ISR_RECALPF_Pos          (16U)                                     

 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */

diff --git a/os/common/ext/ST/STM32F3xx/stm32f398xx.h b/os/common/ext/ST/STM32F3xx/stm32f398xx.h
index 295d3c5a9..5972d1fa4 100644
--- a/os/common/ext/ST/STM32F3xx/stm32f398xx.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f398xx.h
@@ -2,8 +2,6 @@
   ******************************************************************************

   * @file    stm32f398xx.h

   * @author  MCD Application Team

-  * @version V2.3.1

-  * @date    16-December-2016

   * @brief   CMSIS STM32F398xx Devices Peripheral Access Layer Header File.

   *

   *          This file contains:

@@ -7867,6 +7865,10 @@ typedef struct
 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34

 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35

 

+#define EXTI_EMR2_EM_Pos           (0U)                                        

+#define EXTI_EMR2_EM_Msk           (0xFU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000F */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            

+

 /******************  Bit definition for EXTI_RTSR2 register ********************/

 #define EXTI_RTSR2_TR32_Pos        (0U)                                        

 #define EXTI_RTSR2_TR32_Msk        (0x1U << EXTI_RTSR2_TR32_Pos)               /*!< 0x00000001 */

@@ -11469,9 +11471,9 @@ typedef struct
 #define RTC_CR_COSEL_Pos             (19U)                                     

 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */

 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          

-#define RTC_CR_BCK_Pos               (18U)                                     

-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */

-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            

+#define RTC_CR_BKP_Pos               (18U)                                     

+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */

+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            

 #define RTC_CR_SUB1H_Pos             (17U)                                     

 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */

 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          

@@ -11521,6 +11523,11 @@ typedef struct
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */

 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */

 

+/* Legacy defines */

+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos

+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk

+#define RTC_CR_BCK                   RTC_CR_BKP

+

 /********************  Bits definition for RTC_ISR register  ******************/

 #define RTC_ISR_RECALPF_Pos          (16U)                                     

 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */

diff --git a/os/common/ext/ST/STM32F3xx/stm32f3xx.h b/os/common/ext/ST/STM32F3xx/stm32f3xx.h
index bca50c7d1..012868e7c 100644
--- a/os/common/ext/ST/STM32F3xx/stm32f3xx.h
+++ b/os/common/ext/ST/STM32F3xx/stm32f3xx.h
@@ -2,8 +2,6 @@
   ******************************************************************************

   * @file    stm32f3xx.h

   * @author  MCD Application Team

-  * @version V2.3.1

-  * @date    16-December-2016

   * @brief   CMSIS STM32F3xx Device Peripheral Access Layer Header File.           

   *            

   *          The file is the unique include file that the application programmer

@@ -121,11 +119,11 @@
 #endif /* USE_HAL_DRIVER */

 

 /**

-  * @brief CMSIS Device version number V2.3.1

+  * @brief CMSIS Device version number V2.3.2

   */

 #define __STM32F3_CMSIS_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  

 #define __STM32F3_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */

-#define __STM32F3_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */

+#define __STM32F3_CMSIS_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */

 #define __STM32F3_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */

 #define __STM32F3_CMSIS_VERSION        ((__STM32F3_CMSIS_VERSION_MAIN     << 24)\

                                        |(__STM32F3_CMSIS_VERSION_SUB1 << 16)\

diff --git a/os/common/ext/ST/STM32F3xx/system_stm32f3xx.h b/os/common/ext/ST/STM32F3xx/system_stm32f3xx.h
index d17cd7dc7..3670bcffb 100644
--- a/os/common/ext/ST/STM32F3xx/system_stm32f3xx.h
+++ b/os/common/ext/ST/STM32F3xx/system_stm32f3xx.h
@@ -2,8 +2,6 @@
   ******************************************************************************

   * @file    system_stm32f3xx.h

   * @author  MCD Application Team

-  * @version V2.3.1

-  * @date    16-December-2016

   * @brief   CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.  

   ******************************************************************************

   * @attention