diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2008-03-19 15:17:17 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2008-03-19 15:17:17 +0000 |
| commit | d63f9c27be96d7b947b18b82d4398c4aa95d71ba (patch) | |
| tree | 9616bbbc197b53116aba5ce6ab32b562dd40f278 /demos | |
| parent | 7eb7630d937ea87275bafee866e9fd6aaea61902 (diff) | |
| download | ChibiOS-d63f9c27be96d7b947b18b82d4398c4aa95d71ba.tar.gz ChibiOS-d63f9c27be96d7b947b18b82d4398c4aa95d71ba.tar.bz2 ChibiOS-d63f9c27be96d7b947b18b82d4398c4aa95d71ba.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@242 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'demos')
| -rw-r--r-- | demos/ARMCM3-STM32F103-GCC/readme.txt | 27 | ||||
| -rw-r--r-- | demos/ARMCM3-STM32F103-GCC/stm32lib/cortexm3_macro.h | 51 | ||||
| -rw-r--r-- | demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h | 142 | ||||
| -rw-r--r-- | demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_map.h | 857 | ||||
| -rw-r--r-- | demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_type.h | 80 |
5 files changed, 1157 insertions, 0 deletions
diff --git a/demos/ARMCM3-STM32F103-GCC/readme.txt b/demos/ARMCM3-STM32F103-GCC/readme.txt new file mode 100644 index 000000000..33c94445b --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/readme.txt @@ -0,0 +1,27 @@ +*****************************************************************************
+** ChibiOS/RT port for ARM-Cortex-M3 STM32F103. **
+*****************************************************************************
+
+** TARGET **
+
+The demo will on an Olimex STM32-P103 board.
+
+** The Demo **
+
+Not complete yet.
+
+** Build Procedure **
+
+The demo was built using the YAGARTO toolchain but any toolchain based on GCC
+and GNU userspace programs will work.
+
+** Notes **
+
+Some files used by the demo are not part of ChibiOS/RT but are copyright of
+ST Microelectronics and are licensed under a different license, see the header
+present in all the source files under ./demos/ARMCM3-STM32F103/stm32lib for
+details.
+Also note that not all the files present in the ST library are distribuited
+with ChibiOS/RT, you can find the whole library on the ST web site:
+
+ http://www.st.com
diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/cortexm3_macro.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/cortexm3_macro.h new file mode 100644 index 000000000..822d01910 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/cortexm3_macro.h @@ -0,0 +1,51 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : cortexm3_macro.h
+* Author : MCD Application Team
+* Version : V1.0
+* Date : 10/08/2007
+* Description : Header file for cortexm3_macro.s.
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __CORTEXM3_MACRO_H
+#define __CORTEXM3_MACRO_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_type.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void __WFI(void);
+void __WFE(void);
+void __SEV(void);
+void __ISB(void);
+void __DSB(void);
+void __DMB(void);
+void __SVC(void);
+u32 __MRS_CONTROL(void);
+void __MSR_CONTROL(u32 Control);
+u32 __MRS_PSP(void);
+void __MSR_PSP(u32 TopOfProcessStack);
+u32 __MRS_MSP(void);
+void __MSR_MSP(u32 TopOfMainStack);
+void __SETPRIMASK(void);
+void __RESETPRIMASK(void);
+void __SETFAULTMASK(void);
+void __RESETFAULTMASK(void);
+void __BASEPRICONFIG(u32 NewPriority);
+u32 __GetBASEPRI(void);
+u16 __REV_HalfWord(u16 Data);
+u32 __REV_Word(u32 Data);
+
+#endif /* __CORTEXM3_MACRO_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h new file mode 100644 index 000000000..59ae65d01 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h @@ -0,0 +1,142 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_conf.h
+* Author : MCD Application Team
+* Version : V1.0
+* Date : 10/08/2007
+* Description : Library configuration file.
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_type.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to compile the library in DEBUG mode, this will expanse
+ the "assert_param" macro in the firmware library code (see "Exported macro"
+ section below) */
+/* #define DEBUG 1*/
+
+/* Comment the line below to disable the specific peripheral inclusion */
+/************************************* ADC ************************************/
+//#define _ADC
+//#define _ADC1
+//#define _ADC2
+
+/************************************* BKP ************************************/
+//#define _BKP
+
+/************************************* CAN ************************************/
+//#define _CAN
+
+/************************************* DMA ************************************/
+//#define _DMA
+//#define _DMA_Channel1
+//#define _DMA_Channel2
+//#define _DMA_Channel3
+//#define _DMA_Channel4
+//#define _DMA_Channel5
+//#define _DMA_Channel6
+//#define _DMA_Channel7
+
+/************************************* EXTI ***********************************/
+//#define _EXTI
+
+/************************************* FLASH and Option Bytes *****************/
+#define _FLASH
+/* Uncomment the line below to enable FLASH program/erase/protections functions,
+ otherwise only FLASH configuration (latency, prefetch, half cycle) functions
+ are enabled */
+/* #define _FLASH_PROG */
+
+/************************************* GPIO ***********************************/
+//#define _GPIO
+//#define _GPIOA
+//#define _GPIOB
+//#define _GPIOC
+//#define _GPIOD
+//#define _GPIOE
+//#define _AFIO
+
+/************************************* I2C ************************************/
+//#define _I2C
+//#define _I2C1
+//#define _I2C2
+
+/************************************* IWDG ***********************************/
+//#define _IWDG
+
+/************************************* NVIC ***********************************/
+#define _NVIC
+
+/************************************* PWR ************************************/
+//#define _PWR
+
+/************************************* RCC ************************************/
+#define _RCC
+
+/************************************* RTC ************************************/
+//#define _RTC
+
+/************************************* SPI ************************************/
+//#define _SPI
+//#define _SPI1
+//#define _SPI2
+
+/************************************* SysTick ********************************/
+//#define _SysTick
+
+/************************************* TIM1 ***********************************/
+//#define _TIM1
+
+/************************************* TIM ************************************/
+//#define _TIM
+//#define _TIM2
+//#define _TIM3
+//#define _TIM4
+
+/************************************* USART **********************************/
+//#define _USART
+//#define _USART1
+//#define _USART2
+//#define _USART3
+
+/************************************* WWDG ***********************************/
+//#define _WWDG
+
+/* In the following line adjust the value of External High Speed oscillator (HSE)
+ used in your application */
+#define HSE_Value ((u32)8000000) /* Value of the External oscillator in Hz*/
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef DEBUG
+/*******************************************************************************
+* Macro Name : assert_param
+* Description : The assert_param macro is used for function's parameters check.
+* It is used only if the library is compiled in DEBUG mode.
+* Input : - expr: If expr is false, it calls assert_failed function
+* which reports the name of the source file and the source
+* line number of the call that failed.
+* If expr is true, it returns no value.
+* Return : None
+*******************************************************************************/
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(u8* file, u32 line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* DEBUG */
+
+#endif /* __STM32F10x_CONF_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_map.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_map.h new file mode 100644 index 000000000..410d78a6a --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_map.h @@ -0,0 +1,857 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_map.h
+* Author : MCD Application Team
+* Version : V1.0
+* Date : 10/08/2007
+* Description : This file contains all the peripheral register's definitions
+* and memory mapping.
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_MAP_H
+#define __STM32F10x_MAP_H
+
+#ifndef EXT
+ #define EXT extern
+#endif /* EXT */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_conf.h"
+#include "stm32f10x_type.h"
+#include "cortexm3_macro.h"
+
+/* Exported types ------------------------------------------------------------*/
+/******************************************************************************/
+/* Peripheral registers structures */
+/******************************************************************************/
+
+/*------------------------ Analog to Digital Converter -----------------------*/
+typedef struct
+{
+ vu32 SR;
+ vu32 CR1;
+ vu32 CR2;
+ vu32 SMPR1;
+ vu32 SMPR2;
+ vu32 JOFR1;
+ vu32 JOFR2;
+ vu32 JOFR3;
+ vu32 JOFR4;
+ vu32 HTR;
+ vu32 LTR;
+ vu32 SQR1;
+ vu32 SQR2;
+ vu32 SQR3;
+ vu32 JSQR;
+ vu32 JDR1;
+ vu32 JDR2;
+ vu32 JDR3;
+ vu32 JDR4;
+ vu32 DR;
+} ADC_TypeDef;
+
+/*------------------------ Backup Registers ----------------------------------*/
+typedef struct
+{
+ u32 RESERVED0;
+ vu16 DR1;
+ u16 RESERVED1;
+ vu16 DR2;
+ u16 RESERVED2;
+ vu16 DR3;
+ u16 RESERVED3;
+ vu16 DR4;
+ u16 RESERVED4;
+ vu16 DR5;
+ u16 RESERVED5;
+ vu16 DR6;
+ u16 RESERVED6;
+ vu16 DR7;
+ u16 RESERVED7;
+ vu16 DR8;
+ u16 RESERVED8;
+ vu16 DR9;
+ u16 RESERVED9;
+ vu16 DR10;
+ u16 RESERVED10;
+ vu16 RTCCR;
+ u16 RESERVED11;
+ vu16 CR;
+ u16 RESERVED12;
+ vu16 CSR;
+ u16 RESERVED13;
+} BKP_TypeDef;
+
+/*------------------------ Controller Area Network ---------------------------*/
+typedef struct
+{
+ vu32 TIR;
+ vu32 TDTR;
+ vu32 TDLR;
+ vu32 TDHR;
+} CAN_TxMailBox_TypeDef;
+
+typedef struct
+{
+ vu32 RIR;
+ vu32 RDTR;
+ vu32 RDLR;
+ vu32 RDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+typedef struct
+{
+ vu32 FR0;
+ vu32 FR1;
+} CAN_FilterRegister_TypeDef;
+
+typedef struct
+{
+ vu32 MCR;
+ vu32 MSR;
+ vu32 TSR;
+ vu32 RF0R;
+ vu32 RF1R;
+ vu32 IER;
+ vu32 ESR;
+ vu32 BTR;
+ u32 RESERVED0[88];
+ CAN_TxMailBox_TypeDef sTxMailBox[3];
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+ u32 RESERVED1[12];
+ vu32 FMR;
+ vu32 FM0R;
+ u32 RESERVED2[1];
+ vu32 FS0R;
+ u32 RESERVED3[1];
+ vu32 FFA0R;
+ u32 RESERVED4[1];
+ vu32 FA0R;
+ u32 RESERVED5[8];
+ CAN_FilterRegister_TypeDef sFilterRegister[14];
+} CAN_TypeDef;
+
+/*------------------------ DMA Controller ------------------------------------*/
+typedef struct
+{
+ vu32 CCR;
+ vu32 CNDTR;
+ vu32 CPAR;
+ vu32 CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ vu32 ISR;
+ vu32 IFCR;
+} DMA_TypeDef;
+
+/*------------------------ External Interrupt/Event Controller ---------------*/
+typedef struct
+{
+ vu32 IMR;
+ vu32 EMR;
+ vu32 RTSR;
+ vu32 FTSR;
+ vu32 SWIER;
+ vu32 PR;
+} EXTI_TypeDef;
+
+/*------------------------ FLASH and Option Bytes Registers ------------------*/
+typedef struct
+{
+ vu32 ACR;
+ vu32 KEYR;
+ vu32 OPTKEYR;
+ vu32 SR;
+ vu32 CR;
+ vu32 AR;
+ vu32 RESERVED;
+ vu32 OBR;
+ vu32 WRPR;
+} FLASH_TypeDef;
+
+typedef struct
+{
+ vu16 RDP;
+ vu16 USER;
+ vu16 Data0;
+ vu16 Data1;
+ vu16 WRP0;
+ vu16 WRP1;
+ vu16 WRP2;
+ vu16 WRP3;
+} OB_TypeDef;
+
+/*------------------------ General Purpose and Alternate Function IO ---------*/
+typedef struct
+{
+ vu32 CRL;
+ vu32 CRH;
+ vu32 IDR;
+ vu32 ODR;
+ vu32 BSRR;
+ vu32 BRR;
+ vu32 LCKR;
+} GPIO_TypeDef;
+
+typedef struct
+{
+ vu32 EVCR;
+ vu32 MAPR;
+ vu32 EXTICR[4];
+} AFIO_TypeDef;
+
+/*------------------------ Inter-integrated Circuit Interface ----------------*/
+typedef struct
+{
+ vu16 CR1;
+ u16 RESERVED0;
+ vu16 CR2;
+ u16 RESERVED1;
+ vu16 OAR1;
+ u16 RESERVED2;
+ vu16 OAR2;
+ u16 RESERVED3;
+ vu16 DR;
+ u16 RESERVED4;
+ vu16 SR1;
+ u16 RESERVED5;
+ vu16 SR2;
+ u16 RESERVED6;
+ vu16 CCR;
+ u16 RESERVED7;
+ vu16 TRISE;
+ u16 RESERVED8;
+} I2C_TypeDef;
+
+/*------------------------ Independent WATCHDOG ------------------------------*/
+typedef struct
+{
+ vu32 KR;
+ vu32 PR;
+ vu32 RLR;
+ vu32 SR;
+} IWDG_TypeDef;
+
+/*------------------------ Nested Vectored Interrupt Controller --------------*/
+typedef struct
+{
+ vu32 ISER[2];
+ u32 RESERVED0[30];
+ vu32 ICER[2];
+ u32 RSERVED1[30];
+ vu32 ISPR[2];
+ u32 RESERVED2[30];
+ vu32 ICPR[2];
+ u32 RESERVED3[30];
+ vu32 IABR[2];
+ u32 RESERVED4[62];
+ vu32 IPR[11];
+} NVIC_TypeDef;
+
+typedef struct
+{
+ vuc32 CPUID;
+ vu32 ICSR;
+ vu32 VTOR;
+ vu32 AIRCR;
+ vu32 SCR;
+ vu32 CCR;
+ vu32 SHPR[3];
+ vu32 SHCSR;
+ vu32 CFSR;
+ vu32 HFSR;
+ vu32 DFSR;
+ vu32 MMFAR;
+ vu32 BFAR;
+ vu32 AFSR;
+} SCB_TypeDef;
+
+/*------------------------ Power Control -------------------------------------*/
+typedef struct
+{
+ vu32 CR;
+ vu32 CSR;
+} PWR_TypeDef;
+
+/*------------------------ Reset and Clock Control ---------------------------*/
+typedef struct
+{
+ vu32 CR;
+ vu32 CFGR;
+ vu32 CIR;
+ vu32 APB2RSTR;
+ vu32 APB1RSTR;
+ vu32 AHBENR;
+ vu32 APB2ENR;
+ vu32 APB1ENR;
+ vu32 BDCR;
+ vu32 CSR;
+} RCC_TypeDef;
+
+/*------------------------ Real-Time Clock -----------------------------------*/
+typedef struct
+{
+ vu16 CRH;
+ u16 RESERVED0;
+ vu16 CRL;
+ u16 RESERVED1;
+ vu16 PRLH;
+ u16 RESERVED2;
+ vu16 PRLL;
+ u16 RESERVED3;
+ vu16 DIVH;
+ u16 RESERVED4;
+ vu16 DIVL;
+ u16 RESERVED5;
+ vu16 CNTH;
+ u16 RESERVED6;
+ vu16 CNTL;
+ u16 RESERVED7;
+ vu16 ALRH;
+ u16 RESERVED8;
+ vu16 ALRL;
+ u16 RESERVED9;
+} RTC_TypeDef;
+
+/*------------------------ Serial Peripheral Interface -----------------------*/
+typedef struct
+{
+ vu16 CR1;
+ u16 RESERVED0;
+ vu16 CR2;
+ u16 RESERVED1;
+ vu16 SR;
+ u16 RESERVED2;
+ vu16 DR;
+ u16 RESERVED3;
+ vu16 CRCPR;
+ u16 RESERVED4;
+ vu16 RXCRCR;
+ u16 RESERVED5;
+ vu16 TXCRCR;
+ u16 RESERVED6;
+} SPI_TypeDef;
+
+/*------------------------ SystemTick ----------------------------------------*/
+typedef struct
+{
+ vu32 CTRL;
+ vu32 LOAD;
+ vu32 VAL;
+ vuc32 CALIB;
+} SysTick_TypeDef;
+
+/*------------------------ Advanced Control Timer ----------------------------*/
+typedef struct
+{
+ vu16 CR1;
+ u16 RESERVED0;
+ vu16 CR2;
+ u16 RESERVED1;
+ vu16 SMCR;
+ u16 RESERVED2;
+ vu16 DIER;
+ u16 RESERVED3;
+ vu16 SR;
+ u16 RESERVED4;
+ vu16 EGR;
+ u16 RESERVED5;
+ vu16 CCMR1;
+ u16 RESERVED6;
+ vu16 CCMR2;
+ u16 RESERVED7;
+ vu16 CCER;
+ u16 RESERVED8;
+ vu16 CNT;
+ u16 RESERVED9;
+ vu16 PSC;
+ u16 RESERVED10;
+ vu16 ARR;
+ u16 RESERVED11;
+ vu16 RCR;
+ u16 RESERVED12;
+ vu16 CCR1;
+ u16 RESERVED13;
+ vu16 CCR2;
+ u16 RESERVED14;
+ vu16 CCR3;
+ u16 RESERVED15;
+ vu16 CCR4;
+ u16 RESERVED16;
+ vu16 BDTR;
+ u16 RESERVED17;
+ vu16 DCR;
+ u16 RESERVED18;
+ vu16 DMAR;
+ u16 RESERVED19;
+} TIM1_TypeDef;
+
+/*------------------------ General Purpose Timer -----------------------------*/
+typedef struct
+{
+ vu16 CR1;
+ u16 RESERVED0;
+ vu16 CR2;
+ u16 RESERVED1;
+ vu16 SMCR;
+ u16 RESERVED2;
+ vu16 DIER;
+ u16 RESERVED3;
+ vu16 SR;
+ u16 RESERVED4;
+ vu16 EGR;
+ u16 RESERVED5;
+ vu16 CCMR1;
+ u16 RESERVED6;
+ vu16 CCMR2;
+ u16 RESERVED7;
+ vu16 CCER;
+ u16 RESERVED8;
+ vu16 CNT;
+ u16 RESERVED9;
+ vu16 PSC;
+ u16 RESERVED10;
+ vu16 ARR;
+ u16 RESERVED11[3];
+ vu16 CCR1;
+ u16 RESERVED12;
+ vu16 CCR2;
+ u16 RESERVED13;
+ vu16 CCR3;
+ u16 RESERVED14;
+ vu16 CCR4;
+ u16 RESERVED15[3];
+ vu16 DCR;
+ u16 RESERVED16;
+ vu16 DMAR;
+ u16 RESERVED17;
+} TIM_TypeDef;
+
+/*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/
+typedef struct
+{
+ vu16 SR;
+ u16 RESERVED0;
+ vu16 DR;
+ u16 RESERVED1;
+ vu16 BRR;
+ u16 RESERVED2;
+ vu16 CR1;
+ u16 RESERVED3;
+ vu16 CR2;
+ u16 RESERVED4;
+ vu16 CR3;
+ u16 RESERVED5;
+ vu16 GTPR;
+ u16 RESERVED6;
+} USART_TypeDef;
+
+/*------------------------ Window WATCHDOG -----------------------------------*/
+typedef struct
+{
+ vu32 CR;
+ vu32 CFR;
+ vu32 SR;
+} WWDG_TypeDef;
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Peripheral and SRAM base address in the alias region */
+#define PERIPH_BB_BASE ((u32)0x42000000)
+#define SRAM_BB_BASE ((u32)0x22000000)
+
+/* Peripheral and SRAM base address in the bit-band region */
+#define SRAM_BASE ((u32)0x20000000)
+#define PERIPH_BASE ((u32)0x40000000)
+
+/* Flash refisters base address */
+#define FLASH_BASE ((u32)0x40022000)
+/* Flash Option Bytes base address */
+#define OB_BASE ((u32)0x1FFFF800)
+
+/* Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define CAN_BASE (APB1PERIPH_BASE + 0x6400)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+
+#define DMA_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+
+/* System Control Space memory map */
+#define SCS_BASE ((u32)0xE000E000)
+
+#define SysTick_BASE (SCS_BASE + 0x0010)
+#define NVIC_BASE (SCS_BASE + 0x0100)
+#define SCB_BASE (SCS_BASE + 0x0D00)
+
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+
+/*------------------------ Non Debug Mode ------------------------------------*/
+#ifndef DEBUG
+#ifdef _TIM2
+ #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#endif /*_TIM2 */
+
+#ifdef _TIM3
+ #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#endif /*_TIM3 */
+
+#ifdef _TIM4
+ #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#endif /*_TIM4 */
+
+#ifdef _RTC
+ #define RTC ((RTC_TypeDef *) RTC_BASE)
+#endif /*_RTC */
+
+#ifdef _WWDG
+ #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#endif /*_WWDG */
+
+#ifdef _IWDG
+ #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#endif /*_IWDG */
+
+#ifdef _SPI2
+ #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#endif /*_SPI2 */
+
+#ifdef _USART2
+ #define USART2 ((USART_TypeDef *) USART2_BASE)
+#endif /*_USART2 */
+
+#ifdef _USART3
+ #define USART3 ((USART_TypeDef *) USART3_BASE)
+#endif /*_USART3 */
+
+#ifdef _I2C1
+ #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#endif /*_I2C1 */
+
+#ifdef _I2C2
+ #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#endif /*_I2C2 */
+
+#ifdef _CAN
+ #define CAN ((CAN_TypeDef *) CAN_BASE)
+#endif /*_CAN */
+
+#ifdef _BKP
+ #define BKP ((BKP_TypeDef *) BKP_BASE)
+#endif /*_BKP */
+
+#ifdef _PWR
+ #define PWR ((PWR_TypeDef *) PWR_BASE)
+#endif /*_PWR */
+
+#ifdef _AFIO
+ #define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#endif /*_AFIO */
+
+#ifdef _EXTI
+ #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#endif /*_EXTI */
+
+#ifdef _GPIOA
+ #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#endif /*_GPIOA */
+
+#ifdef _GPIOB
+ #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#endif /*_GPIOB */
+
+#ifdef _GPIOC
+ #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#endif /*_GPIOC */
+
+#ifdef _GPIOD
+ #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#endif /*_GPIOD */
+
+#ifdef _GPIOE
+ #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#endif /*_GPIOE */
+
+#ifdef _ADC1
+ #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#endif /*_ADC1 */
+
+#ifdef _ADC2
+ #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#endif /*_ADC2 */
+
+#ifdef _TIM1
+ #define TIM1 ((TIM1_TypeDef *) TIM1_BASE)
+#endif /*_TIM1 */
+
+#ifdef _SPI1
+ #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#endif /*_SPI1 */
+
+#ifdef _USART1
+ #define USART1 ((USART_TypeDef *) USART1_BASE)
+#endif /*_USART1 */
+
+#ifdef _DMA
+ #define DMA ((DMA_TypeDef *) DMA_BASE)
+#endif /*_DMA */
+
+#ifdef _DMA_Channel1
+ #define DMA_Channel1 ((DMA_Channel_TypeDef *) DMA_Channel1_BASE)
+#endif /*_DMA_Channel1 */
+
+#ifdef _DMA_Channel2
+ #define DMA_Channel2 ((DMA_Channel_TypeDef *) DMA_Channel2_BASE)
+#endif /*_DMA_Channel2 */
+
+#ifdef _DMA_Channel3
+ #define DMA_Channel3 ((DMA_Channel_TypeDef *) DMA_Channel3_BASE)
+#endif /*_DMA_Channel3 */
+
+#ifdef _DMA_Channel4
+ #define DMA_Channel4 ((DMA_Channel_TypeDef *) DMA_Channel4_BASE)
+#endif /*_DMA_Channel4 */
+
+#ifdef _DMA_Channel5
+ #define DMA_Channel5 ((DMA_Channel_TypeDef *) DMA_Channel5_BASE)
+#endif /*_DMA_Channel5 */
+
+#ifdef _DMA_Channel6
+ #define DMA_Channel6 ((DMA_Channel_TypeDef *) DMA_Channel6_BASE)
+#endif /*_DMA_Channel6 */
+
+#ifdef _DMA_Channel7
+ #define DMA_Channel7 ((DMA_Channel_TypeDef *) DMA_Channel7_BASE)
+#endif /*_DMA_Channel7 */
+
+#ifdef _FLASH
+ #define FLASH ((FLASH_TypeDef *) FLASH_BASE)
+ #define OB ((OB_TypeDef *) OB_BASE)
+#endif /*_FLASH */
+
+#ifdef _RCC
+ #define RCC ((RCC_TypeDef *) RCC_BASE)
+#endif /*_RCC */
+
+#ifdef _SysTick
+ #define SysTick ((SysTick_TypeDef *) SysTick_BASE)
+#endif /*_SysTick */
+
+#ifdef _NVIC
+ #define NVIC ((NVIC_TypeDef *) NVIC_BASE)
+ #define SCB ((SCB_TypeDef *) SCB_BASE)
+#endif /*_NVIC */
+
+/*------------------------ Debug Mode ----------------------------------------*/
+#else /* DEBUG */
+#ifdef _TIM2
+ EXT TIM_TypeDef *TIM2;
+#endif /*_TIM2 */
+
+#ifdef _TIM3
+ EXT TIM_TypeDef *TIM3;
+#endif /*_TIM3 */
+
+#ifdef _TIM4
+ EXT TIM_TypeDef *TIM4;
+#endif /*_TIM4 */
+
+#ifdef _RTC
+ EXT RTC_TypeDef *RTC;
+#endif /*_RTC */
+
+#ifdef _WWDG
+ EXT WWDG_TypeDef *WWDG;
+#endif /*_WWDG */
+
+#ifdef _IWDG
+ EXT IWDG_TypeDef *IWDG;
+#endif /*_IWDG */
+
+#ifdef _SPI2
+ EXT SPI_TypeDef *SPI2;
+#endif /*_SPI2 */
+
+#ifdef _USART2
+ EXT USART_TypeDef *USART2;
+#endif /*_USART2 */
+
+#ifdef _USART3
+ EXT USART_TypeDef *USART3;
+#endif /*_USART3 */
+
+#ifdef _I2C1
+ EXT I2C_TypeDef *I2C1;
+#endif /*_I2C1 */
+
+#ifdef _I2C2
+ EXT I2C_TypeDef *I2C2;
+#endif /*_I2C2 */
+
+#ifdef _CAN
+ EXT CAN_TypeDef *CAN;
+#endif /*_CAN */
+
+#ifdef _BKP
+ EXT BKP_TypeDef *BKP;
+#endif /*_BKP */
+
+#ifdef _PWR
+ EXT PWR_TypeDef *PWR;
+#endif /*_PWR */
+
+#ifdef _AFIO
+ EXT AFIO_TypeDef *AFIO;
+#endif /*_AFIO */
+
+#ifdef _EXTI
+ EXT EXTI_TypeDef *EXTI;
+#endif /*_EXTI */
+
+#ifdef _GPIOA
+ EXT GPIO_TypeDef *GPIOA;
+#endif /*_GPIOA */
+
+#ifdef _GPIOB
+ EXT GPIO_TypeDef *GPIOB;
+#endif /*_GPIOB */
+
+#ifdef _GPIOC
+ EXT GPIO_TypeDef *GPIOC;
+#endif /*_GPIOC */
+
+#ifdef _GPIOD
+ EXT GPIO_TypeDef *GPIOD;
+#endif /*_GPIOD */
+
+#ifdef _GPIOE
+ EXT GPIO_TypeDef *GPIOE;
+#endif /*_GPIOE */
+
+#ifdef _ADC1
+ EXT ADC_TypeDef *ADC1;
+#endif /*_ADC1 */
+
+#ifdef _ADC2
+ EXT ADC_TypeDef *ADC2;
+#endif /*_ADC2 */
+
+#ifdef _TIM1
+ EXT TIM1_TypeDef *TIM1;
+#endif /*_TIM1 */
+
+#ifdef _SPI1
+ EXT SPI_TypeDef *SPI1;
+#endif /*_SPI1 */
+
+#ifdef _USART1
+ EXT USART_TypeDef *USART1;
+#endif /*_USART1 */
+
+#ifdef _DMA
+ EXT DMA_TypeDef *DMA;
+#endif /*_DMA */
+
+#ifdef _DMA_Channel1
+ EXT DMA_Channel_TypeDef *DMA_Channel1;
+#endif /*_DMA_Channel1 */
+
+#ifdef _DMA_Channel2
+ EXT DMA_Channel_TypeDef *DMA_Channel2;
+#endif /*_DMA_Channel2 */
+
+#ifdef _DMA_Channel3
+ EXT DMA_Channel_TypeDef *DMA_Channel3;
+#endif /*_DMA_Channel3 */
+
+#ifdef _DMA_Channel4
+ EXT DMA_Channel_TypeDef *DMA_Channel4;
+#endif /*_DMA_Channel4 */
+
+#ifdef _DMA_Channel5
+ EXT DMA_Channel_TypeDef *DMA_Channel5;
+#endif /*_DMA_Channel5 */
+
+#ifdef _DMA_Channel6
+ EXT DMA_Channel_TypeDef *DMA_Channel6;
+#endif /*_DMA_Channel6 */
+
+#ifdef _DMA_Channel7
+ EXT DMA_Channel_TypeDef *DMA_Channel7;
+#endif /*_DMA_Channel7 */
+
+#ifdef _FLASH
+ EXT FLASH_TypeDef *FLASH;
+ EXT OB_TypeDef *OB;
+#endif /*_FLASH */
+
+#ifdef _RCC
+ EXT RCC_TypeDef *RCC;
+#endif /*_RCC */
+
+#ifdef _SysTick
+ EXT SysTick_TypeDef *SysTick;
+#endif /*_SysTick */
+
+#ifdef _NVIC
+ EXT NVIC_TypeDef *NVIC;
+ EXT SCB_TypeDef *SCB;
+#endif /*_NVIC */
+
+#endif /* DEBUG */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __STM32F10x_MAP_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_type.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_type.h new file mode 100644 index 000000000..92c8579e1 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_type.h @@ -0,0 +1,80 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
+* File Name : stm32f10x_type.h
+* Author : MCD Application Team
+* Version : V1.0
+* Date : 10/08/2007
+* Description : This file contains all the common data types used for the
+* STM32F10x firmware library.
+********************************************************************************
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_TYPE_H
+#define __STM32F10x_TYPE_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+typedef signed long s32;
+typedef signed short s16;
+typedef signed char s8;
+
+typedef signed long const sc32; /* Read Only */
+typedef signed short const sc16; /* Read Only */
+typedef signed char const sc8; /* Read Only */
+
+typedef volatile signed long vs32;
+typedef volatile signed short vs16;
+typedef volatile signed char vs8;
+
+typedef volatile signed long const vsc32; /* Read Only */
+typedef volatile signed short const vsc16; /* Read Only */
+typedef volatile signed char const vsc8; /* Read Only */
+
+typedef unsigned long u32;
+typedef unsigned short u16;
+typedef unsigned char u8;
+
+typedef unsigned long const uc32; /* Read Only */
+typedef unsigned short const uc16; /* Read Only */
+typedef unsigned char const uc8; /* Read Only */
+
+typedef volatile unsigned long vu32;
+typedef volatile unsigned short vu16;
+typedef volatile unsigned char vu8;
+
+typedef volatile unsigned long const vuc32; /* Read Only */
+typedef volatile unsigned short const vuc16; /* Read Only */
+typedef volatile unsigned char const vuc8; /* Read Only */
+
+typedef enum {FALSE = 0, TRUE = !FALSE} bool;
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) ((STATE == DISABLE) || (STATE == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+#define U8_MAX ((u8)255)
+#define S8_MAX ((s8)127)
+#define S8_MIN ((s8)-128)
+#define U16_MAX ((u16)65535u)
+#define S16_MAX ((s16)32767)
+#define S16_MIN ((s16)-32768)
+#define U32_MAX ((u32)4294967295uL)
+#define S32_MAX ((s32)2147483647)
+#define S32_MIN ((s32)2147483648uL)
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __STM32F10x_TYPE_H */
+
+/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
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