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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-05-14 14:28:44 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-05-14 14:28:44 +0000 |
| commit | 8ae45a5b9616c3214c4fc043b90750ca662b0372 (patch) | |
| tree | 124d70accd682471026cd60e23b0bf823dbb5bdb /demos | |
| parent | e6e83440f31b42fe00f3e3eda65ca81d59aac2fe (diff) | |
| download | ChibiOS-8ae45a5b9616c3214c4fc043b90750ca662b0372.tar.gz ChibiOS-8ae45a5b9616c3214c4fc043b90750ca662b0372.tar.bz2 ChibiOS-8ae45a5b9616c3214c4fc043b90750ca662b0372.zip | |
Re-unified some of the F4 platform code. Probably more code could be shared.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12033 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'demos')
| -rw-r--r-- | demos/STM32/RT-STM32F412ZG-NUCLEO144/mcuconf.h | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/demos/STM32/RT-STM32F412ZG-NUCLEO144/mcuconf.h b/demos/STM32/RT-STM32F412ZG-NUCLEO144/mcuconf.h index 5dfea7cd2..19a9b5c8c 100644 --- a/demos/STM32/RT-STM32F412ZG-NUCLEO144/mcuconf.h +++ b/demos/STM32/RT-STM32F412ZG-NUCLEO144/mcuconf.h @@ -39,15 +39,16 @@ #define STM32_NO_INIT FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
-#define STM32_HSE_ENABLED FALSE
+#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
-#define STM32_PLLSRC STM32_PLLSRC_HSI
-#define STM32_PLLM_VALUE 16
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#define STM32_PLLM_VALUE 8
#define STM32_PLLN_VALUE 384
#define STM32_PLLP_VALUE 4
#define STM32_PLLQ_VALUE 8
+#define STM32_PLLR_VALUE 4
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV1
@@ -57,9 +58,12 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
-#define STM32_I2SSRC STM32_I2SSRC_CKIN
+#define STM32_PLLI2SSRC STM32_PLLI2SSRC_PLLSRC
+#define STM32_I2SCKIN_VALUE 0
+#define STM32_PLLI2SM_VALUE 8
#define STM32_PLLI2SN_VALUE 192
-#define STM32_PLLI2SR_VALUE 5
+#define STM32_PLLI2SR_VALUE 4
+#define STM32_PLLI2SQ_VALUE 4
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
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