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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-09-15 09:58:20 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-09-15 09:58:20 +0000 |
| commit | 5e27a7896c5a115a53bada786849e0c247d8466c (patch) | |
| tree | fc28b0122f62635ae05c6e41611210cbf16c3364 /demos | |
| parent | d1c9b44d96079ff77dd4cecf58cf6eb48f90b9c8 (diff) | |
| download | ChibiOS-5e27a7896c5a115a53bada786849e0c247d8466c.tar.gz ChibiOS-5e27a7896c5a115a53bada786849e0c247d8466c.tar.bz2 ChibiOS-5e27a7896c5a115a53bada786849e0c247d8466c.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12260 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'demos')
| -rw-r--r-- | demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h index 1ca00276d..4f8df2d65 100644 --- a/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h @@ -56,6 +56,73 @@ /*
* HAL driver system settings.
*/
+#define STM32_NO_INIT FALSE
+#define STM32_VOS STM32_VOS_RANGE1
+#define STM32_PVD_ENABLE FALSE
+#define STM32_PLS STM32_PLS_LEV0
+#define STM32_HSI16_ENABLED FALSE
+#define STM32_HSI48_ENABLED FALSE
+#define STM32_LSI_ENABLED TRUE
+#define STM32_HSE_ENABLED FALSE
+#define STM32_LSE_ENABLED FALSE
+#define STM32_MSIPLL_ENABLED FALSE
+#define STM32_ADC_CLOCK_ENABLED TRUE
+#define STM32_USB_CLOCK_ENABLED TRUE
+#define STM32_SAI1_CLOCK_ENABLED TRUE
+#define STM32_SAI2_CLOCK_ENABLED TRUE
+#define STM32_MSIRANGE STM32_MSIRANGE_4M
+#define STM32_MSISRANGE STM32_MSISRANGE_4M
+#define STM32_SW STM32_SW_PLL
+#define STM32_PLLSRC STM32_PLLSRC_MSI
+#define STM32_PLLM_VALUE 1
+#define STM32_PLLN_VALUE 60
+#define STM32_PLLPDIV_VALUE 0
+#define STM32_PLLP_VALUE 7
+#define STM32_PLLQ_VALUE 4
+#define STM32_PLLR_VALUE 2
+#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_PPRE1 STM32_PPRE1_DIV1
+#define STM32_PPRE2 STM32_PPRE2_DIV1
+#define STM32_STOPWUCK STM32_STOPWUCK_MSI
+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
+#define STM32_MCOPRE STM32_MCOPRE_DIV1
+#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
+#define STM32_PLLSAI1N_VALUE 72
+#define STM32_PLLSAI1PDIV_VALUE 6
+#define STM32_PLLSAI1P_VALUE 7
+#define STM32_PLLSAI1Q_VALUE 6
+#define STM32_PLLSAI1R_VALUE 6
+#define STM32_PLLSAI2N_VALUE 72
+#define STM32_PLLSAI2PDIV_VALUE 6
+#define STM32_PLLSAI2P_VALUE 7
+#define STM32_PLLSAI2Q_VALUE 6
+#define STM32_PLLSAI2R_VALUE 6
+
+/*
+ * Peripherals clock sources.
+ */
+#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
+#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
+#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
+#define STM32_UART4SEL STM32_UART4SEL_SYSCLK
+#define STM32_UART5SEL STM32_UART5SEL_SYSCLK
+#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
+#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
+#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
+#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
+#define STM32_I2C4SEL STM32_I2C4SEL_SYSCLK
+#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
+#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
+#define STM32_CLK48SEL STM32_CLK48SEL_PLL
+#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
+#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
+#define STM32_ADFSDMSEL STM32_ADFSDMSEL_SAI1CLK
+#define STM32_SAI1SEL STM32_SAI1SEL_OFF
+#define STM32_SAI2SEL STM32_SAI2SEL_OFF
+#define STM32_DSISEL STM32_DSISEL_DSIPHY
+#define STM32_SDMMC STM32_SDMMCSEL_48CLK
+#define STM32_OSPISEL STM32_OSPISEL_SYSCLK
+#define STM32_RTCSEL STM32_RTCSEL_LSI
/*
* IRQ system settings.
@@ -111,10 +178,14 @@ #define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE
+#define STM32_SERIAL_USE_UART4 FALSE
+#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_LPUART1 TRUE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART3_PRIORITY 12
+#define STM32_SERIAL_UART4_PRIORITY 12
+#define STM32_SERIAL_UART5_PRIORITY 12
#define STM32_SERIAL_LPUART1_PRIORITY 12
/*
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