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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-08-22 10:32:35 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-08-22 10:32:35 +0000 |
| commit | 491c9ac55a0337cd248bb735466bd1dee638de51 (patch) | |
| tree | f9ae2ce590e6cda26c7f1ce1ffde84c5e9fdc8ff /demos | |
| parent | bb48071bc5f863fcecb8c43f88f50235c60a2768 (diff) | |
| download | ChibiOS-491c9ac55a0337cd248bb735466bd1dee638de51.tar.gz ChibiOS-491c9ac55a0337cd248bb735466bd1dee638de51.tar.bz2 ChibiOS-491c9ac55a0337cd248bb735466bd1dee638de51.zip | |
Fixed bug #874.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10457 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'demos')
6 files changed, 8 insertions, 2 deletions
diff --git a/demos/STM32/NIL-STM32F746G-DISCOVERY/mcuconf.h b/demos/STM32/NIL-STM32F746G-DISCOVERY/mcuconf.h index 3b1f2128a..2e7c41a48 100644 --- a/demos/STM32/NIL-STM32F746G-DISCOVERY/mcuconf.h +++ b/demos/STM32/NIL-STM32F746G-DISCOVERY/mcuconf.h @@ -65,6 +65,7 @@ #define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
#define STM32_PLLI2SR_VALUE 4
+#define STM32_PLLI2SDIVQ_VALUE 2
#define STM32_PLLSAIN_VALUE 192
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
diff --git a/demos/STM32/RT-STM32F746G-DISCOVERY-LWIP-FATFS-USB/mcuconf.h b/demos/STM32/RT-STM32F746G-DISCOVERY-LWIP-FATFS-USB/mcuconf.h index a897ed02f..fe9e360ee 100644 --- a/demos/STM32/RT-STM32F746G-DISCOVERY-LWIP-FATFS-USB/mcuconf.h +++ b/demos/STM32/RT-STM32F746G-DISCOVERY-LWIP-FATFS-USB/mcuconf.h @@ -65,6 +65,7 @@ #define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
#define STM32_PLLI2SR_VALUE 4
+#define STM32_PLLI2SDIVQ_VALUE 2
#define STM32_PLLSAIN_VALUE 192
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
diff --git a/demos/STM32/RT-STM32F746G-DISCOVERY/mcuconf.h b/demos/STM32/RT-STM32F746G-DISCOVERY/mcuconf.h index 8da26145e..2e7c41a48 100644 --- a/demos/STM32/RT-STM32F746G-DISCOVERY/mcuconf.h +++ b/demos/STM32/RT-STM32F746G-DISCOVERY/mcuconf.h @@ -65,15 +65,16 @@ #define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
#define STM32_PLLI2SR_VALUE 4
+#define STM32_PLLI2SDIVQ_VALUE 2
#define STM32_PLLSAIN_VALUE 192
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIDIVQ_VALUE 2
-#define STM32_PLLSAIDIVR_VALUE 4
+#define STM32_PLLSAIDIVR_VALUE 2
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
-#define STM32_LCDTFT_REQUIRED TRUE
+#define STM32_LCDTFT_REQUIRED FALSE
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
#define STM32_USART2SEL STM32_USART2SEL_PCLK1
#define STM32_USART3SEL STM32_USART3SEL_PCLK1
diff --git a/demos/STM32/RT-STM32F746ZG-NUCLEO144/mcuconf.h b/demos/STM32/RT-STM32F746ZG-NUCLEO144/mcuconf.h index 83df28692..03c6e9f79 100644 --- a/demos/STM32/RT-STM32F746ZG-NUCLEO144/mcuconf.h +++ b/demos/STM32/RT-STM32F746ZG-NUCLEO144/mcuconf.h @@ -65,6 +65,7 @@ #define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
#define STM32_PLLI2SR_VALUE 4
+#define STM32_PLLI2SDIVQ_VALUE 2
#define STM32_PLLSAIN_VALUE 192
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
diff --git a/demos/STM32/RT-STM32F767ZI-NUCLEO144/mcuconf.h b/demos/STM32/RT-STM32F767ZI-NUCLEO144/mcuconf.h index 83df28692..03c6e9f79 100644 --- a/demos/STM32/RT-STM32F767ZI-NUCLEO144/mcuconf.h +++ b/demos/STM32/RT-STM32F767ZI-NUCLEO144/mcuconf.h @@ -65,6 +65,7 @@ #define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
#define STM32_PLLI2SR_VALUE 4
+#define STM32_PLLI2SDIVQ_VALUE 2
#define STM32_PLLSAIN_VALUE 192
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
diff --git a/demos/STM32/RT-STM32F769I-DISCOVERY/mcuconf.h b/demos/STM32/RT-STM32F769I-DISCOVERY/mcuconf.h index 3b1f2128a..2e7c41a48 100644 --- a/demos/STM32/RT-STM32F769I-DISCOVERY/mcuconf.h +++ b/demos/STM32/RT-STM32F769I-DISCOVERY/mcuconf.h @@ -65,6 +65,7 @@ #define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
#define STM32_PLLI2SR_VALUE 4
+#define STM32_PLLI2SDIVQ_VALUE 2
#define STM32_PLLSAIN_VALUE 192
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
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