Modified the STM32 demo to use the bit definitions in the ST header file.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1050 35acf78f-673a-0410-8e92-d51de3d6d3f4

2 files changed, 21 insertions, 58 deletions

diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c
index 3e3776f4a..34349b827 100644
--- a/demos/ARMCM3-STM32F103-GCC/board.c
+++ b/demos/ARMCM3-STM32F103-GCC/board.c
@@ -46,28 +46,29 @@ void hwinit0(void) {
    * Clocks and PLL initialization.

    */

   // HSI setup.

-  RCC->CR = HSITRIM_RESET_BITS | CR_HSION_MASK;

-  while (!(RCC->CR & CR_HSIRDY_MASK))

+  RCC->CR = RCC_CR_HSITRIM_RESET_BITS | RCC_CR_HSION;

+  while (!(RCC->CR & RCC_CR_HSIRDY))

     ;                           // Waits until HSI stable, it should already be.

   // HSE setup.

-  RCC->CR |= CR_HSEON_MASK;

-  while (!(RCC->CR & CR_HSERDY_MASK))

+  RCC->CR |= RCC_CR_HSEON;

+  while (!(RCC->CR & RCC_CR_HSERDY))

     ;                           // Waits until HSE stable.

   // PLL setup.

-  RCC->CFGR = PLLSRC_HSE_BITS | PLLPREBITS | PLLMULBITS;

-  RCC->CR |= CR_PLLON_MASK;

-  while (!(RCC->CR & CR_PLLRDY_MASK))

+  RCC->CFGR = RCC_CFGR_PLLSRC_HSE_BITS | PLLPREBITS | PLLMULBITS;

+  RCC->CR |= RCC_CR_PLLON;

+  while (!(RCC->CR & RCC_CR_PLLRDY))

     ;                           // Waits until PLL stable.

   // Clock sources.

-  RCC->CFGR |= HPRE_DIV1_BITS | PPRE1_DIV2_BITS | PPRE2_DIV2_BITS |

-               ADCPRE_DIV8_BITS | USBPREBITS | MCO_DISABLED_BITS;

+  RCC->CFGR |= RCC_CFGR_HPRE_DIV1   | RCC_CFGR_PPRE1_DIV2  |

+               RCC_CFGR_PPRE2_DIV2  | RCC_CFGR_ADCPRE_DIV8 |

+               RCC_CFGR_MCO_NOCLOCK | USBPREBITS;

 

   /*

    * Flash setup and final clock selection.

    */

   FLASH->ACR = FLASHBITS;       // Flash wait states depending on clock.

-  RCC->CFGR |= SW_PLL_BITS;     // Switches on the PLL clock.

-  while ((RCC->CFGR & CFGR_SWS_MASK) != SWS_PLL_BITS)

+  RCC->CFGR |= RCC_CFGR_SW_PLL; // Switches on the PLL clock.

+  while ((RCC->CFGR & RCC_CFGR_SW) != RCC_CFGR_SW_PLL)

     ;

 

   /*

diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h
index 755e6e15d..dcf8f8a33 100644
--- a/demos/ARMCM3-STM32F103-GCC/board.h
+++ b/demos/ARMCM3-STM32F103-GCC/board.h
@@ -28,7 +28,6 @@
 #undef FALSE

 #undef TRUE

 #include "stm32f10x_map.h"

-#include "stm32f10x_rcc.h"

 #define FALSE 0

 #define TRUE (!FALSE)

 #endif

@@ -62,62 +61,25 @@
 #define PLLPREBITS      ((PLLPRE - 1) << 17)

 #define PLLMULBITS      ((PLLMUL - 2) << 18)

 #ifdef SYSCLK_48

-  #define USBPREBITS    USBPRE_DIV1_BITS

+  #define USBPREBITS    RCC_CFGR_USBPRE_DIV1_BITS

   #define FLASHBITS     0x00000011

 #else

-  #define USBPREBITS    USBPRE_DIV1P5_BITS

+  #define USBPREBITS    RCC_CFGR_USBPRE_DIV1P5_BITS

   #define FLASHBITS     0x00000012

 #endif

 

 /*

- * Definitions for RCC_CR register.

+ * Extra definitions for RCC_CR register (missing from the ST header file).

  */

-#define CR_HSION_MASK           (0x1 << 0)

-#define CR_HSIRDY_MASK          (0x1 << 1)

-#define CR_HSITRIM_MASK         (0x1F << 3)

-#define   HSITRIM_RESET_BITS    (0x10 << 3)

-#define CR_HSICAL_MASK          (0xFF << 8)

-#define CR_HSEON_MASK           (0x1 << 16)

-#define CR_HSERDY_MASK          (0x1 << 17)

-#define CR_HSEBYP_MASK          (0x1 << 18)

-#define CR_CSSON_MASK           (0x1 << 19)

-#define CR_PLLON_MASK           (0x1 << 24)

-#define CR_PLLRDY_MASK          (0x1 << 25)

+#define RCC_CR_HSITRIM_RESET_BITS       (0x10 << 3)

 

 /*

- * Definitions for RCC_CFGR register.

+ * Extra definitions for RCC_CFGR register (missing from the ST header file).

  */

-#define CFGR_SW_MASK            (0x3 << 0)

-#define   SW_HSI_BITS           (0 << 0)

-#define   SW_HSE_BITS           (1 << 0)

-#define   SW_PLL_BITS           (2 << 0)

-#define CFGR_SWS_MASK           (0x3 << 2)

-#define   SWS_HSI_BITS          (0 << 2)

-#define   SWS_HSE_BITS          (1 << 2)

-#define   SWS_PLL_BITS          (2 << 2)

-#define CFGR_HPRE_MASK          (0xF << 4)

-#define    HPRE_DIV1_BITS       (0 << 4)

-#define CFGR_PPRE1_MASK         (0x7 << 8)

-#define   PPRE1_DIV1_BITS       (0 << 8)

-#define   PPRE1_DIV2_BITS       (4 << 8)

-#define CFGR_PPRE2_MASK         (0x7 << 11)

-#define   PPRE2_DIV1_BITS       (0 << 11)

-#define   PPRE2_DIV2_BITS       (4 << 11)

-#define CFGR_ADCPRE_MASK        (0x3 << 14)

-#define   ADCPRE_DIV2_BITS      (0 << 14)

-#define   ADCPRE_DIV4_BITS      (1 << 14)

-#define   ADCPRE_DIV6_BITS      (2 << 14)

-#define   ADCPRE_DIV8_BITS      (3 << 14)

-#define CFGR_PLLSRC_MASK        (0x1 << 16)

-#define   PLLSRC_HSI_BITS       (0 << 16)

-#define   PLLSRC_HSE_BITS       (1 << 16)

-#define CFGR_PLLXTPRE_MASK      (0x1 << 17)

-#define CFGR_PLLMUL_MASK        (0xF << 18)

-#define CFGR_USBPRE_MASK        (0x1 << 22)

-#define   USBPRE_DIV1P5_BITS    (0 << 22)

-#define   USBPRE_DIV1_BITS      (1 << 22)

-#define CFGR_MCO_MASK           (0x7 << 24)

-#define   MCO_DISABLED_BITS     (0 << 24)

+#define RCC_CFGR_PLLSRC_HSI_BITS        (0 << 16)

+#define RCC_CFGR_PLLSRC_HSE_BITS        (1 << 16)

+#define RCC_CFGR_USBPRE_DIV1P5_BITS     (0 << 22)

+#define RCC_CFGR_USBPRE_DIV1_BITS       (1 << 22)

 

 /*

  * IO pins assignments.