Serial port working.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11189 35acf78f-673a-0410-8e92-d51de3d6d3f4

5 files changed, 14 insertions, 16 deletions

diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/Makefile b/demos/STM32/RT-STM32H743I-NUCLEO144/Makefile
index fd027130d..1a4112fba 100644
--- a/demos/STM32/RT-STM32H743I-NUCLEO144/Makefile
+++ b/demos/STM32/RT-STM32H743I-NUCLEO144/Makefile
@@ -5,7 +5,7 @@
 

 # Compiler options here.

 ifeq ($(USE_OPT),)

-  USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16

+  USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16

 endif

 

 # C specific options here (added to USE_OPT).

@@ -111,9 +111,9 @@ include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
 # Auto-build files in ./source recursively.

 include $(CHIBIOS)/tools/mk/autobuild.mk

 # Other files (optional).

-#include $(CHIBIOS)/test/lib/test.mk

-#include $(CHIBIOS)/test/rt/rt_test.mk

-#include $(CHIBIOS)/test/oslib/oslib_test.mk

+include $(CHIBIOS)/test/lib/test.mk

+include $(CHIBIOS)/test/rt/rt_test.mk

+include $(CHIBIOS)/test/oslib/oslib_test.mk

 

 # Define linker script file here

 LDSCRIPT= $(STARTUPLD)/STM32H743xI.ld

diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch b/demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch
index c69b25933..9c728ae73 100644
--- a/demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch
+++ b/demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch
@@ -33,7 +33,7 @@
 <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
 <stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
 <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList&gt;&lt;content id=&quot;RESERVED10-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB4LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB2LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1HLPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1LLPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB3LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB4LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB2LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB1LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB3LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED9-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB4ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB2ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1HENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1LENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB3ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB4ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB2ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB1ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB3ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RSR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED8-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D3AMR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED7-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;GCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB4RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB2RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1HRSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1LRSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB3RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB4RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB2RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB1RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB3RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED6-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CSR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;BDCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED5-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CICR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CIFR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CIER-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED4-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D3CCIPR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D2CCIP2R-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D2CCIP1R-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D1CCIPR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED3-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL3FRACR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL3DIVR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL2FRACR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL2DIVR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL1FRACR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL1DIVR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLLCFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLLCKSELR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED2-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D3CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D2CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D1CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED1-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED0-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CRRCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;ICSCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;r3-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;r2-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;delta-next-vtlist-null-_idle_thread.lto_priv.25-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR1-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CSR1-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR2-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR3-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;MODER-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;OTYPER-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;OSPEEDR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PUPDR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;IDR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;ODR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;BSRR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;LOCKR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AFRL-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AFRH-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;MODER-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;OTYPER-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;OSPEEDR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PUPDR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;IDR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;ODR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;BSRR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;LOCKR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AFRL-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AFRH-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;/contentList&gt;"/>
+<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList&gt;&lt;content id=&quot;AFRH-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AFRL-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;LOCKR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;BSRR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;ODR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;IDR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PUPDR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;OSPEEDR-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;OTYPER-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;MODER-null-Thread1-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AFRH-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AFRL-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;LOCKR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;BSRR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;ODR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;IDR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PUPDR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;OSPEEDR-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;OTYPER-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;MODER-null-stm32_gpio_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR3-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR2-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CSR1-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR1-pwr-init_pwr-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;delta-next-vtlist-null-_idle_thread.lto_priv.25-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;r2-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;r3-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;ICSCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CRRCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED0-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED1-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D1CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D2CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D3CFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED2-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLLCKSELR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLLCFGR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL1DIVR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL1FRACR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL2DIVR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL2FRACR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL3DIVR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;PLL3FRACR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED3-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D1CCIPR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D2CCIP1R-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D2CCIP2R-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D3CCIPR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED4-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CIER-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CIFR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CICR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED5-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;BDCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;CSR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED6-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB3RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB1RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB2RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB4RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB3RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1LRSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1HRSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB2RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB4RSTR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;GCR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED7-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;D3AMR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED8-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RSR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB3ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB1ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB2ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB4ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB3ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1LENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1HENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB2ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB4ENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED9-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB3LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB1LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB2LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;AHB4LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB3LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1LLPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB1HLPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB2LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;APB4LPENR-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;content id=&quot;RESERVED10-rcc-stm32_clock_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;/contentList&gt;"/>
 <stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;globalVariableList/&gt;&#10;"/>
 <stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList&gt;&#10;&lt;memoryBlockExpressionItem&gt;&#10;&lt;expression text=&quot;0x0&quot;/&gt;&#10;&lt;/memoryBlockExpressionItem&gt;&#10;&lt;memoryBlockExpressionItem&gt;&#10;&lt;expression text=&quot;0x11087000&quot;/&gt;&#10;&lt;/memoryBlockExpressionItem&gt;&#10;&lt;/memoryBlockExpressionList&gt;&#10;"/>
 <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/>
diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/halconf.h b/demos/STM32/RT-STM32H743I-NUCLEO144/halconf.h
index 5aec384f3..d7793e22c 100644
--- a/demos/STM32/RT-STM32H743I-NUCLEO144/halconf.h
+++ b/demos/STM32/RT-STM32H743I-NUCLEO144/halconf.h
@@ -146,7 +146,7 @@
  * @brief   Enables the SERIAL subsystem.

  */

 #if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)

-#define HAL_USE_SERIAL              FALSE

+#define HAL_USE_SERIAL              TRUE

 #endif

 

 /**

diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/main.c b/demos/STM32/RT-STM32H743I-NUCLEO144/main.c
index 13849bd2b..71ade98e0 100644
--- a/demos/STM32/RT-STM32H743I-NUCLEO144/main.c
+++ b/demos/STM32/RT-STM32H743I-NUCLEO144/main.c
@@ -16,8 +16,8 @@
 

 #include "ch.h"

 #include "hal.h"

-//#include "rt_test_root.h"

-//#include "oslib_test_root.h"

+#include "rt_test_root.h"

+#include "oslib_test_root.h"

 

 /*

  * This is a periodic thread that does absolutely nothing except flashing

@@ -54,7 +54,7 @@ int main(void) {
   /*

    * Activates the serial driver 1 using the driver default configuration.

    */

-//  sdStart(&SD1, NULL);

+  sdStart(&SD3, NULL);

 

   /*

    * Creates the example thread.

@@ -66,12 +66,10 @@ int main(void) {
    * sleeping in a loop and check the button state.

    */

   while (1) {

-#if 0

-    if (palReadLine(LINE_BUTTON_USER)) {

-      test_execute((BaseSequentialStream *)&SD1, &rt_test_suite);

-      test_execute((BaseSequentialStream *)&SD1, &oslib_test_suite);

+    if (palReadLine(LINE_BUTTON)) {

+      test_execute((BaseSequentialStream *)&SD3, &rt_test_suite);

+      test_execute((BaseSequentialStream *)&SD3, &oslib_test_suite);

     }

-#endif

     chThdSleepMilliseconds(500);

   }

 }

diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h b/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h
index b347e8c83..4a1b10dcf 100644
--- a/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h
+++ b/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h
@@ -332,9 +332,9 @@
 /*

  * SERIAL driver system settings.

  */

-#define STM32_SERIAL_USE_USART1             TRUE

+#define STM32_SERIAL_USE_USART1             FALSE

 #define STM32_SERIAL_USE_USART2             FALSE

-#define STM32_SERIAL_USE_USART3             FALSE

+#define STM32_SERIAL_USE_USART3             TRUE

 #define STM32_SERIAL_USE_UART4              FALSE

 #define STM32_SERIAL_USE_UART5              FALSE

 #define STM32_SERIAL_USE_USART6             FALSE