diff options
| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-12-22 19:05:03 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-12-22 19:05:03 +0000 |
| commit | e6199d4b5426043b877bb712f47fb759c2fe91ea (patch) | |
| tree | 3ad271bbd06ec9e14f318e98c18ed280c2f063b4 /demos/STM32/RT-STM32H743I-NUCLEO144 | |
| parent | 95cf891ac5e7795b5fdb780cdb7c3194720e4ae3 (diff) | |
| download | ChibiOS-e6199d4b5426043b877bb712f47fb759c2fe91ea.tar.gz ChibiOS-e6199d4b5426043b877bb712f47fb759c2fe91ea.tar.bz2 ChibiOS-e6199d4b5426043b877bb712f47fb759c2fe91ea.zip | |
More H7 code.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11170 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'demos/STM32/RT-STM32H743I-NUCLEO144')
| -rw-r--r-- | demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h | 45 |
1 files changed, 41 insertions, 4 deletions
diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h b/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h index 984569aeb..4933f835d 100644 --- a/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h +++ b/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h @@ -18,7 +18,7 @@ #define MCUCONF_H
/*
- * STM32F7xx drivers configuration.
+ * STM32H7xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
@@ -34,14 +34,15 @@ #define STM32H7xx_MCUCONF
/*
- * General settins.
+ * General settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_HCLK_ENFORCED_VALUE STM32_HSICLK
/*
* PWR system settings.
- * Constants are taken from the ST header, reading manual is required.
+ * Reading STM32 Reference Manual is required.
+ * Constants are taken from the ST header.
*/
#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
#define STM32_PWR_CR2 (PWR_CR2_BREN)
@@ -51,9 +52,45 @@ /*
* Clock tree settings.
- * Constants are taken from the ST header, reading manual is required.
+ * Reading STM32 Reference Manual is required.
*/
#define STM32_HSI_ENABLED TRUE
+#define STM32_LSI_ENABLED FALSE
+#define STM32_CSI_ENABLED FALSE
+#define STM32_HSI48_ENABLED TRUE
+#define STM32_HSE_ENABLED TRUE
+#define STM32_LSE_ENABLED TRUE
+#define STM32_HSIDIV STM32_HSIDIV_DIV1
+#define STM32_RTCPRE_VALUE 8
+#define STM32_RTCSEL STM32_RTCSEL_LSE
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#define STM32_PLL1_ENABLED TRUE
+#define STM32_PLL1_DIVM_VALUE 4
+#define STM32_PLL1_DIVN_VALUE 400
+#define STM32_PLL1_FRACN_VALUE 0
+#define STM32_PLL1_DIVP_VALUE 2
+#define STM32_PLL1_DIVQ_VALUE 8
+#define STM32_PLL1_DIVR_VALUE 8
+#define STM32_PLL2_ENABLED TRUE
+#define STM32_PLL2_DIVM_VALUE 4
+#define STM32_PLL2_DIVN_VALUE 400
+#define STM32_PLL2_FRACN_VALUE 0
+#define STM32_PLL2_DIVP_VALUE 2
+#define STM32_PLL2_DIVQ_VALUE 8
+#define STM32_PLL2_DIVR_VALUE 8
+#define STM32_PLL3_ENABLED TRUE
+#define STM32_PLL3_DIVM_VALUE 4
+#define STM32_PLL3_DIVN_VALUE 400
+#define STM32_PLL3_FRACN_VALUE 0
+#define STM32_PLL3_DIVP_VALUE 2
+#define STM32_PLL3_DIVQ_VALUE 8
+#define STM32_PLL3_DIVR_VALUE 8
+
+
+
+
+
+#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_CSI_ENABLED TRUE
#define STM32_HSI48_ENABLED TRUE
|