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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-01-11 18:16:32 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-01-11 18:16:32 +0000 |
| commit | c0cea335bc590cd86fb385f587e61449e6071c9e (patch) | |
| tree | 70ef4602d0077724d4a6d5eeeabcb741afb27130 /demos/STM32/RT-STM32H743I-NUCLEO144 | |
| parent | 85becea5ec68aa7e963e6d87b7f3fffe5c376d21 (diff) | |
| download | ChibiOS-c0cea335bc590cd86fb385f587e61449e6071c9e.tar.gz ChibiOS-c0cea335bc590cd86fb385f587e61449e6071c9e.tar.bz2 ChibiOS-c0cea335bc590cd86fb385f587e61449e6071c9e.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11263 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'demos/STM32/RT-STM32H743I-NUCLEO144')
| -rw-r--r-- | demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h b/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h index e1ac3d1a5..581563093 100644 --- a/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h +++ b/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h @@ -94,7 +94,7 @@ #define STM32_PLL2_DIVM_VALUE 4
#define STM32_PLL2_DIVN_VALUE 400
#define STM32_PLL2_FRACN_VALUE 0
-#define STM32_PLL2_DIVP_VALUE 2
+#define STM32_PLL2_DIVP_VALUE 8
#define STM32_PLL2_DIVQ_VALUE 8
#define STM32_PLL2_DIVR_VALUE 8
#define STM32_PLL3_ENABLED TRUE
@@ -104,7 +104,7 @@ #define STM32_PLL3_DIVM_VALUE 4
#define STM32_PLL3_DIVN_VALUE 400
#define STM32_PLL3_FRACN_VALUE 0
-#define STM32_PLL3_DIVP_VALUE 2
+#define STM32_PLL3_DIVP_VALUE 8
#define STM32_PLL3_DIVQ_VALUE 8
#define STM32_PLL3_DIVR_VALUE 8
@@ -115,11 +115,11 @@ #define STM32_SW STM32_SW_PLL1_P_CK
#define STM32_RTCSEL STM32_RTCSEL_LSE_CK
#define STM32_D1CPRE STM32_D1CPRE_DIV1
-#define STM32_D1HPRE STM32_D1HPRE_DIV2
-#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2
-#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2
-#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2
-#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2
+#define STM32_D1HPRE STM32_D1HPRE_DIV4
+#define STM32_D1PPRE3 STM32_D1PPRE3_DIV1
+#define STM32_D2PPRE1 STM32_D2PPRE1_DIV1
+#define STM32_D2PPRE2 STM32_D2PPRE2_DIV1
+#define STM32_D3PPRE4 STM32_D3PPRE4_DIV1
/*
* Peripherals clocks static settings.
@@ -183,8 +183,9 @@ /*
* ADC driver system settings.
*/
-#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
-#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
+#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
+#define STM32_ADC_USE_ADC1 TRUE
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC1_DMA_CHANNEL 0
|