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| author | utzig <utzig@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-08-23 17:52:25 +0000 |
|---|---|---|
| committer | utzig <utzig@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-08-23 17:52:25 +0000 |
| commit | 2804bd065591927fd6f818b1af2d4f32562a9a1c (patch) | |
| tree | 12b775ca39e7e8045157f4fafe57eeb4748a3de7 /demos/KINETIS/RT-MCHCK-K20-SPI/mcuconf.h | |
| parent | cd7aae2641ab32cd8b52204ee6ee42276466db5b (diff) | |
| download | ChibiOS-2804bd065591927fd6f818b1af2d4f32562a9a1c.tar.gz ChibiOS-2804bd065591927fd6f818b1af2d4f32562a9a1c.tar.bz2 ChibiOS-2804bd065591927fd6f818b1af2d4f32562a9a1c.zip | |
[KINETIS] Add MC HCK demo
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7187 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'demos/KINETIS/RT-MCHCK-K20-SPI/mcuconf.h')
| -rw-r--r-- | demos/KINETIS/RT-MCHCK-K20-SPI/mcuconf.h | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/demos/KINETIS/RT-MCHCK-K20-SPI/mcuconf.h b/demos/KINETIS/RT-MCHCK-K20-SPI/mcuconf.h new file mode 100644 index 000000000..5177e0729 --- /dev/null +++ b/demos/KINETIS/RT-MCHCK-K20-SPI/mcuconf.h @@ -0,0 +1,65 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#define K20x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+
+/* Select the MCU clocking mode below by enabling the appropriate block. */
+
+#define KINETIS_NO_INIT FALSE
+
+/* FEI mode - 48 MHz with internal 32.768 kHz crystal */
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
+#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+
+/* FEE mode - 24 MHz with external 32.768 kHz crystal */
+#if 0
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */
+#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
+#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
+#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */
+#define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */
+#define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
+#endif /* 0 */
+
+/* FEE mode - 48 MHz */
+#if 0
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
+#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
+#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
+#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#endif /* 0 */
+
+/*
+ * SERIAL driver system settings.
+ */
+#define KINETIS_SERIAL_USE_UART0 TRUE
+
+/*
+ * SPI driver system settings.
+ */
+#define KINETIS_SPI_USE_SPI0 TRUE
+#define KINETIS_SPI_SPI0_IRQ_PRIORITY 8
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