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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2009-06-02 10:59:32 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2009-06-02 10:59:32 +0000 |
| commit | 1aa2773ad03807e3d5c9822ea108bc2e280281db (patch) | |
| tree | 80b497459a6236662487a0651c8b5164b7e7903f /demos/ARMCM3-STM32F103-GCC | |
| parent | 8020fc3d67244318840a337811f2f8a33185603a (diff) | |
| download | ChibiOS-1aa2773ad03807e3d5c9822ea108bc2e280281db.tar.gz ChibiOS-1aa2773ad03807e3d5c9822ea108bc2e280281db.tar.bz2 ChibiOS-1aa2773ad03807e3d5c9822ea108bc2e280281db.zip | |
STM32 initialization cleanup.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1015 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'demos/ARMCM3-STM32F103-GCC')
| -rw-r--r-- | demos/ARMCM3-STM32F103-GCC/board.c | 33 |
1 files changed, 16 insertions, 17 deletions
diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 7ce9248cd..2c73879f7 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -59,24 +59,23 @@ void hwinit0(void) { ;
/*
- * I/O ports initialization as specified in board.h.
+ * I/O ports initialization as specified in board.h. Note that being this
+ * a low level initialization routine it is OK to invoke directly the
+ * low level port functions.
*/
- ioport_init();
- GPIOA->CRL = VAL_GPIOACRL;
- GPIOA->CRH = VAL_GPIOACRH;
- GPIOA->ODR = VAL_GPIOAODR;
-
- GPIOB->CRL = VAL_GPIOBCRL;
- GPIOB->CRH = VAL_GPIOBCRH;
- GPIOB->ODR = VAL_GPIOBODR;
-
- GPIOC->CRL = VAL_GPIOCCRL;
- GPIOC->CRH = VAL_GPIOCCRH;
- GPIOC->ODR = VAL_GPIOCODR;
-
- GPIOD->CRL = VAL_GPIODCRL;
- GPIOD->CRH = VAL_GPIODCRH;
- GPIOD->ODR = VAL_GPIODODR;
+ ioport_init_lld();
+
+ ioport_stm32_setup_lld(IOPORT_A, VAL_GPIOACRH, VAL_GPIOACRL);
+ ioport_write_lld(IOPORT_A, VAL_GPIOAODR);
+
+ ioport_stm32_setup_lld(IOPORT_B, VAL_GPIOBCRH, VAL_GPIOBCRL);
+ ioport_write_lld(IOPORT_B, VAL_GPIOBODR);
+
+ ioport_stm32_setup_lld(IOPORT_C, VAL_GPIOCCRH, VAL_GPIOCCRL);
+ ioport_write_lld(IOPORT_C, VAL_GPIOCODR);
+
+ ioport_stm32_setup_lld(IOPORT_D, VAL_GPIODCRH, VAL_GPIODCRL);
+ ioport_write_lld(IOPORT_D, VAL_GPIODODR);
}
/*
|