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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-05-15 17:01:41 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-05-15 17:01:41 +0000
commite0b177423e1b14ab942fbf40b79d60d13ae02eb5 (patch)
treecf8a4b6ed8e6c67c9d541aabfba02a2dc63d4324 /boards
parent3654758ac274654c051e6b4f401b9a3d71326b83 (diff)
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Initial STM32F0xx support.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4198 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'boards')
-rw-r--r--boards/ST_STM32F0_DISCOVERY/board.c54
-rw-r--r--boards/ST_STM32F0_DISCOVERY/board.h321
-rw-r--r--boards/ST_STM32F0_DISCOVERY/board.mk5
3 files changed, 380 insertions, 0 deletions
diff --git a/boards/ST_STM32F0_DISCOVERY/board.c b/boards/ST_STM32F0_DISCOVERY/board.c
new file mode 100644
index 000000000..025050af4
--- /dev/null
+++ b/boards/ST_STM32F0_DISCOVERY/board.c
@@ -0,0 +1,54 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/boards/ST_STM32F0_DISCOVERY/board.h b/boards/ST_STM32F0_DISCOVERY/board.h
new file mode 100644
index 000000000..af811b057
--- /dev/null
+++ b/boards/ST_STM32F0_DISCOVERY/board.h
@@ -0,0 +1,321 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics STM32F0-Discovery board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM32L_DISCOVERY
+#define BOARD_NAME "ST STM32L-Discovery"
+
+/*
+ * Board frequencies.
+ * NOTE: The both crystals are not fitted by default on the board but there
+ * the option to both mount an 8MHz HE crystal or drive HSE with an
+ * 8MHz clock from the on-board ST-Link. LSE can be optionally mounted
+ * too.
+ */
+#if defined(DISCOVERY_HSE_MOUNTED) && defined(DISCOVERY_HSE_DRIVEN)
+#error "HSE OSC-IN cannot be both crystal equipped and externally driven"
+#endif
+
+#if defined(DISCOVERY_LSE_MOUNTED)
+#define STM32_LSECLK 32768
+#else
+#define STM32_LSECLK 0
+#endif
+
+#if defined(DISCOVERY_HSE_MOUNTED) || defined(DISCOVERY_HSE_DRIVEN)
+#define STM32_HSECLK 8000000
+#else
+#define STM32_HSECLK 0
+#endif
+
+#if defined(DISCOVERY_HSE_DRIVEN)
+#define STM32_HSE_BYPASS
+#endif
+
+/*
+ * MCU type as defined in the ST header file stm32f0xx.h.
+ */
+#define STM32F0XX
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON 0
+
+#define GPIOC_LED4 8
+#define GPIOC_LED3 9
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_400K(n) (0U << ((n) * 2))
+#define PIN_OSPEED_2M(n) (1U << ((n) * 2))
+#define PIN_OSPEED_10M(n) (2U << ((n) * 2))
+#define PIN_OSPEED_40M(n) (3U << ((n) * 2))
+#define PIN_PUDR_FLOATING(n) (0U << ((n) * 2))
+#define PIN_PUDR_PULLUP(n) (1U << ((n) * 2))
+#define PIN_PUDR_PULLDOWN(n) (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
+
+/*
+ * Port A setup.
+ * All input with pull-up except:
+ * PA0 - GPIOA_BUTTON (input floating).
+ * PA13 - JTMS/SWDAT (alternate 0).
+ * PA14 - JTCK/SWCLK (alternate 0).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \
+ PIN_MODE_INPUT(1) | \
+ PIN_MODE_INPUT(2) | \
+ PIN_MODE_INPUT(3) | \
+ PIN_MODE_INPUT(4) | \
+ PIN_MODE_INPUT(5) | \
+ PIN_MODE_INPUT(6) | \
+ PIN_MODE_INPUT(7) | \
+ PIN_MODE_INPUT(8) | \
+ PIN_MODE_INPUT(9) | \
+ PIN_MODE_INPUT(10) | \
+ PIN_MODE_INPUT(11) | \
+ PIN_MODE_INPUT(12) | \
+ PIN_MODE_ALTERNATE(13) | \
+ PIN_MODE_ALTERNATE(14) | \
+ PIN_MODE_INPUT(15))
+#define VAL_GPIOA_OTYPER 0x00000000
+#define VAL_GPIOA_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOA_PUPDR (PIN_PUDR_FLOATING(GPIOA_BUTTON) | \
+ PIN_PUDR_PULLUP(1) | \
+ PIN_PUDR_PULLUP(2) | \
+ PIN_PUDR_PULLUP(3) | \
+ PIN_PUDR_PULLUP(4) | \
+ PIN_PUDR_PULLUP(5) | \
+ PIN_PUDR_PULLUP(6) | \
+ PIN_PUDR_PULLUP(7) | \
+ PIN_PUDR_PULLUP(8) | \
+ PIN_PUDR_PULLUP(9) | \
+ PIN_PUDR_PULLUP(10) | \
+ PIN_PUDR_PULLUP(11) | \
+ PIN_PUDR_PULLUP(12) | \
+ PIN_PUDR_PULLUP(13) | \
+ PIN_PUDR_PULLUP(14) | \
+ PIN_PUDR_PULLUP(15))
+#define VAL_GPIOA_ODR 0xFFFFFFFF
+#define VAL_GPIOA_AFRL 0x00000000
+#define VAL_GPIOA_AFRH 0x00000000
+
+/*
+ * Port B setup.
+ * All input with pull-up except:
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_INPUT(0) | \
+ PIN_MODE_INPUT(1) | \
+ PIN_MODE_INPUT(2) | \
+ PIN_MODE_INPUT(3) | \
+ PIN_MODE_INPUT(4) | \
+ PIN_MODE_INPUT(5) | \
+ PIN_MODE_INPUT(6) | \
+ PIN_MODE_INPUT(7) | \
+ PIN_MODE_INPUT(8) | \
+ PIN_MODE_INPUT(9) | \
+ PIN_MODE_INPUT(10) | \
+ PIN_MODE_INPUT(11) | \
+ PIN_MODE_INPUT(12) | \
+ PIN_MODE_INPUT(13) | \
+ PIN_MODE_INPUT(14) | \
+ PIN_MODE_INPUT(15))
+#define VAL_GPIOB_OTYPER 0x00000000
+#define VAL_GPIOB_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOB_PUPDR (PIN_PUDR_PULLUP(0) | \
+ PIN_PUDR_PULLUP(1) | \
+ PIN_PUDR_PULLUP(2) | \
+ PIN_PUDR_PULLUP(3) | \
+ PIN_PUDR_PULLUP(4) | \
+ PIN_PUDR_PULLUP(5) | \
+ PIN_PUDR_PULLUP(6) | \
+ PIN_PUDR_PULLUP(7) | \
+ PIN_PUDR_PULLUP(8) | \
+ PIN_PUDR_PULLUP(9) | \
+ PIN_PUDR_PULLUP(10) | \
+ PIN_PUDR_PULLUP(11) | \
+ PIN_PUDR_PULLUP(12) | \
+ PIN_PUDR_PULLUP(13) | \
+ PIN_PUDR_PULLUP(14) | \
+ PIN_PUDR_PULLUP(15))
+#define VAL_GPIOB_ODR 0xFFFFFFFF
+#define VAL_GPIOB_AFRL 0x00000000
+#define VAL_GPIOB_AFRH 0x00000000
+
+/*
+ * Port C setup.
+ * All input with pull-up except:
+ * PC8 - GPIOC_LED4 (output push-pull).
+ * PC9 - GPIOC_LED3 (output push-pull).
+ * PC13 - OSC32_OUT (input floating).
+ * PC14 - OSC32_IN (input floating).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_INPUT(0) | \
+ PIN_MODE_INPUT(1) | \
+ PIN_MODE_INPUT(2) | \
+ PIN_MODE_INPUT(3) | \
+ PIN_MODE_INPUT(4) | \
+ PIN_MODE_INPUT(5) | \
+ PIN_MODE_INPUT(6) | \
+ PIN_MODE_INPUT(7) | \
+ PIN_MODE_OUTPUT(GPIOC_LED4) | \
+ PIN_MODE_OUTPUT(GPIOC_LED3) | \
+ PIN_MODE_INPUT(10) | \
+ PIN_MODE_INPUT(11) | \
+ PIN_MODE_INPUT(12) | \
+ PIN_MODE_INPUT(13) | \
+ PIN_MODE_INPUT(14) | \
+ PIN_MODE_INPUT(15))
+#define VAL_GPIOC_OTYPER 0x00000000
+#define VAL_GPIOC_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOC_PUPDR (PIN_PUDR_PULLUP(0) | \
+ PIN_PUDR_PULLUP(1) | \
+ PIN_PUDR_PULLUP(2) | \
+ PIN_PUDR_PULLUP(3) | \
+ PIN_PUDR_PULLUP(4) | \
+ PIN_PUDR_PULLUP(5) | \
+ PIN_PUDR_PULLUP(6) | \
+ PIN_PUDR_PULLUP(7) | \
+ PIN_PUDR_FLOATING(GPIOC_LED4) | \
+ PIN_PUDR_FLOATING(GPIOC_LED3) | \
+ PIN_PUDR_PULLUP(10) | \
+ PIN_PUDR_PULLUP(11) | \
+ PIN_PUDR_PULLUP(12) | \
+ PIN_PUDR_PULLUP(13) | \
+ PIN_PUDR_FLOATING(14) | \
+ PIN_PUDR_FLOATING(15))
+#define VAL_GPIOC_ODR 0xFFFFFCFF
+#define VAL_GPIOC_AFRL 0x00000000
+#define VAL_GPIOC_AFRH 0x00000000
+
+/*
+ * Port D setup.
+ * All input with pull-up.
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(0) | \
+ PIN_MODE_INPUT(1) | \
+ PIN_MODE_INPUT(2) | \
+ PIN_MODE_INPUT(3) | \
+ PIN_MODE_INPUT(4) | \
+ PIN_MODE_INPUT(5) | \
+ PIN_MODE_INPUT(6) | \
+ PIN_MODE_INPUT(7) | \
+ PIN_MODE_INPUT(8) | \
+ PIN_MODE_INPUT(9) | \
+ PIN_MODE_INPUT(10) | \
+ PIN_MODE_INPUT(11) | \
+ PIN_MODE_INPUT(12) | \
+ PIN_MODE_INPUT(13) | \
+ PIN_MODE_INPUT(14) | \
+ PIN_MODE_INPUT(15))
+#define VAL_GPIOD_OTYPER 0x00000000
+#define VAL_GPIOD_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOD_PUPDR (PIN_PUDR_PULLUP(0) | \
+ PIN_PUDR_PULLUP(1) | \
+ PIN_PUDR_PULLUP(2) | \
+ PIN_PUDR_PULLUP(3) | \
+ PIN_PUDR_PULLUP(4) | \
+ PIN_PUDR_PULLUP(5) | \
+ PIN_PUDR_PULLUP(6) | \
+ PIN_PUDR_PULLUP(7) | \
+ PIN_PUDR_PULLUP(8) | \
+ PIN_PUDR_PULLUP(9) | \
+ PIN_PUDR_PULLUP(10) | \
+ PIN_PUDR_PULLUP(11) | \
+ PIN_PUDR_PULLUP(12) | \
+ PIN_PUDR_PULLUP(13) | \
+ PIN_PUDR_PULLUP(14) | \
+ PIN_PUDR_PULLUP(15))
+#define VAL_GPIOD_ODR 0xFFFFFFFF
+#define VAL_GPIOD_AFRL 0x00000000
+#define VAL_GPIOD_AFRH 0x00000000
+
+/*
+ * Port F setup.
+ * All input with pull-up.
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(0) | \
+ PIN_MODE_INPUT(1) | \
+ PIN_MODE_INPUT(2) | \
+ PIN_MODE_INPUT(3) | \
+ PIN_MODE_INPUT(4) | \
+ PIN_MODE_INPUT(5) | \
+ PIN_MODE_INPUT(6) | \
+ PIN_MODE_INPUT(7) | \
+ PIN_MODE_INPUT(8) | \
+ PIN_MODE_INPUT(9) | \
+ PIN_MODE_INPUT(10) | \
+ PIN_MODE_INPUT(11) | \
+ PIN_MODE_INPUT(12) | \
+ PIN_MODE_INPUT(13) | \
+ PIN_MODE_INPUT(14) | \
+ PIN_MODE_INPUT(15))
+#define VAL_GPIOF_OTYPER 0x00000000
+#define VAL_GPIOF_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOF_PUPDR (PIN_PUDR_PULLUP(0) | \
+ PIN_PUDR_PULLUP(1) | \
+ PIN_PUDR_PULLUP(2) | \
+ PIN_PUDR_PULLUP(3) | \
+ PIN_PUDR_PULLUP(4) | \
+ PIN_PUDR_PULLUP(5) | \
+ PIN_PUDR_PULLUP(6) | \
+ PIN_PUDR_PULLUP(7) | \
+ PIN_PUDR_PULLUP(8) | \
+ PIN_PUDR_PULLUP(9) | \
+ PIN_PUDR_PULLUP(10) | \
+ PIN_PUDR_PULLUP(11) | \
+ PIN_PUDR_PULLUP(12) | \
+ PIN_PUDR_PULLUP(13) | \
+ PIN_PUDR_PULLUP(14) | \
+ PIN_PUDR_PULLUP(15))
+#define VAL_GPIOF_ODR 0xFFFFFFFF
+#define VAL_GPIOF_AFRL 0x00000000
+#define VAL_GPIOF_AFRH 0x00000000
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/ST_STM32F0_DISCOVERY/board.mk b/boards/ST_STM32F0_DISCOVERY/board.mk
new file mode 100644
index 000000000..144ae4963
--- /dev/null
+++ b/boards/ST_STM32F0_DISCOVERY/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/ST_STM32F0_DISCOVERY/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/ST_STM32F0_DISCOVERY
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