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authorbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2014-08-05 08:04:20 +0000
committerbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2014-08-05 08:04:20 +0000
commitff627a3d42795771e1d9ab4eb5c6fb8c0966974d (patch)
tree9ab1ab21e16244cb66756fe2a3443867b9ae9320
parent88a09ec74105c34e3eb66eb5ba84f0e448ce7a2a (diff)
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STM32 FSMC NAND. Added testhal
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7124 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat
-rw-r--r--os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c112
-rw-r--r--os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h1196
-rw-r--r--os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.mk5
-rw-r--r--testhal/STM32/STM32F4xx/FSMC_NAND/Makefile209
-rw-r--r--testhal/STM32/STM32F4xx/FSMC_NAND/chconf.h498
-rw-r--r--testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm.h17
-rw-r--r--testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm_adc.c115
-rw-r--r--testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm_spi.c90
-rw-r--r--testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm_uart.c144
-rw-r--r--testhal/STM32/STM32F4xx/FSMC_NAND/halconf.h346
-rw-r--r--testhal/STM32/STM32F4xx/FSMC_NAND/main.c607
-rw-r--r--testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf.h316
12 files changed, 3655 insertions, 0 deletions
diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c
new file mode 100644
index 000000000..fc5cc8220
--- /dev/null
+++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c
@@ -0,0 +1,112 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return TRUE;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return FALSE;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return TRUE;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return FALSE;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h
new file mode 100644
index 000000000..9c17972d0
--- /dev/null
+++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h
@@ -0,0 +1,1196 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics STM32F4-Discovery board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_NAME "NAND flash test board. Codename PNC"
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 32768
+#endif
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 8000000
+#endif
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD 300
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F40_41xxx
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_CTL_27V_P 0
+#define GPIOA_CTL_27V_N 1
+#define GPIOA_CTL_6V_P 2
+#define GPIOA_CTL_6V_N 3
+#define GPIOA_SPI1_NSS 4
+#define GPIOA_SPI1_SCK 5
+#define GPIOA_SPI1_MISO 6
+#define GPIOA_SPI1_MOSI 7
+#define GPIOA_TP1 8
+#define GPIOA_TX_MCU 9
+#define GPIOA_RX_MCU 10
+#define GPIOA_OTG_FS_DM 11
+#define GPIOA_OTG_FS_DP 12
+#define GPIOA_JTMS 13
+#define GPIOA_JTCK 14
+#define GPIOA_JTDI 15
+
+#define GPIOB_DATA_SENT_OUT 0
+#define GPIOB_SPI1_RST 1
+#define GPIOB_PIN2 2
+#define GPIOB_JTDO 3
+#define GPIOB_JTRST 4
+#define GPIOB_NAND_WP 5
+#define GPIOB_I2C1_SCL 6
+#define GPIOB_I2C1_SDA 7
+#define GPIOB_USB_DISCOVERY 8
+#define GPIOB_USB_PRESENT 9
+#define GPIOB_I2C2_SCL 10
+#define GPIOB_I2C2_SDA 11
+#define GPIOB_PIN12 12
+#define GPIOB_SPI2_CLK 13
+#define GPIOB_SPI2_MISO 14
+#define GPIOB_XSENS_EXTTRIG 15
+
+#define GPIOC_PIN0 0
+#define GPIOC_SPI3_CS1 1
+#define GPIOC_SPI3_CS2 2
+#define GPIOC_FLASH_CS 3
+#define GPIOC_SPI2_CS1 4
+#define GPIOC_SPI2_CS2 5
+#define GPIOC_XSENS_TX 6
+#define GPIOC_XSENS_RX 7
+#define GPIOC_MPU6050_CLK 8
+#define GPIOC_TP2 9
+#define GPIOC_FLASH_CLK 10
+#define GPIOC_FLASH_MISO 11
+#define GPIOC_FLASH_MOSI 12
+#define GPIOC_PPS_OUT 13
+#define GPIOC_PIN14 14
+#define GPIOC_PIN15 15
+
+#define GPIOD_NAND_IO2 0
+#define GPIOD_NAND_IO3 1
+#define GPIOD_PIN2 2
+#define GPIOD_PIN3 3
+#define GPIOD_NAND_RE 4
+#define GPIOD_NAND_WE 5
+#define GPIOD_NAND_RB 6
+#define GPIOD_NAND_CE 7
+#define GPIOD_PIN8 8
+#define GPIOD_PIN9 9
+#define GPIOD_PIN10 10
+#define GPIOD_NAND_CLE 11
+#define GPIOD_NAND_ALE 12
+#define GPIOD_PIN13 13
+#define GPIOD_NAND_IO0 14
+#define GPIOD_NAND_IO1 15
+
+#define GPIOE_MPU6050_INT1 0
+#define GPIOE_MPU6050_INT2 1
+#define GPIOE_PIN2 2
+#define GPIOE_SPI1_INT 3
+#define GPIOE_PPS_IN 4
+#define GPIOE_DATA_SENT_IN 5
+#define GPIOE_NAND_RB_INT 6
+#define GPIOE_NAND_IO4 7
+#define GPIOE_NAND_IO5 8
+#define GPIOE_NAND_IO6 9
+#define GPIOE_NAND_IO7 10
+#define GPIOE_LED_G 11
+#define GPIOE_LED_R 12
+#define GPIOE_FLASH_WP 13
+#define GPIOE_FLASH_RST 14
+#define GPIOE_PIN15 15
+
+#define GPIOF_PIN0 0
+#define GPIOF_PIN1 1
+#define GPIOF_PIN2 2
+#define GPIOF_PIN3 3
+#define GPIOF_PIN4 4
+#define GPIOF_PIN5 5
+#define GPIOF_PIN6 6
+#define GPIOF_PIN7 7
+#define GPIOF_PIN8 8
+#define GPIOF_PIN9 9
+#define GPIOF_PIN10 10
+#define GPIOF_PIN11 11
+#define GPIOF_PIN12 12
+#define GPIOF_PIN13 13
+#define GPIOF_PIN14 14
+#define GPIOF_PIN15 15
+
+#define GPIOG_PIN0 0
+#define GPIOG_PIN1 1
+#define GPIOG_PIN2 2
+#define GPIOG_PIN3 3
+#define GPIOG_PIN4 4
+#define GPIOG_PIN5 5
+#define GPIOG_PIN6 6
+#define GPIOG_PIN7 7
+#define GPIOG_PIN8 8
+#define GPIOG_PIN9 9
+#define GPIOG_PIN10 10
+#define GPIOG_PIN11 11
+#define GPIOG_PIN12 12
+#define GPIOG_PIN13 13
+#define GPIOG_PIN14 14
+#define GPIOG_PIN15 15
+
+#define GPIOH_OSC_IN 0
+#define GPIOH_OSC_OUT 1
+#define GPIOH_PIN2 2
+#define GPIOH_PIN3 3
+#define GPIOH_PIN4 4
+#define GPIOH_PIN5 5
+#define GPIOH_PIN6 6
+#define GPIOH_PIN7 7
+#define GPIOH_PIN8 8
+#define GPIOH_PIN9 9
+#define GPIOH_PIN10 10
+#define GPIOH_PIN11 11
+#define GPIOH_PIN12 12
+#define GPIOH_PIN13 13
+#define GPIOH_PIN14 14
+#define GPIOH_PIN15 15
+
+#define GPIOI_PIN0 0
+#define GPIOI_PIN1 1
+#define GPIOI_PIN2 2
+#define GPIOI_PIN3 3
+#define GPIOI_PIN4 4
+#define GPIOI_PIN5 5
+#define GPIOI_PIN6 6
+#define GPIOI_PIN7 7
+#define GPIOI_PIN8 8
+#define GPIOI_PIN9 9
+#define GPIOI_PIN10 10
+#define GPIOI_PIN11 11
+#define GPIOI_PIN12 12
+#define GPIOI_PIN13 13
+#define GPIOI_PIN14 14
+#define GPIOI_PIN15 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n) (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n) (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n) (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
+
+/*
+ * GPIOA setup:
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_CTL_27V_P) | \
+ PIN_MODE_ANALOG(GPIOA_CTL_27V_N) | \
+ PIN_MODE_ANALOG(GPIOA_CTL_6V_P) | \
+ PIN_MODE_ANALOG(GPIOA_CTL_6V_N) | \
+ PIN_MODE_OUTPUT(GPIOA_SPI1_NSS) | \
+ PIN_MODE_ALTERNATE(GPIOA_SPI1_SCK) | \
+ PIN_MODE_ALTERNATE(GPIOA_SPI1_MISO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SPI1_MOSI) | \
+ PIN_MODE_OUTPUT(GPIOA_TP1) | \
+ PIN_MODE_ALTERNATE(GPIOA_TX_MCU) | \
+ PIN_MODE_ALTERNATE(GPIOA_RX_MCU) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \
+ PIN_MODE_ALTERNATE(GPIOA_JTMS) | \
+ PIN_MODE_ALTERNATE(GPIOA_JTCK) | \
+ PIN_MODE_ALTERNATE(GPIOA_JTDI))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_CTL_27V_P) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_CTL_27V_N) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_CTL_6V_P) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_CTL_6V_N) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SPI1_NSS) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SPI1_SCK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MISO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MOSI) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_TP1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_TX_MCU) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_RX_MCU) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_JTMS) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_JTCK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_JTDI))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_2M(GPIOA_CTL_27V_P) | \
+ PIN_OSPEED_2M(GPIOA_CTL_27V_N) | \
+ PIN_OSPEED_2M(GPIOA_CTL_6V_P) | \
+ PIN_OSPEED_2M(GPIOA_CTL_6V_N) | \
+ PIN_OSPEED_50M(GPIOA_SPI1_NSS) | \
+ PIN_OSPEED_100M(GPIOA_SPI1_SCK) | \
+ PIN_OSPEED_100M(GPIOA_SPI1_MISO) | \
+ PIN_OSPEED_100M(GPIOA_SPI1_MOSI) | \
+ PIN_OSPEED_100M(GPIOA_TP1) | \
+ PIN_OSPEED_100M(GPIOA_TX_MCU) | \
+ PIN_OSPEED_100M(GPIOA_RX_MCU) | \
+ PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \
+ PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \
+ PIN_OSPEED_100M(GPIOA_JTMS) | \
+ PIN_OSPEED_100M(GPIOA_JTCK) | \
+ PIN_OSPEED_100M(GPIOA_JTDI))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_CTL_27V_P) | \
+ PIN_PUPDR_FLOATING(GPIOA_CTL_27V_N) | \
+ PIN_PUPDR_FLOATING(GPIOA_CTL_6V_P) | \
+ PIN_PUPDR_FLOATING(GPIOA_CTL_6V_N) | \
+ PIN_PUPDR_PULLUP(GPIOA_SPI1_NSS) | \
+ PIN_PUPDR_PULLUP(GPIOA_SPI1_SCK) | \
+ PIN_PUPDR_PULLUP(GPIOA_SPI1_MISO) | \
+ PIN_PUPDR_PULLUP(GPIOA_SPI1_MOSI) | \
+ PIN_PUPDR_PULLUP(GPIOA_TP1) | \
+ PIN_PUPDR_PULLUP(GPIOA_TX_MCU) | \
+ PIN_PUPDR_PULLUP(GPIOA_RX_MCU) | \
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \
+ PIN_PUPDR_FLOATING(GPIOA_JTMS) | \
+ PIN_PUPDR_FLOATING(GPIOA_JTCK) | \
+ PIN_PUPDR_FLOATING(GPIOA_JTDI))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_CTL_27V_P) | \
+ PIN_ODR_HIGH(GPIOA_CTL_27V_N) | \
+ PIN_ODR_HIGH(GPIOA_CTL_6V_P) | \
+ PIN_ODR_HIGH(GPIOA_CTL_6V_N) | \
+ PIN_ODR_HIGH(GPIOA_SPI1_NSS) | \
+ PIN_ODR_HIGH(GPIOA_SPI1_SCK) | \
+ PIN_ODR_HIGH(GPIOA_SPI1_MISO) | \
+ PIN_ODR_HIGH(GPIOA_SPI1_MOSI) | \
+ PIN_ODR_HIGH(GPIOA_TP1) | \
+ PIN_ODR_HIGH(GPIOA_TX_MCU) | \
+ PIN_ODR_HIGH(GPIOA_RX_MCU) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \
+ PIN_ODR_HIGH(GPIOA_JTMS) | \
+ PIN_ODR_HIGH(GPIOA_JTCK) | \
+ PIN_ODR_HIGH(GPIOA_JTDI))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_CTL_27V_P, 0) | \
+ PIN_AFIO_AF(GPIOA_CTL_27V_N, 0) | \
+ PIN_AFIO_AF(GPIOA_CTL_6V_P, 0) | \
+ PIN_AFIO_AF(GPIOA_CTL_6V_N, 0) | \
+ PIN_AFIO_AF(GPIOA_SPI1_NSS, 0) | \
+ PIN_AFIO_AF(GPIOA_SPI1_SCK, 5) | \
+ PIN_AFIO_AF(GPIOA_SPI1_MISO, 5) | \
+ PIN_AFIO_AF(GPIOA_SPI1_MOSI, 5))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_TP1, 0) | \
+ PIN_AFIO_AF(GPIOA_TX_MCU, 7) | \
+ PIN_AFIO_AF(GPIOA_RX_MCU, 7) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \
+ PIN_AFIO_AF(GPIOA_JTMS, 0) | \
+ PIN_AFIO_AF(GPIOA_JTCK, 0) | \
+ PIN_AFIO_AF(GPIOA_JTDI, 0))
+
+/*
+ * GPIOB setup:
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_DATA_SENT_OUT) | \
+ PIN_MODE_OUTPUT(GPIOB_SPI1_RST) | \
+ PIN_MODE_INPUT(GPIOB_PIN2) | \
+ PIN_MODE_ALTERNATE(GPIOB_JTDO) | \
+ PIN_MODE_ALTERNATE(GPIOB_JTRST) | \
+ PIN_MODE_OUTPUT(GPIOB_NAND_WP) | \
+ PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \
+ PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \
+ PIN_MODE_OUTPUT(GPIOB_USB_DISCOVERY) | \
+ PIN_MODE_INPUT(GPIOB_USB_PRESENT) | \
+ PIN_MODE_ALTERNATE(GPIOB_I2C2_SCL) | \
+ PIN_MODE_ALTERNATE(GPIOB_I2C2_SDA) | \
+ PIN_MODE_INPUT(GPIOB_PIN12) | \
+ PIN_MODE_ALTERNATE(GPIOB_SPI2_CLK) | \
+ PIN_MODE_ALTERNATE(GPIOB_SPI2_MISO) | \
+ PIN_MODE_INPUT(GPIOB_XSENS_EXTTRIG))
+
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_DATA_SENT_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SPI1_RST) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_JTDO) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_JTRST) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_NAND_WP) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_USB_DISCOVERY) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_USB_PRESENT) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_I2C2_SCL) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_I2C2_SDA) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SPI2_CLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SPI2_MISO) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_XSENS_EXTTRIG))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_2M(GPIOB_DATA_SENT_OUT) | \
+ PIN_OSPEED_2M(GPIOB_SPI1_RST) | \
+ PIN_OSPEED_100M(GPIOB_PIN2) | \
+ PIN_OSPEED_100M(GPIOB_JTDO) | \
+ PIN_OSPEED_100M(GPIOB_JTRST) | \
+ PIN_OSPEED_2M(GPIOB_NAND_WP) | \
+ PIN_OSPEED_2M(GPIOB_I2C1_SCL) | \
+ PIN_OSPEED_2M(GPIOB_I2C1_SDA) | \
+ PIN_OSPEED_2M(GPIOB_USB_DISCOVERY) | \
+ PIN_OSPEED_2M(GPIOB_USB_PRESENT) | \
+ PIN_OSPEED_2M(GPIOB_I2C2_SCL) | \
+ PIN_OSPEED_2M(GPIOB_I2C2_SDA) | \
+ PIN_OSPEED_100M(GPIOB_PIN12) | \
+ PIN_OSPEED_100M(GPIOB_SPI2_CLK) | \
+ PIN_OSPEED_100M(GPIOB_SPI2_MISO) | \
+ PIN_OSPEED_100M(GPIOB_XSENS_EXTTRIG))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_DATA_SENT_OUT) | \
+ PIN_PUPDR_PULLDOWN(GPIOB_SPI1_RST) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOB_JTDO) | \
+ PIN_PUPDR_FLOATING(GPIOB_JTRST) | \
+ PIN_PUPDR_PULLDOWN(GPIOB_NAND_WP) | \
+ PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \
+ PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \
+ PIN_PUPDR_FLOATING(GPIOB_USB_DISCOVERY) | \
+ PIN_PUPDR_FLOATING(GPIOB_USB_PRESENT) | \
+ PIN_PUPDR_FLOATING(GPIOB_I2C2_SCL) | \
+ PIN_PUPDR_FLOATING(GPIOB_I2C2_SDA) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOB_SPI2_CLK) | \
+ PIN_PUPDR_PULLUP(GPIOB_SPI2_MISO) | \
+ PIN_PUPDR_PULLUP(GPIOB_XSENS_EXTTRIG))
+#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_DATA_SENT_OUT) | \
+ PIN_ODR_LOW(GPIOB_SPI1_RST) | \
+ PIN_ODR_HIGH(GPIOB_PIN2) | \
+ PIN_ODR_HIGH(GPIOB_JTDO) | \
+ PIN_ODR_HIGH(GPIOB_JTRST) | \
+ PIN_ODR_LOW(GPIOB_NAND_WP) | \
+ PIN_ODR_LOW(GPIOB_I2C1_SCL) | \
+ PIN_ODR_LOW(GPIOB_I2C1_SDA) | \
+ PIN_ODR_HIGH(GPIOB_USB_DISCOVERY) | \
+ PIN_ODR_HIGH(GPIOB_USB_PRESENT) | \
+ PIN_ODR_LOW(GPIOB_I2C2_SCL) | \
+ PIN_ODR_LOW(GPIOB_I2C2_SDA) | \
+ PIN_ODR_HIGH(GPIOB_PIN12) | \
+ PIN_ODR_HIGH(GPIOB_SPI2_CLK) | \
+ PIN_ODR_HIGH(GPIOB_SPI2_MISO) | \
+ PIN_ODR_HIGH(GPIOB_XSENS_EXTTRIG))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_DATA_SENT_OUT, 0) | \
+ PIN_AFIO_AF(GPIOB_SPI1_RST, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOB_JTDO, 0) | \
+ PIN_AFIO_AF(GPIOB_JTRST, 0) | \
+ PIN_AFIO_AF(GPIOB_NAND_WP, 0) | \
+ PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) | \
+ PIN_AFIO_AF(GPIOB_I2C1_SDA, 4))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_USB_DISCOVERY, 0) | \
+ PIN_AFIO_AF(GPIOB_USB_PRESENT, 0) | \
+ PIN_AFIO_AF(GPIOB_I2C2_SCL, 4) | \
+ PIN_AFIO_AF(GPIOB_I2C2_SDA, 4) | \
+ PIN_AFIO_AF(GPIOB_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOB_SPI2_CLK, 5) | \
+ PIN_AFIO_AF(GPIOB_SPI2_MISO, 5) | \
+ PIN_AFIO_AF(GPIOB_XSENS_EXTTRIG, 0))
+
+/*
+ * GPIOC setup:
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_PIN0) |\
+ PIN_MODE_OUTPUT(GPIOC_SPI3_CS1) | \
+ PIN_MODE_OUTPUT(GPIOC_SPI3_CS2) | \
+ PIN_MODE_OUTPUT(GPIOC_FLASH_CS) | \
+ PIN_MODE_OUTPUT(GPIOC_SPI2_CS1) | \
+ PIN_MODE_OUTPUT(GPIOC_SPI2_CS2) | \
+ PIN_MODE_ALTERNATE(GPIOC_XSENS_TX) | \
+ PIN_MODE_ALTERNATE(GPIOC_XSENS_RX) | \
+ PIN_MODE_ALTERNATE(GPIOC_MPU6050_CLK) | \
+ PIN_MODE_OUTPUT(GPIOC_TP2) | \
+ PIN_MODE_ALTERNATE(GPIOC_FLASH_CLK) | \
+ PIN_MODE_ALTERNATE(GPIOC_FLASH_MISO) | \
+ PIN_MODE_ALTERNATE(GPIOC_FLASH_MOSI) | \
+ PIN_MODE_OUTPUT(GPIOC_PPS_OUT) | \
+ PIN_MODE_INPUT(GPIOC_PIN14) | \
+ PIN_MODE_INPUT(GPIOC_PIN15))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) |\
+ PIN_OTYPE_PUSHPULL(GPIOC_SPI3_CS1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SPI3_CS2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_FLASH_CS) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SPI2_CS1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SPI2_CS2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_XSENS_TX) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_XSENS_RX) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_MPU6050_CLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_TP2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_FLASH_CLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_FLASH_MISO) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_FLASH_MOSI) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PPS_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_2M(GPIOC_PIN0) |\
+ PIN_OSPEED_2M(GPIOC_SPI3_CS1) | \
+ PIN_OSPEED_2M(GPIOC_SPI3_CS2) | \
+ PIN_OSPEED_2M(GPIOC_FLASH_CS) | \
+ PIN_OSPEED_2M(GPIOC_SPI2_CS1) | \
+ PIN_OSPEED_2M(GPIOC_SPI2_CS2) | \
+ PIN_OSPEED_2M(GPIOC_XSENS_TX) | \
+ PIN_OSPEED_2M(GPIOC_XSENS_RX) | \
+ PIN_OSPEED_100M(GPIOC_MPU6050_CLK) | \
+ PIN_OSPEED_100M(GPIOC_TP2) | \
+ PIN_OSPEED_100M(GPIOC_FLASH_CLK) | \
+ PIN_OSPEED_100M(GPIOC_FLASH_MISO) | \
+ PIN_OSPEED_100M(GPIOC_FLASH_MOSI) | \
+ PIN_OSPEED_100M(GPIOC_PPS_OUT) | \
+ PIN_OSPEED_100M(GPIOC_PIN14) | \
+ PIN_OSPEED_100M(GPIOC_PIN15))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) |\
+ PIN_PUPDR_PULLUP(GPIOC_SPI3_CS1) | \
+ PIN_PUPDR_PULLUP(GPIOC_SPI3_CS2) | \
+ PIN_PUPDR_PULLUP(GPIOC_FLASH_CS) | \
+ PIN_PUPDR_PULLUP(GPIOC_SPI2_CS1) | \
+ PIN_PUPDR_PULLUP(GPIOC_SPI2_CS2) | \
+ PIN_PUPDR_PULLUP(GPIOC_XSENS_TX) | \
+ PIN_PUPDR_PULLUP(GPIOC_XSENS_RX) | \
+ PIN_PUPDR_PULLUP(GPIOC_MPU6050_CLK) | \
+ PIN_PUPDR_PULLUP(GPIOC_TP2) | \
+ PIN_PUPDR_PULLUP(GPIOC_FLASH_CLK) | \
+ PIN_PUPDR_PULLUP(GPIOC_FLASH_MISO) | \
+ PIN_PUPDR_PULLUP(GPIOC_FLASH_MOSI) | \
+ PIN_PUPDR_PULLUP(GPIOC_PPS_OUT) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN15))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \
+ PIN_ODR_HIGH(GPIOC_SPI3_CS1) | \
+ PIN_ODR_HIGH(GPIOC_SPI3_CS2) | \
+ PIN_ODR_HIGH(GPIOC_FLASH_CS) | \
+ PIN_ODR_HIGH(GPIOC_SPI2_CS1) | \
+ PIN_ODR_HIGH(GPIOC_SPI2_CS2) | \
+ PIN_ODR_HIGH(GPIOC_XSENS_TX) | \
+ PIN_ODR_HIGH(GPIOC_XSENS_RX) | \
+ PIN_ODR_HIGH(GPIOC_MPU6050_CLK) | \
+ PIN_ODR_HIGH(GPIOC_TP2) | \
+ PIN_ODR_HIGH(GPIOC_FLASH_CLK) | \
+ PIN_ODR_HIGH(GPIOC_FLASH_MISO) | \
+ PIN_ODR_HIGH(GPIOC_FLASH_MOSI) | \
+ PIN_ODR_HIGH(GPIOC_PPS_OUT) | \
+ PIN_ODR_HIGH(GPIOC_PIN14) | \
+ PIN_ODR_HIGH(GPIOC_PIN15))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) |\
+ PIN_AFIO_AF(GPIOC_SPI3_CS1, 0) | \
+ PIN_AFIO_AF(GPIOC_SPI3_CS2, 0) | \
+ PIN_AFIO_AF(GPIOC_FLASH_CS, 0) | \
+ PIN_AFIO_AF(GPIOC_SPI2_CS1, 0) | \
+ PIN_AFIO_AF(GPIOC_SPI2_CS2, 0) | \
+ PIN_AFIO_AF(GPIOC_XSENS_TX, 8) | \
+ PIN_AFIO_AF(GPIOC_XSENS_RX, 8))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_MPU6050_CLK, 2) | \
+ PIN_AFIO_AF(GPIOC_TP2, 0) | \
+ PIN_AFIO_AF(GPIOC_FLASH_CLK, 6) | \
+ PIN_AFIO_AF(GPIOC_FLASH_MISO, 6) | \
+ PIN_AFIO_AF(GPIOC_FLASH_MOSI, 6) | \
+ PIN_AFIO_AF(GPIOC_PPS_OUT, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN15, 0))
+
+/*
+ * GPIOD setup:
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_NAND_IO2) | \
+ PIN_MODE_ALTERNATE(GPIOD_NAND_IO3) | \
+ PIN_MODE_INPUT(GPIOD_PIN2) | \
+ PIN_MODE_INPUT(GPIOD_PIN3) | \
+ PIN_MODE_ALTERNATE(GPIOD_NAND_RE) | \
+ PIN_MODE_ALTERNATE(GPIOD_NAND_WE) | \
+ PIN_MODE_INPUT(GPIOD_NAND_RB) | \
+ PIN_MODE_ALTERNATE(GPIOD_NAND_CE) | \
+ PIN_MODE_INPUT(GPIOD_PIN8) | \
+ PIN_MODE_INPUT(GPIOD_PIN9) | \
+ PIN_MODE_INPUT(GPIOD_PIN10) | \
+ PIN_MODE_ALTERNATE(GPIOD_NAND_CLE) | \
+ PIN_MODE_ALTERNATE(GPIOD_NAND_ALE) | \
+ PIN_MODE_INPUT(GPIOD_PIN13) | \
+ PIN_MODE_ALTERNATE(GPIOD_NAND_IO0) | \
+ PIN_MODE_ALTERNATE(GPIOD_NAND_IO1))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_NAND_IO2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_NAND_IO3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_NAND_RE) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_NAND_WE) |\
+ PIN_OTYPE_PUSHPULL(GPIOD_NAND_RB) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_NAND_CE) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_NAND_CLE) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_NAND_ALE) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_NAND_IO0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_NAND_IO1))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_NAND_IO2) | \
+ PIN_OSPEED_100M(GPIOD_NAND_IO3) | \
+ PIN_OSPEED_100M(GPIOD_PIN2) | \
+ PIN_OSPEED_100M(GPIOD_PIN3) | \
+ PIN_OSPEED_100M(GPIOD_NAND_RE) | \
+ PIN_OSPEED_100M(GPIOD_NAND_WE) | \
+ PIN_OSPEED_100M(GPIOD_NAND_RB) | \
+ PIN_OSPEED_100M(GPIOD_NAND_CE) | \
+ PIN_OSPEED_100M(GPIOD_PIN8) | \
+ PIN_OSPEED_100M(GPIOD_PIN9) | \
+ PIN_OSPEED_100M(GPIOD_PIN10) | \
+ PIN_OSPEED_100M(GPIOD_NAND_CLE) | \
+ PIN_OSPEED_100M(GPIOD_NAND_ALE) | \
+ PIN_OSPEED_100M(GPIOD_PIN13) | \
+ PIN_OSPEED_100M(GPIOD_NAND_IO0) | \
+ PIN_OSPEED_100M(GPIOD_NAND_IO1))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_NAND_IO2) | \
+ PIN_PUPDR_PULLUP(GPIOD_NAND_IO3) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOD_NAND_RE) | \
+ PIN_PUPDR_PULLUP(GPIOD_NAND_WE) |\
+ PIN_PUPDR_PULLUP(GPIOD_NAND_RB) | \
+ PIN_PUPDR_PULLUP(GPIOD_NAND_CE) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOD_NAND_CLE) | \
+ PIN_PUPDR_PULLUP(GPIOD_NAND_ALE) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOD_NAND_IO0) | \
+ PIN_PUPDR_PULLUP(GPIOD_NAND_IO1))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_NAND_IO2) | \
+ PIN_ODR_HIGH(GPIOD_NAND_IO3) | \
+ PIN_ODR_HIGH(GPIOD_PIN2) | \
+ PIN_ODR_HIGH(GPIOD_PIN3) | \
+ PIN_ODR_HIGH(GPIOD_NAND_RE) | \
+ PIN_ODR_HIGH(GPIOD_NAND_WE) | \
+ PIN_ODR_HIGH(GPIOD_NAND_RB) | \
+ PIN_ODR_HIGH(GPIOD_NAND_CE) | \
+ PIN_ODR_HIGH(GPIOD_PIN8) | \
+ PIN_ODR_HIGH(GPIOD_PIN9) | \
+ PIN_ODR_HIGH(GPIOD_PIN10) | \
+ PIN_ODR_HIGH(GPIOD_NAND_CLE) | \
+ PIN_ODR_HIGH(GPIOD_NAND_ALE) | \
+ PIN_ODR_HIGH(GPIOD_PIN13) | \
+ PIN_ODR_HIGH(GPIOD_NAND_IO0) | \
+ PIN_ODR_HIGH(GPIOD_NAND_IO1))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_NAND_IO2, 12) | \
+ PIN_AFIO_AF(GPIOD_NAND_IO3, 12) | \
+ PIN_AFIO_AF(GPIOD_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOD_NAND_RE, 12) | \
+ PIN_AFIO_AF(GPIOD_NAND_WE, 12) | \
+ PIN_AFIO_AF(GPIOD_NAND_RB, 0) | \
+ PIN_AFIO_AF(GPIOD_NAND_CE, 12))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOD_NAND_CLE, 12) | \
+ PIN_AFIO_AF(GPIOD_NAND_ALE, 12) | \
+ PIN_AFIO_AF(GPIOD_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOD_NAND_IO0, 12) | \
+ PIN_AFIO_AF(GPIOD_NAND_IO1, 12))
+
+/*
+ * GPIOE setup:
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_MPU6050_INT1) | \
+ PIN_MODE_INPUT(GPIOE_MPU6050_INT2) | \
+ PIN_MODE_INPUT(GPIOE_PIN2) | \
+ PIN_MODE_INPUT(GPIOE_SPI1_INT) | \
+ PIN_MODE_INPUT(GPIOE_PPS_IN) | \
+ PIN_MODE_INPUT(GPIOE_DATA_SENT_IN) | \
+ PIN_MODE_INPUT(GPIOE_NAND_RB_INT) | \
+ PIN_MODE_ALTERNATE(GPIOE_NAND_IO4) | \
+ PIN_MODE_ALTERNATE(GPIOE_NAND_IO5) | \
+ PIN_MODE_ALTERNATE(GPIOE_NAND_IO6) | \
+ PIN_MODE_ALTERNATE(GPIOE_NAND_IO7) | \
+ PIN_MODE_OUTPUT(GPIOE_LED_R) | \
+ PIN_MODE_OUTPUT(GPIOE_LED_G) | \
+ PIN_MODE_ALTERNATE(GPIOE_FLASH_WP) | \
+ PIN_MODE_ALTERNATE(GPIOE_FLASH_RST) | \
+ PIN_MODE_INPUT(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_MPU6050_INT1) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_MPU6050_INT2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_SPI1_INT) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PPS_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_DATA_SENT_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_NAND_RB_INT) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_NAND_IO4) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_NAND_IO5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_NAND_IO6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_NAND_IO7) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_LED_R) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_LED_G) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_FLASH_WP) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_FLASH_RST) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_MPU6050_INT1) | \
+ PIN_OSPEED_100M(GPIOE_MPU6050_INT2) | \
+ PIN_OSPEED_100M(GPIOE_PIN2) | \
+ PIN_OSPEED_100M(GPIOE_SPI1_INT) | \
+ PIN_OSPEED_100M(GPIOE_PPS_IN) | \
+ PIN_OSPEED_100M(GPIOE_DATA_SENT_IN) | \
+ PIN_OSPEED_100M(GPIOE_NAND_RB_INT) | \
+ PIN_OSPEED_100M(GPIOE_NAND_IO4) | \
+ PIN_OSPEED_100M(GPIOE_NAND_IO5) | \
+ PIN_OSPEED_100M(GPIOE_NAND_IO6) | \
+ PIN_OSPEED_100M(GPIOE_NAND_IO7) | \
+ PIN_OSPEED_2M(GPIOE_LED_R) | \
+ PIN_OSPEED_2M(GPIOE_LED_G) | \
+ PIN_OSPEED_2M(GPIOE_FLASH_WP) | \
+ PIN_OSPEED_2M(GPIOE_FLASH_RST) | \
+ PIN_OSPEED_100M(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLDOWN(GPIOE_MPU6050_INT1) | \
+ PIN_PUPDR_PULLDOWN(GPIOE_MPU6050_INT2) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOE_SPI1_INT) | \
+ PIN_PUPDR_PULLUP(GPIOE_PPS_IN) | \
+ PIN_PUPDR_PULLUP(GPIOE_DATA_SENT_IN) | \
+ PIN_PUPDR_PULLUP(GPIOE_NAND_RB_INT) | \
+ PIN_PUPDR_PULLUP(GPIOE_NAND_IO4) | \
+ PIN_PUPDR_PULLUP(GPIOE_NAND_IO5) | \
+ PIN_PUPDR_PULLUP(GPIOE_NAND_IO6) | \
+ PIN_PUPDR_PULLUP(GPIOE_NAND_IO7) | \
+ PIN_PUPDR_PULLDOWN(GPIOE_LED_R) | \
+ PIN_PUPDR_PULLDOWN(GPIOE_LED_G) | \
+ PIN_PUPDR_PULLUP(GPIOE_FLASH_WP) | \
+ PIN_PUPDR_PULLUP(GPIOE_FLASH_RST) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN15))
+#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_MPU6050_INT1) | \
+ PIN_ODR_HIGH(GPIOE_MPU6050_INT2) | \
+ PIN_ODR_HIGH(GPIOE_PIN2) | \
+ PIN_ODR_HIGH(GPIOE_SPI1_INT) | \
+ PIN_ODR_HIGH(GPIOE_PPS_IN) | \
+ PIN_ODR_HIGH(GPIOE_DATA_SENT_IN) | \
+ PIN_ODR_HIGH(GPIOE_NAND_RB_INT) | \
+ PIN_ODR_HIGH(GPIOE_NAND_IO4) | \
+ PIN_ODR_HIGH(GPIOE_NAND_IO5) | \
+ PIN_ODR_HIGH(GPIOE_NAND_IO6) | \
+ PIN_ODR_HIGH(GPIOE_NAND_IO7) | \
+ PIN_ODR_LOW(GPIOE_LED_R) | \
+ PIN_ODR_LOW(GPIOE_LED_G) | \
+ PIN_ODR_HIGH(GPIOE_FLASH_WP) | \
+ PIN_ODR_HIGH(GPIOE_FLASH_RST) | \
+ PIN_ODR_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_MPU6050_INT1, 0) | \
+ PIN_AFIO_AF(GPIOE_MPU6050_INT2, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOE_SPI1_INT, 0) | \
+ PIN_AFIO_AF(GPIOE_PPS_IN, 0) | \
+ PIN_AFIO_AF(GPIOE_DATA_SENT_IN, 0) | \
+ PIN_AFIO_AF(GPIOE_NAND_RB_INT, 0) | \
+ PIN_AFIO_AF(GPIOE_NAND_IO4, 12))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_NAND_IO5, 12) | \
+ PIN_AFIO_AF(GPIOE_NAND_IO6, 12) | \
+ PIN_AFIO_AF(GPIOE_NAND_IO7, 12) | \
+ PIN_AFIO_AF(GPIOE_LED_R, 0) | \
+ PIN_AFIO_AF(GPIOE_LED_G, 0) | \
+ PIN_AFIO_AF(GPIOE_FLASH_WP, 0) | \
+ PIN_AFIO_AF(GPIOE_FLASH_RST, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN15, 0))
+
+/*
+ * GPIOF setup:
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \
+ PIN_MODE_INPUT(GPIOF_PIN1) | \
+ PIN_MODE_INPUT(GPIOF_PIN2) | \
+ PIN_MODE_INPUT(GPIOF_PIN3) | \
+ PIN_MODE_INPUT(GPIOF_PIN4) | \
+ PIN_MODE_INPUT(GPIOF_PIN5) | \
+ PIN_MODE_INPUT(GPIOF_PIN6) | \
+ PIN_MODE_INPUT(GPIOF_PIN7) | \
+ PIN_MODE_INPUT(GPIOF_PIN8) | \
+ PIN_MODE_INPUT(GPIOF_PIN9) | \
+ PIN_MODE_INPUT(GPIOF_PIN10) | \
+ PIN_MODE_INPUT(GPIOF_PIN11) | \
+ PIN_MODE_INPUT(GPIOF_PIN12) | \
+ PIN_MODE_INPUT(GPIOF_PIN13) | \
+ PIN_MODE_INPUT(GPIOF_PIN14) | \
+ PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_PIN0) | \
+ PIN_OSPEED_100M(GPIOF_PIN1) | \
+ PIN_OSPEED_100M(GPIOF_PIN2) | \
+ PIN_OSPEED_100M(GPIOF_PIN3) | \
+ PIN_OSPEED_100M(GPIOF_PIN4) | \
+ PIN_OSPEED_100M(GPIOF_PIN5) | \
+ PIN_OSPEED_100M(GPIOF_PIN6) | \
+ PIN_OSPEED_100M(GPIOF_PIN7) | \
+ PIN_OSPEED_100M(GPIOF_PIN8) | \
+ PIN_OSPEED_100M(GPIOF_PIN9) | \
+ PIN_OSPEED_100M(GPIOF_PIN10) | \
+ PIN_OSPEED_100M(GPIOF_PIN11) | \
+ PIN_OSPEED_100M(GPIOF_PIN12) | \
+ PIN_OSPEED_100M(GPIOF_PIN13) | \
+ PIN_OSPEED_100M(GPIOF_PIN14) | \
+ PIN_OSPEED_100M(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN15))
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \
+ PIN_ODR_HIGH(GPIOF_PIN1) | \
+ PIN_ODR_HIGH(GPIOF_PIN2) | \
+ PIN_ODR_HIGH(GPIOF_PIN3) | \
+ PIN_ODR_HIGH(GPIOF_PIN4) | \
+ PIN_ODR_HIGH(GPIOF_PIN5) | \
+ PIN_ODR_HIGH(GPIOF_PIN6) | \
+ PIN_ODR_HIGH(GPIOF_PIN7) | \
+ PIN_ODR_HIGH(GPIOF_PIN8) | \
+ PIN_ODR_HIGH(GPIOF_PIN9) | \
+ PIN_ODR_HIGH(GPIOF_PIN10) | \
+ PIN_ODR_HIGH(GPIOF_PIN11) | \
+ PIN_ODR_HIGH(GPIOF_PIN12) | \
+ PIN_ODR_HIGH(GPIOF_PIN13) | \
+ PIN_ODR_HIGH(GPIOF_PIN14) | \
+ PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN7, 0))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN15, 0))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0 - PIN0 (input floating).
+ * PG1 - PIN1 (input floating).
+ * PG2 - PIN2 (input floating).
+ * PG3 - PIN3 (input floating).
+ * PG4 - PIN4 (input floating).
+ * PG5 - PIN5 (input floating).
+ * PG6 - PIN6 (input floating).
+ * PG7 - PIN7 (input floating).
+ * PG8 - PIN8 (input floating).
+ * PG9 - PIN9 (input floating).
+ * PG10 - PIN10 (input floating).
+ * PG11 - PIN11 (input floating).
+ * PG12 - PIN12 (input floating).
+ * PG13 - PIN13 (input floating).
+ * PG14 - PIN14 (input floating).
+ * PG15 - PIN15 (input floating).
+ */
+#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \
+ PIN_MODE_INPUT(GPIOG_PIN1) | \
+ PIN_MODE_INPUT(GPIOG_PIN2) | \
+ PIN_MODE_INPUT(GPIOG_PIN3) | \
+ PIN_MODE_INPUT(GPIOG_PIN4) | \
+ PIN_MODE_INPUT(GPIOG_PIN5) | \
+ PIN_MODE_INPUT(GPIOG_PIN6) | \
+ PIN_MODE_INPUT(GPIOG_PIN7) | \
+ PIN_MODE_INPUT(GPIOG_PIN8) | \
+ PIN_MODE_INPUT(GPIOG_PIN9) | \
+ PIN_MODE_INPUT(GPIOG_PIN10) | \
+ PIN_MODE_INPUT(GPIOG_PIN11) | \
+ PIN_MODE_INPUT(GPIOG_PIN12) | \
+ PIN_MODE_INPUT(GPIOG_PIN13) | \
+ PIN_MODE_INPUT(GPIOG_PIN14) | \
+ PIN_MODE_INPUT(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_PIN0) | \
+ PIN_OSPEED_100M(GPIOG_PIN1) | \
+ PIN_OSPEED_100M(GPIOG_PIN2) | \
+ PIN_OSPEED_100M(GPIOG_PIN3) | \
+ PIN_OSPEED_100M(GPIOG_PIN4) | \
+ PIN_OSPEED_100M(GPIOG_PIN5) | \
+ PIN_OSPEED_100M(GPIOG_PIN6) | \
+ PIN_OSPEED_100M(GPIOG_PIN7) | \
+ PIN_OSPEED_100M(GPIOG_PIN8) | \
+ PIN_OSPEED_100M(GPIOG_PIN9) | \
+ PIN_OSPEED_100M(GPIOG_PIN10) | \
+ PIN_OSPEED_100M(GPIOG_PIN11) | \
+ PIN_OSPEED_100M(GPIOG_PIN12) | \
+ PIN_OSPEED_100M(GPIOG_PIN13) | \
+ PIN_OSPEED_100M(GPIOG_PIN14) | \
+ PIN_OSPEED_100M(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN15))
+#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \
+ PIN_ODR_HIGH(GPIOG_PIN1) | \
+ PIN_ODR_HIGH(GPIOG_PIN2) | \
+ PIN_ODR_HIGH(GPIOG_PIN3) | \
+ PIN_ODR_HIGH(GPIOG_PIN4) | \
+ PIN_ODR_HIGH(GPIOG_PIN5) | \
+ PIN_ODR_HIGH(GPIOG_PIN6) | \
+ PIN_ODR_HIGH(GPIOG_PIN7) | \
+ PIN_ODR_HIGH(GPIOG_PIN8) | \
+ PIN_ODR_HIGH(GPIOG_PIN9) | \
+ PIN_ODR_HIGH(GPIOG_PIN10) | \
+ PIN_ODR_HIGH(GPIOG_PIN11) | \
+ PIN_ODR_HIGH(GPIOG_PIN12) | \
+ PIN_ODR_HIGH(GPIOG_PIN13) | \
+ PIN_ODR_HIGH(GPIOG_PIN14) | \
+ PIN_ODR_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN7, 0))
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN15, 0))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0 - OSC_IN (input floating).
+ * PH1 - OSC_OUT (input floating).
+ * PH2 - PIN2 (input floating).
+ * PH3 - PIN3 (input floating).
+ * PH4 - PIN4 (input floating).
+ * PH5 - PIN5 (input floating).
+ * PH6 - PIN6 (input floating).
+ * PH7 - PIN7 (input floating).
+ * PH8 - PIN8 (input floating).
+ * PH9 - PIN9 (input floating).
+ * PH10 - PIN10 (input floating).
+ * PH11 - PIN11 (input floating).
+ * PH12 - PIN12 (input floating).
+ * PH13 - PIN13 (input floating).
+ * PH14 - PIN14 (input floating).
+ * PH15 - PIN15 (input floating).
+ */
+#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
+ PIN_MODE_INPUT(GPIOH_PIN2) | \
+ PIN_MODE_INPUT(GPIOH_PIN3) | \
+ PIN_MODE_INPUT(GPIOH_PIN4) | \
+ PIN_MODE_INPUT(GPIOH_PIN5) | \
+ PIN_MODE_INPUT(GPIOH_PIN6) | \
+ PIN_MODE_INPUT(GPIOH_PIN7) | \
+ PIN_MODE_INPUT(GPIOH_PIN8) | \
+ PIN_MODE_INPUT(GPIOH_PIN9) | \
+ PIN_MODE_INPUT(GPIOH_PIN10) | \
+ PIN_MODE_INPUT(GPIOH_PIN11) | \
+ PIN_MODE_INPUT(GPIOH_PIN12) | \
+ PIN_MODE_INPUT(GPIOH_PIN13) | \
+ PIN_MODE_INPUT(GPIOH_PIN14) | \
+ PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(GPIOH_OSC_IN) | \
+ PIN_OSPEED_100M(GPIOH_OSC_OUT) | \
+ PIN_OSPEED_100M(GPIOH_PIN2) | \
+ PIN_OSPEED_100M(GPIOH_PIN3) | \
+ PIN_OSPEED_100M(GPIOH_PIN4) | \
+ PIN_OSPEED_100M(GPIOH_PIN5) | \
+ PIN_OSPEED_100M(GPIOH_PIN6) | \
+ PIN_OSPEED_100M(GPIOH_PIN7) | \
+ PIN_OSPEED_100M(GPIOH_PIN8) | \
+ PIN_OSPEED_100M(GPIOH_PIN9) | \
+ PIN_OSPEED_100M(GPIOH_PIN10) | \
+ PIN_OSPEED_100M(GPIOH_PIN11) | \
+ PIN_OSPEED_100M(GPIOH_PIN12) | \
+ PIN_OSPEED_100M(GPIOH_PIN13) | \
+ PIN_OSPEED_100M(GPIOH_PIN14) | \
+ PIN_OSPEED_100M(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN15))
+#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \
+ PIN_ODR_HIGH(GPIOH_OSC_OUT) | \
+ PIN_ODR_HIGH(GPIOH_PIN2) | \
+ PIN_ODR_HIGH(GPIOH_PIN3) | \
+ PIN_ODR_HIGH(GPIOH_PIN4) | \
+ PIN_ODR_HIGH(GPIOH_PIN5) | \
+ PIN_ODR_HIGH(GPIOH_PIN6) | \
+ PIN_ODR_HIGH(GPIOH_PIN7) | \
+ PIN_ODR_HIGH(GPIOH_PIN8) | \
+ PIN_ODR_HIGH(GPIOH_PIN9) | \
+ PIN_ODR_HIGH(GPIOH_PIN10) | \
+ PIN_ODR_HIGH(GPIOH_PIN11) | \
+ PIN_ODR_HIGH(GPIOH_PIN12) | \
+ PIN_ODR_HIGH(GPIOH_PIN13) | \
+ PIN_ODR_HIGH(GPIOH_PIN14) | \
+ PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \
+ PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN7, 0))
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN15, 0))
+
+/*
+ * GPIOI setup:
+ *
+ * PI0 - PIN0 (input floating).
+ * PI1 - PIN1 (input floating).
+ * PI2 - PIN2 (input floating).
+ * PI3 - PIN3 (input floating).
+ * PI4 - PIN4 (input floating).
+ * PI5 - PIN5 (input floating).
+ * PI6 - PIN6 (input floating).
+ * PI7 - PIN7 (input floating).
+ * PI8 - PIN8 (input floating).
+ * PI9 - PIN9 (input floating).
+ * PI10 - PIN10 (input floating).
+ * PI11 - PIN11 (input floating).
+ * PI12 - PIN12 (input floating).
+ * PI13 - PIN13 (input floating).
+ * PI14 - PIN14 (input floating).
+ * PI15 - PIN15 (input floating).
+ */
+#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \
+ PIN_MODE_INPUT(GPIOI_PIN1) | \
+ PIN_MODE_INPUT(GPIOI_PIN2) | \
+ PIN_MODE_INPUT(GPIOI_PIN3) | \
+ PIN_MODE_INPUT(GPIOI_PIN4) | \
+ PIN_MODE_INPUT(GPIOI_PIN5) | \
+ PIN_MODE_INPUT(GPIOI_PIN6) | \
+ PIN_MODE_INPUT(GPIOI_PIN7) | \
+ PIN_MODE_INPUT(GPIOI_PIN8) | \
+ PIN_MODE_INPUT(GPIOI_PIN9) | \
+ PIN_MODE_INPUT(GPIOI_PIN10) | \
+ PIN_MODE_INPUT(GPIOI_PIN11) | \
+ PIN_MODE_INPUT(GPIOI_PIN12) | \
+ PIN_MODE_INPUT(GPIOI_PIN13) | \
+ PIN_MODE_INPUT(GPIOI_PIN14) | \
+ PIN_MODE_INPUT(GPIOI_PIN15))
+#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
+#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(GPIOI_PIN0) | \
+ PIN_OSPEED_100M(GPIOI_PIN1) | \
+ PIN_OSPEED_100M(GPIOI_PIN2) | \
+ PIN_OSPEED_100M(GPIOI_PIN3) | \
+ PIN_OSPEED_100M(GPIOI_PIN4) | \
+ PIN_OSPEED_100M(GPIOI_PIN5) | \
+ PIN_OSPEED_100M(GPIOI_PIN6) | \
+ PIN_OSPEED_100M(GPIOI_PIN7) | \
+ PIN_OSPEED_100M(GPIOI_PIN8) | \
+ PIN_OSPEED_100M(GPIOI_PIN9) | \
+ PIN_OSPEED_100M(GPIOI_PIN10) | \
+ PIN_OSPEED_100M(GPIOI_PIN11) | \
+ PIN_OSPEED_100M(GPIOI_PIN12) | \
+ PIN_OSPEED_100M(GPIOI_PIN13) | \
+ PIN_OSPEED_100M(GPIOI_PIN14) | \
+ PIN_OSPEED_100M(GPIOI_PIN15))
+#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN15))
+#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \
+ PIN_ODR_HIGH(GPIOI_PIN1) | \
+ PIN_ODR_HIGH(GPIOI_PIN2) | \
+ PIN_ODR_HIGH(GPIOI_PIN3) | \
+ PIN_ODR_HIGH(GPIOI_PIN4) | \
+ PIN_ODR_HIGH(GPIOI_PIN5) | \
+ PIN_ODR_HIGH(GPIOI_PIN6) | \
+ PIN_ODR_HIGH(GPIOI_PIN7) | \
+ PIN_ODR_HIGH(GPIOI_PIN8) | \
+ PIN_ODR_HIGH(GPIOI_PIN9) | \
+ PIN_ODR_HIGH(GPIOI_PIN10) | \
+ PIN_ODR_HIGH(GPIOI_PIN11) | \
+ PIN_ODR_HIGH(GPIOI_PIN12) | \
+ PIN_ODR_HIGH(GPIOI_PIN13) | \
+ PIN_ODR_HIGH(GPIOI_PIN14) | \
+ PIN_ODR_HIGH(GPIOI_PIN15))
+#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN7, 0))
+#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.mk b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.mk
new file mode 100644
index 000000000..575cd5840
--- /dev/null
+++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2
diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/Makefile b/testhal/STM32/STM32F4xx/FSMC_NAND/Makefile
new file mode 100644
index 000000000..b31fff1dc
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/FSMC_NAND/Makefile
@@ -0,0 +1,209 @@
+##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = yes
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x400
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../..
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.mk
+include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f4xx.mk
+include $(CHIBIOS)/test/rt/test.mk
+
+
+# Define linker script file here
+LDSCRIPT= $(PORTLD)/STM32F407xG.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(PORTSRC) \
+ $(KERNSRC) \
+ $(TESTSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(CHIBIOS)/os/various/chprintf.c \
+ main.c \
+ dma_storm_adc.c \
+ dma_storm_spi.c \
+ dma_storm_uart.c \
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(PORTASM)
+
+INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
+ $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \
+ $(CHIBIOS)/os/various
+
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m4
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/chconf.h b/testhal/STM32/STM32F4xx/FSMC_NAND/chconf.h
new file mode 100644
index 000000000..b9838301a
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/FSMC_NAND/chconf.h
@@ -0,0 +1,498 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 10000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 2
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 0
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop. */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM TRUE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_QUEUES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS TRUE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS TRUE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS TRUE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE TRUE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS TRUE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm.h b/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm.h
new file mode 100644
index 000000000..0be66ba82
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm.h
@@ -0,0 +1,17 @@
+#ifndef DMA_STORM_H_
+#define DMA_STORM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void dma_storm_spi_start(void);
+ uint32_t dma_storm_spi_stop(void);
+ void dma_storm_adc_start(void);
+ uint32_t dma_storm_adc_stop(void);
+ void dma_storm_uart_start(void);
+ uint32_t dma_storm_uart_stop(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DMA_STORM_H_ */
diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm_adc.c b/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm_adc.c
new file mode 100644
index 000000000..c318a623f
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm_adc.c
@@ -0,0 +1,115 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#define ADC_NUM_CHANNELS 6
+#define ADC_BUF_DEPTH 8
+
+/* human readable names */
+#define ADC_CURRENT_SENS ADC_CHANNEL_IN10
+#define ADC_MAIN_SUPPLY ADC_CHANNEL_IN11
+#define ADC_6V_SUPPLY ADC_CHANNEL_IN12
+#define ADC_AN33_0 ADC_CHANNEL_IN13
+#define ADC_AN33_1 ADC_CHANNEL_IN14
+#define ADC_AN33_2 ADC_CHANNEL_IN15
+
+#define ADC_CURRENT_SENS_OFFSET (ADC_CHANNEL_IN10 - 10)
+#define ADC_MAIN_VOLTAGE_OFFSET (ADC_CHANNEL_IN11 - 10)
+#define ADC_6V_OFFSET (ADC_CHANNEL_IN12 - 10)
+#define ADC_AN33_0_OFFSET (ADC_CHANNEL_IN13 - 10)
+#define ADC_AN33_1_OFFSET (ADC_CHANNEL_IN14 - 10)
+#define ADC_AN33_2_OFFSET (ADC_CHANNEL_IN15 - 10)
+
+
+
+static void adcerrorcallback(ADCDriver *adcp, adcerror_t err);
+static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n);
+
+
+
+static adcsample_t samples[ADC_NUM_CHANNELS * ADC_BUF_DEPTH];
+
+volatile uint32_t its = 0;
+volatile uint32_t errors = 0;
+
+static const ADCConversionGroup adccg = {
+ TRUE,
+ ADC_NUM_CHANNELS,
+ adccallback,
+ adcerrorcallback,
+ 0, /* CR1 */
+ ADC_CR2_SWSTART, /* CR2 */
+ ADC_SMPR1_SMP_AN10(ADC_SAMPLE_3) |
+ ADC_SMPR1_SMP_AN11(ADC_SAMPLE_3) |
+ ADC_SMPR1_SMP_AN12(ADC_SAMPLE_3) |
+ ADC_SMPR1_SMP_AN13(ADC_SAMPLE_3) |
+ ADC_SMPR1_SMP_AN14(ADC_SAMPLE_3) |
+ ADC_SMPR1_SMP_AN15(ADC_SAMPLE_3),
+ 0, /* SMPR2 */
+ ADC_SQR1_NUM_CH(ADC_NUM_CHANNELS),
+ 0,
+ ADC_SQR3_SQ6_N(ADC_AN33_2) |
+ ADC_SQR3_SQ5_N(ADC_AN33_1) |
+ ADC_SQR3_SQ4_N(ADC_AN33_0) |
+ ADC_SQR3_SQ3_N(ADC_6V_SUPPLY) |
+ ADC_SQR3_SQ2_N(ADC_MAIN_SUPPLY) |
+ ADC_SQR3_SQ1_N(ADC_CURRENT_SENS)
+};
+
+static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) {
+ (void)adcp;
+ (void)err;
+
+ osalSysHalt("");
+// chSysLockFromIsr();
+// adcStartConversionI(&ADCD1, &adccg, samples, ADC_BUF_DEPTH);
+// chSysUnlockFromIsr();
+}
+
+static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) {
+ (void)adcp;
+ (void)buffer;
+ (void)n;
+ its++;
+}
+
+/*
+ *
+ */
+void dma_storm_adc_start(void){
+ its = 0;
+ errors = 0;
+
+ /* Activates the ADC1 driver and the temperature sensor.*/
+ adcStart(&ADCD1, NULL);
+ adcSTM32EnableTSVREFE();
+
+ /* Starts an ADC continuous conversion.*/
+ adcStartConversion(&ADCD1, &adccg, samples, ADC_BUF_DEPTH);
+}
+
+/*
+ *
+ */
+uint32_t dma_storm_adc_stop(void){
+ adcStopConversion(&ADCD1);
+ adcSTM32DisableTSVREFE();
+ adcStop(&ADCD1);
+ return its;
+}
+
diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm_spi.c b/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm_spi.c
new file mode 100644
index 000000000..894b273dd
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm_spi.c
@@ -0,0 +1,90 @@
+#include "ch.h"
+#include "hal.h"
+
+/*
+ ******************************************************************************
+ * DEFINES
+ ******************************************************************************
+ */
+#define SPI_BUF_SIZE 512
+
+/*
+ ******************************************************************************
+ * EXTERNS
+ ******************************************************************************
+ */
+
+/*
+ ******************************************************************************
+ * PROTOTYPES
+ ******************************************************************************
+ */
+static void spi_end_cb(SPIDriver *spip);
+
+/*
+ ******************************************************************************
+ * GLOBAL VARIABLES
+ ******************************************************************************
+ */
+static uint8_t testbuf_ram[SPI_BUF_SIZE];
+static const uint8_t testbuf_flash[SPI_BUF_SIZE];
+
+/*
+ *
+ */
+static const SPIConfig spicfg = {
+ spi_end_cb,
+ GPIOA,
+ GPIOA_SPI1_NSS,
+ 0, //SPI_CR1_BR_1 | SPI_CR1_BR_0
+};
+
+static uint32_t its;
+static binary_semaphore_t sem;
+static bool stop = false;
+
+/*
+ ******************************************************************************
+ ******************************************************************************
+ * LOCAL FUNCTIONS
+ ******************************************************************************
+ ******************************************************************************
+ */
+
+static void spi_end_cb(SPIDriver *spip){
+ its++;
+
+ if (stop){
+ chSysLockFromISR();
+ chBSemSignalI(&sem);
+ chSysUnlockFromISR();
+ return;
+ }
+ else{
+ chSysLockFromISR();
+ spiStartExchangeI(spip, SPI_BUF_SIZE, testbuf_flash, testbuf_ram);
+ chSysUnlockFromISR();
+ }
+}
+
+/*
+ ******************************************************************************
+ * EXPORTED FUNCTIONS
+ ******************************************************************************
+ */
+
+void dma_storm_spi_start(void){
+ its = 0;
+ stop = false;
+ chBSemObjectInit(&sem, true);
+ spiStart(&SPID1, &spicfg);
+ spiStartExchange(&SPID1, SPI_BUF_SIZE, testbuf_flash, testbuf_ram);
+}
+
+uint32_t dma_storm_spi_stop(void){
+ stop = true;
+ chBSemWait(&sem);
+ spiStop(&SPID1);
+ return its;
+}
+
diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm_uart.c b/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm_uart.c
new file mode 100644
index 000000000..89b105a75
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/FSMC_NAND/dma_storm_uart.c
@@ -0,0 +1,144 @@
+#include "ch.h"
+#include "hal.h"
+
+/*
+ ******************************************************************************
+ * DEFINES
+ ******************************************************************************
+ */
+#define UART_STORM_BAUDRATE 3000000
+#define STORM_BUF_LEN 256
+
+/*
+ ******************************************************************************
+ * EXTERNS
+ ******************************************************************************
+ */
+
+/*
+ ******************************************************************************
+ * PROTOTYPES
+ ******************************************************************************
+ */
+static void txend1(UARTDriver *uartp);
+static void txend2(UARTDriver *uartp);
+static void rxerr(UARTDriver *uartp, uartflags_t e);
+static void rxchar(UARTDriver *uartp, uint16_t c);
+static void rxend(UARTDriver *uartp);
+
+/*
+ ******************************************************************************
+ * GLOBAL VARIABLES
+ ******************************************************************************
+ */
+static uint8_t rxbuf[STORM_BUF_LEN];
+static uint8_t txbuf[STORM_BUF_LEN];
+
+/*
+ * UART driver configuration structure.
+ */
+static const UARTConfig uart_cfg = {
+ txend1,
+ txend2,
+ rxend,
+ rxchar,
+ rxerr,
+ UART_STORM_BAUDRATE,
+ 0,
+ 0,
+ 0
+};
+
+static uint32_t its;
+
+/*
+ ******************************************************************************
+ ******************************************************************************
+ * LOCAL FUNCTIONS
+ ******************************************************************************
+ ******************************************************************************
+ */
+/*
+ * This callback is invoked when a transmission buffer has been completely
+ * read by the driver.
+ */
+static void txend1(UARTDriver *uartp) {
+
+ its++;
+ chSysLockFromISR();
+ uartStartSendI(uartp, STORM_BUF_LEN, txbuf);
+ chSysUnlockFromISR();
+}
+
+/*
+ * This callback is invoked when a transmission has physically completed.
+ */
+static void txend2(UARTDriver *uartp) {
+ (void)uartp;
+
+ chSysLockFromISR();
+ chSysUnlockFromISR();
+}
+
+/*
+ * This callback is invoked on a receive error, the errors mask is passed
+ * as parameter.
+ */
+static void rxerr(UARTDriver *uartp, uartflags_t e) {
+ (void)uartp;
+ (void)e;
+ osalSysHalt("");
+}
+
+/*
+ * This callback is invoked when a character is received but the application
+ * was not ready to receive it, the character is passed as parameter.
+ */
+static void rxchar(UARTDriver *uartp, uint16_t c) {
+ (void)uartp;
+ (void)c;
+}
+
+/*
+ * This callback is invoked when a receive buffer has been completely written.
+ */
+static void rxend(UARTDriver *uartp) {
+ (void)uartp;
+
+ chSysLockFromISR();
+ uartStartReceiveI(&UARTD6, STORM_BUF_LEN, rxbuf);
+ chSysUnlockFromISR();
+}
+
+/*
+ ******************************************************************************
+ * EXPORTED FUNCTIONS
+ ******************************************************************************
+ */
+
+/**
+ *
+ */
+void dma_storm_uart_start(void){
+
+ uint32_t i;
+
+ for (i=0; i<STORM_BUF_LEN; i++){
+ txbuf[i] = 0x55;
+ rxbuf[i] = 0;
+ }
+
+ its = 0;
+ uartStart(&UARTD6, &uart_cfg);
+ uartStartReceive(&UARTD6, STORM_BUF_LEN, rxbuf);
+ uartStartSend(&UARTD6, STORM_BUF_LEN, txbuf);
+}
+
+uint32_t dma_storm_uart_stop(void){
+
+ uartStopSend(&UARTD6);
+ uartStopReceive(&UARTD6);
+ uartStop(&UARTD6);
+
+ return its;
+}
diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/halconf.h b/testhal/STM32/STM32F4xx/FSMC_NAND/halconf.h
new file mode 100644
index 000000000..7a248d93d
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/FSMC_NAND/halconf.h
@@ -0,0 +1,346 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC TRUE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT TRUE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI TRUE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART TRUE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/**
+ * @brief Enables the EMC subsystem.
+ */
+#if !defined(HAL_USE_EMC) || defined(__DOXYGEN__)
+#define HAL_USE_EMC TRUE
+#endif
+
+/**
+ * @brief Enables the NAND over EMC subsystem.
+ */
+#if !defined(HAL_USE_EMCNAND) || defined(__DOXYGEN__)
+#define HAL_USE_EMCNAND TRUE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* EMCNAND driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the @p emcnandAcquireBus() and @p emcnanReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(EMCNAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define EMCNAND_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/**
+ * @brief Enables internal driver map for bad blocks.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(EMCNAND_USE_BAD_MAP) || defined(__DOXYGEN__)
+#define EMCNAND_USE_BAD_MAP TRUE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/main.c b/testhal/STM32/STM32F4xx/FSMC_NAND/main.c
new file mode 100644
index 000000000..bb79aee12
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/FSMC_NAND/main.c
@@ -0,0 +1,607 @@
+/*
+ * Hardware notes.
+ *
+ * Use _external_ pullup on ready/busy pin of NAND IC.
+ *
+ * Chose MCU with 140 (or more) pins package because 100 pins packages
+ * has no dedicated interrupt pins for FSMC.
+ *
+ * If your hardware already done using 100 pin package than you have to:
+ * 1) connect ready/busy pin to GPIOD6 (NWAIT in terms of STM32)
+ * 2) set GPIOD6 pin as input with pullup and connect it to alternate
+ * function0 (not function12)
+ * 3) set up EXTI to catch raising edge on GPIOD6 and call NAND driver's
+ * isr_handler() function from an EXTI callback.
+ *
+ * If you use MLC flash memory do NOT use ECC to detect/correct
+ * errors because of its weakness. Use Rid-Solomon on BCH code instead.
+ * Yes, you have to realize it in sowftware yourself.
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#include "dma_storm.h"
+#include "string.h"
+#include "stdlib.h"
+
+/*
+ ******************************************************************************
+ * DEFINES
+ ******************************************************************************
+ */
+
+#define EMCNAND_TIME_SET ((uint32_t) 2) //(8nS)
+#define EMCNAND_TIME_WAIT ((uint32_t) 6) //(30nS)
+#define EMCNAND_TIME_HOLD ((uint32_t) 1) //(5nS)
+#define EMCNAND_TIME_HIZ ((uint32_t) 4) //(20nS)
+
+#define NAND_BLOCKS_COUNT 8192
+#define NAND_PAGE_DATA_SIZE 2048
+#define NAND_PAGE_SPARE_SIZE 64
+#define NAND_PAGE_SIZE (NAND_PAGE_SPARE_SIZE + NAND_PAGE_DATA_SIZE)
+#define NAND_PAGES_PER_BLOCK 64
+#define NAND_ROW_WRITE_CYCLES 3
+#define NAND_COL_WRITE_CYCLES 2
+
+/* statuses returning by NAND IC on 0x70 command */
+#define NAND_STATUS_OP_FAILED ((uint8_t)1 << 0)
+#define NAND_STATUS_READY ((uint8_t)1 << 6)
+#define NAND_STATUS_NOT_RPOTECTED ((uint8_t)1 << 7)
+
+#define EMCNAND_USE_KILL_TEST TRUE
+
+/*
+ ******************************************************************************
+ * EXTERNS
+ ******************************************************************************
+ */
+
+/*
+ ******************************************************************************
+ * PROTOTYPES
+ ******************************************************************************
+ */
+static void ready_isr_enable(void);
+static void ready_isr_disable(void);
+static void nand_ready_cb(EXTDriver *extp, expchannel_t channel);
+
+/*
+ ******************************************************************************
+ * GLOBAL VARIABLES
+ ******************************************************************************
+ */
+/*
+ *
+ */
+static uint8_t nand_buf[NAND_PAGE_SIZE];
+static uint8_t ref_buf[NAND_PAGE_SIZE];
+
+/*
+ *
+ */
+//static TimeMeasurement tmu_erase;
+//static TimeMeasurement tmu_write_data;
+//static TimeMeasurement tmu_write_spare;
+//static TimeMeasurement tmu_read_data;
+//static TimeMeasurement tmu_read_spare;
+
+/*
+ *
+ */
+static const EMCConfig emccfg = {};
+
+#if EMCNAND_USE_BAD_MAP
+static uint32_t badblock_map[NAND_BLOCKS_COUNT / 32];
+#endif
+
+/*
+ *
+ */
+static const EMCNANDConfig nandcfg = {
+ &EMCD1,
+ NAND_BLOCKS_COUNT,
+ NAND_PAGE_DATA_SIZE,
+ NAND_PAGE_SPARE_SIZE,
+ NAND_PAGES_PER_BLOCK,
+#if EMCNAND_USE_BAD_MAP
+ badblock_map,
+#endif
+ NAND_ROW_WRITE_CYCLES,
+ NAND_COL_WRITE_CYCLES,
+ /* stm32 specific fields */
+ ((EMCNAND_TIME_HIZ << 24) | (EMCNAND_TIME_HOLD << 16) | \
+ (EMCNAND_TIME_WAIT << 8) | EMCNAND_TIME_SET),
+#if !STM32_EMC_EMCNAND_USE_FSMC_INT
+ ready_isr_enable,
+ ready_isr_disable
+#endif
+};
+
+/**
+ *
+ */
+static const EXTConfig extcfg = {
+ {
+ {EXT_CH_MODE_DISABLED, NULL}, //0
+ {EXT_CH_MODE_DISABLED, NULL},
+ {EXT_CH_MODE_DISABLED, NULL},
+ {EXT_CH_MODE_DISABLED, NULL},
+ {EXT_CH_MODE_DISABLED, NULL}, //4
+ {EXT_CH_MODE_DISABLED, NULL},
+ {EXT_CH_MODE_RISING_EDGE | EXT_MODE_GPIOD, nand_ready_cb},
+ {EXT_CH_MODE_DISABLED, NULL},
+ {EXT_CH_MODE_DISABLED, NULL}, //8
+ {EXT_CH_MODE_DISABLED, NULL},
+ {EXT_CH_MODE_DISABLED, NULL},
+ {EXT_CH_MODE_DISABLED, NULL},
+ {EXT_CH_MODE_DISABLED, NULL}, //12
+ {EXT_CH_MODE_DISABLED, NULL},
+ {EXT_CH_MODE_DISABLED, NULL},
+ {EXT_CH_MODE_DISABLED, NULL},
+ {EXT_CH_MODE_DISABLED, NULL}, //16
+ {EXT_CH_MODE_DISABLED, NULL},
+ {EXT_CH_MODE_DISABLED, NULL},
+ {EXT_CH_MODE_DISABLED, NULL},
+ {EXT_CH_MODE_DISABLED, NULL}, //20
+ {EXT_CH_MODE_DISABLED, NULL},
+ {EXT_CH_MODE_DISABLED, NULL},
+ }
+};
+
+/*
+ *
+ */
+volatile uint32_t IdleCnt = 0;
+volatile systime_t T = 0;
+
+#if EMCNAND_USE_KILL_TEST
+volatile uint32_t KillCycle = 0;
+#endif
+
+/*
+ ******************************************************************************
+ ******************************************************************************
+ * LOCAL FUNCTIONS
+ ******************************************************************************
+ ******************************************************************************
+ */
+
+static void nand_ready_cb(EXTDriver *extp, expchannel_t channel){
+ (void)extp;
+ (void)channel;
+#if !STM32_EMC_EMCNAND_USE_FSMC_INT
+ EMCNANDD1.isr_handler(&EMCNANDD1);
+#endif
+}
+
+static void ready_isr_enable(void) {
+ extChannelEnable(&EXTD1, GPIOD_NAND_RB);
+}
+
+static void ready_isr_disable(void) {
+ extChannelDisable(&EXTD1, GPIOD_NAND_RB);
+}
+
+static void nand_wp_assert(void) {
+ palClearPad(GPIOB, GPIOB_NAND_WP);
+}
+
+static void nand_wp_release(void) {
+ palSetPad(GPIOB, GPIOB_NAND_WP);
+}
+
+static void red_led_on(void) {
+ palSetPad(GPIOE, GPIOE_LED_R);
+}
+
+static void red_led_off(void) {
+ palClearPad(GPIOE, GPIOE_LED_R);
+}
+
+static THD_WORKING_AREA(fsmcIdleThreadWA, 128);
+static THD_FUNCTION(fsmcIdleThread, arg) {
+ (void)arg;
+
+ while(true){
+ IdleCnt++;
+ }
+ return 0;
+}
+
+/*
+ *
+ */
+static bool isErased(EMCNANDDriver *dp, size_t block){
+ uint32_t page = 0;
+ size_t i = 0;
+
+ for (page=0; page<EMCNANDD1.config->pages_per_block; page++){
+ emcnandReadPageData(dp, block, page, nand_buf, EMCNANDD1.config->page_data_size, NULL);
+ emcnandReadPageSpare(dp, block, page, &nand_buf[2048], EMCNANDD1.config->page_spare_size);
+ for (i=0; i<sizeof(nand_buf); i++) {
+ if (nand_buf[i] != 0xFF)
+ return false;
+ }
+ }
+
+ return true;
+}
+
+static void pattern_fill(void) {
+
+ size_t i;
+
+
+
+
+ ///////////////////////// FIXME //////////////////////////////////
+ //srand(hal_lld_get_counter_value());
+ srand(0);
+
+
+ for(i=0; i<NAND_PAGE_SIZE; i++){
+ ref_buf[i] = rand() & 0xFF;
+ }
+
+ /* protect bad mark */
+ ref_buf[NAND_PAGE_DATA_SIZE] = 0xFF;
+ ref_buf[NAND_PAGE_DATA_SIZE + 1] = 0xFF;
+ memcpy(nand_buf, ref_buf, NAND_PAGE_SIZE);
+
+ /* paranoid mode ON */
+ osalDbgCheck(0 == memcmp(ref_buf, nand_buf, NAND_PAGE_SIZE));
+}
+
+#if EMCNAND_USE_KILL_TEST
+static void kill_block(EMCNANDDriver *emcnandp, uint32_t block){
+
+ size_t i = 0;
+ size_t page = 0;
+ uint8_t op_status;
+
+ /* This test require good block.*/
+ osalDbgCheck(!emcnandIsBad(emcnandp, block));
+
+ while(true){
+ op_status = emcnandErase(&EMCNANDD1, block);
+ if (0 != (op_status & 1)){
+ if(!isErased(emcnandp, block))
+ osalSysHalt("Block successfully killed");
+ }
+ if(!isErased(emcnandp, block))
+ osalSysHalt("Block block not erased, but erase operation report success");
+
+ for (page=0; page<emcnandp->config->pages_per_block; page++){
+ memset(nand_buf, 0, NAND_PAGE_SIZE);
+ op_status = emcnandWritePageWhole(emcnandp, block, page, nand_buf, NAND_PAGE_SIZE);
+ if (0 != (op_status & 1)){
+ emcnandReadPageWhole(emcnandp, block, page, nand_buf, NAND_PAGE_SIZE);
+ for (i=0; i<NAND_PAGE_SIZE; i++){
+ if (nand_buf[i] != 0)
+ osalSysHalt("Block successfully killed");
+ }
+ }
+
+ emcnandReadPageWhole(emcnandp, block, page, nand_buf, NAND_PAGE_SIZE);
+ for (i=0; i<NAND_PAGE_SIZE; i++){
+ if (nand_buf[i] != 0)
+ osalSysHalt("Page write failed, but write operation report success");
+ }
+ }
+ KillCycle++;
+ }
+}
+#endif /* EMCNAND_USE_KILL_TEST */
+
+typedef enum {
+ ECC_NO_ERROR = 0,
+ ECC_CORRECTABLE_ERROR = 1,
+ ECC_UNCORRECTABLE_ERROR = 2,
+ ECC_CORRUPTED = 3,
+} ecc_result_t;
+
+static ecc_result_t parse_ecc(uint32_t ecclen, uint32_t ecc1, uint32_t ecc2,
+ uint32_t *corrupted){
+
+ size_t i = 0;
+ uint32_t corr = 0;
+ uint32_t e = 0;
+ uint32_t shift = (32 - ecclen);
+ uint32_t b0, b1;
+
+ ecc1 <<= shift;
+ ecc1 >>= shift;
+ ecc2 <<= shift;
+ ecc2 >>= shift;
+ e = ecc1 ^ ecc2;
+
+ if (0 == e){
+ return ECC_NO_ERROR;
+ }
+ else if (((e - 1) & e) == 0){
+ return ECC_CORRUPTED;
+ }
+ else {
+ for (i=0; i<ecclen/2; i++){
+ b0 = e & 1;
+ e >>= 1;
+ b1 = e & 1;
+ e >>= 1;
+ if ((b0 + b1) != 1)
+ return ECC_UNCORRECTABLE_ERROR;
+ corr |= b1 << i;
+ }
+ *corrupted = corr;
+ return ECC_CORRECTABLE_ERROR;
+ }
+}
+
+static void invert_bit(uint8_t *buf, uint32_t byte, uint32_t bit){
+ osalDbgCheck((byte < NAND_PAGE_DATA_SIZE) && (bit < 8));
+ buf[byte] ^= ((uint8_t)1) << bit;
+}
+
+/*
+ *
+ */
+static void ecc_test(EMCNANDDriver *emcnandp, uint32_t block){
+
+ uint32_t corrupted;
+ uint32_t byte, bit;
+ const uint32_t ecclen = 28;
+ uint32_t ecc_ref, ecc_broken;
+ uint8_t op_status;
+ ecc_result_t ecc_result = ECC_NO_ERROR;
+
+ /* This test requires good block.*/
+ osalDbgCheck(!emcnandIsBad(emcnandp, block));
+ if (!isErased(emcnandp, block))
+ emcnandErase(&EMCNANDD1, block);
+
+ pattern_fill();
+
+ /*** Correctable errors ***/
+ op_status = emcnandWritePageData(emcnandp, block, 0,
+ nand_buf, emcnandp->config->page_data_size, &ecc_ref);
+ osalDbgCheck(0 == (op_status & 1)); /* operation failed */
+ emcnandReadPageData(emcnandp, block, 0,
+ nand_buf, emcnandp->config->page_data_size, &ecc_broken);
+ ecc_result = parse_ecc(ecclen, ecc_ref, ecc_broken, &corrupted);
+ osalDbgCheck(ECC_NO_ERROR == ecc_result); /* unexpected error */
+
+ /**/
+ byte = 0;
+ bit = 7;
+ invert_bit(nand_buf, byte, bit);
+ op_status = emcnandWritePageData(emcnandp, block, 1,
+ nand_buf, emcnandp->config->page_data_size, &ecc_broken);
+ osalDbgCheck(0 == (op_status & 1)); /* operation failed */
+ invert_bit(nand_buf, byte, bit);
+ ecc_result = parse_ecc(ecclen, ecc_ref, ecc_broken, &corrupted);
+ osalDbgCheck(ECC_CORRECTABLE_ERROR == ecc_result); /* this error must be correctable */
+ osalDbgCheck(corrupted == (byte * 8 + bit)); /* wrong correction code */
+
+ /**/
+ byte = 2047;
+ bit = 0;
+ invert_bit(nand_buf, byte, bit);
+ op_status = emcnandWritePageData(emcnandp, block, 2,
+ nand_buf, emcnandp->config->page_data_size, &ecc_broken);
+ osalDbgCheck(0 == (op_status & 1)); /* operation failed */
+ invert_bit(nand_buf, byte, bit);
+ ecc_result = parse_ecc(ecclen, ecc_ref, ecc_broken, &corrupted);
+ osalDbgCheck(ECC_CORRECTABLE_ERROR == ecc_result); /* this error must be correctable */
+ osalDbgCheck(corrupted == (byte * 8 + bit)); /* wrong correction code */
+
+ /**/
+ byte = 1027;
+ bit = 3;
+ invert_bit(nand_buf, byte, bit);
+ op_status = emcnandWritePageData(emcnandp, block, 3,
+ nand_buf, emcnandp->config->page_data_size, &ecc_broken);
+ osalDbgCheck(0 == (op_status & 1)); /* operation failed */
+ invert_bit(nand_buf, byte, bit);
+ ecc_result = parse_ecc(ecclen, ecc_ref, ecc_broken, &corrupted);
+ osalDbgCheck(ECC_CORRECTABLE_ERROR == ecc_result); /* this error must be correctable */
+ osalDbgCheck(corrupted == (byte * 8 + bit)); /* wrong correction code */
+
+ /*** Uncorrectable error ***/
+ byte = 1027;
+ invert_bit(nand_buf, byte, 3);
+ invert_bit(nand_buf, byte, 4);
+ op_status = emcnandWritePageData(emcnandp, block, 4,
+ nand_buf, emcnandp->config->page_data_size, &ecc_broken);
+ osalDbgCheck(0 == (op_status & 1)); /* operation failed */
+ invert_bit(nand_buf, byte, 3);
+ invert_bit(nand_buf, byte, 4);
+ ecc_result = parse_ecc(28, ecc_ref, ecc_broken, &corrupted);
+ osalDbgCheck(ECC_UNCORRECTABLE_ERROR == ecc_result); /* This error must be NOT correctable */
+
+ /*** make clean ***/
+ emcnandErase(&EMCNANDD1, block);
+}
+
+/*
+ *
+ */
+static void general_test (EMCNANDDriver *emcnandp, size_t first,
+ size_t last, size_t read_rounds){
+
+ size_t block, page, round;
+ bool status;
+ uint8_t op_status;
+ uint32_t recc, wecc;
+
+ red_led_on();
+
+ /* initialize time measurement units */
+ ////////////////////////////// FIXME //////////////////////////////
+// tmObjectInit(&tmu_erase);
+// tmObjectInit(&tmu_write_data);
+// tmObjectInit(&tmu_write_spare);
+// tmObjectInit(&tmu_read_data);
+// tmObjectInit(&tmu_read_spare);
+
+ /* perform basic checks */
+ for (block=first; block<last; block++){
+ if (!emcnandIsBad(emcnandp, block)){
+ if (!isErased(emcnandp, block)){
+ op_status = emcnandErase(emcnandp, block);
+ osalDbgCheck(0 == (op_status & 1)); /* operation failed */
+ }
+ }
+ }
+
+ /* write block with pattern, read it back and compare */
+ for (block=first; block<last; block++){
+ if (!emcnandIsBad(emcnandp, block)){
+ for (page=0; page<emcnandp->config->pages_per_block; page++){
+ pattern_fill();
+
+ //tmStartMeasurement(&tmu_write_data);
+ op_status = emcnandWritePageData(emcnandp, block, page,
+ nand_buf, emcnandp->config->page_data_size, &wecc);
+ //tmStopMeasurement(&tmu_write_data);
+ osalDbgCheck(0 == (op_status & 1)); /* operation failed */
+
+ //tmStartMeasurement(&tmu_write_spare);
+ op_status = emcnandWritePageSpare(emcnandp, block, page,
+ nand_buf + emcnandp->config->page_data_size,
+ emcnandp->config->page_spare_size);
+ //tmStopMeasurement(&tmu_write_spare);
+ osalDbgCheck(0 == (op_status & 1)); /* operation failed */
+
+ /* read back and compare */
+ for (round=0; round<read_rounds; round++){
+ memset(nand_buf, 0, NAND_PAGE_SIZE);
+
+ //tmStartMeasurement(&tmu_read_data);
+ emcnandReadPageData(emcnandp, block, page,
+ nand_buf, emcnandp->config->page_data_size, &recc);
+ //tmStopMeasurement(&tmu_read_data);
+ osalDbgCheck(0 == (recc ^ wecc)); /* ECC error detected */
+
+ //tmStartMeasurement(&tmu_read_spare);
+ emcnandReadPageSpare(emcnandp, block, page,
+ nand_buf + emcnandp->config->page_data_size,
+ emcnandp->config->page_spare_size);
+ //tmStopMeasurement(&tmu_read_spare);
+
+ osalDbgCheck(0 == memcmp(ref_buf, nand_buf, NAND_PAGE_SIZE)); /* Read back failed */
+ }
+ }
+
+ /* make clean */
+ //tmStartMeasurement(&tmu_erase);
+ op_status = emcnandErase(emcnandp, block);
+ //tmStopMeasurement(&tmu_erase);
+ osalDbgCheck(0 == (op_status & 1)); /* operation failed */
+
+ status = isErased(emcnandp, block);
+ osalDbgCheck(true == status); /* blocks was not erased successfully */
+ }/* if (!emcnandIsBad(emcnandp, block)){ */
+ }
+ red_led_off();
+}
+
+
+/*
+ ******************************************************************************
+ * EXPORTED FUNCTIONS
+ ******************************************************************************
+ */
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ size_t start = 1100;
+ size_t end = 1150;
+ volatile int32_t adc_its = 0;
+ volatile int32_t spi_its = 0;
+ volatile int32_t uart_its = 0;
+ volatile int32_t adc_its_idle = 0;
+ volatile int32_t spi_its_idle = 0;
+ volatile int32_t uart_its_idle = 0;
+ volatile uint32_t idle_thread_cnt = 0;
+
+ #if EMCNAND_USE_KILL_TEST
+ size_t kill = 8000;
+ #endif
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ emcStart(&EMCD1, &emccfg);
+ extStart(&EXTD1, &extcfg);
+ emcnandStart(&EMCNANDD1, &nandcfg);
+
+ chThdSleepMilliseconds(4000);
+
+ chThdCreateStatic(fsmcIdleThreadWA,
+ sizeof(fsmcIdleThreadWA),
+ NORMALPRIO - 20,
+ fsmcIdleThread,
+ NULL);
+
+ nand_wp_release();
+
+ dma_storm_adc_start();
+ dma_storm_uart_start();
+ dma_storm_spi_start();
+ T = chVTGetSystemTimeX();
+ general_test(&EMCNANDD1, start, end, 1);
+ T = chVTGetSystemTimeX() - T;
+ adc_its = dma_storm_adc_stop();
+ uart_its = dma_storm_uart_stop();
+ spi_its = dma_storm_spi_stop();
+ chSysLock();
+ idle_thread_cnt = IdleCnt;
+ IdleCnt = 0;
+ chSysUnlock();
+
+ dma_storm_adc_start();
+ dma_storm_uart_start();
+ dma_storm_spi_start();
+ chThdSleep(T);
+ adc_its_idle = dma_storm_adc_stop();
+ uart_its_idle = dma_storm_uart_stop();
+ spi_its_idle = dma_storm_spi_stop();
+
+ osalDbgCheck(idle_thread_cnt > (IdleCnt / 4));
+ osalDbgCheck(abs(adc_its - adc_its_idle) < (adc_its_idle / 20));
+ osalDbgCheck(abs(uart_its - uart_its_idle) < (uart_its_idle / 20));
+ osalDbgCheck(abs(spi_its - spi_its_idle) < (spi_its_idle / 10));
+
+ ecc_test(&EMCNANDD1, end);
+
+#if EMCNAND_USE_KILL_TEST
+ kill_block(&EMCNANDD1, kill);
+#endif
+
+ nand_wp_assert();
+
+ /*
+ * Normal main() thread activity, in this demo it does nothing.
+ */
+ while (TRUE) {
+ chThdSleepMilliseconds(500);
+ }
+
+ /*warning suppressor */
+#if STM32_EMC_EMCNAND_USE_FSMC_INT
+ (void)ready_isr_enable;
+ (void)ready_isr_disable;
+#endif
+}
+
+
diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf.h b/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf.h
new file mode 100644
index 000000000..b390f1b37
--- /dev/null
+++ b/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf.h
@@ -0,0 +1,316 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F4xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0 Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3 Lowest...Highest.
+ */
+
+#define STM32F4xx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT FALSE
+#define STM32_HSI_ENABLED TRUE
+#define STM32_LSI_ENABLED TRUE
+#define STM32_HSE_ENABLED TRUE
+#define STM32_LSE_ENABLED FALSE
+#define STM32_CLOCK48_REQUIRED TRUE
+#define STM32_SW STM32_SW_PLL
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#define STM32_PLLM_VALUE 8
+#define STM32_PLLN_VALUE 336
+#define STM32_PLLP_VALUE 2
+#define STM32_PLLQ_VALUE 7
+#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_PPRE1 STM32_PPRE1_DIV4
+#define STM32_PPRE2 STM32_PPRE2_DIV2
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+#define STM32_RTCPRE_VALUE 8
+#define STM32_MCO1SEL STM32_MCO1SEL_HSI
+#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
+#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
+#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
+#define STM32_I2SSRC STM32_I2SSRC_CKIN
+#define STM32_PLLI2SN_VALUE 192
+#define STM32_PLLI2SR_VALUE 5
+#define STM32_PVD_ENABLE FALSE
+#define STM32_PLS STM32_PLS_LEV0
+#define STM32_BKPRAM_ENABLE FALSE
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
+#define STM32_ADC_USE_ADC1 TRUE
+#define STM32_ADC_USE_ADC2 FALSE
+#define STM32_ADC_USE_ADC3 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC1_DMA_PRIORITY 3
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_IRQ_PRIORITY 6
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
+
+/*
+ * CAN driver system settings.
+ */
+#define STM32_CAN_USE_CAN1 FALSE
+#define STM32_CAN_USE_CAN2 FALSE
+#define STM32_CAN_CAN1_IRQ_PRIORITY 11
+#define STM32_CAN_CAN2_IRQ_PRIORITY 11
+
+/*
+ * EXT driver system settings.
+ */
+#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
+#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
+#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1 FALSE
+#define STM32_GPT_USE_TIM2 FALSE
+#define STM32_GPT_USE_TIM3 FALSE
+#define STM32_GPT_USE_TIM4 FALSE
+#define STM32_GPT_USE_TIM5 FALSE
+#define STM32_GPT_USE_TIM6 FALSE
+#define STM32_GPT_USE_TIM7 FALSE
+#define STM32_GPT_USE_TIM8 FALSE
+#define STM32_GPT_USE_TIM9 FALSE
+#define STM32_GPT_USE_TIM11 FALSE
+#define STM32_GPT_USE_TIM12 FALSE
+#define STM32_GPT_USE_TIM14 FALSE
+#define STM32_GPT_TIM1_IRQ_PRIORITY 7
+#define STM32_GPT_TIM2_IRQ_PRIORITY 7
+#define STM32_GPT_TIM3_IRQ_PRIORITY 7
+#define STM32_GPT_TIM4_IRQ_PRIORITY 7
+#define STM32_GPT_TIM5_IRQ_PRIORITY 7
+#define STM32_GPT_TIM6_IRQ_PRIORITY 7
+#define STM32_GPT_TIM7_IRQ_PRIORITY 7
+#define STM32_GPT_TIM8_IRQ_PRIORITY 7
+#define STM32_GPT_TIM9_IRQ_PRIORITY 7
+#define STM32_GPT_TIM11_IRQ_PRIORITY 7
+#define STM32_GPT_TIM12_IRQ_PRIORITY 7
+#define STM32_GPT_TIM14_IRQ_PRIORITY 7
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1 FALSE
+#define STM32_I2C_USE_I2C2 FALSE
+#define STM32_I2C_USE_I2C3 FALSE
+#define STM32_I2C_BUSY_TIMEOUT 50
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2C_I2C1_IRQ_PRIORITY 5
+#define STM32_I2C_I2C2_IRQ_PRIORITY 5
+#define STM32_I2C_I2C3_IRQ_PRIORITY 5
+#define STM32_I2C_I2C1_DMA_PRIORITY 3
+#define STM32_I2C_I2C2_DMA_PRIORITY 3
+#define STM32_I2C_I2C3_DMA_PRIORITY 3
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1 FALSE
+#define STM32_ICU_USE_TIM2 FALSE
+#define STM32_ICU_USE_TIM3 FALSE
+#define STM32_ICU_USE_TIM4 FALSE
+#define STM32_ICU_USE_TIM5 FALSE
+#define STM32_ICU_USE_TIM8 FALSE
+#define STM32_ICU_USE_TIM9 FALSE
+#define STM32_ICU_TIM1_IRQ_PRIORITY 7
+#define STM32_ICU_TIM2_IRQ_PRIORITY 7
+#define STM32_ICU_TIM3_IRQ_PRIORITY 7
+#define STM32_ICU_TIM4_IRQ_PRIORITY 7
+#define STM32_ICU_TIM5_IRQ_PRIORITY 7
+#define STM32_ICU_TIM8_IRQ_PRIORITY 7
+#define STM32_ICU_TIM9_IRQ_PRIORITY 7
+
+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS 2
+#define STM32_MAC_RECEIVE_BUFFERS 4
+#define STM32_MAC_BUFFERS_SIZE 1522
+#define STM32_MAC_PHY_TIMEOUT 100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY 13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_ADVANCED FALSE
+#define STM32_PWM_USE_TIM1 FALSE
+#define STM32_PWM_USE_TIM2 FALSE
+#define STM32_PWM_USE_TIM3 FALSE
+#define STM32_PWM_USE_TIM4 FALSE
+#define STM32_PWM_USE_TIM5 FALSE
+#define STM32_PWM_USE_TIM8 FALSE
+#define STM32_PWM_USE_TIM9 FALSE
+#define STM32_PWM_TIM1_IRQ_PRIORITY 7
+#define STM32_PWM_TIM2_IRQ_PRIORITY 7
+#define STM32_PWM_TIM3_IRQ_PRIORITY 7
+#define STM32_PWM_TIM4_IRQ_PRIORITY 7
+#define STM32_PWM_TIM5_IRQ_PRIORITY 7
+#define STM32_PWM_TIM8_IRQ_PRIORITY 7
+#define STM32_PWM_TIM9_IRQ_PRIORITY 7
+
+/*
+ * SDC driver system settings.
+ */
+#define STM32_SDC_SDIO_DMA_PRIORITY 3
+#define STM32_SDC_SDIO_IRQ_PRIORITY 9
+#define STM32_SDC_WRITE_TIMEOUT_MS 250
+#define STM32_SDC_READ_TIMEOUT_MS 25
+#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
+#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
+#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1 FALSE
+#define STM32_SERIAL_USE_USART2 FALSE
+#define STM32_SERIAL_USE_USART3 FALSE
+#define STM32_SERIAL_USE_UART4 FALSE
+#define STM32_SERIAL_USE_UART5 FALSE
+#define STM32_SERIAL_USE_USART6 FALSE
+#define STM32_SERIAL_USART1_PRIORITY 12
+#define STM32_SERIAL_USART2_PRIORITY 12
+#define STM32_SERIAL_USART3_PRIORITY 12
+#define STM32_SERIAL_UART4_PRIORITY 12
+#define STM32_SERIAL_UART5_PRIORITY 12
+#define STM32_SERIAL_USART6_PRIORITY 12
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1 TRUE
+#define STM32_SPI_USE_SPI2 FALSE
+#define STM32_SPI_USE_SPI3 FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_SPI_SPI1_DMA_PRIORITY 1
+#define STM32_SPI_SPI2_DMA_PRIORITY 1
+#define STM32_SPI_SPI3_DMA_PRIORITY 1
+#define STM32_SPI_SPI1_IRQ_PRIORITY 10
+#define STM32_SPI_SPI2_IRQ_PRIORITY 10
+#define STM32_SPI_SPI3_IRQ_PRIORITY 10
+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
+
+/*
+ * ST driver system settings.
+ */
+#define STM32_ST_IRQ_PRIORITY 8
+#define STM32_ST_USE_TIMER 2
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1 FALSE
+#define STM32_UART_USE_USART2 FALSE
+#define STM32_UART_USE_USART3 FALSE
+#define STM32_UART_USE_UART4 FALSE
+#define STM32_UART_USE_UART5 FALSE
+#define STM32_UART_USE_USART6 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
+#define STM32_UART_USART1_IRQ_PRIORITY 12
+#define STM32_UART_USART2_IRQ_PRIORITY 12
+#define STM32_UART_USART3_IRQ_PRIORITY 12
+#define STM32_UART_UART4_IRQ_PRIORITY 12
+#define STM32_UART_UART5_IRQ_PRIORITY 12
+#define STM32_UART_USART6_IRQ_PRIORITY 6
+#define STM32_UART_USART1_DMA_PRIORITY 0
+#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_USART3_DMA_PRIORITY 0
+#define STM32_UART_UART4_DMA_PRIORITY 0
+#define STM32_UART_UART5_DMA_PRIORITY 0
+#define STM32_UART_USART6_DMA_PRIORITY 2
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
+
+/*
+ * USB driver system settings.
+ */
+#define STM32_USB_USE_OTG1 FALSE
+#define STM32_USB_USE_OTG2 FALSE
+#define STM32_USB_OTG1_IRQ_PRIORITY 14
+#define STM32_USB_OTG2_IRQ_PRIORITY 14
+#define STM32_USB_OTG1_RX_FIFO_SIZE 512
+#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
+#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
+#define STM32_USB_OTG_THREAD_STACK_SIZE 128
+#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
+
+/*
+ * EMC driver system settings.
+ */
+#define STM32_EMC_USE_FSMC1 TRUE
+#define STM32_EMC_FSMC1_IRQ_PRIORITY 10
+#define STM32_EMC_EMCNAND_USE_FSMC_INT FALSE
+
+#define STM32_EMCNAND_USE_EMCNAND1 TRUE
+#define STM32_EMCNAND_EMCNAND1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_EMCNAND_EMCNAND1_DMA_PRIORITY 0
+#define STM32_EMCNAND_DMA_ERROR_HOOK(emcnandp) osalSysHalt("DMA failure")
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-24 00:17:06 +0000