git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6074 35acf78f-673a-0410-8e92-d51de3d6d3f4

3 files changed, 82 insertions, 88 deletions

diff --git a/os/halnew/platforms/STM32/can_lld.c b/os/halnew/platforms/STM32/can_lld.c
index 30e9dd7cf..36da951b8 100644
--- a/os/halnew/platforms/STM32/can_lld.c
+++ b/os/halnew/platforms/STM32/can_lld.c
@@ -22,7 +22,6 @@
  * @{

  */

 

-#include "ch.h"

 #include "hal.h"

 

 #if HAL_USE_CAN || defined(__DOXYGEN__)

@@ -130,11 +129,10 @@ static void can_lld_tx_handler(CANDriver *canp) {
 

   /* No more events until a message is transmitted.*/

   canp->can->TSR = CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2;

-  chSysLockFromIsr();

-  while (chSemGetCounterI(&canp->txsem) < 0)

-    chSemSignalI(&canp->txsem);

-  chEvtBroadcastFlagsI(&canp->txempty_event, CAN_MAILBOX_TO_MASK(1));

-  chSysUnlockFromIsr();

+  osalSysLockFromISR();

+  osalQueueWakeupAllI(&canp->txqueue, MSG_OK);

+  osalEventBroadcastFlagsI(&canp->txempty_event, CAN_MAILBOX_TO_MASK(1));

+  osalSysUnlockFromISR();

 }

 

 /**

@@ -151,18 +149,17 @@ static void can_lld_rx0_handler(CANDriver *canp) {
   if ((rf0r & CAN_RF0R_FMP0) > 0) {

     /* No more receive events until the queue 0 has been emptied.*/

     canp->can->IER &= ~CAN_IER_FMPIE0;

-    chSysLockFromIsr();

-    while (chSemGetCounterI(&canp->rxsem) < 0)

-      chSemSignalI(&canp->rxsem);

-    chEvtBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(1));

-    chSysUnlockFromIsr();

+    osalSysLockFromISR();

+    osalQueueWakeupAllI(&canp->rxqueue, MSG_OK);

+    osalEventBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(1));

+    osalSysUnlockFromISR();

   }

   if ((rf0r & CAN_RF0R_FOVR0) > 0) {

     /* Overflow events handling.*/

     canp->can->RF0R = CAN_RF0R_FOVR0;

-    chSysLockFromIsr();

-    chEvtBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR);

-    chSysUnlockFromIsr();

+    osalSysLockFromISR();

+    osalEventBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR);

+    osalSysUnlockFromISR();

   }

 }

 

@@ -180,18 +177,17 @@ static void can_lld_rx1_handler(CANDriver *canp) {
   if ((rf1r & CAN_RF1R_FMP1) > 0) {

     /* No more receive events until the queue 0 has been emptied.*/

     canp->can->IER &= ~CAN_IER_FMPIE1;

-    chSysLockFromIsr();

-    while (chSemGetCounterI(&canp->rxsem) < 0)

-      chSemSignalI(&canp->rxsem);

-    chEvtBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(2));

-    chSysUnlockFromIsr();

+    osalSysLockFromISR();

+    osalQueueWakeupAllI(&canp->rxqueue, MSG_OK);

+    osalEventBroadcastFlagsI(&canp->rxfull_event, CAN_MAILBOX_TO_MASK(2));

+    osalSysUnlockFromISR();

   }

   if ((rf1r & CAN_RF1R_FOVR1) > 0) {

     /* Overflow events handling.*/

     canp->can->RF1R = CAN_RF1R_FOVR1;

-    chSysLockFromIsr();

-    chEvtBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR);

-    chSysUnlockFromIsr();

+    osalSysLockFromISR();

+    osalEventBroadcastFlagsI(&canp->error_event, CAN_OVERFLOW_ERROR);

+    osalSysUnlockFromISR();

   }

 }

 

@@ -212,26 +208,26 @@ static void can_lld_sce_handler(CANDriver *canp) {
   if (msr & CAN_MSR_WKUI) {

     canp->state = CAN_READY;

     canp->can->MCR &= ~CAN_MCR_SLEEP;

-    chSysLockFromIsr();

-    chEvtBroadcastI(&canp->wakeup_event);

-    chSysUnlockFromIsr();

+    osalSysLockFromISR();

+    osalEventBroadcastFlagsI(&canp->wakeup_event, 0);

+    osalSysUnlockFromISR();

   }

 #endif /* CAN_USE_SLEEP_MODE */

   /* Error event.*/

   if (msr & CAN_MSR_ERRI) {

-    flagsmask_t flags;

+    eventflags_t flags;

     uint32_t esr = canp->can->ESR;

 

     canp->can->ESR &= ~CAN_ESR_LEC;

-    flags = (flagsmask_t)(esr & 7);

+    flags = (eventflags_t)(esr & 7);

     if ((esr & CAN_ESR_LEC) > 0)

       flags |= CAN_FRAMING_ERROR;

 

-    chSysLockFromIsr();

+    osalSysLockFromISR();

     /* The content of the ESR register is copied unchanged in the upper

        half word of the listener flags mask.*/

-    chEvtBroadcastFlagsI(&canp->error_event, flags | (flagsmask_t)(esr << 16));

-    chSysUnlockFromIsr();

+    osalEventBroadcastFlagsI(&canp->error_event, flags | (eventflags_t)(esr << 16));

+    osalSysUnlockFromISR();

   }

 }

 

@@ -245,13 +241,13 @@ static void can_lld_sce_handler(CANDriver *canp) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(STM32_CAN1_TX_HANDLER) {

+OSAL_IRQ_HANDLER(STM32_CAN1_TX_HANDLER) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   can_lld_tx_handler(&CAND1);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /*

@@ -259,13 +255,13 @@ CH_IRQ_HANDLER(STM32_CAN1_TX_HANDLER) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(STM32_CAN1_RX0_HANDLER) {

+OSAL_IRQ_HANDLER(STM32_CAN1_RX0_HANDLER) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   can_lld_rx0_handler(&CAND1);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -273,13 +269,13 @@ CH_IRQ_HANDLER(STM32_CAN1_RX0_HANDLER) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(STM32_CAN1_RX1_HANDLER) {

+OSAL_IRQ_HANDLER(STM32_CAN1_RX1_HANDLER) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   can_lld_rx1_handler(&CAND1);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -287,13 +283,13 @@ CH_IRQ_HANDLER(STM32_CAN1_RX1_HANDLER) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(STM32_CAN1_SCE_HANDLER) {

+OSAL_IRQ_HANDLER(STM32_CAN1_SCE_HANDLER) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   can_lld_sce_handler(&CAND1);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif /* STM32_CAN_USE_CAN1 */

 

@@ -303,13 +299,13 @@ CH_IRQ_HANDLER(STM32_CAN1_SCE_HANDLER) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(STM32_CAN2_TX_HANDLER) {

+OSAL_IRQ_HANDLER(STM32_CAN2_TX_HANDLER) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   can_lld_tx_handler(&CAND2);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /*

@@ -317,13 +313,13 @@ CH_IRQ_HANDLER(STM32_CAN2_TX_HANDLER) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(STM32_CAN2_RX0_HANDLER) {

+OSAL_IRQ_HANDLER(STM32_CAN2_RX0_HANDLER) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   can_lld_rx0_handler(&CAND2);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -331,13 +327,13 @@ CH_IRQ_HANDLER(STM32_CAN2_RX0_HANDLER) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(STM32_CAN2_RX1_HANDLER) {

+OSAL_IRQ_HANDLER(STM32_CAN2_RX1_HANDLER) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   can_lld_rx1_handler(&CAND2);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -345,13 +341,13 @@ CH_IRQ_HANDLER(STM32_CAN2_RX1_HANDLER) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(STM32_CAN2_SCE_HANDLER) {

+OSAL_IRQ_HANDLER(STM32_CAN2_SCE_HANDLER) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   can_lld_sce_handler(&CAND2);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif /* STM32_CAN_USE_CAN2 */

 

@@ -412,8 +408,8 @@ void can_lld_start(CANDriver *canp) {
 #if STM32_CAN_USE_CAN2

   if (&CAND2 == canp) {

 

-    chDbgAssert(CAND1.state != CAN_STOP,

-                "can_lld_start(), #1", "CAN1 must be started");

+    osalDbgAssert(CAND1.state != CAN_STOP,

+                  "can_lld_start(), #1", "CAN1 must be started");

 

     nvicEnableVector(STM32_CAN2_TX_NUMBER,

                      CORTEX_PRIORITY_MASK(STM32_CAN_CAN2_IRQ_PRIORITY));

@@ -431,7 +427,7 @@ void can_lld_start(CANDriver *canp) {
   canp->state = CAN_STARTING;

   canp->can->MCR = CAN_MCR_INRQ;

   while ((canp->can->MSR & CAN_MSR_INAK) == 0)

-    chThdSleepS(1);

+    osalThreadSleepS(1);

   /* BTR initialization.*/

   canp->can->BTR = canp->config->btr;

   /* MCR initialization.*/

@@ -459,8 +455,8 @@ void can_lld_stop(CANDriver *canp) {
     if (&CAND1 == canp) {

 

 #if STM32_CAN_USE_CAN2

-      chDbgAssert(CAND2.state == CAN_STOP,

-                  "can_lld_stop(), #1", "CAN2 must be stopped");

+      osalDbgAssert(CAND2.state == CAN_STOP,

+                    "can_lld_stop(), #1", "CAN2 must be stopped");

 #endif

 

       CAN1->MCR = 0x00010002;                   /* Register reset value.    */

@@ -698,17 +694,16 @@ void can_lld_wakeup(CANDriver *canp) {
  */

 void canSTM32SetFilters(uint32_t can2sb, uint32_t num, const CANFilter *cfp) {

 

-  chDbgCheck((can2sb > 1) && (can2sb < STM32_CAN_MAX_FILTERS) &&

-             (num < STM32_CAN_MAX_FILTERS),

-             "canSTM32SetFilters");

+  osalDbgCheck((can2sb > 1) && (can2sb < STM32_CAN_MAX_FILTERS) &&

+               (num < STM32_CAN_MAX_FILTERS));

 

 #if STM32_CAN_USE_CAN1

-  chDbgAssert(CAND1.state == CAN_STOP,

-              "canSTM32SetFilters(), #1", "invalid state");

+  osalDbgAssert(CAND1.state == CAN_STOP,

+                "canSTM32SetFilters(), #1", "invalid state");

 #endif

 #if STM32_CAN_USE_CAN2

-  chDbgAssert(CAND2.state == CAN_STOP,

-              "canSTM32SetFilters(), #2", "invalid state");

+  osalDbgAssert(CAND2.state == CAN_STOP,

+                "canSTM32SetFilters(), #2", "invalid state");

 #endif

 

   can_lld_set_filters(can2sb, num, cfp);

diff --git a/os/halnew/platforms/STM32F30x/adc_lld.c b/os/halnew/platforms/STM32F30x/adc_lld.c
index 7936be680..e951df14e 100644
--- a/os/halnew/platforms/STM32F30x/adc_lld.c
+++ b/os/halnew/platforms/STM32F30x/adc_lld.c
@@ -22,7 +22,6 @@
  * @{

  */

 

-#include "ch.h"

 #include "hal.h"

 

 #if HAL_USE_ADC || defined(__DOXYGEN__)

@@ -148,14 +147,14 @@ static void adc_lld_analog_off(ADCDriver *adcp) {
  */

 static void adc_lld_calibrate(ADCDriver *adcp) {

 

-  chDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN_0, "adc_lld_calibrate(), #1",

-                                                   "invalid register state");

+  osalDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN_0, "adc_lld_calibrate(), #1",

+                                                     "invalid register state");

   adcp->adcm->CR |= ADC_CR_ADCAL;

   while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0)

     ;

 #if STM32_ADC_DUAL_MODE

-  chDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN_0, "adc_lld_calibrate(), #2",

-                                                   "invalid register state");

+  osalDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN_0, "adc_lld_calibrate(), #2",

+                                                     "invalid register state");

   adcp->adcs->CR |= ADC_CR_ADCAL;

   while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0)

     ;

@@ -250,10 +249,10 @@ static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector88) {

+OSAL_IRQ_HANDLER(Vector88) {

   uint32_t isr;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

 #if STM32_ADC_DUAL_MODE

   isr  = ADC1->ISR;

@@ -267,7 +266,7 @@ CH_IRQ_HANDLER(Vector88) {
 

   adc_lld_serve_interrupt(&ADCD1, isr);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif /* STM32_ADC_USE_ADC1 */

 

@@ -277,17 +276,17 @@ CH_IRQ_HANDLER(Vector88) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(VectorFC) {

+OSAL_IRQ_HANDLER(VectorFC) {

   uint32_t isr;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   isr  = ADC3->ISR;

   ADC3->ISR = isr;

 

   adc_lld_serve_interrupt(&ADCD3, isr);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 #if STM32_ADC_DUAL_MODE

@@ -296,17 +295,17 @@ CH_IRQ_HANDLER(VectorFC) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector134) {

+OSAL_IRQ_HANDLER(Vector134) {

   uint32_t isr;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   isr  = ADC4->ISR;

   ADC4->ISR = isr;

 

   adc_lld_serve_interrupt(&ADCD3, isr);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif /* STM32_ADC_DUAL_MODE */

 #endif /* STM32_ADC_USE_ADC3 */

@@ -381,7 +380,7 @@ void adc_lld_start(ADCDriver *adcp) {
                             STM32_ADC_ADC12_DMA_IRQ_PRIORITY,

                             (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,

                             (void *)adcp);

-      chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");

+      osalDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");

       rccEnableADC12(FALSE);

     }

 #endif /* STM32_ADC_USE_ADC1 */

@@ -393,7 +392,7 @@ void adc_lld_start(ADCDriver *adcp) {
                             STM32_ADC_ADC34_DMA_IRQ_PRIORITY,

                             (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,

                             (void *)adcp);

-      chDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated");

+      osalDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated");

       rccEnableADC34(FALSE);

     }

 #endif /* STM32_ADC_USE_ADC2 */

@@ -462,9 +461,9 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
   uint32_t dmamode, ccr, cfgr;

   const ADCConversionGroup *grpp = adcp->grpp;

 

-  chDbgAssert(!STM32_ADC_DUAL_MODE || ((grpp->num_channels & 1) == 0),

-              "adc_lld_start_conversion(), #1",

-              "odd number of channels in dual mode");

+  osalDbgAssert(!STM32_ADC_DUAL_MODE || ((grpp->num_channels & 1) == 0),

+                "adc_lld_start_conversion(), #1",

+                "odd number of channels in dual mode");

 

   /* Calculating control registers values.*/

   dmamode = adcp->dmamode;

diff --git a/os/halnew/src/can.c b/os/halnew/src/can.c
index 394e1d6a8..9a352ddd1 100644
--- a/os/halnew/src/can.c
+++ b/os/halnew/src/can.c
@@ -249,7 +249,7 @@ void canSleep(CANDriver *canp) {
   if (canp->state == CAN_READY) {

     can_lld_sleep(canp);

     canp->state = CAN_SLEEP;

-    osalEventBroadcastI(&canp->sleep_event);

+    osalEventBroadcastFlagsI(&canp->sleep_event, 0);

     osalOsRescheduleS();

   }

   osalSysUnlock();

@@ -272,8 +272,8 @@ void canWakeup(CANDriver *canp) {
   if (canp->state == CAN_SLEEP) {

     can_lld_wakeup(canp);

     canp->state = CAN_READY;

-    osalEventBroadcastI(&canp->wakeup_event);

-    chSchRescheduleS();

+    osalEventBroadcastFlagsI(&canp->wakeup_event, 0);

+    osalOsRescheduleS();

   }

   osalSysUnlock();

 }