diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-09-19 14:01:42 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-09-19 14:01:42 +0000 |
| commit | f5c7e2f7cd4e43f272db4e9f053053eea9f92dde (patch) | |
| tree | b7d3967ce317ed913816d56863a06aec6cc12e99 | |
| parent | 31a099cb104ea4d7d957bb65bbdc7e8edbdbe636 (diff) | |
| download | ChibiOS-f5c7e2f7cd4e43f272db4e9f053053eea9f92dde.tar.gz ChibiOS-f5c7e2f7cd4e43f272db4e9f053053eea9f92dde.tar.bz2 ChibiOS-f5c7e2f7cd4e43f272db4e9f053053eea9f92dde.zip | |
Fixed an STM32 GPT driver problem.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3353 35acf78f-673a-0410-8e92-d51de3d6d3f4
| -rw-r--r-- | os/hal/platforms/STM32/gpt_lld.c | 4 | ||||
| -rw-r--r-- | testhal/STM32L1xx/GPT/main.c | 2 |
2 files changed, 5 insertions, 1 deletions
diff --git a/os/hal/platforms/STM32/gpt_lld.c b/os/hal/platforms/STM32/gpt_lld.c index 0fd5dde73..af8737f04 100644 --- a/os/hal/platforms/STM32/gpt_lld.c +++ b/os/hal/platforms/STM32/gpt_lld.c @@ -401,6 +401,10 @@ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { gptp->tim->ARR = interval - 1; /* Time constant. */
gptp->tim->EGR = TIM_EGR_UG; /* Update event. */
+ gptp->tim->CNT = 0; /* Reset counter. */
+ /* NOTE: After generating the UG event it takes several clock cycles before
+ SR bit 0 goes to 1. This is because the clearing of CNT has been inserted
+ before the clearing of SR, to give it some time.*/
gptp->tim->SR = 0; /* Clear pending IRQs (if any). */
gptp->tim->DIER = TIM_DIER_UIE; /* Update Event IRQ enabled. */
gptp->tim->CR1 = TIM_CR1_URS | TIM_CR1_CEN;
diff --git a/testhal/STM32L1xx/GPT/main.c b/testhal/STM32L1xx/GPT/main.c index 4fadc4f9c..380d9650c 100644 --- a/testhal/STM32L1xx/GPT/main.c +++ b/testhal/STM32L1xx/GPT/main.c @@ -29,7 +29,7 @@ static void gpt2cb(GPTDriver *gptp) { (void)gptp;
palSetPad(GPIOB, GPIOB_LED4);
chSysLockFromIsr();
- gptStartOneShotI(&GPTD3, 200); /* 0.02 second pulse.*/
+ gptStartOneShotI(&GPTD3, 1000); /* 0.02 second pulse.*/
chSysUnlockFromIsr();
}
|