git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1429 35acf78f-673a-0410-8e92-d51de3d6d3f4

5 files changed, 64 insertions, 8 deletions

diff --git a/os/hal/include/pwm.h b/os/hal/include/pwm.h
index b48f067c9..9cb6ce4c4 100644
--- a/os/hal/include/pwm.h
+++ b/os/hal/include/pwm.h
@@ -42,8 +42,10 @@ typedef enum {
  * @brief PWM logic mode.

  */

 typedef enum {

-  PWM_ACTIVE_HIGH = 0,                  /**< @brief Idle is logic level 0.  */

-  PWM_ACTIVE_LOW = 1                    /**< @brief Idle is logic level 1.  */

+  PWM_OUTPUT_DISABLED = 0,              /**< @brief Output not driven, callback

+                                                    only.                   */

+  PWM_OUTPUT_ACTIVE_HIGH = 1,           /**< @brief Idle is logic level 0.  */

+  PWM_OUTPUT_ACTIVE_LOW = 2             /**< @brief Idle is logic level 1.  */

 } pwmmode_t;

 

 /**

diff --git a/os/hal/platforms/STM32/pal_lld.c b/os/hal/platforms/STM32/pal_lld.c
index dee03a2de..3966f9c69 100644
--- a/os/hal/platforms/STM32/pal_lld.c
+++ b/os/hal/platforms/STM32/pal_lld.c
@@ -129,6 +129,16 @@ void _pal_lld_setgroupmode(ioportid_t port,
     0,          /* PAL_MODE_INPUT_ANALOG */

     3,          /* PAL_MODE_OUTPUT_PUSHPULL, 50MHz.*/

     7,          /* PAL_MODE_OUTPUT_OPENDRAIN, 50MHz.*/

+    8,          /* Reserved.*/

+    8,          /* Reserved.*/

+    8,          /* Reserved.*/

+    8,          /* Reserved.*/

+    8,          /* Reserved.*/

+    8,          /* Reserved.*/

+    8,          /* Reserved.*/

+    8,          /* Reserved.*/

+    0xB,        /* PAL_MODE_STM32_ALTERNATE_PUSHPULL, 50MHz.*/

+    0xF,        /* PAL_MODE_STM32_ALTERNATE_OPENDRAIN, 50MHz.*/

   };

   uint32_t mh, ml, crh, crl, cfg;

   unsigned i;

diff --git a/os/hal/platforms/STM32/pal_lld.h b/os/hal/platforms/STM32/pal_lld.h
index 5029766e5..7b052ae3f 100644
--- a/os/hal/platforms/STM32/pal_lld.h
+++ b/os/hal/platforms/STM32/pal_lld.h
@@ -34,6 +34,16 @@
 /*===========================================================================*/

 

 /**

+ * @brief STM32 specific alternate push-pull output mode.

+ */

+#define PAL_MODE_STM32_ALTERNATE_PUSHPULL   16

+

+/**

+ * @brief STM32 specific alternate open-drain output mode.

+ */

+#define PAL_MODE_STM32_ALTERNATE_OPENDRAIN  17

+

+/**

  * @brief GPIO port setup info.

  */

 typedef struct {

diff --git a/os/hal/platforms/STM32/pwm_lld.c b/os/hal/platforms/STM32/pwm_lld.c
index 7fbaf5eae..6b5d7d71c 100644
--- a/os/hal/platforms/STM32/pwm_lld.c
+++ b/os/hal/platforms/STM32/pwm_lld.c
@@ -95,7 +95,7 @@ CH_IRQ_HANDLER(VectorAC) {
 

   CH_IRQ_PROLOGUE();

 

-  sr = TIM1->SR;

+  sr = TIM1->SR & TIM1->DIER;

   TIM1->SR = ~(TIM_SR_CC1IF | TIM_SR_CC2IF | TIM_SR_CC3IF | TIM_SR_CC4IF);

   if ((sr & TIM_SR_CC1IF) != 0)

     PWMD1.pd_config->pc_channels[0].pcc_callback();

@@ -160,19 +160,45 @@ void pwm_lld_start(PWMDriver *pwmp) {
   pwmp->pd_tim->PSC  = pwmp->pd_config->pc_psc;

   pwmp->pd_tim->CNT  = 0;

   pwmp->pd_tim->ARR  = pwmp->pd_config->pc_arr;

-  ccer = TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E;

-  if (pwmp->pd_config->pc_channels[0].pcc_mode == PWM_ACTIVE_LOW)

+  /* Output enables and polarities setup.*/

+  ccer = 0;

+  switch (pwmp->pd_config->pc_channels[0].pcc_mode) {

+  case PWM_OUTPUT_ACTIVE_LOW:

     ccer |= TIM_CCER_CC1P;

-  if (pwmp->pd_config->pc_channels[1].pcc_mode == PWM_ACTIVE_LOW)

+  case PWM_OUTPUT_ACTIVE_HIGH:

+    ccer |= TIM_CCER_CC1E;

+  default:

+    ;

+  }

+  switch (pwmp->pd_config->pc_channels[1].pcc_mode) {

+  case PWM_OUTPUT_ACTIVE_LOW:

     ccer |= TIM_CCER_CC2P;

-  if (pwmp->pd_config->pc_channels[2].pcc_mode == PWM_ACTIVE_LOW)

+  case PWM_OUTPUT_ACTIVE_HIGH:

+    ccer |= TIM_CCER_CC2E;

+  default:

+    ;

+  }

+  switch (pwmp->pd_config->pc_channels[2].pcc_mode) {

+  case PWM_OUTPUT_ACTIVE_LOW:

     ccer |= TIM_CCER_CC3P;

-  if (pwmp->pd_config->pc_channels[3].pcc_mode == PWM_ACTIVE_LOW)

+  case PWM_OUTPUT_ACTIVE_HIGH:

+    ccer |= TIM_CCER_CC3E;

+  default:

+    ;

+  }

+  switch (pwmp->pd_config->pc_channels[3].pcc_mode) {

+  case PWM_OUTPUT_ACTIVE_LOW:

     ccer |= TIM_CCER_CC4P;

+  case PWM_OUTPUT_ACTIVE_HIGH:

+    ccer |= TIM_CCER_CC4E;

+  default:

+    ;

+  }

   pwmp->pd_tim->CCER = ccer;

   pwmp->pd_tim->EGR  = TIM_EGR_UG;          /* Update event.                */

   pwmp->pd_tim->SR   = 0;                   /* Clear pending IRQs.          */

   pwmp->pd_tim->DIER = pwmp->pd_config->pc_callback == NULL ? 0 : TIM_DIER_UIE;

+  pwmp->pd_tim->BDTR = TIM_BDTR_MOE;

   pwmp->pd_tim->CR1  = TIM_CR1_ARPE | TIM_CR1_URS |

                        TIM_CR1_CEN;         /* Timer configured and started.*/

 }

@@ -187,6 +213,7 @@ void pwm_lld_stop(PWMDriver *pwmp) {
   if (pwmp->pd_state == PWM_READY) {

     stop_channels(pwmp);

     pwmp->pd_tim->CR1 = 0;

+    pwmp->pd_tim->BDTR = 0;

     pwmp->pd_tim->DIER = 0;

 

 #if USE_STM32_PWM1

diff --git a/readme.txt b/readme.txt
index db8792585..59b68dc0a 100644
--- a/readme.txt
+++ b/readme.txt
@@ -3,6 +3,13 @@
 *****************************************************************************

 

 *** 1.3.6 ***

+- FIX: Fixed missing STM32 PWM low level driver error in platform.mk by

+  adding the driver files (bug 2913560).

+- NEW: STM32 PWM driver implementation.

+- NEW: Added custom mode settings to the STM32 PAL driver:

+  - PAL_MODE_STM32_ALTERNATE_PUSHPULL

+  - PAL_MODE_STM32_ALTERNATE_OPENDRAIN

+- CHANGE: Changes to the PWM driver model, made it simpler.

 

 *** 1.3.5 ***

 - FIX: Fixed problem with memory core allocator (bug 2912528).