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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-05-27 14:44:33 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-05-27 14:44:33 +0000 |
| commit | f269531a409d8f757a1e98fddf66142a0d331040 (patch) | |
| tree | 375d43bc769071de5c65d91db667119ff04dcf51 | |
| parent | b9df092c8c8134e51dd63b2e5046842d14019c59 (diff) | |
| download | ChibiOS-f269531a409d8f757a1e98fddf66142a0d331040.tar.gz ChibiOS-f269531a409d8f757a1e98fddf66142a0d331040.tar.bz2 ChibiOS-f269531a409d8f757a1e98fddf66142a0d331040.zip | |
Fixed bug #838.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10202 35acf78f-673a-0410-8e92-d51de3d6d3f4
| -rw-r--r-- | os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c | 16 | ||||
| -rw-r--r-- | readme.txt | 2 |
2 files changed, 10 insertions, 8 deletions
diff --git a/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c b/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c index 1990ba712..6b36178ae 100644 --- a/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c +++ b/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c @@ -565,10 +565,10 @@ void uart_lld_start(UARTDriver *uartp) { if (&UARTD4 == uartp) {
bool b;
- chDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
- "specified invalid bits in UART4 CR2 register settings");
- chDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
- "specified invalid bits in UART4 CR3 register settings");
+ osalDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
+ "specified invalid bits in UART4 CR2 register settings");
+ osalDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
+ "specified invalid bits in UART4 CR3 register settings");
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_UART4_IRQ_PRIORITY,
@@ -591,10 +591,10 @@ void uart_lld_start(UARTDriver *uartp) { if (&UARTD5 == uartp) {
bool b;
- chDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
- "specified invalid bits in UART5 CR2 register settings");
- chDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
- "specified invalid bits in UART5 CR3 register settings");
+ osalDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
+ "specified invalid bits in UART5 CR2 register settings");
+ osalDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
+ "specified invalid bits in UART5 CR3 register settings");
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_UART5_IRQ_PRIORITY,
diff --git a/readme.txt b/readme.txt index ddd88ccbf..011269dfd 100644 --- a/readme.txt +++ b/readme.txt @@ -161,6 +161,8 @@ - RT: Merged RT4.
- NIL: Merged NIL2.
- NIL: Added STM32F7 demo.
+- HAL: Fixed dependency to kernel in uart lld (v1) (bug #838)(backported
+ to 16.1.9).
- HAL: Fixed STM32 OTGv1 number of endpoints (bug #833)(backported to 16.1.8).
- HAL: Fixed transaction end problem with STM32 OTGv1 driver (bug #832)
(backported to 16.1.8).
|