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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-02-06 10:57:56 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-02-06 10:57:56 +0000 |
| commit | efc74c184bfbb2dae2195c20795f3f7862b7c5e9 (patch) | |
| tree | a5c545f2895813554c158c90b4772d77edc27bf6 | |
| parent | 8311f8dc8ec2bdc968fe44ec7371310532880e7f (diff) | |
| download | ChibiOS-efc74c184bfbb2dae2195c20795f3f7862b7c5e9.tar.gz ChibiOS-efc74c184bfbb2dae2195c20795f3f7862b7c5e9.tar.bz2 ChibiOS-efc74c184bfbb2dae2195c20795f3f7862b7c5e9.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5121 35acf78f-673a-0410-8e92-d51de3d6d3f4
| -rw-r--r-- | os/ports/GCC/PPC/SPC56ELxx/bam.s | 53 | ||||
| -rw-r--r-- | os/ports/GCC/PPC/SPC56ELxx/core.s | 83 |
2 files changed, 66 insertions, 70 deletions
diff --git a/os/ports/GCC/PPC/SPC56ELxx/bam.s b/os/ports/GCC/PPC/SPC56ELxx/bam.s index bccf5d0c5..1d9f1c6b5 100644 --- a/os/ports/GCC/PPC/SPC56ELxx/bam.s +++ b/os/ports/GCC/PPC/SPC56ELxx/bam.s @@ -31,59 +31,10 @@ /* BAM info, SWT off, WTE off, VLE from settings.*/
.section .bam, "ax"
.long 0x015A0000
- .long .clear_ecc
-
- /* RAM clearing, this device requires a write to all RAM location in
- order to initialize the ECC detection hardware, this is going to
- slow down the startup but there is no way around.
- Note all registers are cleared in order to avoid possible problems
- with lockstep mode.*/
-.clear_ecc:
- xor %r0, %r0, %r0
- xor %r1, %r1, %r1
- xor %r2, %r2, %r2
- xor %r3, %r3, %r3
- xor %r4, %r4, %r4
- xor %r5, %r5, %r5
- xor %r6, %r6, %r6
- xor %r7, %r7, %r7
- xor %r8, %r8, %r8
- xor %r9, %r9, %r9
- xor %r10, %r10, %r10
- xor %r11, %r11, %r11
- xor %r12, %r12, %r12
- xor %r13, %r13, %r13
- xor %r14, %r14, %r14
- xor %r15, %r15, %r15
- xor %r16, %r16, %r16
- xor %r17, %r17, %r17
- xor %r18, %r18, %r18
- xor %r19, %r19, %r19
- xor %r20, %r20, %r20
- xor %r21, %r21, %r21
- xor %r22, %r22, %r22
- xor %r23, %r23, %r23
- xor %r24, %r24, %r24
- xor %r25, %r25, %r25
- xor %r26, %r26, %r26
- xor %r27, %r27, %r27
- xor %r28, %r28, %r28
- xor %r29, %r29, %r29
- xor %r30, %r30, %r30
- xor %r31, %r31, %r31
- lis %r4, __ram_start__@h
- ori %r4, %r4, __ram_start__@l
- lis %r5, __ram_end__@h
- ori %r5, %r5, __ram_end__@l
-.cleareccloop:
- cmpl cr0, %r4, %r5
- bge cr0, .cleareccend
- stmw %r16, 0(%r4)
- addi %r4, %r4, 64
- b .cleareccloop
-.cleareccend:
+ .long .init
/* HW configuration.*/
+.init:
bl _coreinit
b _boot_address
diff --git a/os/ports/GCC/PPC/SPC56ELxx/core.s b/os/ports/GCC/PPC/SPC56ELxx/core.s index 4d24e7ff9..7e1cb2273 100644 --- a/os/ports/GCC/PPC/SPC56ELxx/core.s +++ b/os/ports/GCC/PPC/SPC56ELxx/core.s @@ -158,38 +158,31 @@ /*
* Unhandled exceptions handler.
*/
- .weak _IVOR0
+ .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
+ .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
+ .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15, _IVOR32, _IVOR33
+ .weak _IVOR34
+ .weak _unhandled_exception
_IVOR0:
- .weak _IVOR1
_IVOR1:
- .weak _IVOR2
_IVOR2:
- .weak _IVOR3
_IVOR3:
- .weak _IVOR5
_IVOR5:
- .weak _IVOR6
_IVOR6:
- .weak _IVOR7
_IVOR7:
- .weak _IVOR8
_IVOR8:
- .weak _IVOR9
_IVOR9:
- .weak _IVOR11
_IVOR11:
- .weak _IVOR12
_IVOR12:
- .weak _IVOR13
_IVOR13:
- .weak _IVOR14
_IVOR14:
- .weak _IVOR15
_IVOR15:
- .weak _unhandled_exception
+_IVOR32:
+_IVOR33:
+_IVOR34:
.type _unhandled_exception, @function
_unhandled_exception:
- b _unhandled_exception
+ b _unhandled_exception
.section .coreinit, "ax"
@@ -198,12 +191,62 @@ _unhandled_exception: .type _coreinit, @function
_coreinit:
/*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ * Note all registers are cleared in order to avoid possible problems
+ * with lockstep mode.
+ */
+.clear_ecc:
+ xor %r0, %r0, %r0
+ xor %r1, %r1, %r1
+ xor %r2, %r2, %r2
+ xor %r3, %r3, %r3
+ xor %r4, %r4, %r4
+ xor %r5, %r5, %r5
+ xor %r6, %r6, %r6
+ xor %r7, %r7, %r7
+ xor %r8, %r8, %r8
+ xor %r9, %r9, %r9
+ xor %r10, %r10, %r10
+ xor %r11, %r11, %r11
+ xor %r12, %r12, %r12
+ xor %r13, %r13, %r13
+ xor %r14, %r14, %r14
+ xor %r15, %r15, %r15
+ xor %r16, %r16, %r16
+ xor %r17, %r17, %r17
+ xor %r18, %r18, %r18
+ xor %r19, %r19, %r19
+ xor %r20, %r20, %r20
+ xor %r21, %r21, %r21
+ xor %r22, %r22, %r22
+ xor %r23, %r23, %r23
+ xor %r24, %r24, %r24
+ xor %r25, %r25, %r25
+ xor %r26, %r26, %r26
+ xor %r27, %r27, %r27
+ xor %r28, %r28, %r28
+ xor %r29, %r29, %r29
+ xor %r30, %r30, %r30
+ xor %r31, %r31, %r31
+ lis %r4, __ram_start__@h
+ ori %r4, %r4, __ram_start__@l
+ lis %r5, __ram_end__@h
+ ori %r5, %r5, __ram_end__@l
+.cleareccloop:
+ cmpl %cr0, %r4, %r5
+ bge %cr0, .cleareccend
+ stmw %r16, 0(%r4)
+ addi %r4, %r4, 64
+ b .cleareccloop
+.cleareccend:
+
+ /*
* Special function registers clearing, required in order to avoid
* possible problems with lockstep mode.
*/
- xor %r31, %r31, %r31
mtcrf 0xFF, %r31
- mtspr 8, %r31 /* LR */
mtspr 9, %r31 /* CTR */
mtspr 22, %r31 /* DEC */
mtspr 26, %r31 /* SRR0-1 */
@@ -231,7 +274,9 @@ _coreinit: mtspr 604, %r31 /* SPRG8-9 */
mtspr 605, %r31
- /* MSR initialization.*/
+ /*
+ * MSR initialization.
+ */
lis %r3, MSR_DEFAULT@h
ori %r3, %r3, MSR_DEFAULT@l
mtMSR %r3
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