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authorGiovanni Di Sirio <gdisirio@gmail.com>2018-03-18 12:43:14 +0000
committerGiovanni Di Sirio <gdisirio@gmail.com>2018-03-18 12:43:14 +0000
commitecfed423dbaeda8cd0e7ad5f51fe8a76ea82f409 (patch)
tree41f8f64e5910b0dfd65e1322688d186f932f6583
parenta18251e55dfe905bc0d41844e9f0b011a6d59faa (diff)
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Fixed bug #927.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11811 110e8d01-0319-4d1e-a829-52ad28d1bb01
-rw-r--r--os/hal/ports/STM32/STM32F0xx/hal_lld.c3
-rw-r--r--os/hal/ports/STM32/STM32F1xx/hal_lld.c3
-rw-r--r--os/hal/ports/STM32/STM32F37x/hal_lld.c3
-rw-r--r--os/hal/ports/STM32/STM32F3xx/hal_lld.c3
-rw-r--r--os/hal/ports/STM32/STM32F4xx/hal_lld.c3
-rw-r--r--os/hal/ports/STM32/STM32F7xx/hal_lld.c3
-rw-r--r--readme.txt2
7 files changed, 8 insertions, 12 deletions
diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.c b/os/hal/ports/STM32/STM32F0xx/hal_lld.c
index ef3469484..d512e786c 100644
--- a/os/hal/ports/STM32/STM32F0xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.c
@@ -272,8 +272,7 @@ void stm32_clock_init(void) {
/* HSI is selected as new source without touching the other fields in
CFGR. Clearing the register has to be postponed after HSI is the
new source.*/
- RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */
- RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/
+ RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW, selecting HSI. */
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
; /* Wait until HSI is selected. */
diff --git a/os/hal/ports/STM32/STM32F1xx/hal_lld.c b/os/hal/ports/STM32/STM32F1xx/hal_lld.c
index d72e1c65b..5b948be05 100644
--- a/os/hal/ports/STM32/STM32F1xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F1xx/hal_lld.c
@@ -253,8 +253,7 @@ void stm32_clock_init(void) {
/* HSI is selected as new source without touching the other fields in
CFGR. Clearing the register has to be postponed after HSI is the
new source.*/
- RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */
- RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/
+ RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW, selecting HSI. */
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
; /* Wait until HSI is selected. */
diff --git a/os/hal/ports/STM32/STM32F37x/hal_lld.c b/os/hal/ports/STM32/STM32F37x/hal_lld.c
index e759ec85b..fb398536c 100644
--- a/os/hal/ports/STM32/STM32F37x/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F37x/hal_lld.c
@@ -154,8 +154,7 @@ void stm32_clock_init(void) {
/* HSI is selected as new source without touching the other fields in
CFGR. Clearing the register has to be postponed after HSI is the
new source.*/
- RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */
- RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/
+ RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW, selecting HSI. */
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
; /* Wait until HSI is selected. */
diff --git a/os/hal/ports/STM32/STM32F3xx/hal_lld.c b/os/hal/ports/STM32/STM32F3xx/hal_lld.c
index 71e298147..766675b65 100644
--- a/os/hal/ports/STM32/STM32F3xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F3xx/hal_lld.c
@@ -159,8 +159,7 @@ void stm32_clock_init(void) {
/* HSI is selected as new source without touching the other fields in
CFGR. Clearing the register has to be postponed after HSI is the
new source.*/
- RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */
- RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/
+ RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW, selecting HSI. */
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
; /* Wait until HSI is selected. */
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
index dd4f2b866..d74ddbf0e 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
@@ -177,8 +177,7 @@ void stm32_clock_init(void) {
/* HSI is selected as new source without touching the other fields in
CFGR. Clearing the register has to be postponed after HSI is the
new source.*/
- RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */
- RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/
+ RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW, selecting HSI. */
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
; /* Wait until HSI is selected. */
diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.c b/os/hal/ports/STM32/STM32F7xx/hal_lld.c
index 770c84444..706082d57 100644
--- a/os/hal/ports/STM32/STM32F7xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.c
@@ -184,8 +184,7 @@ void stm32_clock_init(void) {
/* HSI is selected as new source without touching the other fields in
CFGR. Clearing the register has to be postponed after HSI is the
new source.*/
- RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */
- RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/
+ RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW, selecting HSI. */
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
; /* Wait until HSI is selected. */
diff --git a/readme.txt b/readme.txt
index f5c5901bb..99067edb3 100644
--- a/readme.txt
+++ b/readme.txt
@@ -110,6 +110,8 @@
- EX: Updated LIS302DL to 1.1.0 (backported to 18.2.1).
- EX: Updated LPS25H to 1.1.0 (backported to 18.2.1).
- EX: Updated LSM303DLHC to 1.1.0 (backported to 18.2.1).
+- HAL: Fixed useless writes in read-only CFGR_SWS field on all STM32Fxx
+ (bug #927)(backported to 18.2.1 and 17.6.4).
- HAL: Fixed typo in hal_pal.h (bug #926)(backported to 18.2.1).
- HAL: Fixed I2C address not accepted (bug #923)(backported to 18.2.1
and 17.6.4).