Added mcuconf.h generator for STM32L432xx.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12289 110e8d01-0319-4d1e-a829-52ad28d1bb01

5 files changed, 303 insertions, 29 deletions

diff --git a/demos/STM32/RT-STM32L432KC-NUCLEO32/mcuconf.h b/demos/STM32/RT-STM32L432KC-NUCLEO32/mcuconf.h
index 6803c8b24..cfe6c1538 100644
--- a/demos/STM32/RT-STM32L432KC-NUCLEO32/mcuconf.h
+++ b/demos/STM32/RT-STM32L432KC-NUCLEO32/mcuconf.h
@@ -14,11 +14,8 @@
     limitations under the License.

 */

 

-#ifndef MCUCONF_H

-#define MCUCONF_H

-

 /*

- * STM32L1xx drivers configuration.

+ * STM32L4xx drivers configuration.

  * The following settings override the default settings present in

  * the various device driver implementation headers.

  * Note that the settings for each driver only have effect if the whole

@@ -31,7 +28,11 @@
  * 0...3        Lowest...Highest.

  */

 

+#ifndef MCUCONF_H

+#define MCUCONF_H

+

 #define STM32L4xx_MCUCONF

+#define STM32L432_MCUCONF

 

 /*

  * HAL driver system settings.

@@ -46,16 +47,13 @@
 #define STM32_HSE_ENABLED                   FALSE

 #define STM32_LSE_ENABLED                   TRUE

 #define STM32_MSIPLL_ENABLED                TRUE

-#define STM32_ADC_CLOCK_ENABLED             TRUE

-#define STM32_USB_CLOCK_ENABLED             TRUE

-#define STM32_SAI1_CLOCK_ENABLED            TRUE

-#define STM32_SAI2_CLOCK_ENABLED            TRUE

 #define STM32_MSIRANGE                      STM32_MSIRANGE_4M

 #define STM32_MSISRANGE                     STM32_MSISRANGE_4M

 #define STM32_SW                            STM32_SW_PLL

 #define STM32_PLLSRC                        STM32_PLLSRC_MSI

 #define STM32_PLLM_VALUE                    1

 #define STM32_PLLN_VALUE                    80

+#define STM32_PLLPDIV_VALUE                 0

 #define STM32_PLLP_VALUE                    7

 #define STM32_PLLQ_VALUE                    6

 #define STM32_PLLR_VALUE                    4

@@ -67,29 +65,25 @@
 #define STM32_MCOPRE                        STM32_MCOPRE_DIV1

 #define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK

 #define STM32_PLLSAI1N_VALUE                72

+#define STM32_PLLSAI1PDIV_VALUE             6

 #define STM32_PLLSAI1P_VALUE                7

 #define STM32_PLLSAI1Q_VALUE                6

 #define STM32_PLLSAI1R_VALUE                6

-#define STM32_PLLSAI2N_VALUE                72

-#define STM32_PLLSAI2P_VALUE                7

-#define STM32_PLLSAI2R_VALUE                6

+

+/*

+ * Peripherals clock sources.

+ */

 #define STM32_USART1SEL                     STM32_USART1SEL_SYSCLK

 #define STM32_USART2SEL                     STM32_USART2SEL_SYSCLK

-#define STM32_USART3SEL                     STM32_USART3SEL_SYSCLK

-#define STM32_UART4SEL                      STM32_UART4SEL_SYSCLK

-#define STM32_UART5SEL                      STM32_UART5SEL_SYSCLK

 #define STM32_LPUART1SEL                    STM32_LPUART1SEL_SYSCLK

 #define STM32_I2C1SEL                       STM32_I2C1SEL_SYSCLK

-#define STM32_I2C2SEL                       STM32_I2C2SEL_SYSCLK

 #define STM32_I2C3SEL                       STM32_I2C3SEL_SYSCLK

 #define STM32_LPTIM1SEL                     STM32_LPTIM1SEL_PCLK1

 #define STM32_LPTIM2SEL                     STM32_LPTIM2SEL_PCLK1

 #define STM32_SAI1SEL                       STM32_SAI1SEL_OFF

-#define STM32_SAI2SEL                       STM32_SAI2SEL_OFF

 #define STM32_CLK48SEL                      STM32_CLK48SEL_PLLSAI1

 #define STM32_ADCSEL                        STM32_ADCSEL_SYSCLK

 #define STM32_SWPMI1SEL                     STM32_SWPMI1SEL_PCLK1

-#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK2

 #define STM32_RTCSEL                        STM32_RTCSEL_LSI

 

 /*

@@ -111,11 +105,11 @@
 /*

  * ADC driver system settings.

  */

-#define STM32_ADC_DUAL_MODE                 FALSE

 #define STM32_ADC_COMPACT_SAMPLES           FALSE

 #define STM32_ADC_USE_ADC1                  FALSE

 #define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)

 #define STM32_ADC_ADC1_DMA_PRIORITY         2

+#define STM32_ADC_ADC12_IRQ_PRIORITY        5

 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5

 #define STM32_ADC_ADC123_CLOCK_MODE         ADC_CCR_CKMODE_AHB_DIV1

 

@@ -145,14 +139,10 @@
 #define STM32_GPT_USE_TIM2                  FALSE

 #define STM32_GPT_USE_TIM6                  FALSE

 #define STM32_GPT_USE_TIM7                  FALSE

-#define STM32_GPT_USE_TIM15                 FALSE

-#define STM32_GPT_USE_TIM16                 FALSE

 #define STM32_GPT_TIM1_IRQ_PRIORITY         7

 #define STM32_GPT_TIM2_IRQ_PRIORITY         7

 #define STM32_GPT_TIM6_IRQ_PRIORITY         7

 #define STM32_GPT_TIM7_IRQ_PRIORITY         7

-#define STM32_GPT_TIM15_IRQ_PRIORITY        7

-#define STM32_GPT_TIM16_IRQ_PRIORITY        7

 

 /*

  * I2C driver system settings.

@@ -229,18 +219,14 @@
  */

 #define STM32_UART_USE_USART1               FALSE

 #define STM32_UART_USE_USART2               TRUE

-#define STM32_UART_USE_LPUART1              FALSE

 #define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)

 #define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 6)

 #define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)

 #define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)

-#define STM32_UART_LPUART1_RX_DMA_STREAM    STM32_DMA_STREAM_ID(2, 7)

-#define STM32_UART_LPUART1_TX_DMA_STREAM    STM32_DMA_STREAM_ID(2, 6)

 #define STM32_UART_USART1_IRQ_PRIORITY      12

 #define STM32_UART_USART2_IRQ_PRIORITY      12

 #define STM32_UART_USART1_DMA_PRIORITY      0

 #define STM32_UART_USART2_DMA_PRIORITY      0

-#define STM32_UART_LPUART1_DMA_PRIORITY     0

 #define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")

 

 /*

diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.h b/os/hal/ports/STM32/STM32L4xx/hal_lld.h
index dd5d75195..d3b5578f4 100644
--- a/os/hal/ports/STM32/STM32L4xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.h
@@ -760,7 +760,10 @@
 

 /* Only some devices have strongly checked mcuconf.h files. Others will be

    added gradually.*/

-#if defined(STM32L476xx) && !defined(STM32L476_MCUCONF)

+#if defined(STM32L432xx) && !defined(STM32L432_MCUCONF)

+#error "Using a wrong mcuconf.h file, STM32L432_MCUCONF not defined"

+

+#elif defined(STM32L476xx) && !defined(STM32L476_MCUCONF)

 #error "Using a wrong mcuconf.h file, STM32L476_MCUCONF not defined"

 

 #elif defined(STM32L496xx) && !defined(STM32L496_MCUCONF)

diff --git a/readme.txt b/readme.txt
index e8fa7fe25..cb97eaccc 100644
--- a/readme.txt
+++ b/readme.txt
@@ -91,8 +91,8 @@
 *****************************************************************************

 

 *** Next ***

-- NEW: Added mcuconf.h generators for STM32L476xx, STM32L496xx and STM32L4R5xx

-       devices.

+- NEW: Added mcuconf.h generators for STM32L432xx, STM32L476xx, STM32L496xx

+       and STM32L4R5xx devices.

 - NEW: Added demo for STM32L496ZG-Nucleo144 and STM32L4R5ZI-Nucleo144 boards.

 - NEW: Modified USARTv2 to support HW FIFOs where present.

 - NEW: STM32 DMAv1, ADCv3, DACv1, I2Cv2, SPIv2 and USARTv2 are now

diff --git a/tools/ftl/processors/conf/mcuconf_stm32l432xx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32l432xx/mcuconf.h.ftl
new file mode 100644
index 000000000..8f4d9476e
--- /dev/null
+++ b/tools/ftl/processors/conf/mcuconf_stm32l432xx/mcuconf.h.ftl
@@ -0,0 +1,256 @@
+[#ftl]

+[#--

+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.

+

+    This file is part of ChibiOS.

+

+    ChibiOS is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+  --]

+[@pp.dropOutputFile /]

+[#import "/@lib/libutils.ftl" as utils /]

+[#import "/@lib/liblicense.ftl" as license /]

+[@pp.changeOutputFile name="mcuconf.h" /]

+/*

+[@license.EmitLicenseAsText /]

+*/

+

+/*

+ * STM32L4xx drivers configuration.

+ * The following settings override the default settings present in

+ * the various device driver implementation headers.

+ * Note that the settings for each driver only have effect if the whole

+ * driver is enabled in halconf.h.

+ *

+ * IRQ priorities:

+ * 15...0       Lowest...Highest.

+ *

+ * DMA priorities:

+ * 0...3        Lowest...Highest.

+ */

+

+#ifndef MCUCONF_H

+#define MCUCONF_H

+

+#define STM32L4xx_MCUCONF

+#define STM32L432_MCUCONF

+

+/*

+ * HAL driver system settings.

+ */

+#define STM32_NO_INIT                       ${doc.STM32_NO_INIT!"FALSE"}

+#define STM32_VOS                           ${doc.STM32_VOS!"STM32_VOS_RANGE1"}

+#define STM32_PVD_ENABLE                    ${doc.STM32_PVD_ENABLE!"FALSE"}

+#define STM32_PLS                           ${doc.STM32_PLS!"STM32_PLS_LEV0"}

+#define STM32_HSI16_ENABLED                 ${doc.STM32_HSI16_ENABLED!"FALSE"}

+#define STM32_HSI48_ENABLED                 ${doc.STM32_HSI48_ENABLED!"FALSE"}

+#define STM32_LSI_ENABLED                   ${doc.STM32_LSI_ENABLED!"TRUE"}

+#define STM32_HSE_ENABLED                   ${doc.STM32_HSE_ENABLED!"FALSE"}

+#define STM32_LSE_ENABLED                   ${doc.STM32_LSE_ENABLED!"FALSE"}

+#define STM32_MSIPLL_ENABLED                ${doc.STM32_MSIPLL_ENABLED!"FALSE"}

+#define STM32_MSIRANGE                      ${doc.STM32_MSIRANGE!"STM32_MSIRANGE_4M"}

+#define STM32_MSISRANGE                     ${doc.STM32_MSISRANGE!"STM32_MSISRANGE_4M"}

+#define STM32_SW                            ${doc.STM32_SW!"STM32_SW_PLL"}

+#define STM32_PLLSRC                        ${doc.STM32_PLLSRC!"STM32_PLLSRC_MSI"}

+#define STM32_PLLM_VALUE                    ${doc.STM32_PLLM_VALUE!"1"}

+#define STM32_PLLN_VALUE                    ${doc.STM32_PLLN_VALUE!"80"}

+#define STM32_PLLPDIV_VALUE                 ${doc.STM32_PLLPDIV_VALUE!"0"}

+#define STM32_PLLP_VALUE                    ${doc.STM32_PLLP_VALUE!"7"}

+#define STM32_PLLQ_VALUE                    ${doc.STM32_PLLQ_VALUE!"6"}

+#define STM32_PLLR_VALUE                    ${doc.STM32_PLLR_VALUE!"4"}

+#define STM32_HPRE                          ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}

+#define STM32_PPRE1                         ${doc.STM32_PPRE1!"STM32_PPRE1_DIV1"}

+#define STM32_PPRE2                         ${doc.STM32_PPRE2!"STM32_PPRE2_DIV1"}

+#define STM32_STOPWUCK                      ${doc.STM32_STOPWUCK!"STM32_STOPWUCK_MSI"}

+#define STM32_MCOSEL                        ${doc.STM32_MCOSEL!"STM32_MCOSEL_NOCLOCK"}

+#define STM32_MCOPRE                        ${doc.STM32_MCOPRE!"STM32_MCOPRE_DIV1"}

+#define STM32_LSCOSEL                       ${doc.STM32_LSCOSEL!"STM32_LSCOSEL_NOCLOCK"}

+#define STM32_PLLSAI1N_VALUE                ${doc.STM32_PLLSAI1N_VALUE!"72"}

+#define STM32_PLLSAI1PDIV_VALUE             ${doc.STM32_PLLSAI1PDIV_VALUE!"6"}

+#define STM32_PLLSAI1P_VALUE                ${doc.STM32_PLLSAI1P_VALUE!"7"}

+#define STM32_PLLSAI1Q_VALUE                ${doc.STM32_PLLSAI1Q_VALUE!"6"}

+#define STM32_PLLSAI1R_VALUE                ${doc.STM32_PLLSAI1R_VALUE!"6"}

+

+/*

+ * Peripherals clock sources.

+ */

+#define STM32_USART1SEL                     ${doc.STM32_USART1SEL!"STM32_USART1SEL_SYSCLK"}

+#define STM32_USART2SEL                     ${doc.STM32_USART2SEL!"STM32_USART2SEL_SYSCLK"}

+#define STM32_LPUART1SEL                    ${doc.STM32_LPUART1SEL!"STM32_LPUART1SEL_SYSCLK"}

+#define STM32_I2C1SEL                       ${doc.STM32_I2C1SEL!"STM32_I2C1SEL_SYSCLK"}

+#define STM32_I2C3SEL                       ${doc.STM32_I2C3SEL!"STM32_I2C3SEL_SYSCLK"}

+#define STM32_LPTIM1SEL                     ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK1"}

+#define STM32_LPTIM2SEL                     ${doc.STM32_LPTIM2SEL!"STM32_LPTIM2SEL_PCLK1"}

+#define STM32_SAI1SEL                       ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_OFF"}

+#define STM32_CLK48SEL                      ${doc.STM32_CLK48SEL!"STM32_CLK48SEL_PLL"}

+#define STM32_ADCSEL                        ${doc.STM32_ADCSEL!"STM32_ADCSEL_SYSCLK"}

+#define STM32_SWPMI1SEL                     ${doc.STM32_SWPMI1SEL!"STM32_SWPMI1SEL_PCLK1"}

+#define STM32_RTCSEL                        ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSI"}

+

+/*

+ * IRQ system settings.

+ */

+#define STM32_IRQ_EXTI0_PRIORITY            ${doc.STM32_IRQ_EXTI0_PRIORITY!"6"}

+#define STM32_IRQ_EXTI1_PRIORITY            ${doc.STM32_IRQ_EXTI1_PRIORITY!"6"}

+#define STM32_IRQ_EXTI2_PRIORITY            ${doc.STM32_IRQ_EXTI2_PRIORITY!"6"}

+#define STM32_IRQ_EXTI3_PRIORITY            ${doc.STM32_IRQ_EXTI3_PRIORITY!"6"}

+#define STM32_IRQ_EXTI4_PRIORITY            ${doc.STM32_IRQ_EXTI4_PRIORITY!"6"}

+#define STM32_IRQ_EXTI5_9_PRIORITY          ${doc.STM32_IRQ_EXTI5_9_PRIORITY!"6"}

+#define STM32_IRQ_EXTI10_15_PRIORITY        ${doc.STM32_IRQ_EXTI10_15_PRIORITY!"6"}

+#define STM32_IRQ_EXTI1635_38_PRIORITY      ${doc.STM32_IRQ_EXTI1635_38_PRIORITY!"6"}

+#define STM32_IRQ_EXTI18_PRIORITY           ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"}

+#define STM32_IRQ_EXTI19_PRIORITY           ${doc.STM32_IRQ_EXTI19_PRIORITY!"6"}

+#define STM32_IRQ_EXTI20_PRIORITY           ${doc.STM32_IRQ_EXTI20_PRIORITY!"6"}

+#define STM32_IRQ_EXTI21_22_PRIORITY        ${doc.STM32_IRQ_EXTI21_22_PRIORITY!"6"}

+

+/*

+ * ADC driver system settings.

+ */

+#define STM32_ADC_COMPACT_SAMPLES           ${doc.STM32_ADC_COMPACT_SAMPLES!"FALSE"}

+#define STM32_ADC_USE_ADC1                  ${doc.STM32_ADC_USE_ADC1!"FALSE"}

+#define STM32_ADC_ADC1_DMA_STREAM           ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}

+#define STM32_ADC_ADC1_DMA_PRIORITY         ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}

+#define STM32_ADC_ADC12_IRQ_PRIORITY        ${doc.STM32_ADC_ADC12_IRQ_PRIORITY!"5"}

+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"5"}

+#define STM32_ADC_ADC123_CLOCK_MODE         ${doc.STM32_ADC_ADC123_CLOCK_MODE!"ADC_CCR_CKMODE_AHB_DIV1"}

+

+/*

+ * CAN driver system settings.

+ */

+#define STM32_CAN_USE_CAN1                  ${doc.STM32_CAN_USE_CAN1!"FALSE"}

+#define STM32_CAN_CAN1_IRQ_PRIORITY         ${doc.STM32_CAN_CAN1_IRQ_PRIORITY!"11"}

+

+/*

+ * DAC driver system settings.

+ */

+#define STM32_DAC_DUAL_MODE                 ${doc.STM32_DAC_DUAL_MODE!"FALSE"}

+#define STM32_DAC_USE_DAC1_CH1              ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"}

+#define STM32_DAC_USE_DAC1_CH2              ${doc.STM32_DAC_USE_DAC1_CH2!"FALSE"}

+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"10"}

+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"10"}

+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY     ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}

+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY     ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}

+#define STM32_DAC_DAC1_CH1_DMA_STREAM       ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}

+#define STM32_DAC_DAC1_CH2_DMA_STREAM       ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}

+

+/*

+ * GPT driver system settings.

+ */

+#define STM32_GPT_USE_TIM1                  ${doc.STM32_GPT_USE_TIM1!"FALSE"}

+#define STM32_GPT_USE_TIM2                  ${doc.STM32_GPT_USE_TIM2!"FALSE"}

+#define STM32_GPT_USE_TIM6                  ${doc.STM32_GPT_USE_TIM6!"FALSE"}

+#define STM32_GPT_USE_TIM7                  ${doc.STM32_GPT_USE_TIM7!"FALSE"}

+#define STM32_GPT_TIM1_IRQ_PRIORITY         ${doc.STM32_GPT_TIM1_IRQ_PRIORITY!"7"}

+#define STM32_GPT_TIM2_IRQ_PRIORITY         ${doc.STM32_GPT_TIM2_IRQ_PRIORITY!"7"}

+#define STM32_GPT_TIM6_IRQ_PRIORITY         ${doc.STM32_GPT_TIM6_IRQ_PRIORITY!"7"}

+#define STM32_GPT_TIM7_IRQ_PRIORITY         ${doc.STM32_GPT_TIM7_IRQ_PRIORITY!"7"}

+

+/*

+ * I2C driver system settings.

+ */

+#define STM32_I2C_USE_I2C1                  ${doc.STM32_I2C_USE_I2C1!"FALSE"}

+#define STM32_I2C_USE_I2C3                  ${doc.STM32_I2C_USE_I2C3!"FALSE"}

+#define STM32_I2C_BUSY_TIMEOUT              ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}

+#define STM32_I2C_I2C1_RX_DMA_STREAM        ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}

+#define STM32_I2C_I2C1_TX_DMA_STREAM        ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}

+#define STM32_I2C_I2C3_RX_DMA_STREAM        ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}

+#define STM32_I2C_I2C3_TX_DMA_STREAM        ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}

+#define STM32_I2C_I2C1_IRQ_PRIORITY         ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}

+#define STM32_I2C_I2C3_IRQ_PRIORITY         ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}

+#define STM32_I2C_I2C1_DMA_PRIORITY         ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}

+#define STM32_I2C_I2C3_DMA_PRIORITY         ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"3"}

+#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}

+

+/*

+ * ICU driver system settings.

+ */

+#define STM32_ICU_USE_TIM1                  ${doc.STM32_ICU_USE_TIM1!"FALSE"}

+#define STM32_ICU_USE_TIM2                  ${doc.STM32_ICU_USE_TIM2!"FALSE"}

+#define STM32_ICU_TIM1_IRQ_PRIORITY         ${doc.STM32_ICU_TIM1_IRQ_PRIORITY!"7"}

+#define STM32_ICU_TIM2_IRQ_PRIORITY         ${doc.STM32_ICU_TIM2_IRQ_PRIORITY!"7"}

+

+/*

+ * PWM driver system settings.

+ */

+#define STM32_PWM_USE_ADVANCED              ${doc.STM32_PWM_USE_ADVANCED!"FALSE"}

+#define STM32_PWM_USE_TIM1                  ${doc.STM32_PWM_USE_TIM1!"FALSE"}

+#define STM32_PWM_USE_TIM2                  ${doc.STM32_PWM_USE_TIM2!"FALSE"}

+#define STM32_PWM_TIM1_IRQ_PRIORITY         ${doc.STM32_PWM_TIM1_IRQ_PRIORITY!"7"}

+#define STM32_PWM_TIM2_IRQ_PRIORITY         ${doc.STM32_PWM_TIM2_IRQ_PRIORITY!"7"}

+

+/*

+ * QSPI driver system settings.

+ */

+#define STM32_QSPI_USE_QUADSPI1             ${doc.STM32_QSPI_USE_QUADSPI1!"FALSE"}

+#define STM32_QSPI_QUADSPI1_DMA_STREAM      ${doc.STM32_QSPI_QUADSPI1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}

+

+/*

+ * SERIAL driver system settings.

+ */

+#define STM32_SERIAL_USE_USART1             ${doc.STM32_SERIAL_USE_USART1!"FALSE"}

+#define STM32_SERIAL_USE_USART2             ${doc.STM32_SERIAL_USE_USART2!"FALSE"}

+#define STM32_SERIAL_USE_LPUART1            ${doc.STM32_SERIAL_USE_LPUART1!"FALSE"}

+#define STM32_SERIAL_USART1_PRIORITY        ${doc.STM32_SERIAL_USART1_PRIORITY!"12"}

+#define STM32_SERIAL_USART2_PRIORITY        ${doc.STM32_SERIAL_USART2_PRIORITY!"12"}

+#define STM32_SERIAL_LPUART1_PRIORITY       ${doc.STM32_SERIAL_LPUART1_PRIORITY!"12"}

+

+/*

+ * SPI driver system settings.

+ */

+#define STM32_SPI_USE_SPI1                  ${doc.STM32_SPI_USE_SPI1!"FALSE"}

+#define STM32_SPI_USE_SPI3                  ${doc.STM32_SPI_USE_SPI3!"FALSE"}

+#define STM32_SPI_SPI1_RX_DMA_STREAM        ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}

+#define STM32_SPI_SPI1_TX_DMA_STREAM        ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}

+#define STM32_SPI_SPI3_RX_DMA_STREAM        ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}

+#define STM32_SPI_SPI3_TX_DMA_STREAM        ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}

+#define STM32_SPI_SPI1_DMA_PRIORITY         ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}

+#define STM32_SPI_SPI3_DMA_PRIORITY         ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}

+#define STM32_SPI_SPI1_IRQ_PRIORITY         ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"10"}

+#define STM32_SPI_SPI3_IRQ_PRIORITY         ${doc.STM32_SPI_SPI3_IRQ_PRIORITY!"10"}

+#define STM32_SPI_DMA_ERROR_HOOK(spip)      ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}

+

+/*

+ * ST driver system settings.

+ */

+#define STM32_ST_IRQ_PRIORITY               ${doc.STM32_ST_IRQ_PRIORITY!"8"}

+#define STM32_ST_USE_TIMER                  ${doc.STM32_ST_USE_TIMER!"2"}

+

+/*

+ * UART driver system settings.

+ */

+#define STM32_UART_USE_USART1               ${doc.STM32_UART_USE_USART1!"FALSE"}

+#define STM32_UART_USE_USART2               ${doc.STM32_UART_USE_USART2!"FALSE"}

+#define STM32_UART_USART1_RX_DMA_STREAM     ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}

+#define STM32_UART_USART1_TX_DMA_STREAM     ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 6)"}

+#define STM32_UART_USART2_RX_DMA_STREAM     ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}

+#define STM32_UART_USART2_TX_DMA_STREAM     ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}

+#define STM32_UART_USART1_IRQ_PRIORITY      ${doc.STM32_UART_USART1_IRQ_PRIORITY!"12"}

+#define STM32_UART_USART2_IRQ_PRIORITY      ${doc.STM32_UART_USART2_IRQ_PRIORITY!"12"}

+#define STM32_UART_USART1_DMA_PRIORITY      ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}

+#define STM32_UART_USART2_DMA_PRIORITY      ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}

+#define STM32_UART_DMA_ERROR_HOOK(uartp)    ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}

+

+/*

+ * USB driver system settings.

+ */

+#define STM32_USB_USE_USB1                  ${doc.STM32_USB_USE_USB1!"FALSE"}

+#define STM32_USB_LOW_POWER_ON_SUSPEND      ${doc.STM32_USB_LOW_POWER_ON_SUSPEND!"FALSE"}

+#define STM32_USB_USB1_HP_IRQ_PRIORITY      ${doc.STM32_USB_USB1_HP_IRQ_PRIORITY!"13"}

+#define STM32_USB_USB1_LP_IRQ_PRIORITY      ${doc.STM32_USB_USB1_LP_IRQ_PRIORITY!"14"}

+

+/*

+ * WDG driver system settings.

+ */

+#define STM32_WDG_USE_IWDG                  ${doc.STM32_WDG_USE_IWDG!"FALSE"}

+

+#endif /* MCUCONF_H */

diff --git a/tools/updater/update_mcuconf_stm32l432xx.sh b/tools/updater/update_mcuconf_stm32l432xx.sh
new file mode 100644
index 000000000..becaea389
--- /dev/null
+++ b/tools/updater/update_mcuconf_stm32l432xx.sh
@@ -0,0 +1,29 @@
+#!/bin/bash
+if [ $# -eq 2 ]
+  then
+  if [ $1 = "rootpath" ]
+  then
+    find $2 -name "mcuconf.h" -exec bash update_mcuconf_stm32l432xx.sh "{}" \;
+  else
+    echo "Usage: update_mcuconf_stm32l432xx.sh [rootpath <root path>]"
+  fi
+elif [ $# -eq 1 ]
+then
+  declare conffile=$(<$1)
+  if egrep -q "STM32L432_MCUCONF" <<< "$conffile"
+  then
+    echo Processing: $1
+    egrep -e "\#define\s+[a-zA-Z0-9_()]*\s+[a-zA-Z0-9_]" <<< "$conffile" | sed -r 's/\#define\s+([a-zA-Z0-9_]*)(\([^)]*\))?\s+/\1=/g' > ./values.txt
+    if ! fmpp -q -C conf.fmpp -S ../ftl/processors/conf/mcuconf_stm32l432xx
+    then
+      echo
+      echo "aborted"
+      exit 1
+    fi
+    cp ./mcuconf.h $1
+    rm ./mcuconf.h ./values.txt
+  fi
+else
+ echo "Usage: update_mcuconf_stm32l432xx.sh [rootpath <root path>]"
+ echo "       update_mcuconf_stm32l432xx.sh <configuration file>]"
+fi