diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-03-22 11:32:17 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-03-22 11:32:17 +0000 |
| commit | d90b1f5b373449f3993eca639a8f611069a182f8 (patch) | |
| tree | 4fe674991563a48378d2c21842550cb6ef55f758 | |
| parent | c90c3286061fcbff0c19b46c3cfa6e20cc177a99 (diff) | |
| download | ChibiOS-d90b1f5b373449f3993eca639a8f611069a182f8.tar.gz ChibiOS-d90b1f5b373449f3993eca639a8f611069a182f8.tar.bz2 ChibiOS-d90b1f5b373449f3993eca639a8f611069a182f8.zip | |
Fixed bug #479.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6800 35acf78f-673a-0410-8e92-d51de3d6d3f4
| -rw-r--r-- | os/hal/ports/STM32/STM32F37x/adc_lld.c | 13 | ||||
| -rw-r--r-- | testhal/STM32F37x/SDADC/.cproject | 1 |
2 files changed, 10 insertions, 4 deletions
diff --git a/os/hal/ports/STM32/STM32F37x/adc_lld.c b/os/hal/ports/STM32/STM32F37x/adc_lld.c index 54679b62f..3d4ede887 100644 --- a/os/hal/ports/STM32/STM32F37x/adc_lld.c +++ b/os/hal/ports/STM32/STM32F37x/adc_lld.c @@ -427,7 +427,7 @@ void adc_lld_start(ADCDriver *adcp) { (void *)adcp);
osalDbgAssert(!b, "stream already allocated");
dmaStreamSetPeripheral(adcp->dmastp, &SDADC2->JDATAR);
- rccEnableSDADC1(FALSE);
+ rccEnableSDADC2(FALSE);
PWR->CR |= PWR_CR_SDADC2EN;
adcp->sdadc->CR2 = 0;
adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
@@ -444,7 +444,7 @@ void adc_lld_start(ADCDriver *adcp) { (void *)adcp);
osalDbgAssert(!b, "stream already allocated");
dmaStreamSetPeripheral(adcp->dmastp, &SDADC3->JDATAR);
- rccEnableSDADC1(FALSE);
+ rccEnableSDADC2(FALSE);
PWR->CR |= PWR_CR_SDADC3EN;
adcp->sdadc->CR2 = 0;
adcp->sdadc->CR1 = (adcp->config->cr1 | SDADC_ENFORCED_CR1_FLAGS) &
@@ -583,11 +583,16 @@ void adc_lld_start_conversion(ADCDriver *adcp) { adcp->sdadc->CONFCHR1 = grpp->u.sdadc.confchr[0];
adcp->sdadc->CONFCHR2 = grpp->u.sdadc.confchr[1];
+ /* SDADC trigger modes, this write must be performed when
+ SDADC_CR1_INIT=1.*/
+ adcp->sdadc->CR2 = cr2;
+
/* Leaving initialization mode.*/
adcp->sdadc->CR1 &= ~SDADC_CR1_INIT;
- /* SDADC conversion start, the start is performed using the method
- specified in the CR2 configuration, usually SDADC_CR2_JSWSTART.*/
+ /* Special case, if SDADC_CR2_JSWSTART is specified it has to be
+ written after SDADC_CR1_INIT has been set to zero. Just a write is
+ performed, any other bit is ingore if not in initialization mode.*/
adcp->sdadc->CR2 = cr2;
}
#endif /* STM32_ADC_USE_SDADC */
diff --git a/testhal/STM32F37x/SDADC/.cproject b/testhal/STM32F37x/SDADC/.cproject index e3d709437..f3f922904 100644 --- a/testhal/STM32F37x/SDADC/.cproject +++ b/testhal/STM32F37x/SDADC/.cproject @@ -48,4 +48,5 @@ </scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="refreshScope"/>
</cproject>
|