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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-06-18 17:21:04 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-06-18 17:21:04 +0000
commitcdb43a7cd26172cd6ee32dae5f160e615a7af4f5 (patch)
tree7460be318aa77954f0727c8419c37992dfc50f42
parenta0fa191aa30684d9bbe2ce78dd49c2559b5f7e13 (diff)
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4298 35acf78f-673a-0410-8e92-d51de3d6d3f4
-rw-r--r--os/hal/platforms/STM32F2xx/hal_lld.h4
1 files changed, 0 insertions, 4 deletions
diff --git a/os/hal/platforms/STM32F2xx/hal_lld.h b/os/hal/platforms/STM32F2xx/hal_lld.h
index 736853605..ee260fdbb 100644
--- a/os/hal/platforms/STM32F2xx/hal_lld.h
+++ b/os/hal/platforms/STM32F2xx/hal_lld.h
@@ -144,10 +144,6 @@
* @name PWR_CR register bits definitions
* @{
*/
-#define STM32_VOS_MASK (1 << 14) /**< Core voltage mask. */
-#define STM32_VOS_LOW (0 << 14) /**< Core voltage set to low. */
-#define STM32_VOS_HIGH (1 << 14) /**< Core voltage set to high. */
-
#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */