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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2011-12-21 19:06:32 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2011-12-21 19:06:32 +0000
commita8a2a5eaee75923546b46eabf705b43a5b5052ea (patch)
treebc1bb53bab2d57d571770f8a303c39550d6d9ea4
parent334c7d645d1eccc59b9e19678b5e47d1e3ae2320 (diff)
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3646 35acf78f-673a-0410-8e92-d51de3d6d3f4
-rw-r--r--docs/reports/STM32F407-168-GCC-FPU.txt26
-rw-r--r--readme.txt2
2 files changed, 15 insertions, 13 deletions
diff --git a/docs/reports/STM32F407-168-GCC-FPU.txt b/docs/reports/STM32F407-168-GCC-FPU.txt
index 6605e4d62..de0f57cda 100644
--- a/docs/reports/STM32F407-168-GCC-FPU.txt
+++ b/docs/reports/STM32F407-168-GCC-FPU.txt
@@ -6,7 +6,7 @@ Settings: SYSCLK=168, ACR=0x705 (5 wait states)
*** ChibiOS/RT test suite
***
*** Kernel: 2.3.5unstable
-*** Compiled: Dec 17 2011 - 10:02:17
+*** Compiled: Dec 21 2011 - 19:56:38
*** Compiler: GCC 4.6.2
*** Architecture: ARMv7-ME
*** Core Variant: Cortex-M4F
@@ -100,51 +100,51 @@ Settings: SYSCLK=168, ACR=0x705 (5 wait states)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.1 (Benchmark, messages #1)
---- Score : 559411 msgs/S, 1118822 ctxswc/S
+--- Score : 559403 msgs/S, 1118806 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Benchmark, messages #2)
---- Score : 476772 msgs/S, 953544 ctxswc/S
+--- Score : 476766 msgs/S, 953532 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Benchmark, messages #3)
---- Score : 476772 msgs/S, 953544 ctxswc/S
+--- Score : 476766 msgs/S, 953532 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Benchmark, context switch)
---- Score : 1639368 ctxswc/S
+--- Score : 1639344 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Benchmark, threads, full cycle)
---- Score : 371300 threads/S
+--- Score : 371295 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Benchmark, threads, create only)
---- Score : 496529 threads/S
+--- Score : 496523 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
---- Score : 151019 reschedules/S, 906114 ctxswc/S
+--- Score : 151017 reschedules/S, 906102 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Benchmark, round robin context switching)
---- Score : 1018648 ctxswc/S
+--- Score : 1018640 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Benchmark, I/O Queues throughput)
---- Score : 1766664 bytes/S
+--- Score : 1766624 bytes/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Benchmark, virtual timers set/reset)
---- Score : 1997998 timers/S
+--- Score : 1997996 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Benchmark, semaphores wait/signal)
---- Score : 2602024 wait+signal/S
+--- Score : 2601996 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (Benchmark, mutexes lock/unlock)
---- Score : 1766644 lock+unlock/S
+--- Score : 1766624 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.13 (Benchmark, RAM footprint)
diff --git a/readme.txt b/readme.txt
index e4ea879df..fdb6db9ab 100644
--- a/readme.txt
+++ b/readme.txt
@@ -87,6 +87,8 @@
- NEW: Added experimental support for the Cortex-M4 FPU (default when the
FPU is present).
- NEW: Improved I2C driver model and STM32 implementation by Barthess.
+- CHANGE: Removed the option to change the stack alignment in the GCC
+ Cortex-Mx ports, now alignment is always 64 bits.
*** 2.3.4 ***
- FIX: Fixed Extra initialization in STM32 SPI driver (bug 3436127)