More on bug #525.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7174 35acf78f-673a-0410-8e92-d51de3d6d3f4

2 files changed, 9 insertions, 8 deletions

diff --git a/os/hal/ports/STM32/STM32F30x/hal_lld.c b/os/hal/ports/STM32/STM32F30x/hal_lld.c
index 53ac4d11b..1f4666a05 100644
--- a/os/hal/ports/STM32/STM32F30x/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F30x/hal_lld.c
@@ -170,6 +170,9 @@ void stm32_clock_init(void) {
                STM32_PLLSRC    | STM32_PPRE1     | STM32_PPRE2    |

                STM32_HPRE;

   RCC->CFGR2 = STM32_ADC34PRES | STM32_ADC12PRES | STM32_PREDIV;

+  RCC->CFGR3 = STM32_UART5SW   | STM32_UART4SW   | STM32_USART3SW |

+               STM32_USART2SW  | STM32_I2C2SW    | STM32_I2C1SW   |

+               STM32_USART1SW;

 

 #if STM32_ACTIVATE_PLL

   /* PLL activation.*/

@@ -178,12 +181,6 @@ void stm32_clock_init(void) {
     ;                                       /* Waits until PLL is stable.   */

 #endif

 

-  /* After PLL activation because the special requirements for TIM1 and

-     TIM8 bits.*/

-  RCC->CFGR3 = STM32_UART5SW   | STM32_UART4SW   | STM32_USART3SW |

-               STM32_USART2SW  | STM32_TIM8SW    | STM32_TIM1SW   |

-               STM32_I2C2SW    | STM32_I2C1SW    | STM32_USART1SW;

-

   /* Flash setup and final clock selection.   */

   FLASH->ACR = STM32_FLASHBITS;

 

@@ -194,6 +191,10 @@ void stm32_clock_init(void) {
   while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))

     ;                                       /* Waits selection complete.    */

 #endif

+

+  /* After PLL activation because the special requirements for TIM1 and

+     TIM8 bits.*/

+  RCC->CFGR3 |= STM32_TIM8SW | STM32_TIM1SW;

 #endif /* !STM32_NO_INIT */

 }

 

diff --git a/os/hal/ports/STM32/STM32F30x/hal_lld.h b/os/hal/ports/STM32/STM32F30x/hal_lld.h
index 0d567e0ed..605edb879 100644
--- a/os/hal/ports/STM32/STM32F30x/hal_lld.h
+++ b/os/hal/ports/STM32/STM32F30x/hal_lld.h
@@ -1021,7 +1021,7 @@
 #elif STM32_TIM1SW == STM32_TIM1SW_PLLX2

 #if (STM32_SW != STM32_SW_PLL) ||                                           \

     (STM32_HPRE != STM32_HPRE_DIV1) ||                                      \

-    (STM32_PPRE2 != STM32_PPRE2_DIV2)

+    (STM32_PPRE2 != STM32_PPRE2_DIV1)

 #error "double clock mode cannot be activated for TIM1 under the current settings"

 #endif

 #define STM32_TIM1CLK               (STM32_PLLCLKOUT * 2)

@@ -1039,7 +1039,7 @@
 #elif STM32_TIM8SW == STM32_TIM8SW_PLLX2

 #if (STM32_SW != STM32_SW_PLL) ||                                           \

     (STM32_HPRE != STM32_HPRE_DIV1) ||                                      \

-    (STM32_PPRE2 != STM32_PPRE2_DIV2)

+    (STM32_PPRE2 != STM32_PPRE2_DIV1)

 #error "double clock mode cannot be activated for TIM8 under the current settings"

 #endif

 #define STM32_TIM8CLK               (STM32_PLLCLKOUT * 2)