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authorGiovanni Di Sirio <gdisirio@gmail.com>2018-06-15 09:38:13 +0000
committerGiovanni Di Sirio <gdisirio@gmail.com>2018-06-15 09:38:13 +0000
commit95752b318caf77acf1983090d6cd96152c7a0020 (patch)
treeac7c1a2f1cd8cdb577740b2e85c441425d7a4858
parent2fa8776c7699d260e28d19233254f03f491569df (diff)
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Fixed compile time regression in USARTv1 driver.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12102 110e8d01-0319-4d1e-a829-52ad28d1bb01
-rw-r--r--os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c b/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c
index db7ab9250..f4370d28d 100644
--- a/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c
+++ b/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c
@@ -217,7 +217,7 @@ static void usart_start(UARTDriver *uartp) {
Fraction is still 4 bits wide, but only lower 3 bits used.
Mantissa is doubled, but Fraction is left the same.*/
#if defined(USART_CR1_OVER8)
- if (config->cr1 & USART_CR1_OVER8)
+ if (uartp->config->cr1 & USART_CR1_OVER8)
fck = ((fck & ~7) * 2) | (fck & 7);
#endif
u->BRR = fck;